1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
20 // The inverse of CCIfSubtarget
21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
23 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
24 def RetCC_F128SoftFloat : CallingConv<[
25 CCAssignToReg<[V0_64, A0_64]>
28 // For hard-float, f128 values are returned as a pair of f64's rather than a
30 def RetCC_F128HardFloat : CallingConv<[
31 CCBitConvertToType<f64>,
32 CCAssignToReg<[D0_64, D2_64]>
35 // Handle F128 specially since we can't identify the original type during the
36 // tablegen-erated code.
37 def RetCC_F128 : CallingConv<[
38 CCIfSubtarget<"abiUsesSoftFloat()",
39 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
40 CCIfSubtargetNot<"abiUsesSoftFloat()",
41 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
44 //===----------------------------------------------------------------------===//
45 // Mips O32 Calling Convention
46 //===----------------------------------------------------------------------===//
48 // Only the return rules are defined here for O32. The rules for argument
49 // passing are defined in MipsISelLowering.cpp.
50 def RetCC_MipsO32 : CallingConv<[
51 // i32 are returned in registers V0, V1, A0, A1
52 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
54 // f32 are returned in registers F0, F2
55 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
57 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
58 // in D0 and D1 in FP32bit mode.
59 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
60 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
63 //===----------------------------------------------------------------------===//
64 // Mips N32/64 Calling Convention
65 //===----------------------------------------------------------------------===//
67 def CC_MipsN : CallingConv<[
68 // Promote i8/i16 arguments to i32.
69 CCIfType<[i8, i16], CCPromoteToType<i32>>,
71 // Integer arguments are passed in integer registers.
72 CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
75 F16, F17, F18, F19]>>,
77 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
78 T0_64, T1_64, T2_64, T3_64],
79 [D12_64, D13_64, D14_64, D15_64,
80 D16_64, D17_64, D18_64, D19_64]>>,
82 // f32 arguments are passed in single precision FP registers.
83 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
85 [A0_64, A1_64, A2_64, A3_64,
86 T0_64, T1_64, T2_64, T3_64]>>,
88 // f64 arguments are passed in double precision FP registers.
89 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
90 D16_64, D17_64, D18_64, D19_64],
91 [A0_64, A1_64, A2_64, A3_64,
92 T0_64, T1_64, T2_64, T3_64]>>,
94 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
95 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
96 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
99 // N32/64 variable arguments.
100 // All arguments are passed in integer registers.
101 def CC_MipsN_VarArg : CallingConv<[
102 // Promote i8/i16 arguments to i32.
103 CCIfType<[i8, i16], CCPromoteToType<i32>>,
105 CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
107 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
108 T0_64, T1_64, T2_64, T3_64]>>,
110 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
111 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
112 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
115 def RetCC_MipsN : CallingConv<[
116 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
117 // legal and is lowered to i128 which is further lowered to a pair of i64's.
118 // This presents us with a problem for the calling convention since hard-float
119 // still needs to pass them in FPU registers, and soft-float needs to use $v0,
120 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
121 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
122 // whether the result was originally an f128 into the tablegen-erated code.
124 // f128 should only occur for the N64 ABI where long double is 128-bit. On
125 // N32, long double is equivalent to double.
127 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)",
128 CCDelegateTo<RetCC_F128>>>,
130 // Aggregate returns are positioned at the lowest address in the slot for
131 // both little and big-endian targets. When passing in registers, this
132 // requires that big-endian targets shift the value into the upper bits.
133 CCIfSubtarget<"isLittle()",
134 CCIfType<[i8, i16, i32], CCIfInReg<CCPromoteToType<i64>>>>,
135 CCIfSubtargetNot<"isLittle()",
136 CCIfType<[i8, i16, i32], CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
138 // i32 are returned in registers V0, V1
139 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
141 // i64 are returned in registers V0_64, V1_64
142 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
144 // f32 are returned in registers F0, F2
145 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
147 // f64 are returned in registers D0, D2
148 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
151 //===----------------------------------------------------------------------===//
152 // Mips EABI Calling Convention
153 //===----------------------------------------------------------------------===//
155 def CC_MipsEABI : CallingConv<[
156 // Promote i8/i16 arguments to i32.
157 CCIfType<[i8, i16], CCPromoteToType<i32>>,
159 // Integer arguments are passed in integer registers.
160 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
162 // Single fp arguments are passed in pairs within 32-bit mode
163 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
164 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
166 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
167 CCAssignToReg<[F12, F14, F16, F18]>>>,
169 // The first 4 double fp arguments are passed in single fp registers.
170 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
171 CCAssignToReg<[D6, D7, D8, D9]>>>,
173 // Integer values get stored in stack slots that are 4 bytes in
174 // size and 4-byte aligned.
175 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
177 // Integer values get stored in stack slots that are 8 bytes in
178 // size and 8-byte aligned.
179 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
182 def RetCC_MipsEABI : CallingConv<[
183 // i32 are returned in registers V0, V1
184 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
186 // f32 are returned in registers F0, F1
187 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
189 // f64 are returned in register D0
190 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
193 //===----------------------------------------------------------------------===//
194 // Mips FastCC Calling Convention
195 //===----------------------------------------------------------------------===//
196 def CC_MipsO32_FastCC : CallingConv<[
197 // f64 arguments are passed in double-precision floating pointer registers.
198 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
199 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
201 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
202 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
203 D4_64, D5_64, D6_64, D7_64,
204 D8_64, D9_64, D10_64, D11_64,
205 D12_64, D13_64, D14_64, D15_64,
206 D16_64, D17_64, D18_64,
208 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
209 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
210 D8_64, D10_64, D12_64, D14_64,
213 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
214 CCIfType<[f64], CCAssignToStack<8, 8>>
217 def CC_MipsN_FastCC : CallingConv<[
218 // Integer arguments are passed in integer registers.
219 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
220 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
223 // f64 arguments are passed in double-precision floating pointer registers.
224 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
225 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
226 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
229 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
231 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
234 def CC_Mips_FastCC : CallingConv<[
235 // Handles byval parameters.
236 CCIfByVal<CCPassByVal<4, 4>>,
238 // Promote i8/i16 arguments to i32.
239 CCIfType<[i8, i16], CCPromoteToType<i32>>,
241 // Integer arguments are passed in integer registers. All scratch registers,
242 // except for AT, V0 and T9, are available to be used as argument registers.
243 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
244 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
246 // In NaCl, T6, T7 and T8 are reserved and not available as argument
247 // registers for fastcc. T6 contains the mask for sandboxing control flow
248 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
249 // accesses (loads and stores). T8 contains the thread pointer.
250 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
251 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
253 // f32 arguments are passed in single-precision floating pointer registers.
254 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
255 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
256 F14, F15, F16, F17, F18, F19]>>>,
258 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
259 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
260 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
262 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
263 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
265 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
266 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
267 CCDelegateTo<CC_MipsN_FastCC>
272 def CC_Mips16RetHelper : CallingConv<[
273 // Integer arguments are passed in integer registers.
274 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
277 //===----------------------------------------------------------------------===//
278 // Mips Calling Convention Dispatch
279 //===----------------------------------------------------------------------===//
281 def RetCC_Mips : CallingConv<[
282 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
283 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
284 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
285 CCDelegateTo<RetCC_MipsO32>
288 //===----------------------------------------------------------------------===//
289 // Callee-saved register lists.
290 //===----------------------------------------------------------------------===//
292 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
293 (sequence "S%u", 7, 0))>;
295 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
296 (sequence "S%u", 7, 0))> {
297 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
300 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
301 (sequence "S%u", 7, 0))>;
304 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
305 (sequence "S%u", 7, 0))>;
307 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
308 D30_64, RA_64, FP_64, GP_64,
309 (sequence "S%u_64", 7, 0))>;
311 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
312 GP_64, (sequence "S%u_64", 7, 0))>;
314 def CSR_Mips16RetHelper :
315 CalleeSavedRegs<(add V0, V1, FP,
316 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
317 (sequence "D%u", 15, 10))>;