1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm16_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
24 def simm10_64 : Operand<i64>;
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 // Node immediate fits as 10-bit sign extended on target immediate.
36 def immSExt10_64 : PatLeaf<(i64 imm),
37 [{ return isInt<10>(N->getSExtValue()); }]>;
39 //===----------------------------------------------------------------------===//
40 // Instructions specific format
41 //===----------------------------------------------------------------------===//
42 let usesCustomInserter = 1 in {
43 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
44 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
45 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
46 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
47 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
48 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
49 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
50 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
53 /// Pseudo instructions for loading and storing accumulator registers.
54 let isPseudo = 1, isCodeGenOnly = 1 in {
55 def LOAD_ACC128 : Load<"", ACC128>;
56 def STORE_ACC128 : Store<"", ACC128>;
59 //===----------------------------------------------------------------------===//
60 // Instruction definition
61 //===----------------------------------------------------------------------===//
62 let DecoderNamespace = "Mips64" in {
63 /// Arithmetic Instructions (ALU Immediate)
64 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
66 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
68 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
70 let isCodeGenOnly = 1 in {
71 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
73 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
75 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
77 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
79 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
81 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
84 /// Arithmetic Instructions (3-Operand, R-Type)
85 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
87 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
89 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
91 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
94 let isCodeGenOnly = 1 in {
95 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
96 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
97 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
98 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
99 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
100 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
103 /// Shift Instructions
104 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
105 SRA_FM<0x38, 0>, ISA_MIPS3;
106 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
107 SRA_FM<0x3a, 0>, ISA_MIPS3;
108 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
109 SRA_FM<0x3b, 0>, ISA_MIPS3;
110 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
111 SRLV_FM<0x14, 0>, ISA_MIPS3;
112 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
113 SRLV_FM<0x16, 0>, ISA_MIPS3;
114 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
115 SRLV_FM<0x17, 0>, ISA_MIPS3;
116 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
117 SRA_FM<0x3c, 0>, ISA_MIPS3;
118 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
119 SRA_FM<0x3e, 0>, ISA_MIPS3;
120 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
121 SRA_FM<0x3f, 0>, ISA_MIPS3;
123 // Rotate Instructions
124 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
126 SRA_FM<0x3a, 1>, ISA_MIPS64R2;
127 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
128 SRLV_FM<0x16, 1>, ISA_MIPS64R2;
129 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
130 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
132 /// Load and Store Instructions
134 let isCodeGenOnly = 1 in {
135 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
136 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
137 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
138 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
139 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
140 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
141 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
142 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
145 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
146 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
147 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
149 /// load/store left/right
150 let isCodeGenOnly = 1 in {
151 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
152 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
153 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
154 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
157 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
158 ISA_MIPS3_NOT_32R6_64R6;
159 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
160 ISA_MIPS3_NOT_32R6_64R6;
161 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
162 ISA_MIPS3_NOT_32R6_64R6;
163 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
164 ISA_MIPS3_NOT_32R6_64R6;
166 /// Load-linked, Store-conditional
167 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3;
168 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3;
170 /// Jump and Branch Instructions
171 let isCodeGenOnly = 1 in {
172 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
173 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
174 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
175 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
176 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
177 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
178 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
179 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
180 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
181 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
184 /// Multiply and Divide Instructions.
185 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
186 MULT_FM<0, 0x1c>, ISA_MIPS3;
187 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
188 MULT_FM<0, 0x1d>, ISA_MIPS3;
189 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
191 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
193 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
194 MULT_FM<0, 0x1e>, ISA_MIPS3;
195 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
196 MULT_FM<0, 0x1f>, ISA_MIPS3;
197 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
199 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
202 let isCodeGenOnly = 1 in {
203 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;
204 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>;
205 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>;
206 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>;
207 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>;
208 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>;
209 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>;
211 /// Sign Ext In Register Instructions.
212 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
214 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
219 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64;
220 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64;
222 /// Double Word Swap Bytes/HalfWords
223 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
224 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
226 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
228 let isCodeGenOnly = 1 in
229 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
231 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
232 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
233 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
235 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
236 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
237 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
239 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
240 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
241 "dsll\t$rd, $rt, 32", [], II_DSLL>;
242 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
243 "sll\t$rd, $rt, 0", [], II_SLL>;
244 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
245 "sll\t$rd, $rt, 0", [], II_SLL>;
248 // We need the following pseudo instruction to avoid offset calculation for
249 // long branches. See the comment in file MipsLongBranch.cpp for detailed
252 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
253 // where %PART may be %hi or %lo, depending on the relocation kind
254 // that $tgt is annotated with.
255 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
256 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
258 // Cavium Octeon cmMIPS instructions
259 let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
260 AdditionalPredicates = [HasCnMips] in {
262 class Count1s<string opstr, RegisterOperand RO>:
263 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
264 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
265 let TwoOperandAliasConstraint = "$rd = $rs";
268 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
269 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
270 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
271 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
272 NoItinerary, FrmR, opstr> {
273 let TwoOperandAliasConstraint = "$rt = $rs";
276 class SetCC64_R<string opstr, PatFrag cond_op> :
277 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
278 !strconcat(opstr, "\t$rd, $rs, $rt"),
279 [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
280 II_SEQ_SNE, FrmR, opstr> {
281 let TwoOperandAliasConstraint = "$rd = $rs";
284 class SetCC64_I<string opstr, PatFrag cond_op>:
285 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
286 !strconcat(opstr, "\t$rt, $rs, $imm10"),
287 [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
288 II_SEQI_SNEI, FrmI, opstr> {
289 let TwoOperandAliasConstraint = "$rt = $rs";
293 let Pattern = [(set GPR64Opnd:$rd,
294 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
295 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
298 // Multiply Doubleword to GPR
299 let Defs = [HI0, LO0, P0, P1, P2] in
300 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
303 // Extract a signed bit field /+32
304 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
305 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
307 // Clear and insert a bit field /+32
308 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
309 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
311 // Move to multiplier/product register
312 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
313 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
314 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
315 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
316 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
317 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
319 // Count Ones in a Word/Doubleword
320 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
321 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
323 // Set on equal/not equal
324 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
325 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
326 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
327 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
329 // 192-bit x 64-bit Unsigned Multiply and Add
330 let Defs = [P0, P1, P2] in
331 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
334 // 64-bit Unsigned Multiply and Add Move
335 let Defs = [MPL0, P0, P1, P2] in
336 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
339 // 64-bit Unsigned Multiply and Add
340 let Defs = [MPL1, MPL2, P0, P1, P2] in
341 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
348 //===----------------------------------------------------------------------===//
349 // Arbitrary patterns that map to one or more instructions
350 //===----------------------------------------------------------------------===//
353 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
354 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
355 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
356 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
359 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
360 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
361 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
362 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
363 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
364 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
366 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
367 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
368 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
369 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
370 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
371 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
372 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
374 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
375 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
376 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
377 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
378 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
379 (DADDiu GPR64:$hi, tjumptable:$lo)>;
380 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
381 (DADDiu GPR64:$hi, tconstpool:$lo)>;
382 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
383 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
385 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
386 def : WrapperPat<tconstpool, DADDiu, GPR64>;
387 def : WrapperPat<texternalsym, DADDiu, GPR64>;
388 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
389 def : WrapperPat<tjumptable, DADDiu, GPR64>;
390 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
392 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
395 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
396 (BLEZ64 i64:$lhs, bb:$dst)>;
397 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
398 (BGEZ64 i64:$lhs, bb:$dst)>;
401 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
402 defm : SetlePats<GPR64, SLT64, SLTu64>;
403 defm : SetgtPats<GPR64, SLT64, SLTu64>;
404 defm : SetgePats<GPR64, SLT64, SLTu64>;
405 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
408 def : MipsPat<(i32 (trunc GPR64:$src)),
409 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
411 // 32-to-64-bit extension
412 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
413 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
414 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
416 // Sign extend in register
417 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
418 (SLL64_64 GPR64:$src)>;
421 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
423 //===----------------------------------------------------------------------===//
424 // Instruction aliases
425 //===----------------------------------------------------------------------===//
426 def : MipsInstAlias<"move $dst, $src",
427 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
429 def : MipsInstAlias<"daddu $rs, $rt, $imm",
430 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
432 def : MipsInstAlias<"dadd $rs, $rt, $imm",
433 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
435 def : MipsInstAlias<"daddu $rs, $imm",
436 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
438 def : MipsInstAlias<"dadd $rs, $imm",
439 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
441 def : MipsInstAlias<"add $rs, $imm",
442 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
444 def : MipsInstAlias<"addu $rs, $imm",
445 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
447 def : MipsInstAlias<"dsll $rd, $rt, $rs",
448 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
450 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
451 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
452 InvertedImOperand64:$imm), 0>;
453 def : MipsInstAlias<"dsub $rs, $imm",
454 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
455 InvertedImOperand64:$imm),
457 def : MipsInstAlias<"dsubu $rs, $imm",
458 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
459 InvertedImOperand64:$imm),
461 def : MipsInstAlias<"dsra $rd, $rt, $rs",
462 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
464 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
465 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
468 /// Move between CPU and coprocessor registers
469 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
470 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
471 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
472 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
473 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
476 // Two operand (implicit 0 selector) versions:
477 def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
478 def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
479 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
480 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;