1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: jr -> jalr
19 // Reencoded: jr.hb -> jalr.hb
22 def brtarget21 : Operand<OtherVT> {
23 let EncoderMethod = "getBranchTarget21OpValue";
24 let OperandType = "OPERAND_PCREL";
25 let DecoderMethod = "DecodeBranchTarget21";
26 let ParserMatchClass = MipsJumpTargetAsmOperand;
29 def brtarget26 : Operand<OtherVT> {
30 let EncoderMethod = "getBranchTarget26OpValue";
31 let OperandType = "OPERAND_PCREL";
32 let DecoderMethod = "DecodeBranchTarget26";
33 let ParserMatchClass = MipsJumpTargetAsmOperand;
36 def jmpoffset16 : Operand<OtherVT> {
37 let EncoderMethod = "getJumpOffset16OpValue";
38 let ParserMatchClass = MipsJumpTargetAsmOperand;
41 def calloffset16 : Operand<iPTR> {
42 let EncoderMethod = "getJumpOffset16OpValue";
43 let ParserMatchClass = MipsJumpTargetAsmOperand;
46 //===----------------------------------------------------------------------===//
48 // Instruction Encodings
50 //===----------------------------------------------------------------------===//
52 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
53 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
54 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
55 class AUI_ENC : AUI_FM;
56 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
58 class BAL_ENC : BAL_FM;
59 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
60 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
61 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
62 DecodeDisambiguates<"AddiGroupBranch">;
63 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
64 DecodeDisambiguatedBy<"DaddiGroupBranch">;
65 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
66 DecodeDisambiguates<"DaddiGroupBranch">;
67 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
68 DecodeDisambiguatedBy<"DaddiGroupBranch">;
70 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
71 DecodeDisambiguates<"BgtzlGroupBranch">;
72 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
73 DecodeDisambiguatedBy<"BlezlGroupBranch">;
74 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
75 DecodeDisambiguatedBy<"BlezGroupBranch">;
76 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
77 DecodeDisambiguates<"BlezlGroupBranch">;
78 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
79 DecodeDisambiguatedBy<"BgtzGroupBranch">;
81 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
82 DecodeDisambiguatedBy<"BlezlGroupBranch">;
83 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
84 DecodeDisambiguates<"BgtzGroupBranch">;
85 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
86 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
88 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
89 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
90 DecodeDisambiguates<"BlezGroupBranch">;
91 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
93 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
94 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
95 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
96 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
98 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
99 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
100 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
101 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
102 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
103 DecodeDisambiguatedBy<"BlezGroupBranch">;
104 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
105 DecodeDisambiguatedBy<"DaddiGroupBranch">;
106 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
107 DecodeDisambiguatedBy<"AddiGroupBranch">;
108 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
109 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
110 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
111 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
112 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
113 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
114 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
115 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
117 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
118 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
119 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
120 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
122 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
123 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
125 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
126 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
128 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
129 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
131 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
132 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
133 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
134 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
136 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
137 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
138 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
139 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
141 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
142 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
143 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
144 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
146 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
147 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
148 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
149 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
151 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
152 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
154 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
155 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
156 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
157 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
159 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
160 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
162 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
163 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
165 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
166 RegisterOperand FGROpnd,
167 SDPatternOperator Op = null_frag> {
168 dag OutOperandList = (outs FGRCCOpnd:$fd);
169 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
170 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
171 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
174 //===----------------------------------------------------------------------===//
176 // Instruction Multiclasses
178 //===----------------------------------------------------------------------===//
180 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
181 RegisterOperand FGROpnd>{
182 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
183 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
185 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
186 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
188 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
189 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
191 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
192 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
194 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
195 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
197 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
198 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
200 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
201 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
203 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
204 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
206 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
207 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
209 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
210 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
212 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
213 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
215 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
216 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
218 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
219 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
221 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
222 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
224 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
225 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
227 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
228 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
232 //===----------------------------------------------------------------------===//
234 // Instruction Descriptions
236 //===----------------------------------------------------------------------===//
238 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
240 dag OutOperandList = (outs GPROpnd:$rs);
241 dag InOperandList = (ins ImmOpnd:$imm);
242 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
243 list<dag> Pattern = [];
246 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
247 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
248 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
250 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
252 dag OutOperandList = (outs GPROpnd:$rd);
253 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
254 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
255 list<dag> Pattern = [];
258 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
260 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
261 dag OutOperandList = (outs GPROpnd:$rs);
262 dag InOperandList = (ins simm16:$imm);
263 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
264 list<dag> Pattern = [];
267 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
268 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
270 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
271 dag OutOperandList = (outs GPROpnd:$rs);
272 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
273 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
274 list<dag> Pattern = [];
277 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
279 class BRANCH_DESC_BASE {
281 bit isTerminator = 1;
282 bit hasDelaySlot = 0;
285 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
286 dag InOperandList = (ins opnd:$offset);
287 dag OutOperandList = (outs);
288 string AsmString = !strconcat(instr_asm, "\t$offset");
292 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
293 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
294 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
295 dag OutOperandList = (outs);
296 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
297 list<Register> Defs = [AT];
300 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
301 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
302 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
303 dag OutOperandList = (outs);
304 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
305 list<Register> Defs = [AT];
308 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
309 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
310 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
311 dag OutOperandList = (outs);
312 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
313 list<Register> Defs = [AT];
316 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
318 bit hasDelaySlot = 1;
319 list<Register> Defs = [RA];
322 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
324 list<Register> Defs = [RA];
327 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
328 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
329 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
330 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
331 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
333 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
334 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
336 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
337 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
339 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
340 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
342 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
343 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
344 dag OutOperandList = (outs);
345 string AsmString = instr_asm;
346 bit hasDelaySlot = 1;
349 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
350 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
352 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
353 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
354 dag OutOperandList = (outs);
355 string AsmString = instr_asm;
356 bit hasDelaySlot = 1;
359 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
360 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
362 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
363 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
365 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
366 RegisterOperand GPROpnd> {
367 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
368 string AsmString = !strconcat(opstr, "\t$rt, $offset");
369 list<dag> Pattern = [];
370 bit isTerminator = 1;
371 bit hasDelaySlot = 0;
372 string DecoderMethod = "DecodeSimm16";
375 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
378 list<Register> Defs = [RA];
381 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
383 list<Register> Defs = [AT];
386 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
388 bit isIndirectBranch = 1;
389 bit hasDelaySlot = 1;
394 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
395 dag OutOperandList = (outs GPROpnd:$rd);
396 dag InOperandList = (ins GPROpnd:$rt);
397 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
398 list<dag> Pattern = [];
401 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
403 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
404 SDPatternOperator Op=null_frag> {
405 dag OutOperandList = (outs GPROpnd:$rd);
406 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
407 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
408 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
410 // This instruction doesn't trap division by zero itself. We must insert
411 // teq instructions as well.
412 bit usesCustomInserter = 1;
415 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
416 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
417 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
418 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
420 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
421 list<Register> Defs = [RA];
424 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
425 list<Register> Defs = [RA];
428 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
429 list<Register> Defs = [RA];
432 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
433 list<Register> Defs = [RA];
436 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
437 list<Register> Defs = [RA];
440 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
441 list<Register> Defs = [RA];
444 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
445 SDPatternOperator Op=null_frag> {
446 dag OutOperandList = (outs GPROpnd:$rd);
447 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
448 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
449 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
452 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
453 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
454 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
455 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
457 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
458 dag OutOperandList = (outs FGROpnd:$fd);
459 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
460 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
461 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
464 string Constraints = "$fd_in = $fd";
467 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
468 // We must insert a SUBREG_TO_REG around $fd_in
469 bit usesCustomInserter = 1;
471 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
473 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
474 dag OutOperandList = (outs GPROpnd:$rd);
475 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
476 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
477 list<dag> Pattern = [];
480 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
481 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
483 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
484 dag OutOperandList = (outs FGROpnd:$fd);
485 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
486 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
487 list<dag> Pattern = [];
488 string Constraints = "$fd_in = $fd";
491 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
492 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
493 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
494 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
496 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
497 dag OutOperandList = (outs FGROpnd:$fd);
498 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
499 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
500 list<dag> Pattern = [];
503 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
504 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
505 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
506 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
508 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
509 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
510 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
511 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
513 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
514 dag OutOperandList = (outs FGROpnd:$fd);
515 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
516 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
517 list<dag> Pattern = [];
520 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
521 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
522 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
523 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
525 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
526 dag OutOperandList = (outs FGROpnd:$fd);
527 dag InOperandList = (ins FGROpnd:$fs);
528 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
529 list<dag> Pattern = [];
532 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
533 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
534 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
535 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
537 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
538 RegisterOperand GPROpnd> {
539 dag OutOperandList = (outs);
540 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
541 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
542 list<dag> Pattern = [];
545 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
546 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>;
548 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
549 dag OutOperandList = (outs COPOpnd:$rt);
550 dag InOperandList = (ins mem_simm11:$addr);
551 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
552 list<dag> Pattern = [];
556 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
557 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>;
559 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
560 dag OutOperandList = (outs);
561 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
562 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
563 list<dag> Pattern = [];
567 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;
568 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
570 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
571 dag OutOperandList = (outs GPROpnd:$rt);
572 dag InOperandList = (ins mem_simm9:$addr);
573 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
574 list<dag> Pattern = [];
578 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>;
580 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
581 dag OutOperandList = (outs GPROpnd:$dst);
582 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
583 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
584 list<dag> Pattern = [];
586 string Constraints = "$rt = $dst";
589 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
591 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
592 dag OutOperandList = (outs GPROpnd:$rd);
593 dag InOperandList = (ins GPROpnd:$rs);
594 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
597 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
598 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
599 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
602 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
603 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
604 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
607 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
608 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
610 //===----------------------------------------------------------------------===//
612 // Instruction Definitions
614 //===----------------------------------------------------------------------===//
616 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
617 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
618 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
619 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
620 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
621 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
622 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
623 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
624 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
625 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
626 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
627 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
628 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
629 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
630 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
631 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
632 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
633 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
634 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
635 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
636 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
637 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
638 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
639 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
640 def BLTC; // Also aliased to bgtc with operands swapped
641 def BLTUC; // Also aliased to bgtuc with operands swapped
642 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
643 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
644 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
645 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
646 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
647 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
648 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
649 def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
650 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
651 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
652 def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
653 def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
654 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
655 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
656 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
657 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
658 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
659 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
660 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
661 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
662 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
663 // def LSA; // See MSA
664 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
665 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
666 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
667 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
668 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
669 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
670 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
671 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
672 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
673 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
674 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
675 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
676 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
677 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
678 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
679 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
680 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
681 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
682 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
683 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
684 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
685 def NAL; // BAL with rd=0
686 def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6;
687 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
688 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
689 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
690 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
691 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
692 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
693 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
694 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
695 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
696 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
697 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
698 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
699 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
701 //===----------------------------------------------------------------------===//
703 // Patterns and Pseudo Instructions
705 //===----------------------------------------------------------------------===//
707 // f32 comparisons supported via another comparison
708 def : MipsPat<(setone f32:$lhs, f32:$rhs),
709 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
710 def : MipsPat<(seto f32:$lhs, f32:$rhs),
711 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
712 def : MipsPat<(setune f32:$lhs, f32:$rhs),
713 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
714 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
716 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
718 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
720 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
722 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
724 def : MipsPat<(setne f32:$lhs, f32:$rhs),
725 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
727 // f64 comparisons supported via another comparison
728 def : MipsPat<(setone f64:$lhs, f64:$rhs),
729 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
730 def : MipsPat<(seto f64:$lhs, f64:$rhs),
731 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
732 def : MipsPat<(setune f64:$lhs, f64:$rhs),
733 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
734 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
736 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
738 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
740 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
742 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
744 def : MipsPat<(setne f64:$lhs, f64:$rhs),
745 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
748 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
749 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
751 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
752 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
754 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
755 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
757 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
758 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
759 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
761 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
762 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
763 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
765 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
767 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
768 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
770 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
772 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
773 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
776 def : MipsPat<(select i32:$cond, i32:$t, immz),
777 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
778 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
779 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
780 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
781 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
782 def : MipsPat<(select i32:$cond, immz, i32:$f),
783 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
784 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
785 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
786 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
787 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;