lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def mem_mm_9 : Operand<i32> {
  15   let PrintMethod = "printMemOperand";
  16   let MIOperandInfo = (ops GPR32, simm9);
  17   let EncoderMethod = "getMemEncodingMMImm9";
  18   let ParserMatchClass = MipsMemAsmOperand;
  19   let OperandType = "OPERAND_MEMORY";
  20 }
  21
  22 //===----------------------------------------------------------------------===//
  23 //
  24 // Instruction Encodings
  25 //
  26 //===----------------------------------------------------------------------===//
  27 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  28 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  29 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  30 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  31 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  32 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  33 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  34 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  35 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  36 class AUI_MMR6_ENC : AUI_FM_MMR6;
  37 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  38 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  39 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  40 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  41 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  42 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  43 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  44 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  45 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  46 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  47 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  48 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  49 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  50 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  51 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  52 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  53 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  54 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  55 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  56 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  57 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  58 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  59 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  60 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  61 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  62 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  63 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  64 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  65 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  66 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  67 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  68 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  69 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  70 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  71 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  72 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  73 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  74 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  75 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  76 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  77 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  78 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  79 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  80 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  81 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  82 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
  83 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
  84 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
  85 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
  86 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
  87 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
  88 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
  89 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
  90 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
  91 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
  92 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
  93 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
  94 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
  95 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
  96 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
  97 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
  98 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
  99 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
 100 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
 101 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 102 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 103 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 104 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 105 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 106 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 107
 108 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 109                                   RegisterOperand GPROpnd>
 110     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 111   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 112   dag OutOperandList = (outs);
 113   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 114   list<Register> Defs = [AT];
 115 }
 116
 117 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 118                                                       GPR32Opnd> {
 119   list<Register> Defs = [RA];
 120 }
 121
 122 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 123                                                       GPR32Opnd> {
 124   list<Register> Defs = [RA];
 125 }
 126
 127 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 128                                                       GPR32Opnd> {
 129   list<Register> Defs = [RA];
 130 }
 131
 132 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 133                                                       GPR32Opnd> {
 134   list<Register> Defs = [RA];
 135 }
 136
 137 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 138                                                       GPR32Opnd> {
 139   list<Register> Defs = [RA];
 140 }
 141
 142 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 143                                                       GPR32Opnd> {
 144   list<Register> Defs = [RA];
 145 }
 146
 147 /// Floating Point Instructions
 148 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 149 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 150 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 151 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 152 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 153 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 154 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 155 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 156 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 157 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 158 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 159 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 160 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 161 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 162 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 163 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 164 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 165 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 166 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 167 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 168 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 169 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 170 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 171 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 172
 173 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 174 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 175 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 176 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 177 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 178 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 179 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 180 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 181 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 182 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 183
 184 //===----------------------------------------------------------------------===//
 185 //
 186 // Operand Definitions
 187 //
 188 //===----------------------------------------------------------------------===//
 189
 190 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
 191   let Name = "MemOffsetSimm9GPR";
 192   let SuperClasses = [MipsMemAsmOperand];
 193   let RenderMethod = "addMemOperands";
 194   let ParserMethod = "parseMemOperand";
 195   let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
 196 }
 197
 198 def mem_simm9gpr : mem_generic {
 199   let MIOperandInfo = (ops ptr_rc, simm9);
 200   let EncoderMethod = "getMemEncoding";
 201   let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
 202 }
 203
 204 //===----------------------------------------------------------------------===//
 205 //
 206 // Instruction Descriptions
 207 //
 208 //===----------------------------------------------------------------------===//
 209
 210 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 211 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 212 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 213 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 214 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 215 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 216 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 217
 218 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 219     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 220   dag InOperandList = (ins opnd:$offset);
 221   dag OutOperandList = (outs);
 222   string AsmString = !strconcat(instr_asm, "\t$offset");
 223   bit isBarrier = 1;
 224 }
 225
 226 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
 227   bit isCall = 1;
 228   list<Register> Defs = [RA];
 229 }
 230 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 231
 232 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 233                                        !strconcat("bc16", "\t$offset"), [],
 234                                        IIBranch, FrmI>,
 235                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 236   let isBranch = 1;
 237   let isTerminator = 1;
 238   let isBarrier = 1;
 239   let hasDelaySlot = 0;
 240   let AdditionalPredicates = [RelocPIC];
 241   let Defs = [AT];
 242 }
 243
 244 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 245     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 246   let isBranch = 1;
 247   let isTerminator = 1;
 248   let hasDelaySlot = 0;
 249   let Defs = [AT];
 250 }
 251 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 252 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 253
 254 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 255 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 256
 257 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 258     : MMR6Arch<instr_asm> {
 259   dag OutOperandList = (outs GPROpnd:$rd);
 260   dag InOperandList = (ins GPROpnd:$rt);
 261   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 262   list<dag> Pattern = [];
 263 }
 264
 265 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 266
 267 class BRK_MMR6_DESC : BRK_FT<"break">;
 268
 269 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 270                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 271   dag OutOperandList = (outs);
 272   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 273   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 274   list<dag> Pattern = [];
 275   string DecoderMethod = "DecodeCacheOpMM";
 276 }
 277
 278 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 279 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 280
 281 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 282     : MMR6Arch<instr_asm> {
 283   dag OutOperandList = (outs GPROpnd:$rt);
 284   dag InOperandList = (ins GPROpnd:$rs);
 285   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 286 }
 287
 288 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 289 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 290
 291 class EHB_MMR6_DESC : Barrier<"ehb">;
 292 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 293
 294 class ERET_MMR6_DESC : ER_FT<"eret">;
 295 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 296
 297 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 298                                      RegisterOperand GPROpnd>
 299     : MMR6Arch<opstr> {
 300   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 301   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 302   list<dag> Pattern = [];
 303   bit isTerminator = 1;
 304   bit hasDelaySlot = 0;
 305 }
 306
 307 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 308                                                        GPR32Opnd> {
 309   bit isCall = 1;
 310   list<Register> Defs = [RA];
 311 }
 312
 313 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 314                                                      GPR32Opnd> {
 315   bit isBarrier = 1;
 316   list<Register> Defs = [AT];
 317 }
 318
 319 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 320                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 321   dag OutOperandList = (outs GPROpnd:$rd);
 322   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 323   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 324   list<dag> Pattern = [];
 325 }
 326
 327 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 328
 329 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 330     : MMR6Arch<instr_asm> {
 331   dag OutOperandList = (outs GPROpnd:$rt);
 332   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 333   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 334   list<dag> Pattern = [];
 335 }
 336
 337 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 338
 339 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 340 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 341 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 342     : MMR6Arch<instr_asm> {
 343   dag OutOperandList = (outs GPROpnd:$rt);
 344   dag InOperandList = (ins simm16:$imm);
 345   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 346   list<dag> Pattern = [];
 347 }
 348
 349 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 350 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 351
 352 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 353                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 354   dag OutOperandList = (outs GPROpnd:$rd);
 355   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 356   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 357   list<dag> Pattern = [];
 358 }
 359
 360 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
 361
 362 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 363                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 364   dag OutOperandList = (outs GPROpnd:$rt);
 365   dag InOperandList = (ins ImmOpnd:$imm);
 366   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 367   list<dag> Pattern = [];
 368 }
 369
 370 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 371 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 372
 373 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 374     : MMR6Arch<instr_asm> {
 375   dag OutOperandList = (outs GPROpnd:$rd);
 376   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 377   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 378   list<dag> Pattern = [];
 379 }
 380
 381 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 382 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 383 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 384 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 385 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 386 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 387 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 388 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 389 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 390 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 391 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 392 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 393 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 394 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 395
 396 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 397                   SDPatternOperator OpNode = null_frag,
 398                   InstrItinClass Itin = NoItinerary,
 399                   ComplexPattern Addr = addr> :
 400   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 401          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 402   let DecoderMethod = "DecodeMem";
 403   let mayStore = 1;
 404 }
 405 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 406 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
 407
 408 /// Floating Point Instructions
 409 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 410                             InstrItinClass Itin, bit isComm,
 411                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 412   dag OutOperandList = (outs RC:$fd);
 413   dag InOperandList = (ins RC:$ft, RC:$fs);
 414   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 415   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 416   InstrItinClass Itinerary = Itin;
 417   bit isCommutable = isComm;
 418 }
 419 class FADD_S_MMR6_DESC
 420   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 421 class FADD_D_MMR6_DESC
 422   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 423 class FSUB_S_MMR6_DESC
 424   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 425 class FSUB_D_MMR6_DESC
 426   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 427 class FMUL_S_MMR6_DESC
 428   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 429 class FMUL_D_MMR6_DESC
 430   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 431 class FDIV_S_MMR6_DESC
 432   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 433 class FDIV_D_MMR6_DESC
 434   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 435 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 436 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 437 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 438 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 439
 440 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 441                                RegisterOperand SrcRC, InstrItinClass Itin,
 442                                SDPatternOperator OpNode = null_frag>
 443                                : HARDFLOAT, NeverHasSideEffects {
 444   dag OutOperandList = (outs DstRC:$ft);
 445   dag InOperandList = (ins SrcRC:$fs);
 446   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 447   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 448   InstrItinClass Itinerary = Itin;
 449   Format Form = FrmFR;
 450 }
 451 class FMOV_S_MMR6_DESC
 452   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 453 class FMOV_D_MMR6_DESC
 454   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 455 class FNEG_S_MMR6_DESC
 456   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 457 class FNEG_D_MMR6_DESC
 458   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 459
 460 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 461 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 462 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 463 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 464
 465 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 466 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 467 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 468 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 469
 470 class CVT_MMR6_DESC_BASE<
 471     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 472     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 473     : HARDFLOAT, NeverHasSideEffects {
 474   dag OutOperandList = (outs DstRC:$ft);
 475   dag InOperandList = (ins SrcRC:$fs);
 476   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 477   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 478   InstrItinClass Itinerary = Itin;
 479   Format Form = FrmFR;
 480 }
 481
 482 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 483                                              II_CVT>;
 484 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 485                                              II_CVT>;
 486 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 487                                              II_CVT>;
 488 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 489                                              II_CVT>;
 490 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 491                                              II_CVT>;
 492 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 493                                              II_CVT>;
 494 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 495                                              II_CVT>, FGR_64;
 496 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 497                                              II_CVT>;
 498 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 499                                              II_CVT>;
 500 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 501                                              II_CVT>, FGR_64;
 502
 503 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 504                        RegisterOperand FGROpnd> {
 505   def CMP_AF_#NAME : POOL32F_CMP_FM<
 506       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 507       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 508       ISA_MICROMIPS32R6;
 509   def CMP_UN_#NAME : POOL32F_CMP_FM<
 510       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 511       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 512       ISA_MICROMIPS32R6;
 513   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 514       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 515       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 516       ISA_MICROMIPS32R6;
 517   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 518       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 519       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 520       ISA_MICROMIPS32R6;
 521   def CMP_LT_#NAME : POOL32F_CMP_FM<
 522       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 523       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 524       ISA_MICROMIPS32R6;
 525   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 526       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 527       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 528       ISA_MICROMIPS32R6;
 529   def CMP_LE_#NAME : POOL32F_CMP_FM<
 530       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 531       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 532       ISA_MICROMIPS32R6;
 533   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 534       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 535       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 536       ISA_MICROMIPS32R6;
 537   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 538       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 539       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 540       ISA_MICROMIPS32R6;
 541   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 542       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 543       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 544       ISA_MICROMIPS32R6;
 545   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 546       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 547       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 548       ISA_MICROMIPS32R6;
 549   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 550       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 551       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 552       ISA_MICROMIPS32R6;
 553   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 554       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 555       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 556       ISA_MICROMIPS32R6;
 557   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 558       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 559       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 560       ISA_MICROMIPS32R6;
 561   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 562       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 563       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 564       ISA_MICROMIPS32R6;
 565   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 566       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 567       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 568       ISA_MICROMIPS32R6;
 569 }
 570
 571 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 572                              RegisterOperand SrcRC, InstrItinClass Itin,
 573                              SDPatternOperator OpNode = null_frag>
 574     : HARDFLOAT, NeverHasSideEffects {
 575   dag OutOperandList = (outs DstRC:$ft);
 576   dag InOperandList  = (ins SrcRC:$fs);
 577   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 578   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 579   InstrItinClass Itinerary = Itin;
 580   Format Form = FrmFR;
 581   list<Predicate> EncodingPredicates = [HasStdEnc];
 582 }
 583
 584 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 585                                                 II_ABS, fabs>;
 586 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 587                                                 II_ABS, fabs>;
 588 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 589                                                     FGR32Opnd, II_FLOOR>;
 590 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 591                                                     FGR64Opnd, II_FLOOR>;
 592 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 593                                                     FGR32Opnd, II_FLOOR>;
 594 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 595                                                     AFGR64Opnd, II_FLOOR>;
 596 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 597                                                    FGR32Opnd, II_CEIL>;
 598 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 599                                                    FGR64Opnd, II_CEIL>;
 600 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 601                                                    FGR32Opnd, II_CEIL>;
 602 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 603                                                    AFGR64Opnd, II_CEIL>;
 604 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 605                                                     FGR32Opnd, II_TRUNC>;
 606 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 607                                                     FGR64Opnd, II_TRUNC>;
 608 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 609                                                     FGR32Opnd, II_TRUNC>;
 610 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 611                                                     AFGR64Opnd, II_TRUNC>;
 612 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 613                                                  II_SQRT_S, fsqrt>;
 614 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 615                                                  II_SQRT_D, fsqrt>;
 616 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 617                                                   FGR32Opnd, II_TRUNC>;
 618 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 619                                                   AFGR64Opnd, II_TRUNC>;
 620
 621 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 622     : Store<opstr, RO>, MMR6Arch<opstr> {
 623   let DecoderMethod = "DecodeMemMMImm16";
 624 }
 625 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 626
 627 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 628     : MMR6Arch<instr_asm>, MipsR6Inst {
 629   dag OutOperandList = (outs);
 630   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 631   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 632   string DecoderMethod = "DecodeStoreEvaOpMM";
 633   bit mayStore = 1;
 634 }
 635 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 636 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 637 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 638 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 639
 640 //===----------------------------------------------------------------------===//
 641 //
 642 // Instruction Definitions
 643 //
 644 //===----------------------------------------------------------------------===//
 645
 646 let DecoderNamespace = "MicroMipsR6" in {
 647 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 648 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 649 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 650 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 651                    ISA_MICROMIPS32R6;
 652 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 653                   ISA_MICROMIPS32R6;
 654 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 655 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 656 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 657 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 658 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 659 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 660 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 661 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 662 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 663                    ISA_MICROMIPS32R6;
 664 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 665                    ISA_MICROMIPS32R6;
 666 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 667                    ISA_MICROMIPS32R6;
 668 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 669                    ISA_MICROMIPS32R6;
 670 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 671                    ISA_MICROMIPS32R6;
 672 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 673                    ISA_MICROMIPS32R6;
 674 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 675                    ISA_MICROMIPS32R6;
 676 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 677                    ISA_MICROMIPS32R6;
 678 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 679                    ISA_MICROMIPS32R6;
 680 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 681 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 682 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 683 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 684 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 685 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 686 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 687 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 688 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 689 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 690                   ISA_MICROMIPS32R6;
 691 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 692 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 693 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 694 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 695 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 696 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 697 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 698 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 699 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 700 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 701 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 702 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 703 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 704 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 705 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 706 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 707 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 708                   ISA_MICROMIPS32R6;
 709 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
 710                   ISA_MICROMIPS32R6;
 711 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 712 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 713 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 714 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 715 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 716 let DecoderMethod = "DecodeMemMMImm16" in {
 717   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
 718 }
 719 let DecoderMethod = "DecodeMemMMImm9" in {
 720   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
 721 }
 722 /// Floating Point Instructions
 723 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
 724                   ISA_MICROMIPS32R6;
 725 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
 726                   ISA_MICROMIPS32R6;
 727 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
 728                   ISA_MICROMIPS32R6;
 729 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
 730                   ISA_MICROMIPS32R6;
 731 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
 732                   ISA_MICROMIPS32R6;
 733 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
 734                   ISA_MICROMIPS32R6;
 735 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
 736                   ISA_MICROMIPS32R6;
 737 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
 738                   ISA_MICROMIPS32R6;
 739 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
 740                    ISA_MICROMIPS32R6;
 741 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
 742                    ISA_MICROMIPS32R6;
 743 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
 744                    ISA_MICROMIPS32R6;
 745 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
 746                    ISA_MICROMIPS32R6;
 747 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
 748                   ISA_MICROMIPS32R6;
 749 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
 750                   ISA_MICROMIPS32R6;
 751 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
 752                   ISA_MICROMIPS32R6;
 753 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
 754                   ISA_MICROMIPS32R6;
 755 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
 756 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
 757 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
 758 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
 759 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
 760                   ISA_MICROMIPS32R6;
 761 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
 762                   ISA_MICROMIPS32R6;
 763 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
 764                   ISA_MICROMIPS32R6;
 765 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
 766                   ISA_MICROMIPS32R6;
 767 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
 768                    ISA_MICROMIPS32R6;
 769 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
 770                    ISA_MICROMIPS32R6;
 771 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
 772                    ISA_MICROMIPS32R6;
 773 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
 774                    ISA_MICROMIPS32R6;
 775 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
 776                    ISA_MICROMIPS32R6;
 777 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
 778                    ISA_MICROMIPS32R6;
 779 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
 780                    ISA_MICROMIPS32R6;
 781 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
 782                    ISA_MICROMIPS32R6;
 783 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
 784                    ISA_MICROMIPS32R6;
 785 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
 786                    ISA_MICROMIPS32R6;
 787 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
 788 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
 789 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
 790 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
 791 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
 792                      ISA_MICROMIPS32R6;
 793 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
 794                      ISA_MICROMIPS32R6;
 795 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
 796                      ISA_MICROMIPS32R6;
 797 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
 798                      ISA_MICROMIPS32R6;
 799 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
 800                     ISA_MICROMIPS32R6;
 801 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
 802                     ISA_MICROMIPS32R6;
 803 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
 804                     ISA_MICROMIPS32R6;
 805 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
 806                     ISA_MICROMIPS32R6;
 807 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
 808                      ISA_MICROMIPS32R6;
 809 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
 810                      ISA_MICROMIPS32R6;
 811 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
 812                      ISA_MICROMIPS32R6;
 813 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
 814                      ISA_MICROMIPS32R6;
 815 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
 816                   ISA_MICROMIPS32R6;
 817 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
 818                   ISA_MICROMIPS32R6;
 819 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
 820                    ISA_MICROMIPS32R6;
 821 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
 822                    ISA_MICROMIPS32R6;
 823 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 824 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 825 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
 826 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
 827 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
 828 }
 829
 830 //===----------------------------------------------------------------------===//
 831 //
 832 // MicroMips instruction aliases
 833 //
 834 //===----------------------------------------------------------------------===//
 835
 836 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 837 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
 838 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
 839                                       !strconcat("b", "\t$offset")>,
 840                     MicroMipsR6Inst16;