lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 //
  16 // Instruction Encodings
  17 //
  18 //===----------------------------------------------------------------------===//
  19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  26 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  28 class AUI_MMR6_ENC : AUI_FM_MMR6;
  29 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  31 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  32 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  33 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  34 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  35 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  36 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  37 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  38 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  39 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  40 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  41 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  42 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  43 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  44 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  45 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  46 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  47 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  48 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  49 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  50 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  51 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  52 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  53 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  54 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  55 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  56 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  57 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  58 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  59 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  60 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  61 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  62 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  63 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  64 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  65 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  66 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  67 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  68 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  69 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  70 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  71 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
  72 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
  73
  74 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
  75                                   RegisterOperand GPROpnd>
  76     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
  77   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
  78   dag OutOperandList = (outs);
  79   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
  80   list<Register> Defs = [AT];
  81 }
  82
  83 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
  84                                                       GPR32Opnd> {
  85   list<Register> Defs = [RA];
  86 }
  87
  88 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
  89                                                       GPR32Opnd> {
  90   list<Register> Defs = [RA];
  91 }
  92
  93 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
  94                                                       GPR32Opnd> {
  95   list<Register> Defs = [RA];
  96 }
  97
  98 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
  99                                                       GPR32Opnd> {
 100   list<Register> Defs = [RA];
 101 }
 102
 103 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 104                                                       GPR32Opnd> {
 105   list<Register> Defs = [RA];
 106 }
 107
 108 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 109                                                       GPR32Opnd> {
 110   list<Register> Defs = [RA];
 111 }
 112
 113 /// Floating Point Instructions
 114 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 115 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 116 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 117 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 118 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 119 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 120 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 121 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 122 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 123 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 124 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 125 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 126 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 127 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 128 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 129 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 130 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 131 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 132 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 133 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 134 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 135 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 136 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 137 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 138
 139 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 140 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 141 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 142 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 143 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 144 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 145 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 146 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 147 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 148 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 149
 150 //===----------------------------------------------------------------------===//
 151 //
 152 // Operand Definitions
 153 //
 154 //===----------------------------------------------------------------------===//
 155
 156 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
 157   let Name = "MemOffsetSimm9GPR";
 158   let SuperClasses = [MipsMemAsmOperand];
 159   let RenderMethod = "addMemOperands";
 160   let ParserMethod = "parseMemOperand";
 161   let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
 162 }
 163
 164 def mem_simm9gpr : mem_generic {
 165   let MIOperandInfo = (ops ptr_rc, simm9);
 166   let EncoderMethod = "getMemEncoding";
 167   let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
 168 }
 169
 170 //===----------------------------------------------------------------------===//
 171 //
 172 // Instruction Descriptions
 173 //
 174 //===----------------------------------------------------------------------===//
 175
 176 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 177 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 178 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 179 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 180 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 181 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 182 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 183
 184 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 185     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 186   dag InOperandList = (ins opnd:$offset);
 187   dag OutOperandList = (outs);
 188   string AsmString = !strconcat(instr_asm, "\t$offset");
 189   bit isBarrier = 1;
 190 }
 191
 192 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
 193   bit isCall = 1;
 194   list<Register> Defs = [RA];
 195 }
 196 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 197 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 198 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 199
 200 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 201     : MMR6Arch<instr_asm> {
 202   dag OutOperandList = (outs GPROpnd:$rd);
 203   dag InOperandList = (ins GPROpnd:$rt);
 204   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 205   list<dag> Pattern = [];
 206 }
 207
 208 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 209
 210 class BRK_MMR6_DESC : BRK_FT<"break">;
 211
 212 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 213                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 214   dag OutOperandList = (outs);
 215   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 216   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 217   list<dag> Pattern = [];
 218   string DecoderMethod = "DecodeCacheOpMM";
 219 }
 220
 221 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 222 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 223
 224 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 225     : MMR6Arch<instr_asm> {
 226   dag OutOperandList = (outs GPROpnd:$rt);
 227   dag InOperandList = (ins GPROpnd:$rs);
 228   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 229 }
 230
 231 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 232 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 233
 234 class EHB_MMR6_DESC : Barrier<"ehb">;
 235 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 236
 237 class ERET_MMR6_DESC : ER_FT<"eret">;
 238 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 239
 240 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 241                                      RegisterOperand GPROpnd>
 242     : MMR6Arch<opstr> {
 243   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 244   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 245   list<dag> Pattern = [];
 246   bit isTerminator = 1;
 247   bit hasDelaySlot = 0;
 248 }
 249
 250 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 251                                                        GPR32Opnd> {
 252   bit isCall = 1;
 253   list<Register> Defs = [RA];
 254 }
 255
 256 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 257                                                      GPR32Opnd> {
 258   bit isBarrier = 1;
 259   list<Register> Defs = [AT];
 260 }
 261
 262 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 263                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 264   dag OutOperandList = (outs GPROpnd:$rd);
 265   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 266   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 267   list<dag> Pattern = [];
 268 }
 269
 270 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 271
 272 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 273     : MMR6Arch<instr_asm> {
 274   dag OutOperandList = (outs GPROpnd:$rt);
 275   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 276   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 277   list<dag> Pattern = [];
 278 }
 279
 280 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 281
 282 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 283 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 284 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 285     : MMR6Arch<instr_asm> {
 286   dag OutOperandList = (outs GPROpnd:$rt);
 287   dag InOperandList = (ins simm16:$imm);
 288   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 289   list<dag> Pattern = [];
 290 }
 291
 292 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 293 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 294
 295 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 296                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 297   dag OutOperandList = (outs GPROpnd:$rd);
 298   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 299   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 300   list<dag> Pattern = [];
 301 }
 302
 303 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
 304
 305 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 306                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 307   dag OutOperandList = (outs GPROpnd:$rt);
 308   dag InOperandList = (ins ImmOpnd:$imm);
 309   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 310   list<dag> Pattern = [];
 311 }
 312
 313 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 314 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 315
 316 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 317     : MMR6Arch<instr_asm> {
 318   dag OutOperandList = (outs GPROpnd:$rd);
 319   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 320   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 321   list<dag> Pattern = [];
 322 }
 323
 324 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 325 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 326 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 327 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 328 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 329 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 330 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 331 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 332 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 333 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 334 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 335 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 336 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 337 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 338
 339 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 340                   SDPatternOperator OpNode = null_frag,
 341                   InstrItinClass Itin = NoItinerary,
 342                   ComplexPattern Addr = addr> :
 343   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 344          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 345   let DecoderMethod = "DecodeMem";
 346   let mayStore = 1;
 347 }
 348 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 349 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
 350
 351 /// Floating Point Instructions
 352 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 353                             InstrItinClass Itin, bit isComm,
 354                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 355   dag OutOperandList = (outs RC:$fd);
 356   dag InOperandList = (ins RC:$ft, RC:$fs);
 357   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 358   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 359   InstrItinClass Itinerary = Itin;
 360   bit isCommutable = isComm;
 361 }
 362 class FADD_S_MMR6_DESC
 363   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 364 class FADD_D_MMR6_DESC
 365   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 366 class FSUB_S_MMR6_DESC
 367   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 368 class FSUB_D_MMR6_DESC
 369   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 370 class FMUL_S_MMR6_DESC
 371   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 372 class FMUL_D_MMR6_DESC
 373   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 374 class FDIV_S_MMR6_DESC
 375   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 376 class FDIV_D_MMR6_DESC
 377   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 378 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 379 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 380 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 381 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 382
 383 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 384                                RegisterOperand SrcRC, InstrItinClass Itin,
 385                                SDPatternOperator OpNode = null_frag>
 386                                : HARDFLOAT, NeverHasSideEffects {
 387   dag OutOperandList = (outs DstRC:$ft);
 388   dag InOperandList = (ins SrcRC:$fs);
 389   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 390   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 391   InstrItinClass Itinerary = Itin;
 392   Format Form = FrmFR;
 393 }
 394 class FMOV_S_MMR6_DESC
 395   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 396 class FMOV_D_MMR6_DESC
 397   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 398 class FNEG_S_MMR6_DESC
 399   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 400 class FNEG_D_MMR6_DESC
 401   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 402
 403 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 404 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 405 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 406 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 407
 408 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 409 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 410 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 411 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 412
 413 class CVT_MMR6_DESC_BASE<
 414     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 415     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 416     : HARDFLOAT, NeverHasSideEffects {
 417   dag OutOperandList = (outs DstRC:$ft);
 418   dag InOperandList = (ins SrcRC:$fs);
 419   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 420   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 421   InstrItinClass Itinerary = Itin;
 422   Format Form = FrmFR;
 423 }
 424
 425 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 426                                              II_CVT>;
 427 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 428                                              II_CVT>;
 429 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 430                                              II_CVT>;
 431 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 432                                              II_CVT>;
 433 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 434                                              II_CVT>;
 435 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 436                                              II_CVT>;
 437 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 438                                              II_CVT>, FGR_64;
 439 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 440                                              II_CVT>;
 441 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 442                                              II_CVT>;
 443 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 444                                              II_CVT>, FGR_64;
 445
 446 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 447                        RegisterOperand FGROpnd> {
 448   def CMP_AF_#NAME : POOL32F_CMP_FM<
 449       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 450       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 451       ISA_MICROMIPS32R6;
 452   def CMP_UN_#NAME : POOL32F_CMP_FM<
 453       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 454       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 455       ISA_MICROMIPS32R6;
 456   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 457       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 458       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 459       ISA_MICROMIPS32R6;
 460   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 461       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 462       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 463       ISA_MICROMIPS32R6;
 464   def CMP_LT_#NAME : POOL32F_CMP_FM<
 465       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 466       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 467       ISA_MICROMIPS32R6;
 468   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 469       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 470       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 471       ISA_MICROMIPS32R6;
 472   def CMP_LE_#NAME : POOL32F_CMP_FM<
 473       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 474       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 475       ISA_MICROMIPS32R6;
 476   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 477       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 478       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 479       ISA_MICROMIPS32R6;
 480   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 481       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 482       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 483       ISA_MICROMIPS32R6;
 484   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 485       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 486       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 487       ISA_MICROMIPS32R6;
 488   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 489       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 490       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 491       ISA_MICROMIPS32R6;
 492   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 493       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 494       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 495       ISA_MICROMIPS32R6;
 496   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 497       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 498       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 499       ISA_MICROMIPS32R6;
 500   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 501       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 502       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 503       ISA_MICROMIPS32R6;
 504   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 505       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 506       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 507       ISA_MICROMIPS32R6;
 508   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 509       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 510       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 511       ISA_MICROMIPS32R6;
 512 }
 513
 514 //===----------------------------------------------------------------------===//
 515 //
 516 // Instruction Definitions
 517 //
 518 //===----------------------------------------------------------------------===//
 519
 520 let DecoderNamespace = "MicroMipsR6" in {
 521 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 522 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 523 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 524 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 525                    ISA_MICROMIPS32R6;
 526 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 527                   ISA_MICROMIPS32R6;
 528 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 529 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 530 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 531 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 532 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 533 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 534 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 535 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 536                    ISA_MICROMIPS32R6;
 537 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 538                    ISA_MICROMIPS32R6;
 539 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 540                    ISA_MICROMIPS32R6;
 541 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 542                    ISA_MICROMIPS32R6;
 543 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 544                    ISA_MICROMIPS32R6;
 545 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 546                    ISA_MICROMIPS32R6;
 547 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 548                    ISA_MICROMIPS32R6;
 549 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 550 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 551 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 552 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 553 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 554 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 555 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 556 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 557 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 558 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 559                   ISA_MICROMIPS32R6;
 560 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 561 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 562 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 563 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 564 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 565 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 566 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 567 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 568 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 569 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 570 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 571 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 572 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 573 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 574 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 575 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 576 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 577                   ISA_MICROMIPS32R6;
 578 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
 579                   ISA_MICROMIPS32R6;
 580 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 581 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 582 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 583 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 584 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 585 let DecoderMethod = "DecodeMemMMImm16" in {
 586   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
 587 }
 588 let DecoderMethod = "DecodeMemMMImm9" in {
 589   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
 590 }
 591 /// Floating Point Instructions
 592 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
 593                   ISA_MICROMIPS32R6;
 594 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
 595                   ISA_MICROMIPS32R6;
 596 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
 597                   ISA_MICROMIPS32R6;
 598 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
 599                   ISA_MICROMIPS32R6;
 600 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
 601                   ISA_MICROMIPS32R6;
 602 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
 603                   ISA_MICROMIPS32R6;
 604 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
 605                   ISA_MICROMIPS32R6;
 606 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
 607                   ISA_MICROMIPS32R6;
 608 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
 609                    ISA_MICROMIPS32R6;
 610 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
 611                    ISA_MICROMIPS32R6;
 612 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
 613                    ISA_MICROMIPS32R6;
 614 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
 615                    ISA_MICROMIPS32R6;
 616 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
 617                   ISA_MICROMIPS32R6;
 618 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
 619                   ISA_MICROMIPS32R6;
 620 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
 621                   ISA_MICROMIPS32R6;
 622 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
 623                   ISA_MICROMIPS32R6;
 624 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
 625 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
 626 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
 627 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
 628 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
 629                   ISA_MICROMIPS32R6;
 630 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
 631                   ISA_MICROMIPS32R6;
 632 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
 633                   ISA_MICROMIPS32R6;
 634 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
 635                   ISA_MICROMIPS32R6;
 636 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
 637                    ISA_MICROMIPS32R6;
 638 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
 639                    ISA_MICROMIPS32R6;
 640 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
 641                    ISA_MICROMIPS32R6;
 642 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
 643                    ISA_MICROMIPS32R6;
 644 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
 645                    ISA_MICROMIPS32R6;
 646 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
 647                    ISA_MICROMIPS32R6;
 648 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
 649                    ISA_MICROMIPS32R6;
 650 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
 651                    ISA_MICROMIPS32R6;
 652 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
 653                    ISA_MICROMIPS32R6;
 654 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
 655                    ISA_MICROMIPS32R6;
 656 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
 657 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
 658 }
 659
 660 //===----------------------------------------------------------------------===//
 661 //
 662 // MicroMips instruction aliases
 663 //
 664 //===----------------------------------------------------------------------===//
 665
 666 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 667 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;