lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

   1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides Mips specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "InstPrinter/MipsInstPrinter.h"
  15 #include "MipsELFStreamer.h"
  16 #include "MipsMCAsmInfo.h"
  17 #include "MipsMCNaCl.h"
  18 #include "MipsMCTargetDesc.h"
  19 #include "MipsTargetStreamer.h"
  20 #include "llvm/ADT/Triple.h"
  21 #include "llvm/MC/MCCodeGenInfo.h"
  22 #include "llvm/MC/MCELFStreamer.h"
  23 #include "llvm/MC/MCInstrInfo.h"
  24 #include "llvm/MC/MCRegisterInfo.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/MC/MCSymbol.h"
  27 #include "llvm/MC/MachineLocation.h"
  28 #include "llvm/Support/CommandLine.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/FormattedStream.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32
  33 using namespace llvm;
  34
  35 #define GET_INSTRINFO_MC_DESC
  36 #include "MipsGenInstrInfo.inc"
  37
  38 #define GET_SUBTARGETINFO_MC_DESC
  39 #include "MipsGenSubtargetInfo.inc"
  40
  41 #define GET_REGINFO_MC_DESC
  42 #include "MipsGenRegisterInfo.inc"
  43
  44 /// Select the Mips CPU for the given triple and cpu name.
  45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
  46 StringRef MIPS_MC::selectMipsCPU(StringRef TT, StringRef CPU) {
  47   if (CPU.empty() || CPU == "generic") {
  48     Triple TheTriple(TT);
  49     if (TheTriple.getArch() == Triple::mips ||
  50         TheTriple.getArch() == Triple::mipsel)
  51       CPU = "mips32";
  52     else
  53       CPU = "mips64";
  54   }
  55   return CPU;
  56 }
  57
  58 static MCInstrInfo *createMipsMCInstrInfo() {
  59   MCInstrInfo *X = new MCInstrInfo();
  60   InitMipsMCInstrInfo(X);
  61   return X;
  62 }
  63
  64 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
  65   MCRegisterInfo *X = new MCRegisterInfo();
  66   InitMipsMCRegisterInfo(X, Mips::RA);
  67   return X;
  68 }
  69
  70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
  71                                                   StringRef FS) {
  72   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
  73   MCSubtargetInfo *X = new MCSubtargetInfo();
  74   InitMipsMCSubtargetInfo(X, TT, CPU, FS);
  75   return X;
  76 }
  77
  78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
  79                                       const Triple &TT) {
  80   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
  81
  82   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
  83   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
  84   MAI->addInitialFrameState(Inst);
  85
  86   return MAI;
  87 }
  88
  89 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
  90                                               CodeModel::Model CM,
  91                                               CodeGenOpt::Level OL) {
  92   MCCodeGenInfo *X = new MCCodeGenInfo();
  93   if (CM == CodeModel::JITDefault)
  94     RM = Reloc::Static;
  95   else if (RM == Reloc::Default)
  96     RM = Reloc::PIC_;
  97   X->initMCCodeGenInfo(RM, CM, OL);
  98   return X;
  99 }
 100
 101 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
 102                                               unsigned SyntaxVariant,
 103                                               const MCAsmInfo &MAI,
 104                                               const MCInstrInfo &MII,
 105                                               const MCRegisterInfo &MRI) {
 106   return new MipsInstPrinter(MAI, MII, MRI);
 107 }
 108
 109 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
 110                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
 111                                     MCCodeEmitter *Emitter, bool RelaxAll) {
 112   MCStreamer *S;
 113   if (!T.isOSNaCl())
 114     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
 115   else
 116     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
 117   return S;
 118 }
 119
 120 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
 121                                                      formatted_raw_ostream &OS,
 122                                                      MCInstPrinter *InstPrint,
 123                                                      bool isVerboseAsm) {
 124   return new MipsTargetAsmStreamer(S, OS);
 125 }
 126
 127 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
 128   return new MipsTargetStreamer(S);
 129 }
 130
 131 static MCTargetStreamer *
 132 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
 133   return new MipsTargetELFStreamer(S, STI);
 134 }
 135
 136 extern "C" void LLVMInitializeMipsTargetMC() {
 137   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
 138                     &TheMips64elTarget}) {
 139     // Register the MC asm info.
 140     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
 141
 142     // Register the MC codegen info.
 143     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
 144
 145     // Register the MC instruction info.
 146     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
 147
 148     // Register the MC register info.
 149     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
 150
 151     // Register the elf streamer.
 152     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
 153
 154     // Register the asm target streamer.
 155     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
 156
 157     TargetRegistry::RegisterNullTargetStreamer(*T,
 158                                                createMipsNullTargetStreamer);
 159
 160     // Register the MC subtarget info.
 161     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
 162
 163     // Register the MCInstPrinter.
 164     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
 165
 166     TargetRegistry::RegisterObjectTargetStreamer(
 167         *T, createMipsObjectTargetStreamer);
 168   }
 169
 170   // Register the MC Code Emitter
 171   for (Target *T : {&TheMipsTarget, &TheMips64Target})
 172     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
 173
 174   for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
 175     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
 176
 177   // Register the asm backend.
 178   TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
 179                                        createMipsAsmBackendEB32);
 180   TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
 181                                        createMipsAsmBackendEL32);
 182   TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
 183                                        createMipsAsmBackendEB64);
 184   TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
 185                                        createMipsAsmBackendEL64);
 186
 187 }