lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disasembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsN64(STI.getFeatureBits() & Mips::FeatureN64),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isN64() const { return IsN64; }
  45
  46 private:
  47   bool IsN64;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 118                                            unsigned Insn,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 123                                             unsigned RegNo,
 124                                             uint64_t Address,
 125                                             const void *Decoder);
 126
 127 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 128                                              unsigned RegNo,
 129                                              uint64_t Address,
 130                                              const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 138                                            unsigned RegNo,
 139                                            uint64_t Address,
 140                                            const void *Decoder);
 141
 142 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 148                                              uint64_t Address,
 149                                              const void *Decoder);
 150
 151 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 152                                               unsigned Insn,
 153                                               uint64_t Address,
 154                                               const void *Decoder);
 155
 156 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 157                                               unsigned RegNo,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 162                                                 unsigned RegNo,
 163                                                 uint64_t Address,
 164                                                 const void *Decoder);
 165
 166 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 202                                             unsigned RegNo,
 203                                             uint64_t Address,
 204                                             const void *Decoder);
 205
 206 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 207                                        unsigned Offset,
 208                                        uint64_t Address,
 209                                        const void *Decoder);
 210
 211 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 212                                      unsigned Insn,
 213                                      uint64_t Address,
 214                                      const void *Decoder);
 215
 216 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 217                                          unsigned Offset,
 218                                          uint64_t Address,
 219                                          const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 227 // shifted left by 1 bit.
 228 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 229                                          unsigned Offset,
 230                                          uint64_t Address,
 231                                          const void *Decoder);
 232
 233 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 234 // shifted left by 1 bit.
 235 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 236                                        unsigned Insn,
 237                                        uint64_t Address,
 238                                        const void *Decoder);
 239
 240 static DecodeStatus DecodeMem(MCInst &Inst,
 241                               unsigned Insn,
 242                               uint64_t Address,
 243                               const void *Decoder);
 244
 245 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 246                               unsigned Insn,
 247                               uint64_t Address,
 248                               const void *Decoder);
 249
 250 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 251                                     uint64_t Address, const void *Decoder);
 252
 253 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 254                                      unsigned Insn,
 255                                      uint64_t Address,
 256                                      const void *Decoder);
 257
 258 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 259                                      unsigned Insn,
 260                                      uint64_t Address,
 261                                      const void *Decoder);
 262
 263 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 264                                uint64_t Address,
 265                                const void *Decoder);
 266
 267 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 268                                uint64_t Address,
 269                                const void *Decoder);
 270
 271 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 272                                uint64_t Address,
 273                                const void *Decoder);
 274
 275 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 276                                        unsigned Insn,
 277                                        uint64_t Address,
 278                                        const void *Decoder);
 279
 280 static DecodeStatus DecodeSimm16(MCInst &Inst,
 281                                  unsigned Insn,
 282                                  uint64_t Address,
 283                                  const void *Decoder);
 284
 285 // Decode the immediate field of an LSA instruction which
 286 // is off by one.
 287 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 288                                  unsigned Insn,
 289                                  uint64_t Address,
 290                                  const void *Decoder);
 291
 292 static DecodeStatus DecodeInsSize(MCInst &Inst,
 293                                   unsigned Insn,
 294                                   uint64_t Address,
 295                                   const void *Decoder);
 296
 297 static DecodeStatus DecodeExtSize(MCInst &Inst,
 298                                   unsigned Insn,
 299                                   uint64_t Address,
 300                                   const void *Decoder);
 301
 302 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 303                                      uint64_t Address, const void *Decoder);
 304
 305 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 306                                      uint64_t Address, const void *Decoder);
 307
 308 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 309 /// handle.
 310 template <typename InsnType>
 311 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 312                                    const void *Decoder);
 313
 314 template <typename InsnType>
 315 static DecodeStatus
 316 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 317                       const void *Decoder);
 318
 319 template <typename InsnType>
 320 static DecodeStatus
 321 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 322                        const void *Decoder);
 323
 324 template <typename InsnType>
 325 static DecodeStatus
 326 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 327                        const void *Decoder);
 328
 329 template <typename InsnType>
 330 static DecodeStatus
 331 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 332                        const void *Decoder);
 333
 334 template <typename InsnType>
 335 static DecodeStatus
 336 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 337                       const void *Decoder);
 338
 339 template <typename InsnType>
 340 static DecodeStatus
 341 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 342                        const void *Decoder);
 343
 344 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 345                                          uint64_t Address,
 346                                          const void *Decoder);
 347
 348 namespace llvm {
 349 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 350               TheMips64elTarget;
 351 }
 352
 353 static MCDisassembler *createMipsDisassembler(
 354                        const Target &T,
 355                        const MCSubtargetInfo &STI,
 356                        MCContext &Ctx) {
 357   return new MipsDisassembler(STI, Ctx, true);
 358 }
 359
 360 static MCDisassembler *createMipselDisassembler(
 361                        const Target &T,
 362                        const MCSubtargetInfo &STI,
 363                        MCContext &Ctx) {
 364   return new MipsDisassembler(STI, Ctx, false);
 365 }
 366
 367 static MCDisassembler *createMips64Disassembler(
 368                        const Target &T,
 369                        const MCSubtargetInfo &STI,
 370                        MCContext &Ctx) {
 371   return new Mips64Disassembler(STI, Ctx, true);
 372 }
 373
 374 static MCDisassembler *createMips64elDisassembler(
 375                        const Target &T,
 376                        const MCSubtargetInfo &STI,
 377                        MCContext &Ctx) {
 378   return new Mips64Disassembler(STI, Ctx, false);
 379 }
 380
 381 extern "C" void LLVMInitializeMipsDisassembler() {
 382   // Register the disassembler.
 383   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 384                                          createMipsDisassembler);
 385   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 386                                          createMipselDisassembler);
 387   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 388                                          createMips64Disassembler);
 389   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 390                                          createMips64elDisassembler);
 391 }
 392
 393 #include "MipsGenDisassemblerTables.inc"
 394
 395 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 396   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 397   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 398   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 399 }
 400
 401 template <typename InsnType>
 402 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 403                                    const void *Decoder) {
 404   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 405   // The size of the n field depends on the element size
 406   // The register class also depends on this.
 407   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 408   unsigned NSize = 0;
 409   DecodeFN RegDecoder = nullptr;
 410   if ((tmp & 0x18) == 0x00) { // INSVE_B
 411     NSize = 4;
 412     RegDecoder = DecodeMSA128BRegisterClass;
 413   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 414     NSize = 3;
 415     RegDecoder = DecodeMSA128HRegisterClass;
 416   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 417     NSize = 2;
 418     RegDecoder = DecodeMSA128WRegisterClass;
 419   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 420     NSize = 1;
 421     RegDecoder = DecodeMSA128DRegisterClass;
 422   } else
 423     llvm_unreachable("Invalid encoding");
 424
 425   assert(NSize != 0 && RegDecoder != nullptr);
 426
 427   // $wd
 428   tmp = fieldFromInstruction(insn, 6, 5);
 429   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 430     return MCDisassembler::Fail;
 431   // $wd_in
 432   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 433     return MCDisassembler::Fail;
 434   // $n
 435   tmp = fieldFromInstruction(insn, 16, NSize);
 436   MI.addOperand(MCOperand::CreateImm(tmp));
 437   // $ws
 438   tmp = fieldFromInstruction(insn, 11, 5);
 439   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 440     return MCDisassembler::Fail;
 441   // $n2
 442   MI.addOperand(MCOperand::CreateImm(0));
 443
 444   return MCDisassembler::Success;
 445 }
 446
 447 template <typename InsnType>
 448 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 449                                           uint64_t Address,
 450                                           const void *Decoder) {
 451   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 452   // (otherwise we would have matched the ADDI instruction from the earlier
 453   // ISA's instead).
 454   //
 455   // We have:
 456   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 457   //      BOVC if rs >= rt
 458   //      BEQZALC if rs == 0 && rt != 0
 459   //      BEQC if rs < rt && rs != 0
 460
 461   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 462   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 463   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 464   bool HasRs = false;
 465
 466   if (Rs >= Rt) {
 467     MI.setOpcode(Mips::BOVC);
 468     HasRs = true;
 469   } else if (Rs != 0 && Rs < Rt) {
 470     MI.setOpcode(Mips::BEQC);
 471     HasRs = true;
 472   } else
 473     MI.setOpcode(Mips::BEQZALC);
 474
 475   if (HasRs)
 476     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 477                                        Rs)));
 478
 479   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 480                                      Rt)));
 481   MI.addOperand(MCOperand::CreateImm(Imm));
 482
 483   return MCDisassembler::Success;
 484 }
 485
 486 template <typename InsnType>
 487 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 488                                            uint64_t Address,
 489                                            const void *Decoder) {
 490   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 491   // (otherwise we would have matched the ADDI instruction from the earlier
 492   // ISA's instead).
 493   //
 494   // We have:
 495   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 496   //      BNVC if rs >= rt
 497   //      BNEZALC if rs == 0 && rt != 0
 498   //      BNEC if rs < rt && rs != 0
 499
 500   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 501   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 502   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 503   bool HasRs = false;
 504
 505   if (Rs >= Rt) {
 506     MI.setOpcode(Mips::BNVC);
 507     HasRs = true;
 508   } else if (Rs != 0 && Rs < Rt) {
 509     MI.setOpcode(Mips::BNEC);
 510     HasRs = true;
 511   } else
 512     MI.setOpcode(Mips::BNEZALC);
 513
 514   if (HasRs)
 515     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 516                                        Rs)));
 517
 518   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 519                                      Rt)));
 520   MI.addOperand(MCOperand::CreateImm(Imm));
 521
 522   return MCDisassembler::Success;
 523 }
 524
 525 template <typename InsnType>
 526 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 527                                            uint64_t Address,
 528                                            const void *Decoder) {
 529   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 530   // (otherwise we would have matched the BLEZL instruction from the earlier
 531   // ISA's instead).
 532   //
 533   // We have:
 534   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 535   //      Invalid if rs == 0
 536   //      BLEZC   if rs == 0  && rt != 0
 537   //      BGEZC   if rs == rt && rt != 0
 538   //      BGEC    if rs != rt && rs != 0  && rt != 0
 539
 540   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 541   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 542   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 543   bool HasRs = false;
 544
 545   if (Rt == 0)
 546     return MCDisassembler::Fail;
 547   else if (Rs == 0)
 548     MI.setOpcode(Mips::BLEZC);
 549   else if (Rs == Rt)
 550     MI.setOpcode(Mips::BGEZC);
 551   else {
 552     HasRs = true;
 553     MI.setOpcode(Mips::BGEC);
 554   }
 555
 556   if (HasRs)
 557     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 558                                        Rs)));
 559
 560   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 561                                      Rt)));
 562
 563   MI.addOperand(MCOperand::CreateImm(Imm));
 564
 565   return MCDisassembler::Success;
 566 }
 567
 568 template <typename InsnType>
 569 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 570                                            uint64_t Address,
 571                                            const void *Decoder) {
 572   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 573   // (otherwise we would have matched the BGTZL instruction from the earlier
 574   // ISA's instead).
 575   //
 576   // We have:
 577   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 578   //      Invalid if rs == 0
 579   //      BGTZC   if rs == 0  && rt != 0
 580   //      BLTZC   if rs == rt && rt != 0
 581   //      BLTC    if rs != rt && rs != 0  && rt != 0
 582
 583   bool HasRs = false;
 584
 585   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 586   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 587   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 588
 589   if (Rt == 0)
 590     return MCDisassembler::Fail;
 591   else if (Rs == 0)
 592     MI.setOpcode(Mips::BGTZC);
 593   else if (Rs == Rt)
 594     MI.setOpcode(Mips::BLTZC);
 595   else {
 596     MI.setOpcode(Mips::BLTC);
 597     HasRs = true;
 598   }
 599
 600   if (HasRs)
 601     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 602                                               Rs)));
 603
 604   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 605                                      Rt)));
 606
 607   MI.addOperand(MCOperand::CreateImm(Imm));
 608
 609   return MCDisassembler::Success;
 610 }
 611
 612 template <typename InsnType>
 613 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 614                                           uint64_t Address,
 615                                           const void *Decoder) {
 616   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 617   // (otherwise we would have matched the BGTZ instruction from the earlier
 618   // ISA's instead).
 619   //
 620   // We have:
 621   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 622   //      BGTZ    if rt == 0
 623   //      BGTZALC if rs == 0 && rt != 0
 624   //      BLTZALC if rs != 0 && rs == rt
 625   //      BLTUC   if rs != 0 && rs != rt
 626
 627   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 628   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 629   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 630   bool HasRs = false;
 631   bool HasRt = false;
 632
 633   if (Rt == 0) {
 634     MI.setOpcode(Mips::BGTZ);
 635     HasRs = true;
 636   } else if (Rs == 0) {
 637     MI.setOpcode(Mips::BGTZALC);
 638     HasRt = true;
 639   } else if (Rs == Rt) {
 640     MI.setOpcode(Mips::BLTZALC);
 641     HasRs = true;
 642   } else {
 643     MI.setOpcode(Mips::BLTUC);
 644     HasRs = true;
 645     HasRt = true;
 646   }
 647
 648   if (HasRs)
 649     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 650                                        Rs)));
 651
 652   if (HasRt)
 653     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 654                                        Rt)));
 655
 656   MI.addOperand(MCOperand::CreateImm(Imm));
 657
 658   return MCDisassembler::Success;
 659 }
 660
 661 template <typename InsnType>
 662 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 663                                            uint64_t Address,
 664                                            const void *Decoder) {
 665   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 666   // (otherwise we would have matched the BLEZL instruction from the earlier
 667   // ISA's instead).
 668   //
 669   // We have:
 670   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 671   //      Invalid   if rs == 0
 672   //      BLEZALC   if rs == 0  && rt != 0
 673   //      BGEZALC   if rs == rt && rt != 0
 674   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 675
 676   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 677   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 678   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 679   bool HasRs = false;
 680
 681   if (Rt == 0)
 682     return MCDisassembler::Fail;
 683   else if (Rs == 0)
 684     MI.setOpcode(Mips::BLEZALC);
 685   else if (Rs == Rt)
 686     MI.setOpcode(Mips::BGEZALC);
 687   else {
 688     HasRs = true;
 689     MI.setOpcode(Mips::BGEUC);
 690   }
 691
 692   if (HasRs)
 693     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 694                                        Rs)));
 695   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 696                                      Rt)));
 697
 698   MI.addOperand(MCOperand::CreateImm(Imm));
 699
 700   return MCDisassembler::Success;
 701 }
 702
 703 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 704 /// according to the given endianess.
 705 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 706                                       uint64_t &Size, uint32_t &Insn,
 707                                       bool IsBigEndian) {
 708   // We want to read exactly 2 Bytes of data.
 709   if (Bytes.size() < 2) {
 710     Size = 0;
 711     return MCDisassembler::Fail;
 712   }
 713
 714   if (IsBigEndian) {
 715     Insn = (Bytes[0] << 8) | Bytes[1];
 716   } else {
 717     Insn = (Bytes[1] << 8) | Bytes[0];
 718   }
 719
 720   return MCDisassembler::Success;
 721 }
 722
 723 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 724 /// according to the given endianess
 725 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 726                                       uint64_t &Size, uint32_t &Insn,
 727                                       bool IsBigEndian, bool IsMicroMips) {
 728   // We want to read exactly 4 Bytes of data.
 729   if (Bytes.size() < 4) {
 730     Size = 0;
 731     return MCDisassembler::Fail;
 732   }
 733
 734   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 735   // always precede the low 16 bits in the instruction stream (that is, they
 736   // are placed at lower addresses in the instruction stream).
 737   //
 738   // microMIPS byte ordering:
 739   //   Big-endian:    0 | 1 | 2 | 3
 740   //   Little-endian: 1 | 0 | 3 | 2
 741
 742   if (IsBigEndian) {
 743     // Encoded as a big-endian 32-bit word in the stream.
 744     Insn =
 745         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 746   } else {
 747     if (IsMicroMips) {
 748       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 749              (Bytes[1] << 24);
 750     } else {
 751       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 752              (Bytes[3] << 24);
 753     }
 754   }
 755
 756   return MCDisassembler::Success;
 757 }
 758
 759 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 760                                               ArrayRef<uint8_t> Bytes,
 761                                               uint64_t Address,
 762                                               raw_ostream &VStream,
 763                                               raw_ostream &CStream) const {
 764   uint32_t Insn;
 765   DecodeStatus Result;
 766
 767   if (IsMicroMips) {
 768     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 769
 770     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 771     // Calling the auto-generated decoder function.
 772     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 773                                this, STI);
 774     if (Result != MCDisassembler::Fail) {
 775       Size = 2;
 776       return Result;
 777     }
 778
 779     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 780     if (Result == MCDisassembler::Fail)
 781       return MCDisassembler::Fail;
 782
 783     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 784     // Calling the auto-generated decoder function.
 785     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 786                                this, STI);
 787     if (Result != MCDisassembler::Fail) {
 788       Size = 4;
 789       return Result;
 790     }
 791     return MCDisassembler::Fail;
 792   }
 793
 794   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 795   if (Result == MCDisassembler::Fail)
 796     return MCDisassembler::Fail;
 797
 798   if (hasCOP3()) {
 799     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 800     Result =
 801         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 802     if (Result != MCDisassembler::Fail) {
 803       Size = 4;
 804       return Result;
 805     }
 806   }
 807
 808   if (hasMips32r6() && isGP64()) {
 809     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 810     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 811                                Address, this, STI);
 812     if (Result != MCDisassembler::Fail) {
 813       Size = 4;
 814       return Result;
 815     }
 816   }
 817
 818   if (hasMips32r6()) {
 819     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 820     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 821                                Address, this, STI);
 822     if (Result != MCDisassembler::Fail) {
 823       Size = 4;
 824       return Result;
 825     }
 826   }
 827
 828   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 829   // Calling the auto-generated decoder function.
 830   Result =
 831       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 832   if (Result != MCDisassembler::Fail) {
 833     Size = 4;
 834     return Result;
 835   }
 836
 837   return MCDisassembler::Fail;
 838 }
 839
 840 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 841                                                 ArrayRef<uint8_t> Bytes,
 842                                                 uint64_t Address,
 843                                                 raw_ostream &VStream,
 844                                                 raw_ostream &CStream) const {
 845   uint32_t Insn;
 846
 847   DecodeStatus Result =
 848       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 849   if (Result == MCDisassembler::Fail)
 850     return MCDisassembler::Fail;
 851
 852   // Calling the auto-generated decoder function.
 853   Result =
 854       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 855   if (Result != MCDisassembler::Fail) {
 856     Size = 4;
 857     return Result;
 858   }
 859   // If we fail to decode in Mips64 decoder space we can try in Mips32
 860   Result =
 861       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 862   if (Result != MCDisassembler::Fail) {
 863     Size = 4;
 864     return Result;
 865   }
 866
 867   return MCDisassembler::Fail;
 868 }
 869
 870 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 871                                                  unsigned RegNo,
 872                                                  uint64_t Address,
 873                                                  const void *Decoder) {
 874
 875   return MCDisassembler::Fail;
 876
 877 }
 878
 879 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 880                                              unsigned RegNo,
 881                                              uint64_t Address,
 882                                              const void *Decoder) {
 883
 884   if (RegNo > 31)
 885     return MCDisassembler::Fail;
 886
 887   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 888   Inst.addOperand(MCOperand::CreateReg(Reg));
 889   return MCDisassembler::Success;
 890 }
 891
 892 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 893                                                unsigned RegNo,
 894                                                uint64_t Address,
 895                                                const void *Decoder) {
 896   if (RegNo > 7)
 897     return MCDisassembler::Fail;
 898   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 899   Inst.addOperand(MCOperand::CreateReg(Reg));
 900   return MCDisassembler::Success;
 901 }
 902
 903 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 904                                              unsigned RegNo,
 905                                              uint64_t Address,
 906                                              const void *Decoder) {
 907   if (RegNo > 31)
 908     return MCDisassembler::Fail;
 909   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 910   Inst.addOperand(MCOperand::CreateReg(Reg));
 911   return MCDisassembler::Success;
 912 }
 913
 914 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 915                                            unsigned RegNo,
 916                                            uint64_t Address,
 917                                            const void *Decoder) {
 918   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 919     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 920
 921   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 922 }
 923
 924 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 925                                             unsigned RegNo,
 926                                             uint64_t Address,
 927                                             const void *Decoder) {
 928   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 929 }
 930
 931 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 932                                              unsigned RegNo,
 933                                              uint64_t Address,
 934                                              const void *Decoder) {
 935   if (RegNo > 31)
 936     return MCDisassembler::Fail;
 937
 938   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 939   Inst.addOperand(MCOperand::CreateReg(Reg));
 940   return MCDisassembler::Success;
 941 }
 942
 943 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 944                                              unsigned RegNo,
 945                                              uint64_t Address,
 946                                              const void *Decoder) {
 947   if (RegNo > 31)
 948     return MCDisassembler::Fail;
 949
 950   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 951   Inst.addOperand(MCOperand::CreateReg(Reg));
 952   return MCDisassembler::Success;
 953 }
 954
 955 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 956                                            unsigned RegNo,
 957                                            uint64_t Address,
 958                                            const void *Decoder) {
 959   if (RegNo > 31)
 960     return MCDisassembler::Fail;
 961   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 962   Inst.addOperand(MCOperand::CreateReg(Reg));
 963   return MCDisassembler::Success;
 964 }
 965
 966 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 967                                            unsigned RegNo,
 968                                            uint64_t Address,
 969                                            const void *Decoder) {
 970   if (RegNo > 7)
 971     return MCDisassembler::Fail;
 972   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 973   Inst.addOperand(MCOperand::CreateReg(Reg));
 974   return MCDisassembler::Success;
 975 }
 976
 977 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 978                                              uint64_t Address,
 979                                              const void *Decoder) {
 980   if (RegNo > 31)
 981     return MCDisassembler::Fail;
 982
 983   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 984   Inst.addOperand(MCOperand::CreateReg(Reg));
 985   return MCDisassembler::Success;
 986 }
 987
 988 static DecodeStatus DecodeMem(MCInst &Inst,
 989                               unsigned Insn,
 990                               uint64_t Address,
 991                               const void *Decoder) {
 992   int Offset = SignExtend32<16>(Insn & 0xffff);
 993   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 994   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 995
 996   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 997   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 998
 999   if(Inst.getOpcode() == Mips::SC){
1000     Inst.addOperand(MCOperand::CreateReg(Reg));
1001   }
1002
1003   Inst.addOperand(MCOperand::CreateReg(Reg));
1004   Inst.addOperand(MCOperand::CreateReg(Base));
1005   Inst.addOperand(MCOperand::CreateImm(Offset));
1006
1007   return MCDisassembler::Success;
1008 }
1009
1010 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1011                               unsigned Insn,
1012                               uint64_t Address,
1013                               const void *Decoder) {
1014   int Offset = SignExtend32<16>(Insn & 0xffff);
1015   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1016   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1017
1018   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1019
1020   Inst.addOperand(MCOperand::CreateReg(Base));
1021   Inst.addOperand(MCOperand::CreateImm(Offset));
1022   Inst.addOperand(MCOperand::CreateImm(Hint));
1023
1024   return MCDisassembler::Success;
1025 }
1026
1027 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1028                                     uint64_t Address, const void *Decoder) {
1029   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1030   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1031   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1032
1033   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1034   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1035
1036   Inst.addOperand(MCOperand::CreateReg(Reg));
1037   Inst.addOperand(MCOperand::CreateReg(Base));
1038
1039   // The immediate field of an LD/ST instruction is scaled which means it must
1040   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1041   // data format.
1042   // .b - 1 byte
1043   // .h - 2 bytes
1044   // .w - 4 bytes
1045   // .d - 8 bytes
1046   switch(Inst.getOpcode())
1047   {
1048   default:
1049     assert (0 && "Unexpected instruction");
1050     return MCDisassembler::Fail;
1051     break;
1052   case Mips::LD_B:
1053   case Mips::ST_B:
1054     Inst.addOperand(MCOperand::CreateImm(Offset));
1055     break;
1056   case Mips::LD_H:
1057   case Mips::ST_H:
1058     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1059     break;
1060   case Mips::LD_W:
1061   case Mips::ST_W:
1062     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1063     break;
1064   case Mips::LD_D:
1065   case Mips::ST_D:
1066     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1067     break;
1068   }
1069
1070   return MCDisassembler::Success;
1071 }
1072
1073 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1074                                      unsigned Insn,
1075                                      uint64_t Address,
1076                                      const void *Decoder) {
1077   int Offset = SignExtend32<12>(Insn & 0x0fff);
1078   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1079   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1080
1081   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1082   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1083
1084   switch (Inst.getOpcode()) {
1085   case Mips::SWM32_MM:
1086   case Mips::LWM32_MM:
1087     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1088         == MCDisassembler::Fail)
1089       return MCDisassembler::Fail;
1090     Inst.addOperand(MCOperand::CreateReg(Base));
1091     Inst.addOperand(MCOperand::CreateImm(Offset));
1092     break;
1093   case Mips::SC_MM:
1094     Inst.addOperand(MCOperand::CreateReg(Reg));
1095     // fallthrough
1096   default:
1097     Inst.addOperand(MCOperand::CreateReg(Reg));
1098     Inst.addOperand(MCOperand::CreateReg(Base));
1099     Inst.addOperand(MCOperand::CreateImm(Offset));
1100   }
1101
1102   return MCDisassembler::Success;
1103 }
1104
1105 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1106                                      unsigned Insn,
1107                                      uint64_t Address,
1108                                      const void *Decoder) {
1109   int Offset = SignExtend32<16>(Insn & 0xffff);
1110   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1111   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1112
1113   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1114   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1115
1116   Inst.addOperand(MCOperand::CreateReg(Reg));
1117   Inst.addOperand(MCOperand::CreateReg(Base));
1118   Inst.addOperand(MCOperand::CreateImm(Offset));
1119
1120   return MCDisassembler::Success;
1121 }
1122
1123 static DecodeStatus DecodeFMem(MCInst &Inst,
1124                                unsigned Insn,
1125                                uint64_t Address,
1126                                const void *Decoder) {
1127   int Offset = SignExtend32<16>(Insn & 0xffff);
1128   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1129   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1130
1131   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1132   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1133
1134   Inst.addOperand(MCOperand::CreateReg(Reg));
1135   Inst.addOperand(MCOperand::CreateReg(Base));
1136   Inst.addOperand(MCOperand::CreateImm(Offset));
1137
1138   return MCDisassembler::Success;
1139 }
1140
1141 static DecodeStatus DecodeFMem2(MCInst &Inst,
1142                                unsigned Insn,
1143                                uint64_t Address,
1144                                const void *Decoder) {
1145   int Offset = SignExtend32<16>(Insn & 0xffff);
1146   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1147   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1148
1149   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1150   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1151
1152   Inst.addOperand(MCOperand::CreateReg(Reg));
1153   Inst.addOperand(MCOperand::CreateReg(Base));
1154   Inst.addOperand(MCOperand::CreateImm(Offset));
1155
1156   return MCDisassembler::Success;
1157 }
1158
1159 static DecodeStatus DecodeFMem3(MCInst &Inst,
1160                                unsigned Insn,
1161                                uint64_t Address,
1162                                const void *Decoder) {
1163   int Offset = SignExtend32<16>(Insn & 0xffff);
1164   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1165   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1166
1167   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1168   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1169
1170   Inst.addOperand(MCOperand::CreateReg(Reg));
1171   Inst.addOperand(MCOperand::CreateReg(Base));
1172   Inst.addOperand(MCOperand::CreateImm(Offset));
1173
1174   return MCDisassembler::Success;
1175 }
1176
1177 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1178                                        unsigned Insn,
1179                                        uint64_t Address,
1180                                        const void *Decoder) {
1181   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1182   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1183   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1184
1185   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1186   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1187
1188   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1189     Inst.addOperand(MCOperand::CreateReg(Rt));
1190   }
1191
1192   Inst.addOperand(MCOperand::CreateReg(Rt));
1193   Inst.addOperand(MCOperand::CreateReg(Base));
1194   Inst.addOperand(MCOperand::CreateImm(Offset));
1195
1196   return MCDisassembler::Success;
1197 }
1198
1199 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1200                                               unsigned RegNo,
1201                                               uint64_t Address,
1202                                               const void *Decoder) {
1203   // Currently only hardware register 29 is supported.
1204   if (RegNo != 29)
1205     return  MCDisassembler::Fail;
1206   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1207   return MCDisassembler::Success;
1208 }
1209
1210 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1211                                               unsigned RegNo,
1212                                               uint64_t Address,
1213                                               const void *Decoder) {
1214   if (RegNo > 30 || RegNo %2)
1215     return MCDisassembler::Fail;
1216
1217   ;
1218   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1219   Inst.addOperand(MCOperand::CreateReg(Reg));
1220   return MCDisassembler::Success;
1221 }
1222
1223 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1224                                                 unsigned RegNo,
1225                                                 uint64_t Address,
1226                                                 const void *Decoder) {
1227   if (RegNo >= 4)
1228     return MCDisassembler::Fail;
1229
1230   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1231   Inst.addOperand(MCOperand::CreateReg(Reg));
1232   return MCDisassembler::Success;
1233 }
1234
1235 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1236                                                unsigned RegNo,
1237                                                uint64_t Address,
1238                                                const void *Decoder) {
1239   if (RegNo >= 4)
1240     return MCDisassembler::Fail;
1241
1242   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1243   Inst.addOperand(MCOperand::CreateReg(Reg));
1244   return MCDisassembler::Success;
1245 }
1246
1247 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1248                                                unsigned RegNo,
1249                                                uint64_t Address,
1250                                                const void *Decoder) {
1251   if (RegNo >= 4)
1252     return MCDisassembler::Fail;
1253
1254   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1255   Inst.addOperand(MCOperand::CreateReg(Reg));
1256   return MCDisassembler::Success;
1257 }
1258
1259 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1260                                                unsigned RegNo,
1261                                                uint64_t Address,
1262                                                const void *Decoder) {
1263   if (RegNo > 31)
1264     return MCDisassembler::Fail;
1265
1266   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1267   Inst.addOperand(MCOperand::CreateReg(Reg));
1268   return MCDisassembler::Success;
1269 }
1270
1271 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1272                                                unsigned RegNo,
1273                                                uint64_t Address,
1274                                                const void *Decoder) {
1275   if (RegNo > 31)
1276     return MCDisassembler::Fail;
1277
1278   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1279   Inst.addOperand(MCOperand::CreateReg(Reg));
1280   return MCDisassembler::Success;
1281 }
1282
1283 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1284                                                unsigned RegNo,
1285                                                uint64_t Address,
1286                                                const void *Decoder) {
1287   if (RegNo > 31)
1288     return MCDisassembler::Fail;
1289
1290   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1291   Inst.addOperand(MCOperand::CreateReg(Reg));
1292   return MCDisassembler::Success;
1293 }
1294
1295 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1296                                                unsigned RegNo,
1297                                                uint64_t Address,
1298                                                const void *Decoder) {
1299   if (RegNo > 31)
1300     return MCDisassembler::Fail;
1301
1302   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1303   Inst.addOperand(MCOperand::CreateReg(Reg));
1304   return MCDisassembler::Success;
1305 }
1306
1307 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1308                                                unsigned RegNo,
1309                                                uint64_t Address,
1310                                                const void *Decoder) {
1311   if (RegNo > 7)
1312     return MCDisassembler::Fail;
1313
1314   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1315   Inst.addOperand(MCOperand::CreateReg(Reg));
1316   return MCDisassembler::Success;
1317 }
1318
1319 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1320                                             unsigned RegNo,
1321                                             uint64_t Address,
1322                                             const void *Decoder) {
1323   if (RegNo > 31)
1324     return MCDisassembler::Fail;
1325
1326   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1327   Inst.addOperand(MCOperand::CreateReg(Reg));
1328   return MCDisassembler::Success;
1329 }
1330
1331 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1332                                        unsigned Offset,
1333                                        uint64_t Address,
1334                                        const void *Decoder) {
1335   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1336   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1337   return MCDisassembler::Success;
1338 }
1339
1340 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1341                                      unsigned Insn,
1342                                      uint64_t Address,
1343                                      const void *Decoder) {
1344
1345   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1346   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1347   return MCDisassembler::Success;
1348 }
1349
1350 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1351                                          unsigned Offset,
1352                                          uint64_t Address,
1353                                          const void *Decoder) {
1354   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1355
1356   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1357   return MCDisassembler::Success;
1358 }
1359
1360 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1361                                          unsigned Offset,
1362                                          uint64_t Address,
1363                                          const void *Decoder) {
1364   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1365
1366   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1367   return MCDisassembler::Success;
1368 }
1369
1370 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1371                                          unsigned Offset,
1372                                          uint64_t Address,
1373                                          const void *Decoder) {
1374   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1375   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1376   return MCDisassembler::Success;
1377 }
1378
1379 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1380                                        unsigned Insn,
1381                                        uint64_t Address,
1382                                        const void *Decoder) {
1383   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1384   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1385   return MCDisassembler::Success;
1386 }
1387
1388 static DecodeStatus DecodeSimm16(MCInst &Inst,
1389                                  unsigned Insn,
1390                                  uint64_t Address,
1391                                  const void *Decoder) {
1392   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1393   return MCDisassembler::Success;
1394 }
1395
1396 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1397                                  unsigned Insn,
1398                                  uint64_t Address,
1399                                  const void *Decoder) {
1400   // We add one to the immediate field as it was encoded as 'imm - 1'.
1401   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1402   return MCDisassembler::Success;
1403 }
1404
1405 static DecodeStatus DecodeInsSize(MCInst &Inst,
1406                                   unsigned Insn,
1407                                   uint64_t Address,
1408                                   const void *Decoder) {
1409   // First we need to grab the pos(lsb) from MCInst.
1410   int Pos = Inst.getOperand(2).getImm();
1411   int Size = (int) Insn - Pos + 1;
1412   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1413   return MCDisassembler::Success;
1414 }
1415
1416 static DecodeStatus DecodeExtSize(MCInst &Inst,
1417                                   unsigned Insn,
1418                                   uint64_t Address,
1419                                   const void *Decoder) {
1420   int Size = (int) Insn  + 1;
1421   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1422   return MCDisassembler::Success;
1423 }
1424
1425 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1426                                      uint64_t Address, const void *Decoder) {
1427   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1428   return MCDisassembler::Success;
1429 }
1430
1431 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1432                                      uint64_t Address, const void *Decoder) {
1433   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1434   return MCDisassembler::Success;
1435 }
1436
1437 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1438                                          unsigned Insn,
1439                                          uint64_t Address,
1440                                          const void *Decoder) {
1441   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1442                      Mips::S6, Mips::FP};
1443   unsigned RegNum;
1444
1445   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1446   // Empty register lists are not allowed.
1447   if (RegLst == 0)
1448     return MCDisassembler::Fail;
1449
1450   RegNum = RegLst & 0xf;
1451   for (unsigned i = 0; i < RegNum; i++)
1452     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1453
1454   if (RegLst & 0x10)
1455     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1456
1457   return MCDisassembler::Success;
1458 }