1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
18 #include "MipsSubtarget.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsMachineFunction.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Module.h"
25 #include "llvm/CodeGen/AsmPrinter.h"
26 #include "llvm/CodeGen/DwarfWriter.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegistry.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/FormattedStream.h"
44 #include "llvm/Support/MathExtras.h"
49 class MipsAsmPrinter : public AsmPrinter {
50 const MipsSubtarget *Subtarget;
52 explicit MipsAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
53 MCContext &Ctx, MCStreamer &Streamer,
55 : AsmPrinter(O, TM, Ctx, Streamer, T) {
56 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 virtual const char *getPassName() const {
60 return "Mips Assembly Printer";
63 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
64 unsigned AsmVariant, const char *ExtraCode);
65 void printOperand(const MachineInstr *MI, int opNum);
66 void printUnsignedImm(const MachineInstr *MI, int opNum);
67 void printMemOperand(const MachineInstr *MI, int opNum,
68 const char *Modifier = 0);
69 void printFCCOperand(const MachineInstr *MI, int opNum,
70 const char *Modifier = 0);
71 void printSavedRegsBitmask();
72 void printHex32(unsigned int Value);
74 const char *emitCurrentABIString();
75 void emitFrameDirective();
77 void printInstruction(const MachineInstr *MI); // autogenerated.
78 void EmitInstruction(const MachineInstr *MI) {
82 virtual void EmitFunctionBodyStart();
83 virtual void EmitFunctionBodyEnd();
84 static const char *getRegisterName(unsigned RegNo);
86 virtual void EmitFunctionEntryLabel();
87 void EmitStartOfAsmFile(Module &M);
89 } // end of anonymous namespace
91 #include "MipsGenAsmWriter.inc"
93 //===----------------------------------------------------------------------===//
95 // Mips Asm Directives
97 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
98 // Describe the stack frame.
100 // -- Mask directives "(f)mask bitmask, offset"
101 // Tells the assembler which registers are saved and where.
102 // bitmask - contain a little endian bitset indicating which registers are
103 // saved on function prologue (e.g. with a 0x80000000 mask, the
104 // assembler knows the register 31 (RA) is saved at prologue.
105 // offset - the position before stack pointer subtraction indicating where
106 // the first saved register on prologue is located. (e.g. with a
108 // Consider the following function prologue:
111 // .mask 0xc0000000,-8
112 // addiu $sp, $sp, -48
116 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
117 // 30 (FP) are saved at prologue. As the save order on prologue is from
118 // left to right, RA is saved first. A -8 offset means that after the
119 // stack pointer subtration, the first register in the mask (RA) will be
120 // saved at address 48-8=40.
122 //===----------------------------------------------------------------------===//
124 //===----------------------------------------------------------------------===//
126 //===----------------------------------------------------------------------===//
128 // Create a bitmask with all callee saved registers for CPU or Floating Point
129 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
130 void MipsAsmPrinter::printSavedRegsBitmask() {
131 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
132 const MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
134 // CPU and FPU Saved Registers Bitmasks
135 unsigned int CPUBitmask = 0;
136 unsigned int FPUBitmask = 0;
138 // Set the CPU and FPU Bitmasks
139 const MachineFrameInfo *MFI = MF->getFrameInfo();
140 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
141 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
142 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg());
143 if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
144 CPUBitmask |= (1 << RegNum);
146 FPUBitmask |= (1 << RegNum);
149 // Return Address and Frame registers must also be set in CPUBitmask.
151 CPUBitmask |= (1 << MipsRegisterInfo::
152 getRegisterNumbering(RI.getFrameRegister(*MF)));
155 CPUBitmask |= (1 << MipsRegisterInfo::
156 getRegisterNumbering(RI.getRARegister()));
159 O << "\t.mask \t"; printHex32(CPUBitmask); O << ','
160 << MipsFI->getCPUTopSavedRegOff() << '\n';
163 O << "\t.fmask\t"; printHex32(FPUBitmask); O << ","
164 << MipsFI->getFPUTopSavedRegOff() << '\n';
167 // Print a 32 bit hex number with all numbers.
168 void MipsAsmPrinter::
169 printHex32(unsigned int Value)
172 for (int i = 7; i >= 0; i--)
173 O << utohexstr( (Value & (0xF << (i*4))) >> (i*4) );
176 //===----------------------------------------------------------------------===//
177 // Frame and Set directives
178 //===----------------------------------------------------------------------===//
181 void MipsAsmPrinter::emitFrameDirective() {
182 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
184 unsigned stackReg = RI.getFrameRegister(*MF);
185 unsigned returnReg = RI.getRARegister();
186 unsigned stackSize = MF->getFrameInfo()->getStackSize();
189 O << "\t.frame\t" << '$' << LowercaseString(getRegisterName(stackReg))
190 << ',' << stackSize << ','
191 << '$' << LowercaseString(getRegisterName(returnReg))
195 /// Emit Set directives.
196 const char *MipsAsmPrinter::emitCurrentABIString() {
197 switch(Subtarget->getTargetABI()) {
198 case MipsSubtarget::O32: return "abi32";
199 case MipsSubtarget::O64: return "abiO64";
200 case MipsSubtarget::N32: return "abiN32";
201 case MipsSubtarget::N64: return "abi64";
202 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
206 llvm_unreachable("Unknown Mips ABI");
210 void MipsAsmPrinter::EmitFunctionEntryLabel() {
211 O << "\t.ent\t" << *CurrentFnSym << '\n';
212 OutStreamer.EmitLabel(CurrentFnSym);
215 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
216 /// the first basic block in the function.
217 void MipsAsmPrinter::EmitFunctionBodyStart() {
218 emitFrameDirective();
219 printSavedRegsBitmask();
222 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
223 /// the last basic block in the function.
224 void MipsAsmPrinter::EmitFunctionBodyEnd() {
225 // There are instruction for this macros, but they must
226 // always be at the function end, and we can't emit and
227 // break with BB logic.
228 O << "\t.set\tmacro\n";
229 O << "\t.set\treorder\n";
231 O << "\t.end\t" << *CurrentFnSym << '\n';
235 // Print out an operand for an inline asm expression.
236 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
237 unsigned AsmVariant,const char *ExtraCode){
238 // Does this asm operand have a single letter operand modifier?
239 if (ExtraCode && ExtraCode[0])
240 return true; // Unknown modifier.
242 printOperand(MI, OpNo);
246 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
247 const MachineOperand &MO = MI->getOperand(opNum);
250 if (MO.getTargetFlags())
253 switch(MO.getTargetFlags()) {
254 case MipsII::MO_GPREL: O << "%gp_rel("; break;
255 case MipsII::MO_GOT_CALL: O << "%call16("; break;
257 if (MI->getOpcode() == Mips::LW)
262 case MipsII::MO_ABS_HILO:
263 if (MI->getOpcode() == Mips::LUi)
270 switch (MO.getType()) {
271 case MachineOperand::MO_Register:
272 O << '$' << LowercaseString(getRegisterName(MO.getReg()));
275 case MachineOperand::MO_Immediate:
276 O << (short int)MO.getImm();
279 case MachineOperand::MO_MachineBasicBlock:
280 O << *MO.getMBB()->getSymbol(OutContext);
283 case MachineOperand::MO_GlobalAddress:
284 O << *GetGlobalValueSymbol(MO.getGlobal());
287 case MachineOperand::MO_ExternalSymbol:
288 O << *GetExternalSymbolSymbol(MO.getSymbolName());
291 case MachineOperand::MO_JumpTableIndex:
292 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
293 << '_' << MO.getIndex();
296 case MachineOperand::MO_ConstantPoolIndex:
297 O << MAI->getPrivateGlobalPrefix() << "CPI"
298 << getFunctionNumber() << "_" << MO.getIndex();
300 O << "+" << MO.getOffset();
304 llvm_unreachable("<unknown operand type>");
307 if (closeP) O << ")";
310 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum) {
311 const MachineOperand &MO = MI->getOperand(opNum);
312 if (MO.getType() == MachineOperand::MO_Immediate)
313 O << (unsigned short int)MO.getImm();
315 printOperand(MI, opNum);
318 void MipsAsmPrinter::
319 printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier) {
320 // when using stack locations for not load/store instructions
321 // print the same way as all normal 3 operand instructions.
322 if (Modifier && !strcmp(Modifier, "stackloc")) {
323 printOperand(MI, opNum+1);
325 printOperand(MI, opNum);
329 // Load/Store memory operands -- imm($reg)
330 // If PIC target the target is loaded as the
331 // pattern lw $25,%call16($28)
332 printOperand(MI, opNum);
334 printOperand(MI, opNum+1);
338 void MipsAsmPrinter::
339 printFCCOperand(const MachineInstr *MI, int opNum, const char *Modifier) {
340 const MachineOperand& MO = MI->getOperand(opNum);
341 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
344 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
345 // FIXME: Use SwitchSection.
347 // Tell the assembler which ABI we are using
348 O << "\t.section .mdebug." << emitCurrentABIString() << '\n';
350 // TODO: handle O64 ABI
351 if (Subtarget->isABI_EABI())
352 O << "\t.section .gcc_compiled_long" <<
353 (Subtarget->isGP32bit() ? "32" : "64") << '\n';
355 // return to previous section
356 O << "\t.previous" << '\n';
359 // Force static initialization.
360 extern "C" void LLVMInitializeMipsAsmPrinter() {
361 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
362 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);