1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "llvm/MC/MCParser/MCAsmLexer.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/Support/TargetRegistry.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCTargetAsmParser.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/Support/MathExtras.h"
23 class MipsAsmParser : public MCTargetAsmParser {
25 #define GET_ASSEMBLER_HEADER
26 #include "MipsGenAsmMatcher.inc"
28 bool MatchAndEmitInstruction(SMLoc IDLoc,
29 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
32 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
34 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
35 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
37 bool ParseDirective(AsmToken DirectiveID);
39 OperandMatchResultTy parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
41 unsigned GetMCInstOperandNum(unsigned Kind, MCInst &Inst,
42 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
46 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
47 : MCTargetAsmParser() {
55 /// MipsOperand - Instances of this class represent a parsed Mips machine
57 class MipsOperand : public MCParsedAsmOperand {
68 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
70 void addRegOperands(MCInst &Inst, unsigned N) const {
71 llvm_unreachable("unimplemented!");
73 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
74 llvm_unreachable("unimplemented!");
76 void addImmOperands(MCInst &Inst, unsigned N) const {
77 llvm_unreachable("unimplemented!");
79 void addMemOperands(MCInst &Inst, unsigned N) const {
80 llvm_unreachable("unimplemented!");
83 bool isReg() const { return Kind == k_Register; }
84 bool isImm() const { return Kind == k_Immediate; }
85 bool isToken() const { return Kind == k_Token; }
86 bool isMem() const { return Kind == k_Memory; }
88 StringRef getToken() const {
89 assert(Kind == k_Token && "Invalid access!");
93 unsigned getReg() const {
94 assert((Kind == k_Register) && "Invalid access!");
98 virtual void print(raw_ostream &OS) const {
99 llvm_unreachable("unimplemented!");
104 unsigned MipsAsmParser::
105 GetMCInstOperandNum(unsigned Kind, MCInst &Inst,
106 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
107 unsigned OperandNum) {
108 assert (0 && "GetMCInstOperandNum() not supported by the Mips target.");
109 // The Mips backend doesn't currently include the matcher implementation, so
110 // the GetMCInstOperandNumImpl() is undefined. This is a temporary
116 MatchAndEmitInstruction(SMLoc IDLoc,
117 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
123 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
128 ParseInstruction(StringRef Name, SMLoc NameLoc,
129 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
134 ParseDirective(AsmToken DirectiveID) {
138 MipsAsmParser::OperandMatchResultTy MipsAsmParser::
139 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&) {
140 return MatchOperand_ParseFail;
143 extern "C" void LLVMInitializeMipsAsmParser() {
144 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
145 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
146 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
147 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);