lib/Target/Hexagon/HexagonScheduleV60.td

   1 //=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // CVI pipes from the "Hexagon Multimedia Co-Processor Extensions Arch Spec".
  11 def CVI_ST     : FuncUnit;
  12 def CVI_XLANE  : FuncUnit;
  13 def CVI_SHIFT  : FuncUnit;
  14 def CVI_MPY0   : FuncUnit;
  15 def CVI_MPY1   : FuncUnit;
  16 def CVI_LD     : FuncUnit;
  17
  18 // Combined functional units.
  19 def CVI_XLSHF  : FuncUnit;
  20 def CVI_MPY01  : FuncUnit;
  21 def CVI_ALL    : FuncUnit;
  22
  23 // Note: When adding additional vector scheduling classes, add the
  24 // corresponding methods to the class HexagonInstrInfo.
  25 def CVI_VA           : InstrItinClass;
  26 def CVI_VA_DV        : InstrItinClass;
  27 def CVI_VX_LONG      : InstrItinClass;
  28 def CVI_VX_LATE      : InstrItinClass;
  29 def CVI_VX           : InstrItinClass;
  30 def CVI_VX_DV_LONG   : InstrItinClass;
  31 def CVI_VX_DV        : InstrItinClass;
  32 def CVI_VX_DV_SLOT2  : InstrItinClass;
  33 def CVI_VP           : InstrItinClass;
  34 def CVI_VP_LONG      : InstrItinClass;
  35 def CVI_VP_VS_EARLY  : InstrItinClass;
  36 def CVI_VP_VS_LONG_EARLY   : InstrItinClass;
  37 def CVI_VP_VS_LONG   : InstrItinClass;
  38 def CVI_VP_VS   : InstrItinClass;
  39 def CVI_VP_DV        : InstrItinClass;
  40 def CVI_VS           : InstrItinClass;
  41 def CVI_VINLANESAT   : InstrItinClass;
  42 def CVI_VM_LD        : InstrItinClass;
  43 def CVI_VM_TMP_LD    : InstrItinClass;
  44 def CVI_VM_CUR_LD    : InstrItinClass;
  45 def CVI_VM_VP_LDU    : InstrItinClass;
  46 def CVI_VM_ST        : InstrItinClass;
  47 def CVI_VM_NEW_ST    : InstrItinClass;
  48 def CVI_VM_STU       : InstrItinClass;
  49 def CVI_HIST         : InstrItinClass;
  50 def CVI_VA_EXT       : InstrItinClass;
  51
  52 // There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
  53 // This file describes that machine information.
  54 //
  55 //    |===========|==================================================|
  56 //    | PIPELINE  |              Instruction Classes                 |
  57 //    |===========|==================================================|
  58 //    | SLOT0     |  LD       ST    ALU32     MEMOP     NV    SYSTEM |
  59 //    |-----------|--------------------------------------------------|
  60 //    | SLOT1     |  LD       ST    ALU32                            |
  61 //    |-----------|--------------------------------------------------|
  62 //    | SLOT2     |  XTYPE          ALU32     J         JR           |
  63 //    |-----------|--------------------------------------------------|
  64 //    | SLOT3     |  XTYPE          ALU32     J         CR           |
  65 //    |===========|==================================================|
  66 //
  67 //
  68 // In addition to using the above SLOTS, there are also six vector pipelines
  69 // in the CVI co-processor in the Hexagon V60 machine.
  70 //
  71 //      |=========| |=========| |=========| |=========| |=========| |=========|
  72 // SLOT | CVI_LD  | |CVI_MPY3 | |CVI_MPY2 | |CVI_SHIFT| |CVI_XLANE| | CVI_ST  |
  73 // ==== |=========| |=========| |=========| |=========| |=========| |=========|
  74 // S0-3 |         | | CVI_VA  | | CVI_VA  | | CVI_VA  | | CVI_VA  | |         |
  75 // S2-3 |         | | CVI_VX  | | CVI_VX  | |         | |         | |         |
  76 // S0-3 |         | |         | |         | |         | | CVI_VP  | |         |
  77 // S0-3 |         | |         | |         | | CVI_VS  | |         | |         |
  78 // S0-1 |(CVI_LD) | | CVI_LD  | | CVI_LD  | | CVI_LD  | | CVI_LD  | |         |
  79 // S0-1 |(C*TMP_LD) |         | |         | |         | |         | |         |
  80 // S01  |(C*_LDU) | |         | |         | |         | | C*_LDU  | |         |
  81 // S0   |         | | CVI_ST  | | CVI_ST  | | CVI_ST  | | CVI_ST  | |(CVI_ST) |
  82 // S0   |         | |         | |         | |         | |         | |(C*TMP_ST)
  83 // S01  |         | |         | |         | |         | | VSTU    | |(C*_STU) |
  84 //      |=========| |=========| |=========| |=========| |=========| |=========|
  85 //                  |=====================| |=====================|
  86 //                  | CVI_MPY2 & CVI_MPY3 | |CVI_XLANE & CVI_SHIFT|
  87 //                  |=====================| |=====================|
  88 // S0-3             | CVI_VA_DV           | | CVI_VA_DV           |
  89 // S0-3             |                     | | CVI_VP_DV           |
  90 // S2-3             | CVI_VX_DV           | |                     |
  91 //                  |=====================| |=====================|
  92 //      |=====================================================================|
  93 // S0-3 | CVI_HIST   Histogram                                                |
  94 // S0123| CVI_VA_EXT Extract                                                  |
  95 //      |=====================================================================|
  96
  97 def HexagonItinerariesV60 :
  98       ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
  99                             CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
 100                             CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL], [], [
 101         // ALU32
 102         InstrItinData<ALU32_2op_tc_1_SLOT0123     ,
 103                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 104         InstrItinData<ALU32_2op_tc_2early_SLOT0123,
 105                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 106         InstrItinData<ALU32_3op_tc_1_SLOT0123     ,
 107                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 108         InstrItinData<ALU32_3op_tc_2_SLOT0123     ,
 109                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 110         InstrItinData<ALU32_3op_tc_2early_SLOT0123,
 111                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 112         InstrItinData<ALU32_ADDI_tc_1_SLOT0123    ,
 113                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 114
 115         // ALU64
 116         InstrItinData<ALU64_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
 117         InstrItinData<ALU64_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
 118         InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
 119         InstrItinData<ALU64_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
 120
 121         // CR -> System
 122         InstrItinData<CR_tc_2_SLOT3      , [InstrStage<2, [SLOT3]>]>,
 123         InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>,
 124         InstrItinData<CR_tc_3x_SLOT3     , [InstrStage<3, [SLOT3]>]>,
 125
 126         // Jump (conditional/unconditional/return etc)
 127         InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
 128         InstrItinData<CR_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
 129         InstrItinData<CJ_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
 130         InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
 131         InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
 132         InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT     , [InstrStage<1, [SLOT2, SLOT3]>]>,
 133
 134         // JR
 135         InstrItinData<J_tc_2early_SLOT2  , [InstrStage<2, [SLOT2]>]>,
 136         InstrItinData<J_tc_3stall_SLOT2  , [InstrStage<3, [SLOT2]>]>,
 137
 138         // Extender
 139         InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1,
 140                               [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 141
 142         // Load
 143         InstrItinData<LD_tc_ld_SLOT01      , [InstrStage<3, [SLOT0, SLOT1]>]>,
 144         InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
 145         InstrItinData<LD_tc_ld_SLOT0       , [InstrStage<3, [SLOT0]>]>,
 146
 147         // M
 148         InstrItinData<M_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
 149         InstrItinData<M_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
 150         InstrItinData<M_tc_3_SLOT23     , [InstrStage<3, [SLOT2, SLOT3]>]>,
 151         InstrItinData<M_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
 152         InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
 153         InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
 154
 155         // Store
 156         InstrItinData<ST_tc_st_SLOT01   , [InstrStage<1, [SLOT0, SLOT1]>]>,
 157         InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
 158         InstrItinData<ST_tc_ld_SLOT0    , [InstrStage<3, [SLOT0]>]>,
 159         InstrItinData<ST_tc_st_SLOT0    , [InstrStage<1, [SLOT0]>]>,
 160
 161         // Subinsn
 162         InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>,
 163         InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
 164         InstrItinData<SUBINSN_tc_ld_SLOT0    , [InstrStage<3, [SLOT0]>]>,
 165         InstrItinData<SUBINSN_tc_1_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
 166         InstrItinData<SUBINSN_tc_2early_SLOT01,
 167                                                [InstrStage<2, [SLOT0, SLOT1]>]>,
 168         InstrItinData<SUBINSN_tc_ld_SLOT01   , [InstrStage<3, [SLOT0, SLOT1]>]>,
 169         InstrItinData<SUBINSN_tc_st_SLOT01   , [InstrStage<1, [SLOT0, SLOT1]>]>,
 170
 171         // S
 172         InstrItinData<S_2op_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
 173         InstrItinData<S_2op_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
 174         InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
 175         // The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60.
 176         InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
 177         InstrItinData<S_3op_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
 178         InstrItinData<S_3op_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
 179         InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
 180         InstrItinData<S_3op_tc_3_SLOT23     , [InstrStage<3, [SLOT2, SLOT3]>]>,
 181         InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
 182         InstrItinData<S_3op_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
 183
 184         // New Value Compare Jump
 185         InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
 186
 187         // Mem ops
 188         InstrItinData<V2LDST_tc_st_SLOT0  , [InstrStage<1, [SLOT0]>]>,
 189         InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
 190         InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
 191         InstrItinData<V4LDST_tc_st_SLOT0  , [InstrStage<1, [SLOT0]>]>,
 192         InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
 193         InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
 194
 195         // Endloop
 196         InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>,
 197
 198         // Vector
 199         InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
 200                              [InstrStage<3, [SLOT0, SLOT1]>]>,
 201         InstrItinData<COPROC_VX_vtc_long_SLOT23  ,
 202                              [InstrStage<3, [SLOT2, SLOT3]>]>,
 203         InstrItinData<COPROC_VX_vtc_SLOT23 ,
 204                              [InstrStage<3, [SLOT2, SLOT3]>]>,
 205         InstrItinData<MAPPING_tc_1_SLOT0123      ,
 206                              [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 207
 208         // Duplex and Compound
 209         InstrItinData<DUPLEX     , [InstrStage<1, [SLOT0]>]>,
 210         InstrItinData<COMPOUND_CJ_ARCHDEPSLOT   , [InstrStage<1, [SLOT2, SLOT3]>]>,
 211         InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
 212         // Misc
 213         InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 214         InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
 215         InstrItinData<PSEUDOM    , [InstrStage<1, [SLOT2, SLOT3], 0>,
 216                                     InstrStage<1, [SLOT2, SLOT3]>]>,
 217
 218         // Latest CVI spec definitions.
 219         InstrItinData<CVI_VA,[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 220                                     InstrStage<1, [CVI_XLANE,CVI_SHIFT,
 221                                                    CVI_MPY0, CVI_MPY1]>]>,
 222         InstrItinData<CVI_VA_DV,
 223                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 224                                     InstrStage<1, [CVI_XLSHF, CVI_MPY01]>]>,
 225         InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
 226                                     InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
 227         InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>,
 228                                     InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
 229         InstrItinData<CVI_VX,[InstrStage<1, [SLOT2, SLOT3], 0>,
 230                                     InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
 231         InstrItinData<CVI_VX_DV_LONG,
 232                                    [InstrStage<1, [SLOT2, SLOT3], 0>,
 233                                     InstrStage<1, [CVI_MPY01]>]>,
 234         InstrItinData<CVI_VX_DV,
 235                                    [InstrStage<1, [SLOT2, SLOT3], 0>,
 236                                     InstrStage<1, [CVI_MPY01]>]>,
 237         InstrItinData<CVI_VX_DV_SLOT2,
 238                                    [InstrStage<1, [SLOT2], 0>,
 239                                     InstrStage<1, [CVI_MPY01]>]>,
 240         InstrItinData<CVI_VP,      [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 241                                     InstrStage<1, [CVI_XLANE]>]>,
 242         InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 243                                     InstrStage<1, [CVI_XLANE]>]>,
 244         InstrItinData<CVI_VP_VS_EARLY,
 245                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 246                                     InstrStage<1, [CVI_XLSHF]>]>,
 247         InstrItinData<CVI_VP_VS_LONG,
 248                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 249                                     InstrStage<1, [CVI_XLSHF]>]>,
 250         InstrItinData<CVI_VP_VS,
 251                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 252                                     InstrStage<1, [CVI_XLSHF]>]>,
 253         InstrItinData<CVI_VP_VS_LONG_EARLY,
 254                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 255                                     InstrStage<1, [CVI_XLSHF]>]>,
 256         InstrItinData<CVI_VP_DV  , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 257                                     InstrStage<1, [CVI_XLSHF]>]>,
 258         InstrItinData<CVI_VS,
 259                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 260                                     InstrStage<1, [CVI_SHIFT]>]>,
 261         InstrItinData<CVI_VINLANESAT,
 262                                    [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 263                                     InstrStage<1, [CVI_SHIFT]>]>,
 264         InstrItinData<CVI_VM_LD  , [InstrStage<1, [SLOT0, SLOT1], 0>,
 265                                     InstrStage<1, [CVI_LD], 0>,
 266                                     InstrStage<1, [CVI_XLANE, CVI_SHIFT,
 267                                                    CVI_MPY0, CVI_MPY1]>]>,
 268         InstrItinData<CVI_VM_TMP_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
 269                                     InstrStage<1, [CVI_LD]>]>,
 270         InstrItinData<CVI_VM_CUR_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
 271                                     InstrStage<1, [CVI_LD], 0>,
 272                                     InstrStage<1, [CVI_XLANE, CVI_SHIFT,
 273                                                    CVI_MPY0, CVI_MPY1]>]>,
 274         InstrItinData<CVI_VM_VP_LDU,[InstrStage<1,[SLOT0], 0>,
 275                                     InstrStage<1, [SLOT1], 0>,
 276                                     InstrStage<1, [CVI_LD], 0>,
 277                                     InstrStage<1, [CVI_XLANE]>]>,
 278         InstrItinData<CVI_VM_ST  , [InstrStage<1, [SLOT0], 0>,
 279                                     InstrStage<1, [CVI_ST], 0>,
 280                                     InstrStage<1, [CVI_XLANE, CVI_SHIFT,
 281                                                    CVI_MPY0, CVI_MPY1]>]>,
 282         InstrItinData<CVI_VM_NEW_ST,[InstrStage<1,[SLOT0], 0>,
 283                                     InstrStage<1, [CVI_ST]>]>,
 284         InstrItinData<CVI_VM_STU , [InstrStage<1, [SLOT0], 0>,
 285                                     InstrStage<1, [SLOT1], 0>,
 286                                     InstrStage<1, [CVI_ST], 0>,
 287                                     InstrStage<1, [CVI_XLANE]>]>,
 288         InstrItinData<CVI_HIST   , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
 289                                     InstrStage<1, [CVI_ALL]>]>
 290       ]>;
 291
 292 def HexagonModelV60 : SchedMachineModel {
 293   // Max issue per cycle == bundle width.
 294   let IssueWidth = 4;
 295   let Itineraries = HexagonItinerariesV60;
 296   let LoadLatency = 1;
 297 }
 298
 299 //===----------------------------------------------------------------------===//
 300 // Hexagon V60 Resource Definitions -
 301 //===----------------------------------------------------------------------===//