lib/Target/Hexagon/HexagonIntrinsicsV4.td

   1 //===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V4 Architecture Extensions
  11 // Application-Level Specification
  12 // 80-V9418-12 Rev. A
  13 // June 15, 2010
  14
  15 // Polynomial multiply words
  16 // Rdd=pmpyw(Rs,Rt)
  17 def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
  18 // Rxx^=pmpyw(Rs,Rt)
  19 def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
  20
  21 //Rxx^=asr(Rss,Rt)
  22 def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
  23 //Rxx^=asl(Rss,Rt)
  24 def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
  25 //Rxx^=lsr(Rss,Rt)
  26 def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
  27 //Rxx^=lsl(Rss,Rt)
  28 def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
  29
  30 // Multiply and use upper result
  31 def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
  32 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
  33 def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
  34 def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
  35 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
  36
  37 def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
  38
  39 def: T_P_pat  <S2_ct0p,      int_hexagon_S2_ct0p>;
  40 def: T_P_pat  <S2_ct1p,      int_hexagon_S2_ct1p>;
  41 def: T_RR_pat<C4_nbitsset,  int_hexagon_C4_nbitsset>;
  42 def: T_RR_pat<C4_nbitsclr,  int_hexagon_C4_nbitsclr>;
  43 def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
  44
  45 def : T_RR_pat<A4_cmpbeq,   int_hexagon_A4_cmpbeq>;
  46 def : T_RR_pat<A4_cmpbgt,   int_hexagon_A4_cmpbgt>;
  47 def : T_RR_pat<A4_cmpbgtu,  int_hexagon_A4_cmpbgtu>;
  48 def : T_RR_pat<A4_cmpheq,   int_hexagon_A4_cmpheq>;
  49 def : T_RR_pat<A4_cmphgt,   int_hexagon_A4_cmphgt>;
  50 def : T_RR_pat<A4_cmphgtu,  int_hexagon_A4_cmphgtu>;
  51
  52 def : T_RI_pat<A4_cmpbeqi,  int_hexagon_A4_cmpbeqi>;
  53 def : T_RI_pat<A4_cmpbgti,  int_hexagon_A4_cmpbgti>;
  54 def : T_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
  55
  56 def : T_RI_pat<A4_cmpheqi,  int_hexagon_A4_cmpheqi>;
  57 def : T_RI_pat<A4_cmphgti,  int_hexagon_A4_cmphgti>;
  58 def : T_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
  59
  60 def : T_RP_pat <A4_boundscheck, int_hexagon_A4_boundscheck>;
  61
  62 def : T_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
  63
  64 def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
  65                                       IntRegs:$src3),
  66            (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
  67
  68 def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
  69 def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
  70 def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
  71 def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
  72 // Multiply 32x32 and use upper result
  73 def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
  74 def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
  75
  76 def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
  77 def : T_PP_pat<A4_ornp,  int_hexagon_A4_ornp>;
  78
  79 // Extract bitfield
  80 def : T_PP_pat  <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
  81 def : T_RP_pat  <S4_extract_rp, int_hexagon_S4_extract_rp>;
  82 def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
  83 def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
  84
  85 // Shift an immediate left by register amount
  86 def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
  87
  88 // Logical xor with xor accumulation
  89 def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
  90
  91 // Shift and add/sub/and/or
  92 def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
  93 def : T_IRI_pat <S4_ori_asl_ri,  int_hexagon_S4_ori_asl_ri>;
  94 def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
  95 def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
  96 def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
  97 def : T_IRI_pat <S4_ori_lsr_ri,  int_hexagon_S4_ori_lsr_ri>;
  98 def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
  99 def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
 100
 101 // Split bitfield
 102 def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
 103 def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
 104
 105 def: T_RR_pat<S4_parity,   int_hexagon_S4_parity>;
 106
 107 def: T_RI_pat<S4_ntstbit_i,  int_hexagon_S4_ntstbit_i>;
 108 def: T_RR_pat<S4_ntstbit_r,  int_hexagon_S4_ntstbit_r>;
 109
 110 def: T_RI_pat<S4_clbaddi,  int_hexagon_S4_clbaddi>;
 111 def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
 112 def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
 113
 114 /********************************************************************
 115 *            ALU32/ALU                                              *
 116 *********************************************************************/
 117
 118 // ALU32 / ALU / Logical Operations.
 119 def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
 120 def: T_RR_pat<A4_orn,  int_hexagon_A4_orn>;
 121
 122 /********************************************************************
 123 *            ALU32/PERM                                             *
 124 *********************************************************************/
 125
 126 // Combine Words Into Doublewords.
 127 def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
 128 def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
 129
 130 /********************************************************************
 131 *            ALU32/PRED                                             *
 132 *********************************************************************/
 133
 134 // Compare
 135 def : T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s10ExtPred>;
 136 def : T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s10ExtPred>;
 137 def : T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u9ExtPred>;
 138
 139 def: T_RR_pat<A4_rcmpeq,  int_hexagon_A4_rcmpeq>;
 140 def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
 141
 142 def: T_RI_pat<A4_rcmpeqi,  int_hexagon_A4_rcmpeqi>;
 143 def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
 144
 145 /********************************************************************
 146 *            CR                                                     *
 147 *********************************************************************/
 148
 149 // CR / Logical Operations On Predicates.
 150
 151 class qi_CRInst_qiqiqi_pat<Intrinsic IntID, InstHexagon Inst> :
 152   Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt, IntRegs:$Ru)),
 153       (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs),
 154                            (C2_tfrrp IntRegs:$Rt),
 155                            (C2_tfrrp IntRegs:$Ru))))>;
 156
 157 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_and,   C4_and_and>;
 158 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_andn,  C4_and_andn>;
 159 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_or,    C4_and_or>;
 160 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_orn,   C4_and_orn>;
 161 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_and,    C4_or_and>;
 162 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_andn,   C4_or_andn>;
 163 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_or,     C4_or_or>;
 164 def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_orn,    C4_or_orn>;
 165
 166 /********************************************************************
 167 *            XTYPE/ALU                                              *
 168 *********************************************************************/
 169
 170 // Add And Accumulate.
 171
 172 def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
 173 def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
 174
 175
 176 // XTYPE / ALU / Logical-logical Words.
 177 def : T_RRR_pat <M4_or_xor,   int_hexagon_M4_or_xor>;
 178 def : T_RRR_pat <M4_and_xor,  int_hexagon_M4_and_xor>;
 179 def : T_RRR_pat <M4_or_and,   int_hexagon_M4_or_and>;
 180 def : T_RRR_pat <M4_and_and,  int_hexagon_M4_and_and>;
 181 def : T_RRR_pat <M4_xor_and,  int_hexagon_M4_xor_and>;
 182 def : T_RRR_pat <M4_or_or,    int_hexagon_M4_or_or>;
 183 def : T_RRR_pat <M4_and_or,   int_hexagon_M4_and_or>;
 184 def : T_RRR_pat <M4_xor_or,   int_hexagon_M4_xor_or>;
 185 def : T_RRR_pat <M4_or_andn,  int_hexagon_M4_or_andn>;
 186 def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
 187 def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
 188
 189 def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
 190 def : T_RRI_pat <S4_or_andix,  int_hexagon_S4_or_andix>;
 191 def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
 192
 193 // Modulo wrap.
 194 def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
 195
 196 // Arithmetic/Convergent round
 197 // Rd=[cround|round](Rs,Rt)[:sat]
 198 // Rd=[cround|round](Rs,#u5)[:sat]
 199 def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
 200 def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
 201
 202 def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
 203 def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
 204
 205 def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
 206 def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
 207
 208 def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
 209
 210 class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
 211   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 212              !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
 213              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 214
 215 class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
 216   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 217              !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
 218              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 219
 220 class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
 221   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 222              !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
 223              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 224
 225 //
 226 // SInst Classes.
 227 //
 228 class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
 229   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 230              !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
 231              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 232
 233 class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
 234   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 235                                      IntRegs:$src3),
 236              !strconcat("$dst = ", !strconcat(opc ,
 237                                               "($src1, and($src2, !$src3)")),
 238              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 239                                          IntRegs:$src3))]>;
 240
 241 class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
 242   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 243                                      IntRegs:$src3),
 244              !strconcat("$dst = ", !strconcat(opc ,
 245                                               "($src1, and($src2, $src3)")),
 246              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 247                                          IntRegs:$src3))]>;
 248
 249 class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
 250   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 251                                      IntRegs:$src3),
 252              !strconcat("$dst = ", !strconcat(opc ,
 253                                               "($src1, or($src2, !$src3)")),
 254              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 255                                          IntRegs:$src3))]>;
 256
 257 class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
 258   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 259                                      IntRegs:$src3),
 260              !strconcat("$dst = ", !strconcat(opc ,
 261                                               "($src1, or($src2, $src3)")),
 262              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 263                                          IntRegs:$src3))]>;
 264
 265 /********************************************************************
 266 *            ALU32/PRED                                             *
 267 *********************************************************************/
 268
 269 // ALU32 / PRED / Conditional Shift Halfword.
 270 // ALU32 / PRED / Conditional Sign Extend.
 271 // ALU32 / PRED / Conditional Zero Extend.
 272 // ALU32 / PRED / Compare.
 273 def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
 274 def Hexagon_C4_cmplte  : qi_neg_ALU32_sisi  <"cmp.gt", int_hexagon_C4_cmplte>;
 275 def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi  <"cmp.gtu",int_hexagon_C4_cmplteu>;
 276
 277 def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
 278 def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
 279 def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
 280
 281
 282 /********************************************************************
 283 *            CR                                                     *
 284 *********************************************************************/
 285
 286 // CR / Corner Detection Acceleration.
 287 def Hexagon_C4_fastcorner9:
 288   qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
 289 def Hexagon_C4_fastcorner9_not:
 290   qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
 291
 292 // CR / Logical Operations On Predicates.
 293 def Hexagon_C4_and_andn:
 294   qi_SInst_qi_andqiqi_neg         <"and",      int_hexagon_C4_and_andn>;
 295 def Hexagon_C4_and_and:
 296   qi_SInst_qi_andqiqi             <"and",      int_hexagon_C4_and_and>;
 297 def Hexagon_C4_and_orn:
 298   qi_SInst_qi_orqiqi_neg          <"and",      int_hexagon_C4_and_orn>;
 299 def Hexagon_C4_and_or:
 300   qi_SInst_qi_orqiqi              <"and",      int_hexagon_C4_and_or>;
 301 def Hexagon_C4_or_andn:
 302   qi_SInst_qi_andqiqi_neg         <"or",       int_hexagon_C4_or_andn>;
 303 def Hexagon_C4_or_and:
 304   qi_SInst_qi_andqiqi             <"or",       int_hexagon_C4_or_and>;
 305 def Hexagon_C4_or_orn:
 306   qi_SInst_qi_orqiqi_neg          <"or",       int_hexagon_C4_or_orn>;
 307 def Hexagon_C4_or_or:
 308   qi_SInst_qi_orqiqi              <"or",       int_hexagon_C4_or_or>;