lib/Target/Hexagon/HexagonInstrInfoV4.td

   1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let neverHasSideEffects = 1 in
  15 def IMMEXT : Immext<(outs), (ins),
  16                     "/* immext #... */",
  17                     []>,
  18              Requires<[HasV4T]>;
  19
  20 // Hexagon V4 Architecture spec defines 8 instruction classes:
  21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
  22 // compiler)
  23
  24 // LD Instructions:
  25 // ========================================
  26 // Loads (8/16/32/64 bit)
  27 // Deallocframe
  28
  29 // ST Instructions:
  30 // ========================================
  31 // Stores (8/16/32/64 bit)
  32 // Allocframe
  33
  34 // ALU32 Instructions:
  35 // ========================================
  36 // Arithmetic / Logical (32 bit)
  37 // Vector Halfword
  38
  39 // XTYPE Instructions (32/64 bit):
  40 // ========================================
  41 // Arithmetic, Logical, Bit Manipulation
  42 // Multiply (Integer, Fractional, Complex)
  43 // Permute / Vector Permute Operations
  44 // Predicate Operations
  45 // Shift / Shift with Add/Sub/Logical
  46 // Vector Byte ALU
  47 // Vector Halfword (ALU, Shift, Multiply)
  48 // Vector Word (ALU, Shift)
  49
  50 // J Instructions:
  51 // ========================================
  52 // Jump/Call PC-relative
  53
  54 // JR Instructions:
  55 // ========================================
  56 // Jump/Call Register
  57
  58 // MEMOP Instructions:
  59 // ========================================
  60 // Operation on memory (8/16/32 bit)
  61
  62 // NV Instructions:
  63 // ========================================
  64 // New-value Jumps
  65 // New-value Stores
  66
  67 // CR Instructions:
  68 // ========================================
  69 // Control-Register Transfers
  70 // Hardware Loop Setup
  71 // Predicate Logicals & Reductions
  72
  73 // SYSTEM Instructions (not implemented in the compiler):
  74 // ========================================
  75 // Prefetch
  76 // Cache Maintenance
  77 // Bus Operations
  78
  79
  80 //===----------------------------------------------------------------------===//
  81 // ALU32 +
  82 //===----------------------------------------------------------------------===//
  83
  84 // Shift halfword.
  85
  86 let isPredicated = 1 in
  87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  88             (ins PredRegs:$src1, IntRegs:$src2),
  89             "if ($src1) $dst = aslh($src2)",
  90             []>,
  91             Requires<[HasV4T]>;
  92
  93 let isPredicated = 1 in
  94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  95             (ins PredRegs:$src1, IntRegs:$src2),
  96             "if (!$src1) $dst = aslh($src2)",
  97             []>,
  98             Requires<[HasV4T]>;
  99
 100 let isPredicated = 1 in
 101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 102             (ins PredRegs:$src1, IntRegs:$src2),
 103             "if ($src1.new) $dst = aslh($src2)",
 104             []>,
 105             Requires<[HasV4T]>;
 106
 107 let isPredicated = 1 in
 108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 109             (ins PredRegs:$src1, IntRegs:$src2),
 110             "if (!$src1.new) $dst = aslh($src2)",
 111             []>,
 112             Requires<[HasV4T]>;
 113
 114 let isPredicated = 1 in
 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 116             (ins PredRegs:$src1, IntRegs:$src2),
 117             "if ($src1) $dst = asrh($src2)",
 118             []>,
 119             Requires<[HasV4T]>;
 120
 121 let isPredicated = 1 in
 122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 123             (ins PredRegs:$src1, IntRegs:$src2),
 124             "if (!$src1) $dst = asrh($src2)",
 125             []>,
 126             Requires<[HasV4T]>;
 127
 128 let isPredicated = 1 in
 129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 130             (ins PredRegs:$src1, IntRegs:$src2),
 131             "if ($src1.new) $dst = asrh($src2)",
 132             []>,
 133             Requires<[HasV4T]>;
 134
 135 let isPredicated = 1 in
 136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 137             (ins PredRegs:$src1, IntRegs:$src2),
 138             "if (!$src1.new) $dst = asrh($src2)",
 139             []>,
 140             Requires<[HasV4T]>;
 141
 142 // Sign extend.
 143
 144 let isPredicated = 1 in
 145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 146             (ins PredRegs:$src1, IntRegs:$src2),
 147             "if ($src1) $dst = sxtb($src2)",
 148             []>,
 149             Requires<[HasV4T]>;
 150
 151 let isPredicated = 1 in
 152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 153             (ins PredRegs:$src1, IntRegs:$src2),
 154             "if (!$src1) $dst = sxtb($src2)",
 155             []>,
 156             Requires<[HasV4T]>;
 157
 158 let isPredicated = 1 in
 159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 160             (ins PredRegs:$src1, IntRegs:$src2),
 161             "if ($src1.new) $dst = sxtb($src2)",
 162             []>,
 163             Requires<[HasV4T]>;
 164
 165 let isPredicated = 1 in
 166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 167             (ins PredRegs:$src1, IntRegs:$src2),
 168             "if (!$src1.new) $dst = sxtb($src2)",
 169             []>,
 170             Requires<[HasV4T]>;
 171
 172
 173 let isPredicated = 1 in
 174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 175             (ins PredRegs:$src1, IntRegs:$src2),
 176             "if ($src1) $dst = sxth($src2)",
 177             []>,
 178             Requires<[HasV4T]>;
 179
 180 let isPredicated = 1 in
 181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 182             (ins PredRegs:$src1, IntRegs:$src2),
 183             "if (!$src1) $dst = sxth($src2)",
 184             []>,
 185             Requires<[HasV4T]>;
 186
 187 let isPredicated = 1 in
 188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 189             (ins PredRegs:$src1, IntRegs:$src2),
 190             "if ($src1.new) $dst = sxth($src2)",
 191             []>,
 192             Requires<[HasV4T]>;
 193
 194 let isPredicated = 1 in
 195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 196             (ins PredRegs:$src1, IntRegs:$src2),
 197             "if (!$src1.new) $dst = sxth($src2)",
 198             []>,
 199             Requires<[HasV4T]>;
 200
 201 // Zero exten.
 202
 203 let neverHasSideEffects = 1, isPredicated = 1 in
 204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 205             (ins PredRegs:$src1, IntRegs:$src2),
 206             "if ($src1) $dst = zxtb($src2)",
 207             []>,
 208             Requires<[HasV4T]>;
 209
 210 let neverHasSideEffects = 1, isPredicated = 1 in
 211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 212             (ins PredRegs:$src1, IntRegs:$src2),
 213             "if (!$src1) $dst = zxtb($src2)",
 214             []>,
 215             Requires<[HasV4T]>;
 216
 217 let neverHasSideEffects = 1, isPredicated = 1 in
 218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 219             (ins PredRegs:$src1, IntRegs:$src2),
 220             "if ($src1.new) $dst = zxtb($src2)",
 221             []>,
 222             Requires<[HasV4T]>;
 223
 224 let neverHasSideEffects = 1, isPredicated = 1 in
 225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 226             (ins PredRegs:$src1, IntRegs:$src2),
 227             "if (!$src1.new) $dst = zxtb($src2)",
 228             []>,
 229             Requires<[HasV4T]>;
 230
 231 let neverHasSideEffects = 1, isPredicated = 1 in
 232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 233             (ins PredRegs:$src1, IntRegs:$src2),
 234             "if ($src1) $dst = zxth($src2)",
 235             []>,
 236             Requires<[HasV4T]>;
 237
 238 let neverHasSideEffects = 1, isPredicated = 1 in
 239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 240             (ins PredRegs:$src1, IntRegs:$src2),
 241             "if (!$src1) $dst = zxth($src2)",
 242             []>,
 243             Requires<[HasV4T]>;
 244
 245 let neverHasSideEffects = 1, isPredicated = 1 in
 246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 247             (ins PredRegs:$src1, IntRegs:$src2),
 248             "if ($src1.new) $dst = zxth($src2)",
 249             []>,
 250             Requires<[HasV4T]>;
 251
 252 let neverHasSideEffects = 1, isPredicated = 1 in
 253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 254             (ins PredRegs:$src1, IntRegs:$src2),
 255             "if (!$src1.new) $dst = zxth($src2)",
 256             []>,
 257             Requires<[HasV4T]>;
 258
 259 // Generate frame index addresses.
 260 let neverHasSideEffects = 1, isReMaterializable = 1 in
 261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
 262             (ins IntRegs:$src1, s32Imm:$offset),
 263             "$dst = add($src1, ##$offset)",
 264             []>,
 265             Requires<[HasV4T]>;
 266
 267
 268 //===----------------------------------------------------------------------===//
 269 // ALU32 -
 270 //===----------------------------------------------------------------------===//
 271
 272
 273 //===----------------------------------------------------------------------===//
 274 // ALU32/PERM +
 275 //===----------------------------------------------------------------------===//
 276
 277 // Combine
 278 // Rdd=combine(Rs, #s8)
 279 let neverHasSideEffects = 1 in
 280 def COMBINE_ri_V4 : ALU32_ri<(outs DoubleRegs:$dst),
 281             (ins IntRegs:$src1, s8Imm:$src2),
 282             "$dst = combine($src1, #$src2)",
 283             []>,
 284             Requires<[HasV4T]>;
 285 // Rdd=combine(#s8, Rs)
 286 let neverHasSideEffects = 1 in
 287 def COMBINE_ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 288             (ins s8Imm:$src1, IntRegs:$src2),
 289             "$dst = combine(#$src1, $src2)",
 290             []>,
 291             Requires<[HasV4T]>;
 292 //===----------------------------------------------------------------------===//
 293 // ALU32/PERM +
 294 //===----------------------------------------------------------------------===//
 295
 296 //===----------------------------------------------------------------------===//
 297 // LD +
 298 //===----------------------------------------------------------------------===//
 299 //
 300 // These absolute set addressing mode instructions accept immediate as
 301 // an operand. We have duplicated these patterns to take global address.
 302
 303 let neverHasSideEffects = 1 in
 304 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 305             (ins u6Imm:$addr),
 306             "$dst1 = memd($dst2=#$addr)",
 307             []>,
 308             Requires<[HasV4T]>;
 309
 310 // Rd=memb(Re=#U6)
 311 let neverHasSideEffects = 1 in
 312 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 313             (ins u6Imm:$addr),
 314             "$dst1 = memb($dst2=#$addr)",
 315             []>,
 316             Requires<[HasV4T]>;
 317
 318 // Rd=memh(Re=#U6)
 319 let neverHasSideEffects = 1 in
 320 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 321             (ins u6Imm:$addr),
 322             "$dst1 = memh($dst2=#$addr)",
 323             []>,
 324             Requires<[HasV4T]>;
 325
 326 // Rd=memub(Re=#U6)
 327 let neverHasSideEffects = 1 in
 328 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 329             (ins u6Imm:$addr),
 330             "$dst1 = memub($dst2=#$addr)",
 331             []>,
 332             Requires<[HasV4T]>;
 333
 334 // Rd=memuh(Re=#U6)
 335 let neverHasSideEffects = 1 in
 336 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 337             (ins u6Imm:$addr),
 338             "$dst1 = memuh($dst2=#$addr)",
 339             []>,
 340             Requires<[HasV4T]>;
 341
 342 // Rd=memw(Re=#U6)
 343 let neverHasSideEffects = 1 in
 344 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 345             (ins u6Imm:$addr),
 346             "$dst1 = memw($dst2=#$addr)",
 347             []>,
 348             Requires<[HasV4T]>;
 349
 350 // Following patterns are defined for absolute set addressing mode
 351 // instruction which take global address as operand.
 352 let neverHasSideEffects = 1 in
 353 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 354             (ins globaladdress:$addr),
 355             "$dst1 = memd($dst2=##$addr)",
 356             []>,
 357             Requires<[HasV4T]>;
 358
 359 // Rd=memb(Re=#U6)
 360 let neverHasSideEffects = 1 in
 361 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 362             (ins globaladdress:$addr),
 363             "$dst1 = memb($dst2=##$addr)",
 364             []>,
 365             Requires<[HasV4T]>;
 366
 367 // Rd=memh(Re=#U6)
 368 let neverHasSideEffects = 1 in
 369 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 370             (ins globaladdress:$addr),
 371             "$dst1 = memh($dst2=##$addr)",
 372             []>,
 373             Requires<[HasV4T]>;
 374
 375 // Rd=memub(Re=#U6)
 376 let neverHasSideEffects = 1 in
 377 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 378             (ins globaladdress:$addr),
 379             "$dst1 = memub($dst2=##$addr)",
 380             []>,
 381             Requires<[HasV4T]>;
 382
 383 // Rd=memuh(Re=#U6)
 384 let neverHasSideEffects = 1 in
 385 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 386             (ins globaladdress:$addr),
 387             "$dst1 = memuh($dst2=##$addr)",
 388             []>,
 389             Requires<[HasV4T]>;
 390
 391 // Rd=memw(Re=#U6)
 392 let neverHasSideEffects = 1 in
 393 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 394             (ins globaladdress:$addr),
 395             "$dst1 = memw($dst2=##$addr)",
 396             []>,
 397             Requires<[HasV4T]>;
 398
 399 // Load doubleword.
 400 //
 401 // Make sure that in post increment load, the first operand is always the post
 402 // increment operand.
 403 //
 404 // Rdd=memd(Rs+Rt<<#u2)
 405 // Special case pattern for indexed load without offset which is easier to
 406 // match. AddedComplexity of this pattern should be lower than base+offset load
 407 // and lower yet than the more generic version with offset/shift below
 408 // Similar approach is taken for all other base+index loads.
 409 let AddedComplexity = 10, isPredicable = 1 in
 410 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
 411                     (ins IntRegs:$src1, IntRegs:$src2),
 412                     "$dst=memd($src1+$src2<<#0)",
 413                     [(set (i64 DoubleRegs:$dst),
 414                           (i64 (load (add (i32 IntRegs:$src1),
 415                                           (i32 IntRegs:$src2)))))]>,
 416                     Requires<[HasV4T]>;
 417
 418 // multiclass for load instructions with base + register offset
 419 // addressing mode
 420 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
 421                              bit isPredNew> {
 422   let PNewValue = #!if(isPredNew, "new", "") in
 423   def #NAME# : LDInst2<(outs RC:$dst),
 424             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
 425             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
 426             ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
 427             []>, Requires<[HasV4T]>;
 428 }
 429
 430 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
 431   let PredSense = #!if(PredNot, "false", "true") in {
 432     defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
 433     // Predicate new
 434     defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
 435   }
 436 }
 437
 438 let neverHasSideEffects  = 1 in
 439 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
 440   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
 441     let isPredicable = 1 in
 442     def #NAME#_V4 : LDInst2<(outs RC:$dst),
 443             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 444             "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
 445             []>, Requires<[HasV4T]>;
 446
 447     let isPredicated = 1 in {
 448       defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
 449       defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
 450     }
 451   }
 452 }
 453
 454 let addrMode = BaseRegOffset in {
 455   defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
 456   defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
 457   defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
 458   defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
 459   defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
 460   defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
 461 }
 462
 463 // 'def pats' for load instructions with base + register offset and non-zero
 464 // immediate value. Immediate value is used to left-shift the second
 465 // register operand.
 466 let AddedComplexity = 40 in {
 467 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
 468                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 469            (LDrib_indexed_shl_V4 IntRegs:$src1,
 470             IntRegs:$src2, u2ImmPred:$offset)>,
 471             Requires<[HasV4T]>;
 472
 473 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
 474                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 475            (LDriub_indexed_shl_V4 IntRegs:$src1,
 476             IntRegs:$src2, u2ImmPred:$offset)>,
 477             Requires<[HasV4T]>;
 478
 479 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
 480                                 (shl IntRegs:$src2, u2ImmPred:$offset)))),
 481            (LDriub_indexed_shl_V4 IntRegs:$src1,
 482             IntRegs:$src2, u2ImmPred:$offset)>,
 483             Requires<[HasV4T]>;
 484
 485 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
 486                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 487            (LDrih_indexed_shl_V4 IntRegs:$src1,
 488             IntRegs:$src2, u2ImmPred:$offset)>,
 489             Requires<[HasV4T]>;
 490
 491 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
 492                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 493            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 494             IntRegs:$src2, u2ImmPred:$offset)>,
 495             Requires<[HasV4T]>;
 496
 497 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
 498                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 499            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 500             IntRegs:$src2, u2ImmPred:$offset)>,
 501             Requires<[HasV4T]>;
 502
 503 def : Pat <(i32 (load (add IntRegs:$src1,
 504                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 505            (LDriw_indexed_shl_V4 IntRegs:$src1,
 506             IntRegs:$src2, u2ImmPred:$offset)>,
 507             Requires<[HasV4T]>;
 508
 509 def : Pat <(i64 (load (add IntRegs:$src1,
 510                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 511            (LDrid_indexed_shl_V4 IntRegs:$src1,
 512             IntRegs:$src2, u2ImmPred:$offset)>,
 513             Requires<[HasV4T]>;
 514 }
 515
 516 //// Load doubleword conditionally.
 517 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
 518 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 519 let AddedComplexity = 15, isPredicated = 1 in
 520 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 521                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 522                     "if ($src1) $dst=memd($src2+$src3<<#0)",
 523                     []>,
 524                     Requires<[HasV4T]>;
 525
 526 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 527 let AddedComplexity = 15, isPredicated = 1 in
 528 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 529                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 530                     "if ($src1.new) $dst=memd($src2+$src3<<#0)",
 531                     []>,
 532                     Requires<[HasV4T]>;
 533
 534 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 535 let AddedComplexity = 15, isPredicated = 1 in
 536 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 537                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 538                     "if (!$src1) $dst=memd($src2+$src3<<#0)",
 539                     []>,
 540                     Requires<[HasV4T]>;
 541
 542 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 543 let AddedComplexity = 15, isPredicated = 1 in
 544 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 545                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 546                     "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
 547                     []>,
 548                     Requires<[HasV4T]>;
 549
 550 // Rdd=memd(Rt<<#u2+#U6)
 551
 552 //// Load byte.
 553 // Rd=memb(Rs+Rt<<#u2)
 554 let AddedComplexity = 10, isPredicable = 1 in
 555 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
 556                     (ins IntRegs:$src1, IntRegs:$src2),
 557                     "$dst=memb($src1+$src2<<#0)",
 558                     [(set (i32 IntRegs:$dst),
 559                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 560                                                 (i32 IntRegs:$src2)))))]>,
 561                     Requires<[HasV4T]>;
 562
 563 let AddedComplexity = 10, isPredicable = 1 in
 564 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
 565                     (ins IntRegs:$src1, IntRegs:$src2),
 566                     "$dst=memub($src1+$src2<<#0)",
 567                     [(set (i32 IntRegs:$dst),
 568                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 569                                                 (i32 IntRegs:$src2)))))]>,
 570                     Requires<[HasV4T]>;
 571
 572 let AddedComplexity = 10, isPredicable = 1 in
 573 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 574                     (ins IntRegs:$src1, IntRegs:$src2),
 575                     "$dst=memub($src1+$src2<<#0)",
 576                     [(set (i32 IntRegs:$dst),
 577                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 578                                                (i32 IntRegs:$src2)))))]>,
 579                     Requires<[HasV4T]>;
 580
 581 let AddedComplexity = 40, isPredicable = 1 in
 582 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 583                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 584                     "$dst=memub($src1+$src2<<#$offset)",
 585                     [(set (i32 IntRegs:$dst),
 586                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 587                                                (shl (i32 IntRegs:$src2),
 588                                                     u2ImmPred:$offset)))))]>,
 589                     Requires<[HasV4T]>;
 590
 591 //// Load byte conditionally.
 592 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
 593 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 594 let AddedComplexity = 15, isPredicated = 1 in
 595 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 596                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 597                     "if ($src1) $dst=memb($src2+$src3<<#0)",
 598                     []>,
 599                     Requires<[HasV4T]>;
 600
 601 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 602 let AddedComplexity = 15, isPredicated = 1 in
 603 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 604                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 605                     "if ($src1.new) $dst=memb($src2+$src3<<#0)",
 606                     []>,
 607                     Requires<[HasV4T]>;
 608
 609 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 610 let AddedComplexity = 15, isPredicated = 1 in
 611 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 612                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 613                     "if (!$src1) $dst=memb($src2+$src3<<#0)",
 614                     []>,
 615                     Requires<[HasV4T]>;
 616
 617 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 618 let AddedComplexity = 15, isPredicated = 1 in
 619 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 620                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 621                     "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
 622                     []>,
 623                     Requires<[HasV4T]>;
 624
 625 //// Load unsigned byte conditionally.
 626 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
 627 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 628 let AddedComplexity = 15, isPredicated = 1 in
 629 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 630                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 631                     "if ($src1) $dst=memub($src2+$src3<<#0)",
 632                     []>,
 633                     Requires<[HasV4T]>;
 634
 635 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 636 let AddedComplexity = 15, isPredicated = 1 in
 637 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 638                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 639                     "if ($src1.new) $dst=memub($src2+$src3<<#0)",
 640                     []>,
 641                     Requires<[HasV4T]>;
 642
 643 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 644 let AddedComplexity = 15, isPredicated = 1 in
 645 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 646                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 647                     "if (!$src1) $dst=memub($src2+$src3<<#0)",
 648                     []>,
 649                     Requires<[HasV4T]>;
 650
 651 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 652 let AddedComplexity = 15, isPredicated = 1 in
 653 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 654                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 655                     "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
 656                     []>,
 657                     Requires<[HasV4T]>;
 658
 659 // Rd=memb(Rt<<#u2+#U6)
 660
 661 //// Load halfword
 662 // Rd=memh(Rs+Rt<<#u2)
 663 let AddedComplexity = 10, isPredicable = 1 in
 664 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
 665                     (ins IntRegs:$src1, IntRegs:$src2),
 666                     "$dst=memh($src1+$src2<<#0)",
 667                     [(set (i32 IntRegs:$dst),
 668                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 669                                                  (i32 IntRegs:$src2)))))]>,
 670                     Requires<[HasV4T]>;
 671
 672 let AddedComplexity = 10, isPredicable = 1 in
 673 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
 674                     (ins IntRegs:$src1, IntRegs:$src2),
 675                     "$dst=memuh($src1+$src2<<#0)",
 676                     [(set (i32 IntRegs:$dst),
 677                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 678                                                  (i32 IntRegs:$src2)))))]>,
 679                     Requires<[HasV4T]>;
 680
 681 let AddedComplexity = 10, isPredicable = 1 in
 682 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 683                     (ins IntRegs:$src1, IntRegs:$src2),
 684                     "$dst=memuh($src1+$src2<<#0)",
 685                     [(set (i32 IntRegs:$dst),
 686                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 687                                                 (i32 IntRegs:$src2)))))]>,
 688                     Requires<[HasV4T]>;
 689
 690 let AddedComplexity = 40, isPredicable = 1 in
 691 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 692                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 693                     "$dst=memuh($src1+$src2<<#$offset)",
 694                     [(set (i32 IntRegs:$dst),
 695                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 696                                                 (shl (i32 IntRegs:$src2),
 697                                                      u2ImmPred:$offset)))))]>,
 698                     Requires<[HasV4T]>;
 699
 700 //// Load halfword conditionally.
 701 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
 702 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 703 let AddedComplexity = 15, isPredicated = 1 in
 704 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 705                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 706                     "if ($src1) $dst=memh($src2+$src3<<#0)",
 707                     []>,
 708                     Requires<[HasV4T]>;
 709
 710 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 711 let AddedComplexity = 15, isPredicated = 1 in
 712 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 713                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 714                     "if ($src1.new) $dst=memh($src2+$src3<<#0)",
 715                     []>,
 716                     Requires<[HasV4T]>;
 717
 718 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 719 let AddedComplexity = 15, isPredicated = 1 in
 720 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 721                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 722                     "if (!$src1) $dst=memh($src2+$src3<<#0)",
 723                     []>,
 724                     Requires<[HasV4T]>;
 725
 726 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 727 let AddedComplexity = 15, isPredicated = 1 in
 728 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 729                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 730                     "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
 731                     []>,
 732                     Requires<[HasV4T]>;
 733
 734 //// Load unsigned halfword conditionally.
 735 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
 736 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 737 let AddedComplexity = 15, isPredicated = 1 in
 738 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 739                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 740                     "if ($src1) $dst=memuh($src2+$src3<<#0)",
 741                     []>,
 742                     Requires<[HasV4T]>;
 743
 744 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 745 let AddedComplexity = 15, isPredicated = 1 in
 746 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 747                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 748                     "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
 749                     []>,
 750                     Requires<[HasV4T]>;
 751
 752 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 753 let AddedComplexity = 15, isPredicated = 1 in
 754 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 755                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 756                     "if (!$src1) $dst=memuh($src2+$src3<<#0)",
 757                     []>,
 758                     Requires<[HasV4T]>;
 759
 760 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 761 let AddedComplexity = 15, isPredicated = 1 in
 762 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 763                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 764                     "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
 765                     []>,
 766                     Requires<[HasV4T]>;
 767
 768 // Rd=memh(Rt<<#u2+#U6)
 769
 770 //// Load word.
 771 // Load predicate: Fix for bug 5279.
 772 let neverHasSideEffects = 1 in
 773 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
 774             (ins MEMri:$addr),
 775             "Error; should not emit",
 776             []>,
 777             Requires<[HasV4T]>;
 778
 779 // Rd=memw(Re=#U6)
 780
 781 // Rd=memw(Rs+Rt<<#u2)
 782 let AddedComplexity = 10, isPredicable = 1 in
 783 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
 784                     (ins IntRegs:$src1, IntRegs:$src2),
 785                     "$dst=memw($src1+$src2<<#0)",
 786                     [(set (i32 IntRegs:$dst),
 787                           (i32 (load (add (i32 IntRegs:$src1),
 788                                           (i32 IntRegs:$src2)))))]>,
 789                     Requires<[HasV4T]>;
 790
 791 //// Load word conditionally.
 792 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
 793 // if (Pv) Rd=memw(Rs+Rt<<#u2)
 794 let AddedComplexity = 15, isPredicated = 1 in
 795 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 796                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 797                     "if ($src1) $dst=memw($src2+$src3<<#0)",
 798                     []>,
 799                     Requires<[HasV4T]>;
 800
 801 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 802 let AddedComplexity = 15, isPredicated = 1 in
 803 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 804                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 805                     "if ($src1.new) $dst=memw($src2+$src3<<#0)",
 806                     []>,
 807                     Requires<[HasV4T]>;
 808
 809 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 810 let AddedComplexity = 15, isPredicated = 1 in
 811 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 812                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 813                     "if (!$src1) $dst=memw($src2+$src3<<#0)",
 814                     []>,
 815                     Requires<[HasV4T]>;
 816
 817 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 818 let AddedComplexity = 15, isPredicated = 1 in
 819 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 820                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 821                     "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
 822                     []>,
 823                     Requires<[HasV4T]>;
 824
 825 /// Load from global offset
 826
 827 let isPredicable = 1, neverHasSideEffects = 1 in
 828 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
 829             (ins globaladdress:$global, u16Imm:$offset),
 830             "$dst=memd(#$global+$offset)",
 831             []>,
 832             Requires<[HasV4T]>;
 833
 834 let neverHasSideEffects = 1, isPredicated = 1 in
 835 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 836             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 837             "if ($src1) $dst=memd(##$global+$offset)",
 838             []>,
 839             Requires<[HasV4T]>;
 840
 841 let neverHasSideEffects = 1, isPredicated = 1 in
 842 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 843             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 844             "if (!$src1) $dst=memd(##$global+$offset)",
 845             []>,
 846             Requires<[HasV4T]>;
 847
 848 let neverHasSideEffects = 1, isPredicated = 1 in
 849 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 850             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 851             "if ($src1.new) $dst=memd(##$global+$offset)",
 852             []>,
 853             Requires<[HasV4T]>;
 854
 855 let neverHasSideEffects = 1, isPredicated = 1 in
 856 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 857             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 858             "if (!$src1.new) $dst=memd(##$global+$offset)",
 859             []>,
 860             Requires<[HasV4T]>;
 861
 862 let isPredicable = 1, neverHasSideEffects = 1 in
 863 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
 864             (ins globaladdress:$global, u16Imm:$offset),
 865             "$dst=memb(#$global+$offset)",
 866             []>,
 867             Requires<[HasV4T]>;
 868
 869 let neverHasSideEffects = 1, isPredicated = 1 in
 870 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 871             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 872             "if ($src1) $dst=memb(##$global+$offset)",
 873             []>,
 874             Requires<[HasV4T]>;
 875
 876 let neverHasSideEffects = 1, isPredicated = 1 in
 877 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 878             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 879             "if (!$src1) $dst=memb(##$global+$offset)",
 880             []>,
 881             Requires<[HasV4T]>;
 882
 883 let neverHasSideEffects = 1, isPredicated = 1 in
 884 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 885             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 886             "if ($src1.new) $dst=memb(##$global+$offset)",
 887             []>,
 888             Requires<[HasV4T]>;
 889
 890 let neverHasSideEffects = 1, isPredicated = 1 in
 891 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 892             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 893             "if (!$src1.new) $dst=memb(##$global+$offset)",
 894             []>,
 895             Requires<[HasV4T]>;
 896
 897
 898 let isPredicable = 1, neverHasSideEffects = 1 in
 899 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
 900             (ins globaladdress:$global, u16Imm:$offset),
 901             "$dst=memub(#$global+$offset)",
 902             []>,
 903             Requires<[HasV4T]>;
 904
 905
 906 let neverHasSideEffects = 1, isPredicated = 1 in
 907 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 908             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 909             "if ($src1) $dst=memub(##$global+$offset)",
 910             []>,
 911             Requires<[HasV4T]>;
 912
 913 let neverHasSideEffects = 1, isPredicated = 1 in
 914 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 915             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 916             "if (!$src1) $dst=memub(##$global+$offset)",
 917             []>,
 918             Requires<[HasV4T]>;
 919
 920 let neverHasSideEffects = 1, isPredicated = 1 in
 921 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 922             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 923             "if ($src1.new) $dst=memub(##$global+$offset)",
 924             []>,
 925             Requires<[HasV4T]>;
 926
 927 let neverHasSideEffects = 1, isPredicated = 1 in
 928 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 929             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 930             "if (!$src1.new) $dst=memub(##$global+$offset)",
 931             []>,
 932             Requires<[HasV4T]>;
 933
 934
 935 let isPredicable = 1, neverHasSideEffects = 1 in
 936 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
 937             (ins globaladdress:$global, u16Imm:$offset),
 938             "$dst=memh(#$global+$offset)",
 939             []>,
 940             Requires<[HasV4T]>;
 941
 942
 943 let neverHasSideEffects = 1, isPredicated = 1 in
 944 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 945             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 946             "if ($src1) $dst=memh(##$global+$offset)",
 947             []>,
 948             Requires<[HasV4T]>;
 949
 950 let neverHasSideEffects = 1, isPredicated = 1 in
 951 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 952             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 953             "if (!$src1) $dst=memh(##$global+$offset)",
 954             []>,
 955             Requires<[HasV4T]>;
 956
 957 let neverHasSideEffects = 1, isPredicated = 1 in
 958 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 959             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 960             "if ($src1.new) $dst=memh(##$global+$offset)",
 961             []>,
 962             Requires<[HasV4T]>;
 963
 964 let neverHasSideEffects = 1, isPredicated = 1 in
 965 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 966             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 967             "if (!$src1.new) $dst=memh(##$global+$offset)",
 968             []>,
 969             Requires<[HasV4T]>;
 970
 971
 972 let isPredicable = 1, neverHasSideEffects = 1 in
 973 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
 974             (ins globaladdress:$global, u16Imm:$offset),
 975             "$dst=memuh(#$global+$offset)",
 976             []>,
 977             Requires<[HasV4T]>;
 978
 979 let neverHasSideEffects = 1, isPredicated = 1 in
 980 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 981             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 982             "if ($src1) $dst=memuh(##$global+$offset)",
 983             []>,
 984             Requires<[HasV4T]>;
 985
 986 let neverHasSideEffects = 1, isPredicated = 1 in
 987 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 988             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 989             "if (!$src1) $dst=memuh(##$global+$offset)",
 990             []>,
 991             Requires<[HasV4T]>;
 992
 993 let neverHasSideEffects = 1, isPredicated = 1 in
 994 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 995             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 996             "if ($src1.new) $dst=memuh(##$global+$offset)",
 997             []>,
 998             Requires<[HasV4T]>;
 999
1000 let neverHasSideEffects = 1, isPredicated = 1 in
1001 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1002             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1003             "if (!$src1.new) $dst=memuh(##$global+$offset)",
1004             []>,
1005             Requires<[HasV4T]>;
1006
1007 let isPredicable = 1, neverHasSideEffects = 1 in
1008 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1009             (ins globaladdress:$global, u16Imm:$offset),
1010             "$dst=memw(#$global+$offset)",
1011             []>,
1012             Requires<[HasV4T]>;
1013
1014
1015 let neverHasSideEffects = 1, isPredicated = 1 in
1016 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1017             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1018             "if ($src1) $dst=memw(##$global+$offset)",
1019             []>,
1020             Requires<[HasV4T]>;
1021
1022 let neverHasSideEffects = 1, isPredicated = 1 in
1023 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1024             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1025             "if (!$src1) $dst=memw(##$global+$offset)",
1026             []>,
1027             Requires<[HasV4T]>;
1028
1029
1030 let neverHasSideEffects = 1, isPredicated = 1 in
1031 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1032             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1033             "if ($src1.new) $dst=memw(##$global+$offset)",
1034             []>,
1035             Requires<[HasV4T]>;
1036
1037 let neverHasSideEffects = 1, isPredicated = 1 in
1038 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1039             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1040             "if (!$src1.new) $dst=memw(##$global+$offset)",
1041             []>,
1042             Requires<[HasV4T]>;
1043
1044
1045 let isPredicable = 1, neverHasSideEffects = 1 in
1046 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1047             (ins globaladdress:$global),
1048             "$dst=memd(#$global)",
1049             []>,
1050             Requires<[HasV4T]>;
1051
1052 // if (Pv) Rtt=memd(##global)
1053 let neverHasSideEffects = 1, isPredicated = 1 in
1054 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1055             (ins PredRegs:$src1, globaladdress:$global),
1056             "if ($src1) $dst=memd(##$global)",
1057             []>,
1058             Requires<[HasV4T]>;
1059
1060
1061 // if (!Pv) Rtt=memd(##global)
1062 let neverHasSideEffects = 1, isPredicated = 1 in
1063 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1064             (ins PredRegs:$src1, globaladdress:$global),
1065             "if (!$src1) $dst=memd(##$global)",
1066             []>,
1067             Requires<[HasV4T]>;
1068
1069 // if (Pv) Rtt=memd(##global)
1070 let neverHasSideEffects = 1, isPredicated = 1 in
1071 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1072             (ins PredRegs:$src1, globaladdress:$global),
1073             "if ($src1.new) $dst=memd(##$global)",
1074             []>,
1075             Requires<[HasV4T]>;
1076
1077
1078 // if (!Pv) Rtt=memd(##global)
1079 let neverHasSideEffects = 1, isPredicated = 1 in
1080 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1081             (ins PredRegs:$src1, globaladdress:$global),
1082             "if (!$src1.new) $dst=memd(##$global)",
1083             []>,
1084             Requires<[HasV4T]>;
1085
1086 let isPredicable = 1, neverHasSideEffects = 1 in
1087 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1088             (ins globaladdress:$global),
1089             "$dst=memb(#$global)",
1090             []>,
1091             Requires<[HasV4T]>;
1092
1093 // if (Pv) Rt=memb(##global)
1094 let neverHasSideEffects = 1, isPredicated = 1 in
1095 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1096             (ins PredRegs:$src1, globaladdress:$global),
1097             "if ($src1) $dst=memb(##$global)",
1098             []>,
1099             Requires<[HasV4T]>;
1100
1101 // if (!Pv) Rt=memb(##global)
1102 let neverHasSideEffects = 1, isPredicated = 1 in
1103 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1104             (ins PredRegs:$src1, globaladdress:$global),
1105             "if (!$src1) $dst=memb(##$global)",
1106             []>,
1107             Requires<[HasV4T]>;
1108
1109 // if (Pv) Rt=memb(##global)
1110 let neverHasSideEffects = 1, isPredicated = 1 in
1111 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1112             (ins PredRegs:$src1, globaladdress:$global),
1113             "if ($src1.new) $dst=memb(##$global)",
1114             []>,
1115             Requires<[HasV4T]>;
1116
1117 // if (!Pv) Rt=memb(##global)
1118 let neverHasSideEffects = 1, isPredicated = 1 in
1119 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1120             (ins PredRegs:$src1, globaladdress:$global),
1121             "if (!$src1.new) $dst=memb(##$global)",
1122             []>,
1123             Requires<[HasV4T]>;
1124
1125 let isPredicable = 1, neverHasSideEffects = 1 in
1126 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1127             (ins globaladdress:$global),
1128             "$dst=memub(#$global)",
1129             []>,
1130             Requires<[HasV4T]>;
1131
1132 // if (Pv) Rt=memub(##global)
1133 let neverHasSideEffects = 1, isPredicated = 1 in
1134 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1135             (ins PredRegs:$src1, globaladdress:$global),
1136             "if ($src1) $dst=memub(##$global)",
1137             []>,
1138             Requires<[HasV4T]>;
1139
1140
1141 // if (!Pv) Rt=memub(##global)
1142 let neverHasSideEffects = 1, isPredicated = 1 in
1143 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1144             (ins PredRegs:$src1, globaladdress:$global),
1145             "if (!$src1) $dst=memub(##$global)",
1146             []>,
1147             Requires<[HasV4T]>;
1148
1149 // if (Pv) Rt=memub(##global)
1150 let neverHasSideEffects = 1, isPredicated = 1 in
1151 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1152             (ins PredRegs:$src1, globaladdress:$global),
1153             "if ($src1.new) $dst=memub(##$global)",
1154             []>,
1155             Requires<[HasV4T]>;
1156
1157
1158 // if (!Pv) Rt=memub(##global)
1159 let neverHasSideEffects = 1, isPredicated = 1 in
1160 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1161             (ins PredRegs:$src1, globaladdress:$global),
1162             "if (!$src1.new) $dst=memub(##$global)",
1163             []>,
1164             Requires<[HasV4T]>;
1165
1166 let isPredicable = 1, neverHasSideEffects = 1 in
1167 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1168             (ins globaladdress:$global),
1169             "$dst=memh(#$global)",
1170             []>,
1171             Requires<[HasV4T]>;
1172
1173 // if (Pv) Rt=memh(##global)
1174 let neverHasSideEffects = 1, isPredicated = 1 in
1175 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1176             (ins PredRegs:$src1, globaladdress:$global),
1177             "if ($src1) $dst=memh(##$global)",
1178             []>,
1179             Requires<[HasV4T]>;
1180
1181 // if (!Pv) Rt=memh(##global)
1182 let neverHasSideEffects = 1, isPredicated = 1 in
1183 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1184             (ins PredRegs:$src1, globaladdress:$global),
1185             "if (!$src1) $dst=memh(##$global)",
1186             []>,
1187             Requires<[HasV4T]>;
1188
1189 // if (Pv) Rt=memh(##global)
1190 let neverHasSideEffects = 1, isPredicated = 1 in
1191 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1192             (ins PredRegs:$src1, globaladdress:$global),
1193             "if ($src1.new) $dst=memh(##$global)",
1194             []>,
1195             Requires<[HasV4T]>;
1196
1197 // if (!Pv) Rt=memh(##global)
1198 let neverHasSideEffects = 1, isPredicated = 1 in
1199 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1200             (ins PredRegs:$src1, globaladdress:$global),
1201             "if (!$src1.new) $dst=memh(##$global)",
1202             []>,
1203             Requires<[HasV4T]>;
1204
1205 let isPredicable = 1, neverHasSideEffects = 1 in
1206 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1207             (ins globaladdress:$global),
1208             "$dst=memuh(#$global)",
1209             []>,
1210             Requires<[HasV4T]>;
1211
1212 // if (Pv) Rt=memuh(##global)
1213 let neverHasSideEffects = 1, isPredicated = 1 in
1214 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1215             (ins PredRegs:$src1, globaladdress:$global),
1216             "if ($src1) $dst=memuh(##$global)",
1217             []>,
1218             Requires<[HasV4T]>;
1219
1220 // if (!Pv) Rt=memuh(##global)
1221 let neverHasSideEffects = 1, isPredicated = 1 in
1222 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1223             (ins PredRegs:$src1, globaladdress:$global),
1224             "if (!$src1) $dst=memuh(##$global)",
1225             []>,
1226             Requires<[HasV4T]>;
1227
1228 // if (Pv) Rt=memuh(##global)
1229 let neverHasSideEffects = 1, isPredicated = 1 in
1230 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1231             (ins PredRegs:$src1, globaladdress:$global),
1232             "if ($src1.new) $dst=memuh(##$global)",
1233             []>,
1234             Requires<[HasV4T]>;
1235
1236 // if (!Pv) Rt=memuh(##global)
1237 let neverHasSideEffects = 1, isPredicated = 1 in
1238 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1239             (ins PredRegs:$src1, globaladdress:$global),
1240             "if (!$src1.new) $dst=memuh(##$global)",
1241             []>,
1242             Requires<[HasV4T]>;
1243
1244 let isPredicable = 1, neverHasSideEffects = 1 in
1245 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1246             (ins globaladdress:$global),
1247             "$dst=memw(#$global)",
1248             []>,
1249             Requires<[HasV4T]>;
1250
1251 // if (Pv) Rt=memw(##global)
1252 let neverHasSideEffects = 1, isPredicated = 1 in
1253 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1254             (ins PredRegs:$src1, globaladdress:$global),
1255             "if ($src1) $dst=memw(##$global)",
1256             []>,
1257             Requires<[HasV4T]>;
1258
1259
1260 // if (!Pv) Rt=memw(##global)
1261 let neverHasSideEffects = 1, isPredicated = 1 in
1262 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1263             (ins PredRegs:$src1, globaladdress:$global),
1264             "if (!$src1) $dst=memw(##$global)",
1265             []>,
1266             Requires<[HasV4T]>;
1267
1268 // if (Pv) Rt=memw(##global)
1269 let neverHasSideEffects = 1, isPredicated = 1 in
1270 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1271             (ins PredRegs:$src1, globaladdress:$global),
1272             "if ($src1.new) $dst=memw(##$global)",
1273             []>,
1274             Requires<[HasV4T]>;
1275
1276
1277 // if (!Pv) Rt=memw(##global)
1278 let neverHasSideEffects = 1, isPredicated = 1 in
1279 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1280             (ins PredRegs:$src1, globaladdress:$global),
1281             "if (!$src1.new) $dst=memw(##$global)",
1282             []>,
1283             Requires<[HasV4T]>;
1284
1285
1286
1287 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1288            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1289             Requires<[HasV4T]>;
1290
1291 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1292            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1293             Requires<[HasV4T]>;
1294
1295 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1296            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1297             Requires<[HasV4T]>;
1298
1299 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1300            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1301             Requires<[HasV4T]>;
1302
1303 // Map from load(globaladdress) -> memw(#foo + 0)
1304 let AddedComplexity = 100 in
1305 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1306            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1307             Requires<[HasV4T]>;
1308
1309 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1310 let AddedComplexity = 100 in
1311 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1312            (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1313            Requires<[HasV4T]>;
1314
1315 // When the Interprocedural Global Variable optimizer realizes that a certain
1316 // global variable takes only two constant values, it shrinks the global to
1317 // a boolean. Catch those loads here in the following 3 patterns.
1318 let AddedComplexity = 100 in
1319 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1320            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1321             Requires<[HasV4T]>;
1322
1323 let AddedComplexity = 100 in
1324 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1325            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1326             Requires<[HasV4T]>;
1327
1328 // Map from load(globaladdress) -> memb(#foo)
1329 let AddedComplexity = 100 in
1330 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1331            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1332             Requires<[HasV4T]>;
1333
1334 // Map from load(globaladdress) -> memb(#foo)
1335 let AddedComplexity = 100 in
1336 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1337            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1338             Requires<[HasV4T]>;
1339
1340 let AddedComplexity = 100 in
1341 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1342            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1343             Requires<[HasV4T]>;
1344
1345 // Map from load(globaladdress) -> memub(#foo)
1346 let AddedComplexity = 100 in
1347 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1348            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1349             Requires<[HasV4T]>;
1350
1351 // Map from load(globaladdress) -> memh(#foo)
1352 let AddedComplexity = 100 in
1353 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1354            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1355             Requires<[HasV4T]>;
1356
1357 // Map from load(globaladdress) -> memh(#foo)
1358 let AddedComplexity = 100 in
1359 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1360            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1361             Requires<[HasV4T]>;
1362
1363 // Map from load(globaladdress) -> memuh(#foo)
1364 let AddedComplexity = 100 in
1365 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1366            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1367             Requires<[HasV4T]>;
1368
1369 // Map from load(globaladdress) -> memw(#foo)
1370 let AddedComplexity = 100 in
1371 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1372            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1373             Requires<[HasV4T]>;
1374
1375 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1376                                 u16ImmPred:$offset)),
1377            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1378            Requires<[HasV4T]>;
1379
1380 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1381                                 u16ImmPred:$offset)),
1382            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1383             Requires<[HasV4T]>;
1384
1385 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1386                                 u16ImmPred:$offset)),
1387            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1388             Requires<[HasV4T]>;
1389
1390 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1391                                u16ImmPred:$offset)),
1392            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1393            Requires<[HasV4T]>;
1394
1395 // Map from load(globaladdress + x) -> memd(#foo + x)
1396 let AddedComplexity = 100 in
1397 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1398                            u16ImmPred:$offset))),
1399            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1400            Requires<[HasV4T]>;
1401
1402 // Map from load(globaladdress + x) -> memb(#foo + x)
1403 let AddedComplexity = 100 in
1404 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1405                            u16ImmPred:$offset))),
1406            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1407            Requires<[HasV4T]>;
1408
1409 // Map from load(globaladdress + x) -> memb(#foo + x)
1410 let AddedComplexity = 100 in
1411 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1412                             u16ImmPred:$offset))),
1413            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1414            Requires<[HasV4T]>;
1415
1416 // Map from load(globaladdress + x) -> memub(#foo + x)
1417 let AddedComplexity = 100 in
1418 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1419                             u16ImmPred:$offset))),
1420            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1421            Requires<[HasV4T]>;
1422
1423 // Map from load(globaladdress + x) -> memuh(#foo + x)
1424 let AddedComplexity = 100 in
1425 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1426                             u16ImmPred:$offset))),
1427            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1428             Requires<[HasV4T]>;
1429
1430 // Map from load(globaladdress + x) -> memh(#foo + x)
1431 let AddedComplexity = 100 in
1432 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1433                              u16ImmPred:$offset))),
1434            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1435            Requires<[HasV4T]>;
1436
1437
1438 // Map from load(globaladdress + x) -> memuh(#foo + x)
1439 let AddedComplexity = 100 in
1440 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1441                              u16ImmPred:$offset))),
1442            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1443             Requires<[HasV4T]>;
1444
1445 // Map from load(globaladdress + x) -> memw(#foo + x)
1446 let AddedComplexity = 100 in
1447 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1448                       u16ImmPred:$offset))),
1449            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1450             Requires<[HasV4T]>;
1451
1452
1453 //===----------------------------------------------------------------------===//
1454 // LD -
1455 //===----------------------------------------------------------------------===//
1456
1457 //===----------------------------------------------------------------------===//
1458 // ST +
1459 //===----------------------------------------------------------------------===//
1460 ///
1461 /// Assumptions::: ****** DO NOT IGNORE ********
1462 /// 1. Make sure that in post increment store, the zero'th operand is always the
1463 ///    post increment operand.
1464 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1465 ///    last operand.
1466 ///
1467
1468 // memd(Re=#U6)=Rtt
1469 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1470             (ins DoubleRegs:$src1, u6Imm:$src2),
1471             "memd($dst1=#$src2) = $src1",
1472             []>,
1473             Requires<[HasV4T]>;
1474
1475 // memb(Re=#U6)=Rs
1476 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1477             (ins IntRegs:$src1, u6Imm:$src2),
1478             "memb($dst1=#$src2) = $src1",
1479             []>,
1480             Requires<[HasV4T]>;
1481
1482 // memh(Re=#U6)=Rs
1483 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1484             (ins IntRegs:$src1, u6Imm:$src2),
1485             "memh($dst1=#$src2) = $src1",
1486             []>,
1487             Requires<[HasV4T]>;
1488
1489 // memw(Re=#U6)=Rs
1490 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1491             (ins IntRegs:$src1, u6Imm:$src2),
1492             "memw($dst1=#$src2) = $src1",
1493             []>,
1494             Requires<[HasV4T]>;
1495
1496 // memd(Re=#U6)=Rtt
1497 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1498             (ins DoubleRegs:$src1, globaladdress:$src2),
1499             "memd($dst1=##$src2) = $src1",
1500             []>,
1501             Requires<[HasV4T]>;
1502
1503 // memb(Re=#U6)=Rs
1504 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1505             (ins IntRegs:$src1, globaladdress:$src2),
1506             "memb($dst1=##$src2) = $src1",
1507             []>,
1508             Requires<[HasV4T]>;
1509
1510 // memh(Re=#U6)=Rs
1511 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1512             (ins IntRegs:$src1, globaladdress:$src2),
1513             "memh($dst1=##$src2) = $src1",
1514             []>,
1515             Requires<[HasV4T]>;
1516
1517 // memw(Re=#U6)=Rs
1518 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1519             (ins IntRegs:$src1, globaladdress:$src2),
1520             "memw($dst1=##$src2) = $src1",
1521             []>,
1522             Requires<[HasV4T]>;
1523
1524 // memd(Rs+Ru<<#u2)=Rtt
1525 let AddedComplexity = 10, isPredicable = 1 in
1526 def STrid_indexed_shl_V4 : STInst<(outs),
1527             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),
1528             "memd($src1+$src2<<#$src3) = $src4",
1529             [(store (i64 DoubleRegs:$src4),
1530                     (add (i32 IntRegs:$src1),
1531                          (shl (i32 IntRegs:$src2), u2ImmPred:$src3)))]>,
1532             Requires<[HasV4T]>;
1533
1534 // memd(Ru<<#u2+#U6)=Rtt
1535 let AddedComplexity = 10 in
1536 def STrid_shl_V4 : STInst<(outs),
1537             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1538             "memd($src1<<#$src2+#$src3) = $src4",
1539             [(store (i64 DoubleRegs:$src4),
1540                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1541                          u6ImmPred:$src3))]>,
1542             Requires<[HasV4T]>;
1543
1544 // memd(Rx++#s4:3)=Rtt
1545 // memd(Rx++#s4:3:circ(Mu))=Rtt
1546 // memd(Rx++I:circ(Mu))=Rtt
1547 // memd(Rx++Mu)=Rtt
1548 // memd(Rx++Mu:brev)=Rtt
1549 // memd(gp+#u16:3)=Rtt
1550
1551 // Store doubleword conditionally.
1552 // if ([!]Pv[.new]) memd(#u6)=Rtt
1553 // TODO: needs to be implemented.
1554
1555 // if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt
1556 // if (Pv) memd(Rs+Ru<<#u2)=Rtt
1557 let AddedComplexity = 10, neverHasSideEffects = 1,
1558     isPredicated = 1 in
1559 def STrid_indexed_shl_cPt_V4 : STInst2<(outs),
1560             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1561                  DoubleRegs:$src5),
1562             "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1563             []>,
1564             Requires<[HasV4T]>;
1565
1566 // if (Pv.new) memd(Rs+Ru<<#u2)=Rtt
1567 let AddedComplexity = 10, neverHasSideEffects = 1,
1568     isPredicated = 1 in
1569 def STrid_indexed_shl_cdnPt_V4 : STInst2<(outs),
1570             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1571                  DoubleRegs:$src5),
1572             "if ($src1.new) memd($src2+$src3<<#$src4) = $src5",
1573             []>,
1574             Requires<[HasV4T]>;
1575 // if (!Pv) memd(Rs+Ru<<#u2)=Rtt
1576 let AddedComplexity = 10, neverHasSideEffects = 1,
1577     isPredicated = 1 in
1578 def STrid_indexed_shl_cNotPt_V4 : STInst2<(outs),
1579             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1580                  DoubleRegs:$src5),
1581             "if (!$src1) memd($src2+$src3<<#$src4) = $src5",
1582             []>,
1583             Requires<[HasV4T]>;
1584 // if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt
1585 let AddedComplexity = 10, neverHasSideEffects = 1,
1586     isPredicated = 1 in
1587 def STrid_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1588             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1589                  DoubleRegs:$src5),
1590             "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",
1591             []>,
1592             Requires<[HasV4T]>;
1593
1594 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1595 // if (Pv) memd(Rx++#s4:3)=Rtt
1596 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1597 let AddedComplexity = 10, neverHasSideEffects = 1,
1598     isPredicated = 1 in
1599 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1600             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1601                  s4_3Imm:$offset),
1602             "if ($src1.new) memd($src3++#$offset) = $src2",
1603             [],
1604             "$src3 = $dst">,
1605             Requires<[HasV4T]>;
1606
1607 // if (!Pv) memd(Rx++#s4:3)=Rtt
1608 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1609 let AddedComplexity = 10, neverHasSideEffects = 1,
1610     isPredicated = 1 in
1611 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1612             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1613                  s4_3Imm:$offset),
1614             "if (!$src1.new) memd($src3++#$offset) = $src2",
1615             [],
1616             "$src3 = $dst">,
1617             Requires<[HasV4T]>;
1618
1619
1620 // Store byte.
1621 // memb(Rs+#u6:0)=#S8
1622 let AddedComplexity = 10, isPredicable = 1 in
1623 def STrib_imm_V4 : STInst<(outs),
1624             (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
1625             "memb($src1+#$src2) = #$src3",
1626             [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1627                                                  u6_0ImmPred:$src2))]>,
1628             Requires<[HasV4T]>;
1629
1630 // memb(Rs+Ru<<#u2)=Rt
1631 let AddedComplexity = 10, isPredicable = 1 in
1632 def STrib_indexed_shl_V4 : STInst<(outs),
1633             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1634             "memb($src1+$src2<<#$src3) = $src4",
1635             [(truncstorei8 (i32 IntRegs:$src4),
1636                            (add (i32 IntRegs:$src1),
1637                                 (shl (i32 IntRegs:$src2),
1638                                           u2ImmPred:$src3)))]>,
1639             Requires<[HasV4T]>;
1640
1641 // memb(Ru<<#u2+#U6)=Rt
1642 let AddedComplexity = 10 in
1643 def STrib_shl_V4 : STInst<(outs),
1644             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1645             "memb($src1<<#$src2+#$src3) = $src4",
1646             [(truncstorei8 (i32 IntRegs:$src4),
1647                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1648                                 u6ImmPred:$src3))]>,
1649             Requires<[HasV4T]>;
1650
1651 // memb(Rx++#s4:0:circ(Mu))=Rt
1652 // memb(Rx++I:circ(Mu))=Rt
1653 // memb(Rx++Mu)=Rt
1654 // memb(Rx++Mu:brev)=Rt
1655 // memb(gp+#u16:0)=Rt
1656
1657
1658 // Store byte conditionally.
1659 // if ([!]Pv[.new]) memb(#u6)=Rt
1660 // if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6
1661 // if (Pv) memb(Rs+#u6:0)=#S6
1662 let neverHasSideEffects = 1,
1663     isPredicated = 1 in
1664 def STrib_imm_cPt_V4 : STInst2<(outs),
1665             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1666             "if ($src1) memb($src2+#$src3) = #$src4",
1667             []>,
1668             Requires<[HasV4T]>;
1669
1670 // if (Pv.new) memb(Rs+#u6:0)=#S6
1671 let neverHasSideEffects = 1,
1672     isPredicated = 1 in
1673 def STrib_imm_cdnPt_V4 : STInst2<(outs),
1674             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1675             "if ($src1.new) memb($src2+#$src3) = #$src4",
1676             []>,
1677             Requires<[HasV4T]>;
1678
1679 // if (!Pv) memb(Rs+#u6:0)=#S6
1680 let neverHasSideEffects = 1,
1681     isPredicated = 1 in
1682 def STrib_imm_cNotPt_V4 : STInst2<(outs),
1683             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1684             "if (!$src1) memb($src2+#$src3) = #$src4",
1685             []>,
1686             Requires<[HasV4T]>;
1687
1688 // if (!Pv.new) memb(Rs+#u6:0)=#S6
1689 let neverHasSideEffects = 1,
1690     isPredicated = 1 in
1691 def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
1692             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1693             "if (!$src1.new) memb($src2+#$src3) = #$src4",
1694             []>,
1695             Requires<[HasV4T]>;
1696
1697 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt
1698 // if (Pv) memb(Rs+Ru<<#u2)=Rt
1699 let AddedComplexity = 10,
1700     isPredicated = 1 in
1701 def STrib_indexed_shl_cPt_V4 : STInst2<(outs),
1702             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1703                  IntRegs:$src5),
1704             "if ($src1) memb($src2+$src3<<#$src4) = $src5",
1705             []>,
1706             Requires<[HasV4T]>;
1707
1708 // if (Pv.new) memb(Rs+Ru<<#u2)=Rt
1709 let AddedComplexity = 10,
1710     isPredicated = 1 in
1711 def STrib_indexed_shl_cdnPt_V4 : STInst2<(outs),
1712             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1713                  IntRegs:$src5),
1714             "if ($src1.new) memb($src2+$src3<<#$src4) = $src5",
1715             []>,
1716             Requires<[HasV4T]>;
1717
1718 // if (!Pv) memb(Rs+Ru<<#u2)=Rt
1719 let AddedComplexity = 10,
1720     isPredicated = 1 in
1721 def STrib_indexed_shl_cNotPt_V4 : STInst2<(outs),
1722             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1723                  IntRegs:$src5),
1724             "if (!$src1) memb($src2+$src3<<#$src4) = $src5",
1725             []>,
1726             Requires<[HasV4T]>;
1727
1728 // if (!Pv.new) memb(Rs+Ru<<#u2)=Rt
1729 let AddedComplexity = 10,
1730     isPredicated = 1 in
1731 def STrib_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1732             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1733                  IntRegs:$src5),
1734             "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5",
1735             []>,
1736             Requires<[HasV4T]>;
1737
1738 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1739 // if (Pv) memb(Rx++#s4:0)=Rt
1740 // if (Pv.new) memb(Rx++#s4:0)=Rt
1741 let hasCtrlDep = 1,
1742     isPredicated = 1 in
1743 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1744             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1745             "if ($src1.new) memb($src3++#$offset) = $src2",
1746             [],"$src3 = $dst">,
1747             Requires<[HasV4T]>;
1748
1749 // if (!Pv) memb(Rx++#s4:0)=Rt
1750 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1751 let hasCtrlDep = 1,
1752     isPredicated = 1 in
1753 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1754             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1755             "if (!$src1.new) memb($src3++#$offset) = $src2",
1756             [],"$src3 = $dst">,
1757             Requires<[HasV4T]>;
1758
1759
1760 // Store halfword.
1761 // TODO: needs to be implemented
1762 // memh(Re=#U6)=Rt.H
1763 // memh(Rs+#s11:1)=Rt.H
1764 // memh(Rs+#u6:1)=#S8
1765 let AddedComplexity = 10, isPredicable = 1 in
1766 def STrih_imm_V4 : STInst<(outs),
1767             (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
1768             "memh($src1+#$src2) = #$src3",
1769             [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1770                                                   u6_1ImmPred:$src2))]>,
1771             Requires<[HasV4T]>;
1772
1773 // memh(Rs+Ru<<#u2)=Rt.H
1774 // TODO: needs to be implemented.
1775
1776 // memh(Rs+Ru<<#u2)=Rt
1777 let AddedComplexity = 10, isPredicable = 1 in
1778 def STrih_indexed_shl_V4 : STInst<(outs),
1779             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1780             "memh($src1+$src2<<#$src3) = $src4",
1781             [(truncstorei16 (i32 IntRegs:$src4),
1782                             (add (i32 IntRegs:$src1),
1783                                  (shl (i32 IntRegs:$src2),
1784                                       u2ImmPred:$src3)))]>,
1785             Requires<[HasV4T]>;
1786
1787 // memh(Ru<<#u2+#U6)=Rt.H
1788 // memh(Ru<<#u2+#U6)=Rt
1789 let AddedComplexity = 10 in
1790 def STrih_shl_V4 : STInst<(outs),
1791             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1792             "memh($src1<<#$src2+#$src3) = $src4",
1793             [(truncstorei16 (i32 IntRegs:$src4),
1794                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1795                                  u6ImmPred:$src3))]>,
1796             Requires<[HasV4T]>;
1797
1798 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1799 // memh(Rx++#s4:1:circ(Mu))=Rt
1800 // memh(Rx++I:circ(Mu))=Rt.H
1801 // memh(Rx++I:circ(Mu))=Rt
1802 // memh(Rx++Mu)=Rt.H
1803 // memh(Rx++Mu)=Rt
1804 // memh(Rx++Mu:brev)=Rt.H
1805 // memh(Rx++Mu:brev)=Rt
1806 // memh(gp+#u16:1)=Rt
1807 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1808 // if ([!]Pv[.new]) memh(#u6)=Rt
1809
1810 // if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6
1811 // if (Pv) memh(Rs+#u6:1)=#S6
1812 let neverHasSideEffects = 1,
1813     isPredicated = 1 in
1814 def STrih_imm_cPt_V4 : STInst2<(outs),
1815             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1816             "if ($src1) memh($src2+#$src3) = #$src4",
1817             []>,
1818             Requires<[HasV4T]>;
1819
1820 // if (Pv.new) memh(Rs+#u6:1)=#S6
1821 let neverHasSideEffects = 1,
1822     isPredicated = 1 in
1823 def STrih_imm_cdnPt_V4 : STInst2<(outs),
1824             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1825             "if ($src1.new) memh($src2+#$src3) = #$src4",
1826             []>,
1827             Requires<[HasV4T]>;
1828
1829 // if (!Pv) memh(Rs+#u6:1)=#S6
1830 let neverHasSideEffects = 1,
1831     isPredicated = 1 in
1832 def STrih_imm_cNotPt_V4 : STInst2<(outs),
1833             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1834             "if (!$src1) memh($src2+#$src3) = #$src4",
1835             []>,
1836             Requires<[HasV4T]>;
1837
1838 // if (!Pv.new) memh(Rs+#u6:1)=#S6
1839 let neverHasSideEffects = 1,
1840     isPredicated = 1 in
1841 def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
1842             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1843             "if (!$src1.new) memh($src2+#$src3) = #$src4",
1844             []>,
1845             Requires<[HasV4T]>;
1846
1847 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1848 // TODO: needs to be implemented.
1849
1850 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H
1851 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt
1852 // if (Pv) memh(Rs+Ru<<#u2)=Rt
1853 let AddedComplexity = 10,
1854     isPredicated = 1 in
1855 def STrih_indexed_shl_cPt_V4 : STInst2<(outs),
1856             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1857                  IntRegs:$src5),
1858             "if ($src1) memh($src2+$src3<<#$src4) = $src5",
1859             []>,
1860             Requires<[HasV4T]>;
1861
1862 // if (Pv.new) memh(Rs+Ru<<#u2)=Rt
1863 let AddedComplexity = 10,
1864     isPredicated = 1 in
1865 def STrih_indexed_shl_cdnPt_V4 : STInst2<(outs),
1866             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1867                  IntRegs:$src5),
1868             "if ($src1.new) memh($src2+$src3<<#$src4) = $src5",
1869             []>,
1870             Requires<[HasV4T]>;
1871
1872 // if (!Pv) memh(Rs+Ru<<#u2)=Rt
1873 let AddedComplexity = 10,
1874     isPredicated = 1 in
1875 def STrih_indexed_shl_cNotPt_V4 : STInst2<(outs),
1876             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1877                  IntRegs:$src5),
1878             "if (!$src1) memh($src2+$src3<<#$src4) = $src5",
1879             []>,
1880             Requires<[HasV4T]>;
1881
1882 // if (!Pv.new) memh(Rs+Ru<<#u2)=Rt
1883 let AddedComplexity = 10,
1884     isPredicated = 1 in
1885 def STrih_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1886             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1887                  IntRegs:$src5),
1888             "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5",
1889             []>,
1890             Requires<[HasV4T]>;
1891
1892 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1893 // TODO: Needs to be implemented.
1894
1895 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1896 // if (Pv) memh(Rx++#s4:1)=Rt
1897 // if (Pv.new) memh(Rx++#s4:1)=Rt
1898 let hasCtrlDep = 1,
1899     isPredicated = 1 in
1900 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1901             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1902             "if ($src1.new) memh($src3++#$offset) = $src2",
1903             [],"$src3 = $dst">,
1904             Requires<[HasV4T]>;
1905
1906 // if (!Pv) memh(Rx++#s4:1)=Rt
1907 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1908 let hasCtrlDep = 1,
1909     isPredicated = 1 in
1910 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1911             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1912             "if (!$src1.new) memh($src3++#$offset) = $src2",
1913             [],"$src3 = $dst">,
1914             Requires<[HasV4T]>;
1915
1916
1917 // Store word.
1918 // memw(Re=#U6)=Rt
1919 // TODO: Needs to be implemented.
1920
1921 // Store predicate:
1922 let neverHasSideEffects = 1 in
1923 def STriw_pred_V4 : STInst2<(outs),
1924             (ins MEMri:$addr, PredRegs:$src1),
1925             "Error; should not emit",
1926             []>,
1927             Requires<[HasV4T]>;
1928
1929
1930 // memw(Rs+#u6:2)=#S8
1931 let AddedComplexity = 10, isPredicable = 1 in
1932 def STriw_imm_V4 : STInst<(outs),
1933             (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
1934             "memw($src1+#$src2) = #$src3",
1935             [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1936                                           u6_2ImmPred:$src2))]>,
1937             Requires<[HasV4T]>;
1938
1939 // memw(Rs+Ru<<#u2)=Rt
1940 let AddedComplexity = 10, isPredicable = 1 in
1941 def STriw_indexed_shl_V4 : STInst<(outs),
1942             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1943             "memw($src1+$src2<<#$src3) = $src4",
1944             [(store (i32 IntRegs:$src4), (add (i32 IntRegs:$src1),
1945                                     (shl (i32 IntRegs:$src2),
1946                                          u2ImmPred:$src3)))]>,
1947             Requires<[HasV4T]>;
1948
1949 // memw(Ru<<#u2+#U6)=Rt
1950 let AddedComplexity = 10 in
1951 def STriw_shl_V4 : STInst<(outs),
1952             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1953             "memw($src1<<#$src2+#$src3) = $src4",
1954             [(store (i32 IntRegs:$src4),
1955                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1956                               u6ImmPred:$src3))]>,
1957             Requires<[HasV4T]>;
1958
1959 // memw(Rx++#s4:2)=Rt
1960 // memw(Rx++#s4:2:circ(Mu))=Rt
1961 // memw(Rx++I:circ(Mu))=Rt
1962 // memw(Rx++Mu)=Rt
1963 // memw(Rx++Mu:brev)=Rt
1964 // memw(gp+#u16:2)=Rt
1965
1966
1967 // Store word conditionally.
1968
1969 // if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6
1970 // if (Pv) memw(Rs+#u6:2)=#S6
1971 let neverHasSideEffects = 1,
1972     isPredicated = 1 in
1973 def STriw_imm_cPt_V4 : STInst2<(outs),
1974             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1975             "if ($src1) memw($src2+#$src3) = #$src4",
1976             []>,
1977             Requires<[HasV4T]>;
1978
1979 // if (Pv.new) memw(Rs+#u6:2)=#S6
1980 let neverHasSideEffects = 1,
1981     isPredicated = 1 in
1982 def STriw_imm_cdnPt_V4 : STInst2<(outs),
1983             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1984             "if ($src1.new) memw($src2+#$src3) = #$src4",
1985             []>,
1986             Requires<[HasV4T]>;
1987
1988 // if (!Pv) memw(Rs+#u6:2)=#S6
1989 let neverHasSideEffects = 1,
1990     isPredicated = 1 in
1991 def STriw_imm_cNotPt_V4 : STInst2<(outs),
1992             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1993             "if (!$src1) memw($src2+#$src3) = #$src4",
1994             []>,
1995             Requires<[HasV4T]>;
1996
1997 // if (!Pv.new) memw(Rs+#u6:2)=#S6
1998 let neverHasSideEffects = 1,
1999     isPredicated = 1 in
2000 def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
2001             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2002             "if (!$src1.new) memw($src2+#$src3) = #$src4",
2003             []>,
2004             Requires<[HasV4T]>;
2005
2006 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt
2007 // if (Pv) memw(Rs+Ru<<#u2)=Rt
2008 let AddedComplexity = 10,
2009     isPredicated = 1 in
2010 def STriw_indexed_shl_cPt_V4 : STInst2<(outs),
2011             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2012                  IntRegs:$src5),
2013             "if ($src1) memw($src2+$src3<<#$src4) = $src5",
2014             []>,
2015             Requires<[HasV4T]>;
2016
2017 // if (Pv.new) memw(Rs+Ru<<#u2)=Rt
2018 let AddedComplexity = 10,
2019     isPredicated = 1 in
2020 def STriw_indexed_shl_cdnPt_V4 : STInst2<(outs),
2021             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2022                  IntRegs:$src5),
2023             "if ($src1.new) memw($src2+$src3<<#$src4) = $src5",
2024             []>,
2025             Requires<[HasV4T]>;
2026
2027 // if (!Pv) memw(Rs+Ru<<#u2)=Rt
2028 let AddedComplexity = 10,
2029     isPredicated = 1 in
2030 def STriw_indexed_shl_cNotPt_V4 : STInst2<(outs),
2031             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2032                  IntRegs:$src5),
2033             "if (!$src1) memw($src2+$src3<<#$src4) = $src5",
2034             []>,
2035             Requires<[HasV4T]>;
2036
2037 // if (!Pv.new) memw(Rs+Ru<<#u2)=Rt
2038 let AddedComplexity = 10,
2039     isPredicated = 1 in
2040 def STriw_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
2041             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2042                  IntRegs:$src5),
2043             "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5",
2044             []>,
2045             Requires<[HasV4T]>;
2046
2047 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
2048 // if (Pv) memw(Rx++#s4:2)=Rt
2049 // if (Pv.new) memw(Rx++#s4:2)=Rt
2050 let hasCtrlDep = 1,
2051     isPredicated = 1 in
2052 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
2053             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2054             "if ($src1.new) memw($src3++#$offset) = $src2",
2055             [],"$src3 = $dst">,
2056             Requires<[HasV4T]>;
2057
2058 // if (!Pv) memw(Rx++#s4:2)=Rt
2059 // if (!Pv.new) memw(Rx++#s4:2)=Rt
2060 let hasCtrlDep = 1,
2061     isPredicated = 1 in
2062 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
2063             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2064             "if (!$src1.new) memw($src3++#$offset) = $src2",
2065             [],"$src3 = $dst">,
2066             Requires<[HasV4T]>;
2067
2068
2069 /// store to global address
2070
2071 let isPredicable = 1, neverHasSideEffects = 1 in
2072 def STrid_GP_V4 : STInst2<(outs),
2073             (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
2074             "memd(#$global+$offset) = $src",
2075             []>,
2076             Requires<[HasV4T]>;
2077
2078 let neverHasSideEffects = 1, isPredicated = 1 in
2079 def STrid_GP_cPt_V4 : STInst2<(outs),
2080             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2081                                                         DoubleRegs:$src2),
2082             "if ($src1) memd(##$global+$offset) = $src2",
2083             []>,
2084             Requires<[HasV4T]>;
2085
2086 let neverHasSideEffects = 1, isPredicated = 1 in
2087 def STrid_GP_cNotPt_V4 : STInst2<(outs),
2088             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2089                                                         DoubleRegs:$src2),
2090             "if (!$src1) memd(##$global+$offset) = $src2",
2091             []>,
2092             Requires<[HasV4T]>;
2093
2094 let neverHasSideEffects = 1, isPredicated = 1 in
2095 def STrid_GP_cdnPt_V4 : STInst2<(outs),
2096             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2097                                                         DoubleRegs:$src2),
2098             "if ($src1.new) memd(##$global+$offset) = $src2",
2099             []>,
2100             Requires<[HasV4T]>;
2101
2102 let neverHasSideEffects = 1, isPredicated = 1 in
2103 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
2104             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2105                                                         DoubleRegs:$src2),
2106             "if (!$src1.new) memd(##$global+$offset) = $src2",
2107             []>,
2108             Requires<[HasV4T]>;
2109
2110 let isPredicable = 1, neverHasSideEffects = 1 in
2111 def STrib_GP_V4 : STInst2<(outs),
2112             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2113             "memb(#$global+$offset) = $src",
2114             []>,
2115             Requires<[HasV4T]>;
2116
2117 let neverHasSideEffects = 1, isPredicated = 1 in
2118 def STrib_GP_cPt_V4 : STInst2<(outs),
2119             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2120                                                         IntRegs:$src2),
2121             "if ($src1) memb(##$global+$offset) = $src2",
2122             []>,
2123             Requires<[HasV4T]>;
2124
2125 let neverHasSideEffects = 1, isPredicated = 1 in
2126 def STrib_GP_cNotPt_V4 : STInst2<(outs),
2127             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2128                                                         IntRegs:$src2),
2129             "if (!$src1) memb(##$global+$offset) = $src2",
2130             []>,
2131             Requires<[HasV4T]>;
2132
2133 let neverHasSideEffects = 1, isPredicated = 1 in
2134 def STrib_GP_cdnPt_V4 : STInst2<(outs),
2135             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2136                                                         IntRegs:$src2),
2137             "if ($src1.new) memb(##$global+$offset) = $src2",
2138             []>,
2139             Requires<[HasV4T]>;
2140
2141 let neverHasSideEffects = 1, isPredicated = 1 in
2142 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
2143             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2144                                                         IntRegs:$src2),
2145             "if (!$src1.new) memb(##$global+$offset) = $src2",
2146             []>,
2147             Requires<[HasV4T]>;
2148
2149 let isPredicable = 1, neverHasSideEffects = 1 in
2150 def STrih_GP_V4 : STInst2<(outs),
2151             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2152             "memh(#$global+$offset) = $src",
2153             []>,
2154             Requires<[HasV4T]>;
2155
2156 let neverHasSideEffects = 1, isPredicated = 1 in
2157 def STrih_GP_cPt_V4 : STInst2<(outs),
2158             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2159                                                         IntRegs:$src2),
2160             "if ($src1) memh(##$global+$offset) = $src2",
2161             []>,
2162             Requires<[HasV4T]>;
2163
2164 let neverHasSideEffects = 1, isPredicated = 1 in
2165 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2166             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2167                                                         IntRegs:$src2),
2168             "if (!$src1) memh(##$global+$offset) = $src2",
2169             []>,
2170             Requires<[HasV4T]>;
2171
2172 let neverHasSideEffects = 1, isPredicated = 1 in
2173 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2174             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2175                                                         IntRegs:$src2),
2176             "if ($src1.new) memh(##$global+$offset) = $src2",
2177             []>,
2178             Requires<[HasV4T]>;
2179
2180 let neverHasSideEffects = 1, isPredicated = 1 in
2181 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2182             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2183                                                         IntRegs:$src2),
2184             "if (!$src1.new) memh(##$global+$offset) = $src2",
2185             []>,
2186             Requires<[HasV4T]>;
2187
2188 let isPredicable = 1, neverHasSideEffects = 1 in
2189 def STriw_GP_V4 : STInst2<(outs),
2190             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2191             "memw(#$global+$offset) = $src",
2192             []>,
2193             Requires<[HasV4T]>;
2194
2195 let neverHasSideEffects = 1, isPredicated = 1 in
2196 def STriw_GP_cPt_V4 : STInst2<(outs),
2197             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2198                                                         IntRegs:$src2),
2199             "if ($src1) memw(##$global+$offset) = $src2",
2200             []>,
2201             Requires<[HasV4T]>;
2202
2203 let neverHasSideEffects = 1, isPredicated = 1 in
2204 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2205             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2206                                                         IntRegs:$src2),
2207             "if (!$src1) memw(##$global+$offset) = $src2",
2208             []>,
2209             Requires<[HasV4T]>;
2210
2211 let neverHasSideEffects = 1, isPredicated = 1 in
2212 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2213             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2214                                                         IntRegs:$src2),
2215             "if ($src1.new) memw(##$global+$offset) = $src2",
2216             []>,
2217             Requires<[HasV4T]>;
2218
2219 let neverHasSideEffects = 1, isPredicated = 1 in
2220 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2221             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2222                                                         IntRegs:$src2),
2223             "if (!$src1.new) memw(##$global+$offset) = $src2",
2224             []>,
2225             Requires<[HasV4T]>;
2226
2227 // memd(#global)=Rtt
2228 let isPredicable = 1, neverHasSideEffects = 1 in
2229 def STd_GP_V4 : STInst2<(outs),
2230             (ins globaladdress:$global, DoubleRegs:$src),
2231             "memd(#$global) = $src",
2232             []>,
2233             Requires<[HasV4T]>;
2234
2235 // if (Pv) memd(##global) = Rtt
2236 let neverHasSideEffects = 1, isPredicated = 1 in
2237 def STd_GP_cPt_V4 : STInst2<(outs),
2238             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2239             "if ($src1) memd(##$global) = $src2",
2240             []>,
2241             Requires<[HasV4T]>;
2242
2243 // if (!Pv) memd(##global) = Rtt
2244 let neverHasSideEffects = 1, isPredicated = 1 in
2245 def STd_GP_cNotPt_V4 : STInst2<(outs),
2246             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2247             "if (!$src1) memd(##$global) = $src2",
2248             []>,
2249               Requires<[HasV4T]>;
2250
2251 // if (Pv) memd(##global) = Rtt
2252 let neverHasSideEffects = 1, isPredicated = 1 in
2253 def STd_GP_cdnPt_V4 : STInst2<(outs),
2254             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2255             "if ($src1.new) memd(##$global) = $src2",
2256             []>,
2257               Requires<[HasV4T]>;
2258
2259 // if (!Pv) memd(##global) = Rtt
2260 let neverHasSideEffects = 1, isPredicated = 1 in
2261 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2262             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2263             "if (!$src1.new) memd(##$global) = $src2",
2264             []>,
2265             Requires<[HasV4T]>;
2266
2267 // memb(#global)=Rt
2268 let isPredicable = 1, neverHasSideEffects = 1 in
2269 def STb_GP_V4 : STInst2<(outs),
2270             (ins globaladdress:$global, IntRegs:$src),
2271             "memb(#$global) = $src",
2272             []>,
2273             Requires<[HasV4T]>;
2274
2275 // if (Pv) memb(##global) = Rt
2276 let neverHasSideEffects = 1, isPredicated = 1 in
2277 def STb_GP_cPt_V4 : STInst2<(outs),
2278             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2279             "if ($src1) memb(##$global) = $src2",
2280               []>,
2281               Requires<[HasV4T]>;
2282
2283 // if (!Pv) memb(##global) = Rt
2284 let neverHasSideEffects = 1, isPredicated = 1 in
2285 def STb_GP_cNotPt_V4 : STInst2<(outs),
2286             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2287             "if (!$src1) memb(##$global) = $src2",
2288               []>,
2289               Requires<[HasV4T]>;
2290
2291 // if (Pv) memb(##global) = Rt
2292 let neverHasSideEffects = 1, isPredicated = 1 in
2293 def STb_GP_cdnPt_V4 : STInst2<(outs),
2294             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2295             "if ($src1.new) memb(##$global) = $src2",
2296               []>,
2297               Requires<[HasV4T]>;
2298
2299 // if (!Pv) memb(##global) = Rt
2300 let neverHasSideEffects = 1, isPredicated = 1 in
2301 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2302             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2303             "if (!$src1.new) memb(##$global) = $src2",
2304               []>,
2305               Requires<[HasV4T]>;
2306
2307 // memh(#global)=Rt
2308 let isPredicable = 1, neverHasSideEffects = 1 in
2309 def STh_GP_V4 : STInst2<(outs),
2310             (ins globaladdress:$global, IntRegs:$src),
2311             "memh(#$global) = $src",
2312             []>,
2313             Requires<[HasV4T]>;
2314
2315 // if (Pv) memh(##global) = Rt
2316 let neverHasSideEffects = 1, isPredicated = 1 in
2317 def STh_GP_cPt_V4 : STInst2<(outs),
2318             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2319             "if ($src1) memh(##$global) = $src2",
2320               []>,
2321               Requires<[HasV4T]>;
2322
2323 // if (!Pv) memh(##global) = Rt
2324 let neverHasSideEffects = 1, isPredicated = 1 in
2325 def STh_GP_cNotPt_V4 : STInst2<(outs),
2326             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2327             "if (!$src1) memh(##$global) = $src2",
2328               []>,
2329               Requires<[HasV4T]>;
2330
2331 // if (Pv) memh(##global) = Rt
2332 let neverHasSideEffects = 1, isPredicated = 1 in
2333 def STh_GP_cdnPt_V4 : STInst2<(outs),
2334             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2335             "if ($src1.new) memh(##$global) = $src2",
2336               []>,
2337               Requires<[HasV4T]>;
2338
2339 // if (!Pv) memh(##global) = Rt
2340 let neverHasSideEffects = 1, isPredicated = 1 in
2341 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2342             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2343             "if (!$src1.new) memh(##$global) = $src2",
2344               []>,
2345               Requires<[HasV4T]>;
2346
2347 // memw(#global)=Rt
2348 let isPredicable = 1, neverHasSideEffects = 1 in
2349 def STw_GP_V4 : STInst2<(outs),
2350             (ins globaladdress:$global, IntRegs:$src),
2351             "memw(#$global) = $src",
2352               []>,
2353               Requires<[HasV4T]>;
2354
2355 // if (Pv) memw(##global) = Rt
2356 let neverHasSideEffects = 1, isPredicated = 1 in
2357 def STw_GP_cPt_V4 : STInst2<(outs),
2358             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2359             "if ($src1) memw(##$global) = $src2",
2360               []>,
2361               Requires<[HasV4T]>;
2362
2363 // if (!Pv) memw(##global) = Rt
2364 let neverHasSideEffects = 1, isPredicated = 1 in
2365 def STw_GP_cNotPt_V4 : STInst2<(outs),
2366             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2367             "if (!$src1) memw(##$global) = $src2",
2368               []>,
2369               Requires<[HasV4T]>;
2370
2371 // if (Pv) memw(##global) = Rt
2372 let neverHasSideEffects = 1, isPredicated = 1 in
2373 def STw_GP_cdnPt_V4 : STInst2<(outs),
2374             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2375             "if ($src1.new) memw(##$global) = $src2",
2376               []>,
2377               Requires<[HasV4T]>;
2378
2379 // if (!Pv) memw(##global) = Rt
2380 let neverHasSideEffects = 1, isPredicated = 1 in
2381 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2382             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2383             "if (!$src1.new) memw(##$global) = $src2",
2384             []>,
2385               Requires<[HasV4T]>;
2386
2387 // 64 bit atomic store
2388 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2389                             (i64 DoubleRegs:$src1)),
2390            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2391            Requires<[HasV4T]>;
2392
2393 // Map from store(globaladdress) -> memd(#foo)
2394 let AddedComplexity = 100 in
2395 def : Pat <(store (i64 DoubleRegs:$src1),
2396                   (HexagonCONST32_GP tglobaladdr:$global)),
2397            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2398            Requires<[HasV4T]>;
2399
2400 // 8 bit atomic store
2401 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2402                             (i32 IntRegs:$src1)),
2403             (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2404               Requires<[HasV4T]>;
2405
2406 // Map from store(globaladdress) -> memb(#foo)
2407 let AddedComplexity = 100 in
2408 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2409           (HexagonCONST32_GP tglobaladdr:$global)),
2410           (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2411           Requires<[HasV4T]>;
2412
2413 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2414 //       to "r0 = 1; memw(#foo) = r0"
2415 let AddedComplexity = 100 in
2416 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2417           (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2418           Requires<[HasV4T]>;
2419
2420 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2421                            (i32 IntRegs:$src1)),
2422           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2423           Requires<[HasV4T]>;
2424
2425 // Map from store(globaladdress) -> memh(#foo)
2426 let AddedComplexity = 100 in
2427 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2428                          (HexagonCONST32_GP tglobaladdr:$global)),
2429           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2430           Requires<[HasV4T]>;
2431
2432 // 32 bit atomic store
2433 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2434                            (i32 IntRegs:$src1)),
2435           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2436           Requires<[HasV4T]>;
2437
2438 // Map from store(globaladdress) -> memw(#foo)
2439 let AddedComplexity = 100 in
2440 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2441           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2442           Requires<[HasV4T]>;
2443
2444 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2445                                 u16ImmPred:$offset),
2446                            (i64 DoubleRegs:$src1)),
2447           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2448                                             (i64 DoubleRegs:$src1))>,
2449           Requires<[HasV4T]>;
2450
2451 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2452                                 u16ImmPred:$offset),
2453                            (i32 IntRegs:$src1)),
2454           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2455                                             (i32 IntRegs:$src1))>,
2456           Requires<[HasV4T]>;
2457
2458 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2459                                 u16ImmPred:$offset),
2460                            (i32 IntRegs:$src1)),
2461           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2462                                             (i32 IntRegs:$src1))>,
2463           Requires<[HasV4T]>;
2464
2465 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2466                                u16ImmPred:$offset),
2467                           (i32 IntRegs:$src1)),
2468           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2469                                             (i32 IntRegs:$src1))>,
2470           Requires<[HasV4T]>;
2471
2472 // Map from store(globaladdress + x) -> memd(#foo + x)
2473 let AddedComplexity = 100 in
2474 def : Pat<(store (i64 DoubleRegs:$src1),
2475                     (add (HexagonCONST32_GP tglobaladdr:$global),
2476                                         u16ImmPred:$offset)),
2477           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2478                                             (i64 DoubleRegs:$src1))>,
2479           Requires<[HasV4T]>;
2480
2481 // Map from store(globaladdress + x) -> memb(#foo + x)
2482 let AddedComplexity = 100 in
2483 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2484                         (add (HexagonCONST32_GP tglobaladdr:$global),
2485                              u16ImmPred:$offset)),
2486           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2487                                             (i32 IntRegs:$src1))>,
2488           Requires<[HasV4T]>;
2489
2490 // Map from store(globaladdress + x) -> memh(#foo + x)
2491 let AddedComplexity = 100 in
2492 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2493                          (add (HexagonCONST32_GP tglobaladdr:$global),
2494                               u16ImmPred:$offset)),
2495           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2496                                             (i32 IntRegs:$src1))>,
2497           Requires<[HasV4T]>;
2498
2499 // Map from store(globaladdress + x) -> memw(#foo + x)
2500 let AddedComplexity = 100 in
2501 def : Pat<(store (i32 IntRegs:$src1),
2502                  (add (HexagonCONST32_GP tglobaladdr:$global),
2503                                 u16ImmPred:$offset)),
2504           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2505                                             (i32 IntRegs:$src1))>,
2506           Requires<[HasV4T]>;
2507
2508
2509
2510 //===----------------------------------------------------------------------===
2511 // ST -
2512 //===----------------------------------------------------------------------===
2513
2514
2515 //===----------------------------------------------------------------------===//
2516 // NV/ST +
2517 //===----------------------------------------------------------------------===//
2518
2519 // Store new-value byte.
2520
2521 // memb(Re=#U6)=Nt.new
2522 // memb(Rs+#s11:0)=Nt.new
2523 let mayStore = 1, isPredicable = 1 in
2524 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2525             "memb($addr) = $src1.new",
2526             []>,
2527             Requires<[HasV4T]>;
2528
2529 let mayStore = 1, isPredicable = 1 in
2530 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
2531             (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
2532             "memb($src1+#$src2) = $src3.new",
2533             []>,
2534             Requires<[HasV4T]>;
2535
2536 // memb(Rs+Ru<<#u2)=Nt.new
2537 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2538 def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs),
2539             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2540             "memb($src1+$src2<<#$src3) = $src4.new",
2541             []>,
2542             Requires<[HasV4T]>;
2543
2544 // memb(Ru<<#u2+#U6)=Nt.new
2545 let mayStore = 1, AddedComplexity = 10 in
2546 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2547             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2548             "memb($src1<<#$src2+#$src3) = $src4.new",
2549             []>,
2550             Requires<[HasV4T]>;
2551
2552 // memb(Rx++#s4:0)=Nt.new
2553 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2554 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2555             (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2556             "memb($src2++#$offset) = $src1.new",
2557             [],
2558             "$src2 = $dst">,
2559             Requires<[HasV4T]>;
2560
2561 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2562 // memb(Rx++I:circ(Mu))=Nt.new
2563 // memb(Rx++Mu)=Nt.new
2564 // memb(Rx++Mu:brev)=Nt.new
2565
2566 // memb(gp+#u16:0)=Nt.new
2567 let mayStore = 1, neverHasSideEffects = 1 in
2568 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2569             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2570             "memb(#$global+$offset) = $src.new",
2571             []>,
2572             Requires<[HasV4T]>;
2573
2574 // memb(#global)=Nt.new
2575 let mayStore = 1, neverHasSideEffects = 1 in
2576 def STb_GP_nv_V4 : NVInst_V4<(outs),
2577             (ins globaladdress:$global, IntRegs:$src),
2578             "memb(#$global) = $src.new",
2579             []>,
2580             Requires<[HasV4T]>;
2581
2582 // Store new-value byte conditionally.
2583 // if ([!]Pv[.new]) memb(#u6)=Nt.new
2584 // if (Pv) memb(Rs+#u6:0)=Nt.new
2585 let mayStore = 1, neverHasSideEffects = 1,
2586     isPredicated = 1 in
2587 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
2588             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2589             "if ($src1) memb($addr) = $src2.new",
2590             []>,
2591             Requires<[HasV4T]>;
2592
2593 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2594 let mayStore = 1, neverHasSideEffects = 1,
2595     isPredicated = 1 in
2596 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
2597             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2598             "if ($src1.new) memb($addr) = $src2.new",
2599             []>,
2600             Requires<[HasV4T]>;
2601
2602 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2603 let mayStore = 1, neverHasSideEffects = 1,
2604     isPredicated = 1 in
2605 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
2606             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2607             "if (!$src1) memb($addr) = $src2.new",
2608             []>,
2609             Requires<[HasV4T]>;
2610
2611 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2612 let mayStore = 1, neverHasSideEffects = 1,
2613     isPredicated = 1 in
2614 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2615             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2616             "if (!$src1.new) memb($addr) = $src2.new",
2617             []>,
2618             Requires<[HasV4T]>;
2619
2620 // if (Pv) memb(Rs+#u6:0)=Nt.new
2621 let mayStore = 1, neverHasSideEffects = 1,
2622     isPredicated = 1 in
2623 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2624             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2625             "if ($src1) memb($src2+#$src3) = $src4.new",
2626             []>,
2627             Requires<[HasV4T]>;
2628
2629 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2630 let mayStore = 1, neverHasSideEffects = 1,
2631     isPredicated = 1 in
2632 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2633             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2634             "if ($src1.new) memb($src2+#$src3) = $src4.new",
2635             []>,
2636             Requires<[HasV4T]>;
2637
2638 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2639 let mayStore = 1, neverHasSideEffects = 1,
2640     isPredicated = 1 in
2641 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2642             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2643             "if (!$src1) memb($src2+#$src3) = $src4.new",
2644             []>,
2645             Requires<[HasV4T]>;
2646
2647 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2648 let mayStore = 1, neverHasSideEffects = 1,
2649     isPredicated = 1 in
2650 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2651             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2652             "if (!$src1.new) memb($src2+#$src3) = $src4.new",
2653             []>,
2654             Requires<[HasV4T]>;
2655
2656
2657 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new
2658 // if (Pv) memb(Rs+Ru<<#u2)=Nt.new
2659 let mayStore = 1, AddedComplexity = 10,
2660     isPredicated = 1 in
2661 def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
2662             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2663                  IntRegs:$src5),
2664             "if ($src1) memb($src2+$src3<<#$src4) = $src5.new",
2665             []>,
2666             Requires<[HasV4T]>;
2667
2668 // if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new
2669 let mayStore = 1, AddedComplexity = 10,
2670     isPredicated = 1 in
2671 def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
2672             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2673                  IntRegs:$src5),
2674             "if ($src1.new) memb($src2+$src3<<#$src4) = $src5.new",
2675             []>,
2676             Requires<[HasV4T]>;
2677
2678 // if (!Pv) memb(Rs+Ru<<#u2)=Nt.new
2679 let mayStore = 1, AddedComplexity = 10,
2680     isPredicated = 1 in
2681 def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
2682             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2683                  IntRegs:$src5),
2684             "if (!$src1) memb($src2+$src3<<#$src4) = $src5.new",
2685             []>,
2686             Requires<[HasV4T]>;
2687
2688 // if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new
2689 let mayStore = 1, AddedComplexity = 10,
2690     isPredicated = 1 in
2691 def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2692             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2693                  IntRegs:$src5),
2694             "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5.new",
2695             []>,
2696             Requires<[HasV4T]>;
2697
2698 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
2699 // if (Pv) memb(Rx++#s4:0)=Nt.new
2700 let mayStore = 1, hasCtrlDep = 1,
2701     isPredicated = 1 in
2702 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2703             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2704             "if ($src1) memb($src3++#$offset) = $src2.new",
2705             [],"$src3 = $dst">,
2706             Requires<[HasV4T]>;
2707
2708 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
2709 let mayStore = 1, hasCtrlDep = 1,
2710     isPredicated = 1 in
2711 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2712             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2713             "if ($src1.new) memb($src3++#$offset) = $src2.new",
2714             [],"$src3 = $dst">,
2715             Requires<[HasV4T]>;
2716
2717 // if (!Pv) memb(Rx++#s4:0)=Nt.new
2718 let mayStore = 1, hasCtrlDep = 1,
2719     isPredicated = 1 in
2720 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2721             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2722             "if (!$src1) memb($src3++#$offset) = $src2.new",
2723             [],"$src3 = $dst">,
2724             Requires<[HasV4T]>;
2725
2726 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
2727 let mayStore = 1, hasCtrlDep = 1,
2728     isPredicated = 1 in
2729 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2730             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2731             "if (!$src1.new) memb($src3++#$offset) = $src2.new",
2732             [],"$src3 = $dst">,
2733             Requires<[HasV4T]>;
2734
2735
2736 // Store new-value halfword.
2737 // memh(Re=#U6)=Nt.new
2738 // memh(Rs+#s11:1)=Nt.new
2739 let mayStore = 1, isPredicable = 1 in
2740 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2741             "memh($addr) = $src1.new",
2742             []>,
2743             Requires<[HasV4T]>;
2744
2745 let mayStore = 1, isPredicable = 1 in
2746 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
2747             (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
2748             "memh($src1+#$src2) = $src3.new",
2749             []>,
2750             Requires<[HasV4T]>;
2751
2752 // memh(Rs+Ru<<#u2)=Nt.new
2753 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2754 def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs),
2755             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2756             "memh($src1+$src2<<#$src3) = $src4.new",
2757             []>,
2758             Requires<[HasV4T]>;
2759
2760 // memh(Ru<<#u2+#U6)=Nt.new
2761 let mayStore = 1, AddedComplexity = 10 in
2762 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2763             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2764             "memh($src1<<#$src2+#$src3) = $src4.new",
2765             []>,
2766             Requires<[HasV4T]>;
2767
2768 // memh(Rx++#s4:1)=Nt.new
2769 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2770 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2771             (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
2772             "memh($src2++#$offset) = $src1.new",
2773             [],
2774             "$src2 = $dst">,
2775             Requires<[HasV4T]>;
2776
2777 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2778 // memh(Rx++I:circ(Mu))=Nt.new
2779 // memh(Rx++Mu)=Nt.new
2780 // memh(Rx++Mu:brev)=Nt.new
2781
2782 // memh(gp+#u16:1)=Nt.new
2783 let mayStore = 1, neverHasSideEffects = 1 in
2784 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2785             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2786             "memh(#$global+$offset) = $src.new",
2787             []>,
2788             Requires<[HasV4T]>;
2789
2790 // memh(#global)=Nt.new
2791 let mayStore = 1, neverHasSideEffects = 1 in
2792 def STh_GP_nv_V4 : NVInst_V4<(outs),
2793             (ins globaladdress:$global, IntRegs:$src),
2794             "memh(#$global) = $src.new",
2795             []>,
2796             Requires<[HasV4T]>;
2797
2798
2799 // Store new-value halfword conditionally.
2800
2801 // if ([!]Pv[.new]) memh(#u6)=Nt.new
2802
2803 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
2804 // if (Pv) memh(Rs+#u6:1)=Nt.new
2805 let mayStore = 1, neverHasSideEffects = 1,
2806     isPredicated = 1 in
2807 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
2808             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2809             "if ($src1) memh($addr) = $src2.new",
2810             []>,
2811             Requires<[HasV4T]>;
2812
2813 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2814 let mayStore = 1, neverHasSideEffects = 1,
2815     isPredicated = 1 in
2816 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
2817             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2818             "if ($src1.new) memh($addr) = $src2.new",
2819             []>,
2820             Requires<[HasV4T]>;
2821
2822 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2823 let mayStore = 1, neverHasSideEffects = 1,
2824     isPredicated = 1 in
2825 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
2826             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2827             "if (!$src1) memh($addr) = $src2.new",
2828             []>,
2829             Requires<[HasV4T]>;
2830
2831 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2832 let mayStore = 1, neverHasSideEffects = 1,
2833     isPredicated = 1 in
2834 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2835             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2836             "if (!$src1.new) memh($addr) = $src2.new",
2837             []>,
2838             Requires<[HasV4T]>;
2839
2840 // if (Pv) memh(Rs+#u6:1)=Nt.new
2841 let mayStore = 1, neverHasSideEffects = 1,
2842     isPredicated = 1 in
2843 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2844             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2845             "if ($src1) memh($src2+#$src3) = $src4.new",
2846             []>,
2847             Requires<[HasV4T]>;
2848
2849 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2850 let mayStore = 1, neverHasSideEffects = 1,
2851     isPredicated = 1 in
2852 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2853             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2854             "if ($src1.new) memh($src2+#$src3) = $src4.new",
2855             []>,
2856             Requires<[HasV4T]>;
2857
2858 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2859 let mayStore = 1, neverHasSideEffects = 1,
2860     isPredicated = 1 in
2861 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2862             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2863             "if (!$src1) memh($src2+#$src3) = $src4.new",
2864             []>,
2865             Requires<[HasV4T]>;
2866
2867 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2868 let mayStore = 1, neverHasSideEffects = 1,
2869     isPredicated = 1 in
2870 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2871             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2872             "if (!$src1.new) memh($src2+#$src3) = $src4.new",
2873             []>,
2874             Requires<[HasV4T]>;
2875
2876 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new
2877 // if (Pv) memh(Rs+Ru<<#u2)=Nt.new
2878 let mayStore = 1, AddedComplexity = 10,
2879     isPredicated = 1 in
2880 def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
2881             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2882                  IntRegs:$src5),
2883             "if ($src1) memh($src2+$src3<<#$src4) = $src5.new",
2884             []>,
2885             Requires<[HasV4T]>;
2886
2887 // if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new
2888 let mayStore = 1, AddedComplexity = 10,
2889     isPredicated = 1 in
2890 def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
2891             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2892                  IntRegs:$src5),
2893             "if ($src1.new) memh($src2+$src3<<#$src4) = $src5.new",
2894             []>,
2895             Requires<[HasV4T]>;
2896
2897 // if (!Pv) memh(Rs+Ru<<#u2)=Nt.new
2898 let mayStore = 1, AddedComplexity = 10,
2899     isPredicated = 1 in
2900 def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
2901             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2902                  IntRegs:$src5),
2903             "if (!$src1) memh($src2+$src3<<#$src4) = $src5.new",
2904             []>,
2905             Requires<[HasV4T]>;
2906
2907 // if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new
2908 let mayStore = 1, AddedComplexity = 10,
2909     isPredicated = 1 in
2910 def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2911             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2912                  IntRegs:$src5),
2913             "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5.new",
2914             []>,
2915             Requires<[HasV4T]>;
2916
2917 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2918 // if (Pv) memh(Rx++#s4:1)=Nt.new
2919 let mayStore = 1, hasCtrlDep = 1,
2920     isPredicated = 1 in
2921 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2922             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2923             "if ($src1) memh($src3++#$offset) = $src2.new",
2924             [],"$src3 = $dst">,
2925             Requires<[HasV4T]>;
2926
2927 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2928 let mayStore = 1, hasCtrlDep = 1,
2929     isPredicated = 1 in
2930 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2931             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2932             "if ($src1.new) memh($src3++#$offset) = $src2.new",
2933             [],"$src3 = $dst">,
2934             Requires<[HasV4T]>;
2935
2936 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2937 let mayStore = 1, hasCtrlDep = 1,
2938     isPredicated = 1 in
2939 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2940             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2941             "if (!$src1) memh($src3++#$offset) = $src2.new",
2942             [],"$src3 = $dst">,
2943             Requires<[HasV4T]>;
2944
2945 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2946 let mayStore = 1, hasCtrlDep = 1,
2947     isPredicated = 1 in
2948 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2949             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2950             "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2951             [],"$src3 = $dst">,
2952             Requires<[HasV4T]>;
2953
2954
2955 // Store new-value word.
2956
2957 // memw(Re=#U6)=Nt.new
2958 // memw(Rs+#s11:2)=Nt.new
2959 let mayStore = 1, isPredicable = 1 in
2960 def STriw_nv_V4 : NVInst_V4<(outs),
2961             (ins MEMri:$addr, IntRegs:$src1),
2962             "memw($addr) = $src1.new",
2963             []>,
2964             Requires<[HasV4T]>;
2965
2966 let mayStore = 1, isPredicable = 1 in
2967 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
2968             (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2969             "memw($src1+#$src2) = $src3.new",
2970             []>,
2971             Requires<[HasV4T]>;
2972
2973 // memw(Rs+Ru<<#u2)=Nt.new
2974 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2975 def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs),
2976             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2977             "memw($src1+$src2<<#$src3) = $src4.new",
2978             []>,
2979             Requires<[HasV4T]>;
2980
2981 // memw(Ru<<#u2+#U6)=Nt.new
2982 let mayStore = 1, AddedComplexity = 10 in
2983 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2984             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2985             "memw($src1<<#$src2+#$src3) = $src4.new",
2986             []>,
2987             Requires<[HasV4T]>;
2988
2989 // memw(Rx++#s4:2)=Nt.new
2990 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2991 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2992             (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
2993             "memw($src2++#$offset) = $src1.new",
2994             [],
2995             "$src2 = $dst">,
2996             Requires<[HasV4T]>;
2997
2998 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2999 // memw(Rx++I:circ(Mu))=Nt.new
3000 // memw(Rx++Mu)=Nt.new
3001 // memw(Rx++Mu:brev)=Nt.new
3002 // memw(gp+#u16:2)=Nt.new
3003 let mayStore = 1, neverHasSideEffects = 1 in
3004 def STriw_GP_nv_V4 : NVInst_V4<(outs),
3005             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
3006             "memw(#$global+$offset) = $src.new",
3007             []>,
3008             Requires<[HasV4T]>;
3009
3010 let mayStore = 1, neverHasSideEffects = 1 in
3011 def STw_GP_nv_V4 : NVInst_V4<(outs),
3012             (ins globaladdress:$global, IntRegs:$src),
3013             "memw(#$global) = $src.new",
3014             []>,
3015             Requires<[HasV4T]>;
3016
3017 // Store new-value word conditionally.
3018
3019 // if ([!]Pv[.new]) memw(#u6)=Nt.new
3020
3021 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
3022 // if (Pv) memw(Rs+#u6:2)=Nt.new
3023 let mayStore = 1, neverHasSideEffects = 1,
3024     isPredicated = 1 in
3025 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
3026             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3027             "if ($src1) memw($addr) = $src2.new",
3028             []>,
3029             Requires<[HasV4T]>;
3030
3031 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3032 let mayStore = 1, neverHasSideEffects = 1,
3033     isPredicated = 1 in
3034 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
3035             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3036             "if ($src1.new) memw($addr) = $src2.new",
3037             []>,
3038             Requires<[HasV4T]>;
3039
3040 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3041 let mayStore = 1, neverHasSideEffects = 1,
3042     isPredicated = 1 in
3043 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
3044             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3045             "if (!$src1) memw($addr) = $src2.new",
3046             []>,
3047             Requires<[HasV4T]>;
3048
3049 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3050 let mayStore = 1, neverHasSideEffects = 1,
3051     isPredicated = 1 in
3052 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3053             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3054             "if (!$src1.new) memw($addr) = $src2.new",
3055             []>,
3056             Requires<[HasV4T]>;
3057
3058 // if (Pv) memw(Rs+#u6:2)=Nt.new
3059 let mayStore = 1, neverHasSideEffects = 1,
3060     isPredicated = 1 in
3061 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
3062             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3063             "if ($src1) memw($src2+#$src3) = $src4.new",
3064             []>,
3065             Requires<[HasV4T]>;
3066
3067 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3068 let mayStore = 1, neverHasSideEffects = 1,
3069     isPredicated = 1 in
3070 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
3071             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3072             "if ($src1.new) memw($src2+#$src3) = $src4.new",
3073             []>,
3074             Requires<[HasV4T]>;
3075
3076 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3077 let mayStore = 1, neverHasSideEffects = 1,
3078     isPredicated = 1 in
3079 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
3080             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3081             "if (!$src1) memw($src2+#$src3) = $src4.new",
3082             []>,
3083             Requires<[HasV4T]>;
3084
3085 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3086 let mayStore = 1, neverHasSideEffects = 1,
3087     isPredicated = 1 in
3088 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3089             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3090             "if (!$src1.new) memw($src2+#$src3) = $src4.new",
3091             []>,
3092             Requires<[HasV4T]>;
3093
3094
3095 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new
3096 // if (Pv) memw(Rs+Ru<<#u2)=Nt.new
3097 let mayStore = 1, AddedComplexity = 10,
3098     isPredicated = 1 in
3099 def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
3100             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3101                  IntRegs:$src5),
3102             "if ($src1) memw($src2+$src3<<#$src4) = $src5.new",
3103             []>,
3104             Requires<[HasV4T]>;
3105
3106 // if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3107 let mayStore = 1, AddedComplexity = 10,
3108     isPredicated = 1 in
3109 def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
3110             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3111                  IntRegs:$src5),
3112             "if ($src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3113             []>,
3114             Requires<[HasV4T]>;
3115
3116 // if (!Pv) memw(Rs+Ru<<#u2)=Nt.new
3117 let mayStore = 1, AddedComplexity = 10,
3118     isPredicated = 1 in
3119 def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
3120             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3121                  IntRegs:$src5),
3122             "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",
3123             []>,
3124             Requires<[HasV4T]>;
3125
3126 // if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3127 let mayStore = 1, AddedComplexity = 10,
3128     isPredicated = 1 in
3129 def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3130             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3131                  IntRegs:$src5),
3132             "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3133             []>,
3134             Requires<[HasV4T]>;
3135
3136 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
3137 // if (Pv) memw(Rx++#s4:2)=Nt.new
3138 let mayStore = 1, hasCtrlDep = 1,
3139     isPredicated = 1 in
3140 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3141             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3142             "if ($src1) memw($src3++#$offset) = $src2.new",
3143             [],"$src3 = $dst">,
3144             Requires<[HasV4T]>;
3145
3146 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
3147 let mayStore = 1, hasCtrlDep = 1,
3148     isPredicated = 1 in
3149 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3150             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3151             "if ($src1.new) memw($src3++#$offset) = $src2.new",
3152             [],"$src3 = $dst">,
3153             Requires<[HasV4T]>;
3154
3155 // if (!Pv) memw(Rx++#s4:2)=Nt.new
3156 let mayStore = 1, hasCtrlDep = 1,
3157     isPredicated = 1 in
3158 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3159             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3160             "if (!$src1) memw($src3++#$offset) = $src2.new",
3161             [],"$src3 = $dst">,
3162             Requires<[HasV4T]>;
3163
3164 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
3165 let mayStore = 1, hasCtrlDep = 1,
3166     isPredicated = 1 in
3167 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3168             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3169             "if (!$src1.new) memw($src3++#$offset) = $src2.new",
3170             [],"$src3 = $dst">,
3171             Requires<[HasV4T]>;
3172
3173
3174
3175 // if (Pv) memb(##global) = Rt
3176 let mayStore = 1, neverHasSideEffects = 1 in
3177 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
3178             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3179             "if ($src1) memb(##$global) = $src2.new",
3180             []>,
3181             Requires<[HasV4T]>;
3182
3183 // if (!Pv) memb(##global) = Rt
3184 let mayStore = 1, neverHasSideEffects = 1 in
3185 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3186             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3187             "if (!$src1) memb(##$global) = $src2.new",
3188             []>,
3189             Requires<[HasV4T]>;
3190
3191 // if (Pv) memb(##global) = Rt
3192 let mayStore = 1, neverHasSideEffects = 1 in
3193 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3194             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3195             "if ($src1.new) memb(##$global) = $src2.new",
3196             []>,
3197             Requires<[HasV4T]>;
3198
3199 // if (!Pv) memb(##global) = Rt
3200 let mayStore = 1, neverHasSideEffects = 1 in
3201 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3202             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3203             "if (!$src1.new) memb(##$global) = $src2.new",
3204             []>,
3205             Requires<[HasV4T]>;
3206
3207 // if (Pv) memh(##global) = Rt
3208 let mayStore = 1, neverHasSideEffects = 1 in
3209 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
3210             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3211             "if ($src1) memh(##$global) = $src2.new",
3212             []>,
3213             Requires<[HasV4T]>;
3214
3215 // if (!Pv) memh(##global) = Rt
3216 let mayStore = 1, neverHasSideEffects = 1 in
3217 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3218             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3219             "if (!$src1) memh(##$global) = $src2.new",
3220             []>,
3221             Requires<[HasV4T]>;
3222
3223 // if (Pv) memh(##global) = Rt
3224 let mayStore = 1, neverHasSideEffects = 1 in
3225 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3226             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3227             "if ($src1.new) memh(##$global) = $src2.new",
3228             []>,
3229             Requires<[HasV4T]>;
3230
3231 // if (!Pv) memh(##global) = Rt
3232 let mayStore = 1, neverHasSideEffects = 1 in
3233 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3234             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3235             "if (!$src1.new) memh(##$global) = $src2.new",
3236             []>,
3237             Requires<[HasV4T]>;
3238
3239 // if (Pv) memw(##global) = Rt
3240 let mayStore = 1, neverHasSideEffects = 1 in
3241 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3242             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3243             "if ($src1) memw(##$global) = $src2.new",
3244             []>,
3245             Requires<[HasV4T]>;
3246
3247 // if (!Pv) memw(##global) = Rt
3248 let mayStore = 1, neverHasSideEffects = 1 in
3249 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3250             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3251             "if (!$src1) memw(##$global) = $src2.new",
3252             []>,
3253             Requires<[HasV4T]>;
3254
3255 // if (Pv) memw(##global) = Rt
3256 let mayStore = 1, neverHasSideEffects = 1 in
3257 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3258             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3259             "if ($src1.new) memw(##$global) = $src2.new",
3260             []>,
3261             Requires<[HasV4T]>;
3262
3263 // if (!Pv) memw(##global) = Rt
3264 let mayStore = 1, neverHasSideEffects = 1 in
3265 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3266             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3267             "if (!$src1.new) memw(##$global) = $src2.new",
3268             []>,
3269             Requires<[HasV4T]>;
3270
3271 let mayStore = 1, neverHasSideEffects = 1 in
3272 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
3273             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3274                                                         IntRegs:$src2),
3275             "if ($src1) memb(##$global+$offset) = $src2.new",
3276             []>,
3277             Requires<[HasV4T]>;
3278
3279 let mayStore = 1, neverHasSideEffects = 1 in
3280 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3281             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3282                                                         IntRegs:$src2),
3283             "if (!$src1) memb(##$global+$offset) = $src2.new",
3284             []>,
3285             Requires<[HasV4T]>;
3286
3287 let mayStore = 1, neverHasSideEffects = 1 in
3288 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3289             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3290                                                         IntRegs:$src2),
3291             "if ($src1.new) memb(##$global+$offset) = $src2.new",
3292             []>,
3293             Requires<[HasV4T]>;
3294
3295 let mayStore = 1, neverHasSideEffects = 1 in
3296 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3297             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3298                                                         IntRegs:$src2),
3299             "if (!$src1.new) memb(##$global+$offset) = $src2.new",
3300             []>,
3301             Requires<[HasV4T]>;
3302
3303 let mayStore = 1, neverHasSideEffects = 1 in
3304 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
3305             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3306                                                         IntRegs:$src2),
3307             "if ($src1) memh(##$global+$offset) = $src2.new",
3308             []>,
3309             Requires<[HasV4T]>;
3310
3311 let mayStore = 1, neverHasSideEffects = 1 in
3312 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3313             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3314                                                         IntRegs:$src2),
3315             "if (!$src1) memh(##$global+$offset) = $src2.new",
3316             []>,
3317             Requires<[HasV4T]>;
3318
3319 let mayStore = 1, neverHasSideEffects = 1 in
3320 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3321             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3322                                                         IntRegs:$src2),
3323             "if ($src1.new) memh(##$global+$offset) = $src2.new",
3324             []>,
3325             Requires<[HasV4T]>;
3326
3327 let mayStore = 1, neverHasSideEffects = 1 in
3328 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3329             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3330                                                         IntRegs:$src2),
3331             "if (!$src1.new) memh(##$global+$offset) = $src2.new",
3332             []>,
3333             Requires<[HasV4T]>;
3334
3335 let mayStore = 1, neverHasSideEffects = 1 in
3336 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3337             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3338                                                         IntRegs:$src2),
3339             "if ($src1) memw(##$global+$offset) = $src2.new",
3340             []>,
3341             Requires<[HasV4T]>;
3342
3343 let mayStore = 1, neverHasSideEffects = 1 in
3344 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3345             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3346                                                         IntRegs:$src2),
3347             "if (!$src1) memw(##$global+$offset) = $src2.new",
3348             []>,
3349             Requires<[HasV4T]>;
3350
3351 let mayStore = 1, neverHasSideEffects = 1 in
3352 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3353             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3354                                                         IntRegs:$src2),
3355             "if ($src1.new) memw(##$global+$offset) = $src2.new",
3356             []>,
3357             Requires<[HasV4T]>;
3358
3359 let mayStore = 1, neverHasSideEffects = 1 in
3360 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3361             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3362                                                         IntRegs:$src2),
3363             "if (!$src1.new) memw(##$global+$offset) = $src2.new",
3364             []>,
3365             Requires<[HasV4T]>;
3366
3367 //===----------------------------------------------------------------------===//
3368 // NV/ST -
3369 //===----------------------------------------------------------------------===//
3370
3371 //===----------------------------------------------------------------------===//
3372 // NV/J +
3373 //===----------------------------------------------------------------------===//
3374
3375 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
3376   def _ie_nv_V4 : NVInst_V4<(outs),
3377             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3378             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3379             !strconcat("($src1.new, $src2)) jump:",
3380             !strconcat(TakenStr, " $offset"))))),
3381             []>,
3382             Requires<[HasV4T]>;
3383
3384   def _nv_V4 : NVInst_V4<(outs),
3385             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3386             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3387             !strconcat("($src1.new, $src2)) jump:",
3388             !strconcat(TakenStr, " $offset"))))),
3389             []>,
3390             Requires<[HasV4T]>;
3391 }
3392
3393 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
3394                                                    string TakenStr> {
3395   def _ie_nv_V4 : NVInst_V4<(outs),
3396             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3397             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3398             !strconcat("($src1, $src2.new)) jump:",
3399             !strconcat(TakenStr, " $offset"))))),
3400             []>,
3401             Requires<[HasV4T]>;
3402
3403   def _nv_V4 : NVInst_V4<(outs),
3404             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3405             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3406             !strconcat("($src1, $src2.new)) jump:",
3407             !strconcat(TakenStr, " $offset"))))),
3408             []>,
3409             Requires<[HasV4T]>;
3410 }
3411
3412 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
3413   def _ie_nv_V4 : NVInst_V4<(outs),
3414             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3415             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3416             !strconcat("($src1.new, #$src2)) jump:",
3417             !strconcat(TakenStr, " $offset"))))),
3418             []>,
3419             Requires<[HasV4T]>;
3420
3421   def _nv_V4 : NVInst_V4<(outs),
3422             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3423             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3424             !strconcat("($src1.new, #$src2)) jump:",
3425             !strconcat(TakenStr, " $offset"))))),
3426             []>,
3427             Requires<[HasV4T]>;
3428 }
3429
3430 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
3431   def _ie_nv_V4 : NVInst_V4<(outs),
3432             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3433             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3434             !strconcat("($src1.new, #$src2)) jump:",
3435             !strconcat(TakenStr, " $offset"))))),
3436             []>,
3437             Requires<[HasV4T]>;
3438
3439   def _nv_V4 : NVInst_V4<(outs),
3440             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3441             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3442             !strconcat("($src1.new, #$src2)) jump:",
3443             !strconcat(TakenStr, " $offset"))))),
3444             []>,
3445             Requires<[HasV4T]>;
3446 }
3447
3448 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
3449                                                 string TakenStr> {
3450   def _ie_nv_V4 : NVInst_V4<(outs),
3451             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3452             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3453             !strconcat("($src1.new, #$src2)) jump:",
3454             !strconcat(TakenStr, " $offset"))))),
3455             []>,
3456             Requires<[HasV4T]>;
3457
3458   def _nv_V4 : NVInst_V4<(outs),
3459             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3460             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3461             !strconcat("($src1.new, #$src2)) jump:",
3462             !strconcat(TakenStr, " $offset"))))),
3463             []>,
3464             Requires<[HasV4T]>;
3465 }
3466
3467 // Multiclass for regular dot new of Ist operand register.
3468 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
3469   defm Pt  : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
3470   defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
3471 }
3472
3473 // Multiclass for dot new of 2nd operand register.
3474 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
3475   defm Pt  : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
3476   defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
3477 }
3478
3479 // Multiclass for 2nd operand immediate, including -1.
3480 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
3481   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3482   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3483   defm Ptneg  : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
3484   defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
3485 }
3486
3487 // Multiclass for 2nd operand immediate, excluding -1.
3488 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
3489   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3490   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3491 }
3492
3493 // Multiclass for tstbit, where 2nd operand is always #0.
3494 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3495   defm Pt     : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3496   defm Pnt    : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3497 }
3498
3499 // Multiclass for GT.
3500 multiclass NVJ_type_rr_ri<string OpcStr> {
3501   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3502   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3503   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3504   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3505   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3506   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3507 }
3508
3509 // Multiclass for EQ.
3510 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3511   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3512   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3513   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3514   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3515 }
3516
3517 // Multiclass for GTU.
3518 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3519   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3520   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3521   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3522   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3523   defm riNot   : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3524   defm ri      : NVJ_type_br_pred_imm_only<"",  OpcStr>;
3525 }
3526
3527 // Multiclass for tstbit.
3528 multiclass NVJ_type_r0<string OpcStr> {
3529   defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3530   defm r0    : NVJ_type_br_pred_tstbit<"",  OpcStr>;
3531  }
3532
3533 // Base Multiclass for New Value Jump.
3534 multiclass NVJ_type {
3535   defm GT     : NVJ_type_rr_ri<"cmp.gt">;
3536   defm EQ     : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3537   defm GTU    : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3538   defm TSTBIT : NVJ_type_r0<"tstbit">;
3539 }
3540
3541 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3542   defm JMP_ : NVJ_type;
3543 }
3544
3545 //===----------------------------------------------------------------------===//
3546 // NV/J -
3547 //===----------------------------------------------------------------------===//
3548
3549 //===----------------------------------------------------------------------===//
3550 // XTYPE/ALU +
3551 //===----------------------------------------------------------------------===//
3552
3553 //  Add and accumulate.
3554 //  Rd=add(Rs,add(Ru,#s6))
3555 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3556           (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3557           "$dst = add($src1, add($src2, #$src3))",
3558           [(set (i32 IntRegs:$dst),
3559            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3560                                           s6ImmPred:$src3)))]>,
3561           Requires<[HasV4T]>;
3562
3563 //  Rd=add(Rs,sub(#s6,Ru))
3564 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3565           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3566           "$dst = add($src1, sub(#$src2, $src3))",
3567           [(set (i32 IntRegs:$dst),
3568            (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3569                                           (i32 IntRegs:$src3))))]>,
3570           Requires<[HasV4T]>;
3571
3572 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3573 // pattern.
3574 //  Rd=add(Rs,sub(#s6,Ru))
3575 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3576           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3577           "$dst = add($src1, sub(#$src2, $src3))",
3578           [(set (i32 IntRegs:$dst),
3579                 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3580                      (i32 IntRegs:$src3)))]>,
3581           Requires<[HasV4T]>;
3582
3583
3584 //  Add or subtract doublewords with carry.
3585 //TODO:
3586 //  Rdd=add(Rss,Rtt,Px):carry
3587 //TODO:
3588 //  Rdd=sub(Rss,Rtt,Px):carry
3589
3590
3591 //  Logical doublewords.
3592 //  Rdd=and(Rtt,~Rss)
3593 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3594           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3595           "$dst = and($src1, ~$src2)",
3596           [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3597                                       (not (i64 DoubleRegs:$src2))))]>,
3598           Requires<[HasV4T]>;
3599
3600 //  Rdd=or(Rtt,~Rss)
3601 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3602           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3603           "$dst = or($src1, ~$src2)",
3604           [(set (i64 DoubleRegs:$dst),
3605            (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3606           Requires<[HasV4T]>;
3607
3608
3609 //  Logical-logical doublewords.
3610 //  Rxx^=xor(Rss,Rtt)
3611 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3612           (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3613           "$dst ^= xor($src2, $src3)",
3614           [(set (i64 DoubleRegs:$dst),
3615            (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3616                                              (i64 DoubleRegs:$src3))))],
3617           "$src1 = $dst">,
3618           Requires<[HasV4T]>;
3619
3620
3621 // Logical-logical words.
3622 // Rx=or(Ru,and(Rx,#s10))
3623 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3624             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3625             "$dst = or($src1, and($src2, #$src3))",
3626             [(set (i32 IntRegs:$dst),
3627                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3628                                                 s10ImmPred:$src3)))],
3629             "$src2 = $dst">,
3630             Requires<[HasV4T]>;
3631
3632 // Rx[&|^]=and(Rs,Rt)
3633 // Rx&=and(Rs,Rt)
3634 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3635             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3636             "$dst &= and($src2, $src3)",
3637             [(set (i32 IntRegs:$dst),
3638                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3639                                                  (i32 IntRegs:$src3))))],
3640             "$src1 = $dst">,
3641             Requires<[HasV4T]>;
3642
3643 // Rx|=and(Rs,Rt)
3644 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3645             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3646             "$dst |= and($src2, $src3)",
3647             [(set (i32 IntRegs:$dst),
3648                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3649                                                 (i32 IntRegs:$src3))))],
3650             "$src1 = $dst">,
3651             Requires<[HasV4T]>;
3652
3653 // Rx^=and(Rs,Rt)
3654 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3655             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3656             "$dst ^= and($src2, $src3)",
3657             [(set (i32 IntRegs:$dst),
3658              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3659                                             (i32 IntRegs:$src3))))],
3660             "$src1 = $dst">,
3661             Requires<[HasV4T]>;
3662
3663 // Rx[&|^]=and(Rs,~Rt)
3664 // Rx&=and(Rs,~Rt)
3665 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3666             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3667             "$dst &= and($src2, ~$src3)",
3668             [(set (i32 IntRegs:$dst),
3669                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3670                                                  (not (i32 IntRegs:$src3)))))],
3671             "$src1 = $dst">,
3672             Requires<[HasV4T]>;
3673
3674 // Rx|=and(Rs,~Rt)
3675 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3676             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3677             "$dst |= and($src2, ~$src3)",
3678             [(set (i32 IntRegs:$dst),
3679              (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3680                                            (not (i32 IntRegs:$src3)))))],
3681             "$src1 = $dst">,
3682             Requires<[HasV4T]>;
3683
3684 // Rx^=and(Rs,~Rt)
3685 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3686             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3687             "$dst ^= and($src2, ~$src3)",
3688             [(set (i32 IntRegs:$dst),
3689              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3690                                             (not (i32 IntRegs:$src3)))))],
3691             "$src1 = $dst">,
3692             Requires<[HasV4T]>;
3693
3694 // Rx[&|^]=or(Rs,Rt)
3695 // Rx&=or(Rs,Rt)
3696 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3697             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3698             "$dst &= or($src2, $src3)",
3699             [(set (i32 IntRegs:$dst),
3700                   (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3701                                                 (i32 IntRegs:$src3))))],
3702             "$src1 = $dst">,
3703             Requires<[HasV4T]>;
3704
3705 // Rx|=or(Rs,Rt)
3706 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3707             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3708             "$dst |= or($src2, $src3)",
3709             [(set (i32 IntRegs:$dst),
3710                   (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3711                                                (i32 IntRegs:$src3))))],
3712             "$src1 = $dst">,
3713             Requires<[HasV4T]>;
3714
3715 // Rx^=or(Rs,Rt)
3716 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3717             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3718             "$dst ^= or($src2, $src3)",
3719             [(set (i32 IntRegs:$dst),
3720              (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3721                                            (i32 IntRegs:$src3))))],
3722             "$src1 = $dst">,
3723             Requires<[HasV4T]>;
3724
3725 // Rx[&|^]=xor(Rs,Rt)
3726 // Rx&=xor(Rs,Rt)
3727 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3728             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3729             "$dst &= xor($src2, $src3)",
3730             [(set (i32 IntRegs:$dst),
3731                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3732                                                  (i32 IntRegs:$src3))))],
3733             "$src1 = $dst">,
3734             Requires<[HasV4T]>;
3735
3736 // Rx|=xor(Rs,Rt)
3737 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3738             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3739             "$dst |= xor($src2, $src3)",
3740             [(set (i32 IntRegs:$dst),
3741                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3742                                                  (i32 IntRegs:$src3))))],
3743             "$src1 = $dst">,
3744             Requires<[HasV4T]>;
3745
3746 // Rx^=xor(Rs,Rt)
3747 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3748             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3749             "$dst ^= xor($src2, $src3)",
3750             [(set (i32 IntRegs:$dst),
3751              (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3752                                             (i32 IntRegs:$src3))))],
3753             "$src1 = $dst">,
3754             Requires<[HasV4T]>;
3755
3756 // Rx|=and(Rs,#s10)
3757 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3758             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3759             "$dst |= and($src2, #$src3)",
3760             [(set (i32 IntRegs:$dst),
3761                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3762                                                 s10ImmPred:$src3)))],
3763             "$src1 = $dst">,
3764             Requires<[HasV4T]>;
3765
3766 // Rx|=or(Rs,#s10)
3767 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3768             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3769             "$dst |= or($src2, #$src3)",
3770             [(set (i32 IntRegs:$dst),
3771                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3772                                                 s10ImmPred:$src3)))],
3773             "$src1 = $dst">,
3774             Requires<[HasV4T]>;
3775
3776
3777 //    Modulo wrap
3778 //        Rd=modwrap(Rs,Rt)
3779 //    Round
3780 //        Rd=cround(Rs,#u5)
3781 //        Rd=cround(Rs,Rt)
3782 //        Rd=round(Rs,#u5)[:sat]
3783 //        Rd=round(Rs,Rt)[:sat]
3784 //    Vector reduce add unsigned halfwords
3785 //        Rd=vraddh(Rss,Rtt)
3786 //    Vector add bytes
3787 //        Rdd=vaddb(Rss,Rtt)
3788 //    Vector conditional negate
3789 //        Rdd=vcnegh(Rss,Rt)
3790 //        Rxx+=vrcnegh(Rss,Rt)
3791 //    Vector maximum bytes
3792 //        Rdd=vmaxb(Rtt,Rss)
3793 //    Vector reduce maximum halfwords
3794 //        Rxx=vrmaxh(Rss,Ru)
3795 //        Rxx=vrmaxuh(Rss,Ru)
3796 //    Vector reduce maximum words
3797 //        Rxx=vrmaxuw(Rss,Ru)
3798 //        Rxx=vrmaxw(Rss,Ru)
3799 //    Vector minimum bytes
3800 //        Rdd=vminb(Rtt,Rss)
3801 //    Vector reduce minimum halfwords
3802 //        Rxx=vrminh(Rss,Ru)
3803 //        Rxx=vrminuh(Rss,Ru)
3804 //    Vector reduce minimum words
3805 //        Rxx=vrminuw(Rss,Ru)
3806 //        Rxx=vrminw(Rss,Ru)
3807 //    Vector subtract bytes
3808 //        Rdd=vsubb(Rss,Rtt)
3809
3810 //===----------------------------------------------------------------------===//
3811 // XTYPE/ALU -
3812 //===----------------------------------------------------------------------===//
3813
3814
3815 //===----------------------------------------------------------------------===//
3816 // XTYPE/MPY +
3817 //===----------------------------------------------------------------------===//
3818
3819 // Multiply and user lower result.
3820 // Rd=add(#u6,mpyi(Rs,#U6))
3821 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3822             (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
3823             "$dst = add(#$src1, mpyi($src2, #$src3))",
3824             [(set (i32 IntRegs:$dst),
3825                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3826                        u6ImmPred:$src1))]>,
3827             Requires<[HasV4T]>;
3828
3829 // Rd=add(#u6,mpyi(Rs,Rt))
3830
3831 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3832             (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
3833             "$dst = add(#$src1, mpyi($src2, $src3))",
3834             [(set (i32 IntRegs:$dst),
3835                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3836                        u6ImmPred:$src1))]>,
3837             Requires<[HasV4T]>;
3838
3839 // Rd=add(Ru,mpyi(#u6:2,Rs))
3840 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
3841             (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
3842             "$dst = add($src1, mpyi(#$src2, $src3))",
3843             [(set (i32 IntRegs:$dst),
3844              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
3845                                             u6_2ImmPred:$src2)))]>,
3846             Requires<[HasV4T]>;
3847
3848 // Rd=add(Ru,mpyi(Rs,#u6))
3849 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
3850             (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
3851             "$dst = add($src1, mpyi($src2, #$src3))",
3852             [(set (i32 IntRegs:$dst),
3853                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3854                                                  u6ImmPred:$src3)))]>,
3855             Requires<[HasV4T]>;
3856
3857 // Rx=add(Ru,mpyi(Rx,Rs))
3858 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
3859             (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3860             "$dst = add($src1, mpyi($src2, $src3))",
3861             [(set (i32 IntRegs:$dst),
3862              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3863                                             (i32 IntRegs:$src3))))],
3864             "$src2 = $dst">,
3865             Requires<[HasV4T]>;
3866
3867
3868 // Polynomial multiply words
3869 // Rdd=pmpyw(Rs,Rt)
3870 // Rxx^=pmpyw(Rs,Rt)
3871
3872 // Vector reduce multiply word by signed half (32x16)
3873 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
3874 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
3875 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
3876 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
3877
3878 // Multiply and use upper result
3879 // Rd=mpy(Rs,Rt.H):<<1:sat
3880 // Rd=mpy(Rs,Rt.L):<<1:sat
3881 // Rd=mpy(Rs,Rt):<<1
3882 // Rd=mpy(Rs,Rt):<<1:sat
3883 // Rd=mpysu(Rs,Rt)
3884 // Rx+=mpy(Rs,Rt):<<1:sat
3885 // Rx-=mpy(Rs,Rt):<<1:sat
3886
3887 // Vector multiply bytes
3888 // Rdd=vmpybsu(Rs,Rt)
3889 // Rdd=vmpybu(Rs,Rt)
3890 // Rxx+=vmpybsu(Rs,Rt)
3891 // Rxx+=vmpybu(Rs,Rt)
3892
3893 // Vector polynomial multiply halfwords
3894 // Rdd=vpmpyh(Rs,Rt)
3895 // Rxx^=vpmpyh(Rs,Rt)
3896
3897 //===----------------------------------------------------------------------===//
3898 // XTYPE/MPY -
3899 //===----------------------------------------------------------------------===//
3900
3901
3902 //===----------------------------------------------------------------------===//
3903 // XTYPE/SHIFT +
3904 //===----------------------------------------------------------------------===//
3905
3906 // Shift by immediate and accumulate.
3907 // Rx=add(#u8,asl(Rx,#U5))
3908 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3909             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3910             "$dst = add(#$src1, asl($src2, #$src3))",
3911             [(set (i32 IntRegs:$dst),
3912                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3913                        u8ImmPred:$src1))],
3914             "$src2 = $dst">,
3915             Requires<[HasV4T]>;
3916
3917 // Rx=add(#u8,lsr(Rx,#U5))
3918 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3919             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3920             "$dst = add(#$src1, lsr($src2, #$src3))",
3921             [(set (i32 IntRegs:$dst),
3922                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3923                        u8ImmPred:$src1))],
3924             "$src2 = $dst">,
3925             Requires<[HasV4T]>;
3926
3927 // Rx=sub(#u8,asl(Rx,#U5))
3928 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3929             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3930             "$dst = sub(#$src1, asl($src2, #$src3))",
3931             [(set (i32 IntRegs:$dst),
3932                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3933                        u8ImmPred:$src1))],
3934             "$src2 = $dst">,
3935             Requires<[HasV4T]>;
3936
3937 // Rx=sub(#u8,lsr(Rx,#U5))
3938 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3939             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3940             "$dst = sub(#$src1, lsr($src2, #$src3))",
3941             [(set (i32 IntRegs:$dst),
3942                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3943                        u8ImmPred:$src1))],
3944             "$src2 = $dst">,
3945             Requires<[HasV4T]>;
3946
3947
3948 //Shift by immediate and logical.
3949 //Rx=and(#u8,asl(Rx,#U5))
3950 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3951             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3952             "$dst = and(#$src1, asl($src2, #$src3))",
3953             [(set (i32 IntRegs:$dst),
3954                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3955                        u8ImmPred:$src1))],
3956             "$src2 = $dst">,
3957             Requires<[HasV4T]>;
3958
3959 //Rx=and(#u8,lsr(Rx,#U5))
3960 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3961             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3962             "$dst = and(#$src1, lsr($src2, #$src3))",
3963             [(set (i32 IntRegs:$dst),
3964                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3965                        u8ImmPred:$src1))],
3966             "$src2 = $dst">,
3967             Requires<[HasV4T]>;
3968
3969 //Rx=or(#u8,asl(Rx,#U5))
3970 let AddedComplexity = 30 in
3971 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3972             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3973             "$dst = or(#$src1, asl($src2, #$src3))",
3974             [(set (i32 IntRegs:$dst),
3975                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3976                       u8ImmPred:$src1))],
3977             "$src2 = $dst">,
3978             Requires<[HasV4T]>;
3979
3980 //Rx=or(#u8,lsr(Rx,#U5))
3981 let AddedComplexity = 30 in
3982 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3983             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3984             "$dst = or(#$src1, lsr($src2, #$src3))",
3985             [(set (i32 IntRegs:$dst),
3986                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3987                       u8ImmPred:$src1))],
3988             "$src2 = $dst">,
3989             Requires<[HasV4T]>;
3990
3991
3992 //Shift by register.
3993 //Rd=lsl(#s6,Rt)
3994 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
3995             "$dst = lsl(#$src1, $src2)",
3996             [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
3997                                            (i32 IntRegs:$src2)))]>,
3998             Requires<[HasV4T]>;
3999
4000
4001 //Shift by register and logical.
4002 //Rxx^=asl(Rss,Rt)
4003 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4004             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4005             "$dst ^= asl($src2, $src3)",
4006             [(set (i64 DoubleRegs:$dst),
4007                   (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
4008                                                     (i32 IntRegs:$src3))))],
4009             "$src1 = $dst">,
4010             Requires<[HasV4T]>;
4011
4012 //Rxx^=asr(Rss,Rt)
4013 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4014             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4015             "$dst ^= asr($src2, $src3)",
4016             [(set (i64 DoubleRegs:$dst),
4017                   (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
4018                                                     (i32 IntRegs:$src3))))],
4019             "$src1 = $dst">,
4020             Requires<[HasV4T]>;
4021
4022 //Rxx^=lsl(Rss,Rt)
4023 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4024             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4025             "$dst ^= lsl($src2, $src3)",
4026             [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
4027                                               (shl (i64 DoubleRegs:$src2),
4028                                                    (i32 IntRegs:$src3))))],
4029             "$src1 = $dst">,
4030             Requires<[HasV4T]>;
4031
4032 //Rxx^=lsr(Rss,Rt)
4033 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4034             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4035             "$dst ^= lsr($src2, $src3)",
4036             [(set (i64 DoubleRegs:$dst),
4037                   (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
4038                                                     (i32 IntRegs:$src3))))],
4039             "$src1 = $dst">,
4040             Requires<[HasV4T]>;
4041
4042
4043 //===----------------------------------------------------------------------===//
4044 // XTYPE/SHIFT -
4045 //===----------------------------------------------------------------------===//
4046
4047 //===----------------------------------------------------------------------===//
4048 // MEMOP: Word, Half, Byte
4049 //===----------------------------------------------------------------------===//
4050
4051 //===----------------------------------------------------------------------===//
4052 // MEMOP: Word
4053 //
4054 //  Implemented:
4055 //     MEMw_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
4056 //     MEMw_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
4057 //     MEMw_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
4058 //     MEMw_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
4059 //     MEMw_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
4060 //     MEMw_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
4061 //     MEMw_ADDi_V4          : memw(Rs+#u6:2)+=#U5
4062 //     MEMw_SUBi_V4          : memw(Rs+#u6:2)-=#U5
4063 //     MEMw_ADDr_V4          : memw(Rs+#u6:2)+=Rt
4064 //     MEMw_SUBr_V4          : memw(Rs+#u6:2)-=Rt
4065 //     MEMw_CLRr_V4          : memw(Rs+#u6:2)&=Rt
4066 //     MEMw_SETr_V4          : memw(Rs+#u6:2)|=Rt
4067 //
4068 //   Not implemented:
4069 //     MEMw_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
4070 //     MEMw_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
4071 //     MEMw_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
4072 //     MEMw_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
4073 //===----------------------------------------------------------------------===//
4074
4075
4076
4077 // memw(Rs+#u6:2) += #U5
4078 let AddedComplexity = 30 in
4079 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4080             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
4081             "memw($base+#$offset) += #$addend",
4082             []>,
4083             Requires<[HasV4T, UseMEMOP]>;
4084
4085 // memw(Rs+#u6:2) -= #U5
4086 let AddedComplexity = 30 in
4087 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4088             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
4089             "memw($base+#$offset) -= #$subend",
4090             []>,
4091             Requires<[HasV4T, UseMEMOP]>;
4092
4093 // memw(Rs+#u6:2) += Rt
4094 let AddedComplexity = 30 in
4095 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4096             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
4097             "memw($base+#$offset) += $addend",
4098             [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4099                          (i32 IntRegs:$addend)),
4100                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4101             Requires<[HasV4T, UseMEMOP]>;
4102
4103 // memw(Rs+#u6:2) -= Rt
4104 let AddedComplexity = 30 in
4105 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4106             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
4107             "memw($base+#$offset) -= $subend",
4108             [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4109                          (i32 IntRegs:$subend)),
4110                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4111             Requires<[HasV4T, UseMEMOP]>;
4112
4113 // memw(Rs+#u6:2) &= Rt
4114 let AddedComplexity = 30 in
4115 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4116             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
4117             "memw($base+#$offset) &= $andend",
4118             [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4119                          (i32 IntRegs:$andend)),
4120                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4121             Requires<[HasV4T, UseMEMOP]>;
4122
4123 // memw(Rs+#u6:2) |= Rt
4124 let AddedComplexity = 30 in
4125 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4126             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
4127             "memw($base+#$offset) |= $orend",
4128             [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4129                         (i32 IntRegs:$orend)),
4130                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4131             Requires<[HasV4T, UseMEMOP]>;
4132
4133 // memw(Rs+#u6:2) += #U5
4134 let AddedComplexity = 30 in
4135 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
4136             (ins MEMri:$addr, u5Imm:$addend),
4137             "memw($addr) += $addend",
4138             []>,
4139             Requires<[HasV4T, UseMEMOP]>;
4140
4141 // memw(Rs+#u6:2) -= #U5
4142 let AddedComplexity = 30 in
4143 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
4144             (ins MEMri:$addr, u5Imm:$subend),
4145             "memw($addr) -= $subend",
4146             []>,
4147             Requires<[HasV4T, UseMEMOP]>;
4148
4149 // memw(Rs+#u6:2) += Rt
4150 let AddedComplexity = 30 in
4151 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
4152             (ins MEMri:$addr, IntRegs:$addend),
4153             "memw($addr) += $addend",
4154             [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
4155                     ADDRriU6_2:$addr)]>,
4156             Requires<[HasV4T, UseMEMOP]>;
4157
4158 // memw(Rs+#u6:2) -= Rt
4159 let AddedComplexity = 30 in
4160 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
4161             (ins MEMri:$addr, IntRegs:$subend),
4162             "memw($addr) -= $subend",
4163             [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
4164                     ADDRriU6_2:$addr)]>,
4165             Requires<[HasV4T, UseMEMOP]>;
4166
4167 // memw(Rs+#u6:2) &= Rt
4168 let AddedComplexity = 30 in
4169 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
4170             (ins MEMri:$addr, IntRegs:$andend),
4171             "memw($addr) &= $andend",
4172             [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
4173                     ADDRriU6_2:$addr)]>,
4174             Requires<[HasV4T, UseMEMOP]>;
4175
4176 // memw(Rs+#u6:2) |= Rt
4177 let AddedComplexity = 30 in
4178 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
4179             (ins MEMri:$addr, IntRegs:$orend),
4180             "memw($addr) |= $orend",
4181             [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
4182                     ADDRriU6_2:$addr)]>,
4183             Requires<[HasV4T, UseMEMOP]>;
4184
4185 //===----------------------------------------------------------------------===//
4186 // MEMOP: Halfword
4187 //
4188 //  Implemented:
4189 //     MEMh_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
4190 //     MEMh_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
4191 //     MEMh_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
4192 //     MEMh_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
4193 //     MEMh_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
4194 //     MEMh_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
4195 //     MEMh_ADDi_V4          : memw(Rs+#u6:2)+=#U5
4196 //     MEMh_SUBi_V4          : memw(Rs+#u6:2)-=#U5
4197 //     MEMh_ADDr_V4          : memw(Rs+#u6:2)+=Rt
4198 //     MEMh_SUBr_V4          : memw(Rs+#u6:2)-=Rt
4199 //     MEMh_CLRr_V4          : memw(Rs+#u6:2)&=Rt
4200 //     MEMh_SETr_V4          : memw(Rs+#u6:2)|=Rt
4201 //
4202 //   Not implemented:
4203 //     MEMh_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
4204 //     MEMh_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
4205 //     MEMh_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
4206 //     MEMh_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
4207 //===----------------------------------------------------------------------===//
4208
4209
4210 // memh(Rs+#u6:1) += #U5
4211 let AddedComplexity = 30 in
4212 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4213             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
4214             "memh($base+#$offset) += $addend",
4215             []>,
4216             Requires<[HasV4T, UseMEMOP]>;
4217
4218 // memh(Rs+#u6:1) -= #U5
4219 let AddedComplexity = 30 in
4220 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4221             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
4222             "memh($base+#$offset) -= $subend",
4223             []>,
4224             Requires<[HasV4T, UseMEMOP]>;
4225
4226 // memh(Rs+#u6:1) += Rt
4227 let AddedComplexity = 30 in
4228 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4229             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
4230             "memh($base+#$offset) += $addend",
4231             [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
4232                                                    u6_1ImmPred:$offset)),
4233                                  (i32 IntRegs:$addend)),
4234                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4235             Requires<[HasV4T, UseMEMOP]>;
4236
4237 // memh(Rs+#u6:1) -= Rt
4238 let AddedComplexity = 30 in
4239 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4240             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
4241             "memh($base+#$offset) -= $subend",
4242             [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
4243                                                    u6_1ImmPred:$offset)),
4244                                  (i32 IntRegs:$subend)),
4245                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4246             Requires<[HasV4T, UseMEMOP]>;
4247
4248 // memh(Rs+#u6:1) &= Rt
4249 let AddedComplexity = 30 in
4250 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4251             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
4252             "memh($base+#$offset) += $andend",
4253             [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
4254                                                    u6_1ImmPred:$offset)),
4255                                  (i32 IntRegs:$andend)),
4256                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4257             Requires<[HasV4T, UseMEMOP]>;
4258
4259 // memh(Rs+#u6:1) |= Rt
4260 let AddedComplexity = 30 in
4261 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4262             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
4263             "memh($base+#$offset) |= $orend",
4264             [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
4265                                               u6_1ImmPred:$offset)),
4266                              (i32 IntRegs:$orend)),
4267                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4268             Requires<[HasV4T, UseMEMOP]>;
4269
4270 // memh(Rs+#u6:1) += #U5
4271 let AddedComplexity = 30 in
4272 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
4273             (ins MEMri:$addr, u5Imm:$addend),
4274             "memh($addr) += $addend",
4275             []>,
4276             Requires<[HasV4T, UseMEMOP]>;
4277
4278 // memh(Rs+#u6:1) -= #U5
4279 let AddedComplexity = 30 in
4280 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
4281             (ins MEMri:$addr, u5Imm:$subend),
4282             "memh($addr) -= $subend",
4283             []>,
4284             Requires<[HasV4T, UseMEMOP]>;
4285
4286 // memh(Rs+#u6:1) += Rt
4287 let AddedComplexity = 30 in
4288 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
4289             (ins MEMri:$addr, IntRegs:$addend),
4290             "memh($addr) += $addend",
4291             [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
4292                                  (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
4293             Requires<[HasV4T, UseMEMOP]>;
4294
4295 // memh(Rs+#u6:1) -= Rt
4296 let AddedComplexity = 30 in
4297 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
4298             (ins MEMri:$addr, IntRegs:$subend),
4299             "memh($addr) -= $subend",
4300             [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
4301                                  (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
4302             Requires<[HasV4T, UseMEMOP]>;
4303
4304 // memh(Rs+#u6:1) &= Rt
4305 let AddedComplexity = 30 in
4306 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
4307             (ins MEMri:$addr, IntRegs:$andend),
4308             "memh($addr) &= $andend",
4309             [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
4310                                  (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
4311             Requires<[HasV4T, UseMEMOP]>;
4312
4313 // memh(Rs+#u6:1) |= Rt
4314 let AddedComplexity = 30 in
4315 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
4316             (ins MEMri:$addr, IntRegs:$orend),
4317             "memh($addr) |= $orend",
4318             [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
4319                                 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
4320             Requires<[HasV4T, UseMEMOP]>;
4321
4322
4323 //===----------------------------------------------------------------------===//
4324 // MEMOP: Byte
4325 //
4326 //  Implemented:
4327 //     MEMb_ADDi_indexed_V4  : memb(Rs+#u6:0)+=#U5
4328 //     MEMb_SUBi_indexed_V4  : memb(Rs+#u6:0)-=#U5
4329 //     MEMb_ADDr_indexed_V4  : memb(Rs+#u6:0)+=Rt
4330 //     MEMb_SUBr_indexed_V4  : memb(Rs+#u6:0)-=Rt
4331 //     MEMb_CLRr_indexed_V4  : memb(Rs+#u6:0)&=Rt
4332 //     MEMb_SETr_indexed_V4  : memb(Rs+#u6:0)|=Rt
4333 //     MEMb_ADDi_V4          : memb(Rs+#u6:0)+=#U5
4334 //     MEMb_SUBi_V4          : memb(Rs+#u6:0)-=#U5
4335 //     MEMb_ADDr_V4          : memb(Rs+#u6:0)+=Rt
4336 //     MEMb_SUBr_V4          : memb(Rs+#u6:0)-=Rt
4337 //     MEMb_CLRr_V4          : memb(Rs+#u6:0)&=Rt
4338 //     MEMb_SETr_V4          : memb(Rs+#u6:0)|=Rt
4339 //
4340 //   Not implemented:
4341 //     MEMb_CLRi_indexed_V4  : memb(Rs+#u6:0)=clrbit(#U5)
4342 //     MEMb_SETi_indexed_V4  : memb(Rs+#u6:0)=setbit(#U5)
4343 //     MEMb_CLRi_V4          : memb(Rs+#u6:0)=clrbit(#U5)
4344 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
4345 //===----------------------------------------------------------------------===//
4346
4347 // memb(Rs+#u6:0) += #U5
4348 let AddedComplexity = 30 in
4349 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4350             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
4351             "memb($base+#$offset) += $addend",
4352             []>,
4353             Requires<[HasV4T, UseMEMOP]>;
4354
4355 // memb(Rs+#u6:0) -= #U5
4356 let AddedComplexity = 30 in
4357 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4358             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
4359             "memb($base+#$offset) -= $subend",
4360             []>,
4361             Requires<[HasV4T, UseMEMOP]>;
4362
4363 // memb(Rs+#u6:0) += Rt
4364 let AddedComplexity = 30 in
4365 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4366             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
4367             "memb($base+#$offset) += $addend",
4368             [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
4369                                                  u6_0ImmPred:$offset)),
4370                                 (i32 IntRegs:$addend)),
4371                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4372             Requires<[HasV4T, UseMEMOP]>;
4373
4374 // memb(Rs+#u6:0) -= Rt
4375 let AddedComplexity = 30 in
4376 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4377             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
4378             "memb($base+#$offset) -= $subend",
4379             [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
4380                                                  u6_0ImmPred:$offset)),
4381                                 (i32 IntRegs:$subend)),
4382                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4383             Requires<[HasV4T, UseMEMOP]>;
4384
4385 // memb(Rs+#u6:0) &= Rt
4386 let AddedComplexity = 30 in
4387 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4388             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
4389             "memb($base+#$offset) += $andend",
4390             [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
4391                                                  u6_0ImmPred:$offset)),
4392                                 (i32 IntRegs:$andend)),
4393                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4394             Requires<[HasV4T, UseMEMOP]>;
4395
4396 // memb(Rs+#u6:0) |= Rt
4397 let AddedComplexity = 30 in
4398 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4399             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
4400             "memb($base+#$offset) |= $orend",
4401             [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
4402                                                 u6_0ImmPred:$offset)),
4403                                (i32 IntRegs:$orend)),
4404                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4405             Requires<[HasV4T, UseMEMOP]>;
4406
4407 // memb(Rs+#u6:0) += #U5
4408 let AddedComplexity = 30 in
4409 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
4410             (ins MEMri:$addr, u5Imm:$addend),
4411             "memb($addr) += $addend",
4412             []>,
4413             Requires<[HasV4T, UseMEMOP]>;
4414
4415 // memb(Rs+#u6:0) -= #U5
4416 let AddedComplexity = 30 in
4417 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
4418             (ins MEMri:$addr, u5Imm:$subend),
4419             "memb($addr) -= $subend",
4420             []>,
4421             Requires<[HasV4T, UseMEMOP]>;
4422
4423 // memb(Rs+#u6:0) += Rt
4424 let AddedComplexity = 30 in
4425 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
4426             (ins MEMri:$addr, IntRegs:$addend),
4427             "memb($addr) += $addend",
4428             [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
4429                                 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
4430             Requires<[HasV4T, UseMEMOP]>;
4431
4432 // memb(Rs+#u6:0) -= Rt
4433 let AddedComplexity = 30 in
4434 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
4435             (ins MEMri:$addr, IntRegs:$subend),
4436             "memb($addr) -= $subend",
4437             [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
4438                                 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
4439             Requires<[HasV4T, UseMEMOP]>;
4440
4441 // memb(Rs+#u6:0) &= Rt
4442 let AddedComplexity = 30 in
4443 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
4444             (ins MEMri:$addr, IntRegs:$andend),
4445             "memb($addr) &= $andend",
4446             [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
4447                                 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
4448             Requires<[HasV4T, UseMEMOP]>;
4449
4450 // memb(Rs+#u6:0) |= Rt
4451 let AddedComplexity = 30 in
4452 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
4453             (ins MEMri:$addr, IntRegs:$orend),
4454             "memb($addr) |= $orend",
4455             [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
4456                                (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
4457             Requires<[HasV4T, UseMEMOP]>;
4458
4459
4460 //===----------------------------------------------------------------------===//
4461 // XTYPE/PRED +
4462 //===----------------------------------------------------------------------===//
4463
4464 // Hexagon V4 only supports these flavors of byte/half compare instructions:
4465 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
4466 // hardware. However, compiler can still implement these patterns through
4467 // appropriate patterns combinations based on current implemented patterns.
4468 // The implemented patterns are: EQ/GT/GTU.
4469 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
4470
4471 // Following instruction is not being extended as it results into the
4472 // incorrect code for negative numbers.
4473 // Pd=cmpb.eq(Rs,#u8)
4474
4475 let isCompare = 1 in
4476 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
4477             (ins IntRegs:$src1, u8Imm:$src2),
4478             "$dst = cmpb.eq($src1, #$src2)",
4479             [(set (i1 PredRegs:$dst),
4480                   (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
4481             Requires<[HasV4T]>;
4482
4483 // Pd=cmpb.eq(Rs,Rt)
4484 let isCompare = 1 in
4485 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
4486             (ins IntRegs:$src1, IntRegs:$src2),
4487             "$dst = cmpb.eq($src1, $src2)",
4488             [(set (i1 PredRegs:$dst),
4489                   (seteq (and (xor (i32 IntRegs:$src1),
4490                                    (i32 IntRegs:$src2)), 255), 0))]>,
4491             Requires<[HasV4T]>;
4492
4493 // Pd=cmpb.eq(Rs,Rt)
4494 let isCompare = 1 in
4495 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4496             (ins IntRegs:$src1, IntRegs:$src2),
4497             "$dst = cmpb.eq($src1, $src2)",
4498             [(set (i1 PredRegs:$dst),
4499                   (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4500                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4501             Requires<[HasV4T]>;
4502
4503 // Pd=cmpb.gt(Rs,Rt)
4504 let isCompare = 1 in
4505 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4506             (ins IntRegs:$src1, IntRegs:$src2),
4507             "$dst = cmpb.gt($src1, $src2)",
4508             [(set (i1 PredRegs:$dst),
4509                   (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4510                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4511             Requires<[HasV4T]>;
4512
4513 // Pd=cmpb.gtu(Rs,#u7)
4514 let isCompare = 1 in
4515 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4516             (ins IntRegs:$src1, u7Imm:$src2),
4517             "$dst = cmpb.gtu($src1, #$src2)",
4518             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4519                                               u7ImmPred:$src2))]>,
4520             Requires<[HasV4T]>;
4521
4522 // Pd=cmpb.gtu(Rs,Rt)
4523 let isCompare = 1 in
4524 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4525             (ins IntRegs:$src1, IntRegs:$src2),
4526             "$dst = cmpb.gtu($src1, $src2)",
4527             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4528                                              (and (i32 IntRegs:$src2), 255)))]>,
4529             Requires<[HasV4T]>;
4530
4531 // Following instruction is not being extended as it results into the incorrect
4532 // code for negative numbers.
4533
4534 // Signed half compare(.eq) ri.
4535 // Pd=cmph.eq(Rs,#s8)
4536 let isCompare = 1 in
4537 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4538             (ins IntRegs:$src1, s8Imm:$src2),
4539             "$dst = cmph.eq($src1, #$src2)",
4540             [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4541                                              s8ImmPred:$src2))]>,
4542             Requires<[HasV4T]>;
4543
4544 // Signed half compare(.eq) rr.
4545 // Case 1: xor + and, then compare:
4546 //   r0=xor(r0,r1)
4547 //   r0=and(r0,#0xffff)
4548 //   p0=cmp.eq(r0,#0)
4549 // Pd=cmph.eq(Rs,Rt)
4550 let isCompare = 1 in
4551 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4552             (ins IntRegs:$src1, IntRegs:$src2),
4553             "$dst = cmph.eq($src1, $src2)",
4554             [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4555                                                        (i32 IntRegs:$src2)),
4556                                                   65535), 0))]>,
4557             Requires<[HasV4T]>;
4558
4559 // Signed half compare(.eq) rr.
4560 // Case 2: shift left 16 bits then compare:
4561 //   r0=asl(r0,16)
4562 //   r1=asl(r1,16)
4563 //   p0=cmp.eq(r0,r1)
4564 // Pd=cmph.eq(Rs,Rt)
4565 let isCompare = 1 in
4566 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4567             (ins IntRegs:$src1, IntRegs:$src2),
4568             "$dst = cmph.eq($src1, $src2)",
4569             [(set (i1 PredRegs:$dst),
4570                   (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4571                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4572             Requires<[HasV4T]>;
4573
4574 /* Incorrect Pattern -- immediate should be right shifted before being
4575 used in the cmph.gt instruction.
4576 // Signed half compare(.gt) ri.
4577 // Pd=cmph.gt(Rs,#s8)
4578
4579 let isCompare = 1 in
4580 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4581             (ins IntRegs:$src1, s8Imm:$src2),
4582             "$dst = cmph.gt($src1, #$src2)",
4583             [(set (i1 PredRegs:$dst),
4584                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4585                          s8ImmPred:$src2))]>,
4586             Requires<[HasV4T]>;
4587 */
4588
4589 // Signed half compare(.gt) rr.
4590 // Pd=cmph.gt(Rs,Rt)
4591 let isCompare = 1 in
4592 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4593             (ins IntRegs:$src1, IntRegs:$src2),
4594             "$dst = cmph.gt($src1, $src2)",
4595             [(set (i1 PredRegs:$dst),
4596                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4597                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4598             Requires<[HasV4T]>;
4599
4600 // Unsigned half compare rr (.gtu).
4601 // Pd=cmph.gtu(Rs,Rt)
4602 let isCompare = 1 in
4603 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4604             (ins IntRegs:$src1, IntRegs:$src2),
4605             "$dst = cmph.gtu($src1, $src2)",
4606             [(set (i1 PredRegs:$dst),
4607                   (setugt (and (i32 IntRegs:$src1), 65535),
4608                           (and (i32 IntRegs:$src2), 65535)))]>,
4609             Requires<[HasV4T]>;
4610
4611 // Unsigned half compare ri (.gtu).
4612 // Pd=cmph.gtu(Rs,#u7)
4613 let isCompare = 1 in
4614 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4615             (ins IntRegs:$src1, u7Imm:$src2),
4616             "$dst = cmph.gtu($src1, #$src2)",
4617             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4618                                               u7ImmPred:$src2))]>,
4619             Requires<[HasV4T]>;
4620
4621 //===----------------------------------------------------------------------===//
4622 // XTYPE/PRED -
4623 //===----------------------------------------------------------------------===//
4624
4625 //Deallocate frame and return.
4626 //    dealloc_return
4627 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4628   Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4629   def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4630             "dealloc_return",
4631             []>,
4632             Requires<[HasV4T]>;
4633 }
4634
4635 // Restore registers and dealloc return function call.
4636 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4637   Defs = [R29, R30, R31, PC] in {
4638   def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4639                                    (ins calltarget:$dst),
4640              "jump $dst // Restore_and_dealloc_return",
4641              []>,
4642              Requires<[HasV4T]>;
4643 }
4644
4645 // Restore registers and dealloc frame before a tail call.
4646 let isCall = 1, isBarrier = 1,
4647   Defs = [R29, R30, R31, PC] in {
4648   def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4649                                            (ins calltarget:$dst),
4650              "call $dst // Restore_and_dealloc_before_tailcall",
4651              []>,
4652              Requires<[HasV4T]>;
4653 }
4654
4655 // Save registers function call.
4656 let isCall = 1, isBarrier = 1,
4657   Uses = [R29, R31] in {
4658   def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4659                                (ins calltarget:$dst),
4660              "call $dst // Save_calle_saved_registers",
4661              []>,
4662              Requires<[HasV4T]>;
4663 }
4664
4665 //    if (Ps) dealloc_return
4666 let isReturn = 1, isTerminator = 1,
4667     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4668     isPredicated = 1 in {
4669   def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4670                            (ins PredRegs:$src1, i32imm:$amt1),
4671             "if ($src1) dealloc_return",
4672             []>,
4673             Requires<[HasV4T]>;
4674 }
4675
4676 //    if (!Ps) dealloc_return
4677 let isReturn = 1, isTerminator = 1,
4678     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4679     isPredicated = 1 in {
4680   def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4681                                                      i32imm:$amt1),
4682             "if (!$src1) dealloc_return",
4683             []>,
4684             Requires<[HasV4T]>;
4685 }
4686
4687 //    if (Ps.new) dealloc_return:nt
4688 let isReturn = 1, isTerminator = 1,
4689     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4690     isPredicated = 1 in {
4691   def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4692                                                      i32imm:$amt1),
4693             "if ($src1.new) dealloc_return:nt",
4694             []>,
4695             Requires<[HasV4T]>;
4696 }
4697
4698 //    if (!Ps.new) dealloc_return:nt
4699 let isReturn = 1, isTerminator = 1,
4700     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4701     isPredicated = 1 in {
4702   def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4703                                                         i32imm:$amt1),
4704             "if (!$src1.new) dealloc_return:nt",
4705             []>,
4706             Requires<[HasV4T]>;
4707 }
4708
4709 //    if (Ps.new) dealloc_return:t
4710 let isReturn = 1, isTerminator = 1,
4711     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4712     isPredicated = 1 in {
4713   def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4714                                                     i32imm:$amt1),
4715             "if ($src1.new) dealloc_return:t",
4716             []>,
4717             Requires<[HasV4T]>;
4718 }
4719
4720 //    if (!Ps.new) dealloc_return:nt
4721 let isReturn = 1, isTerminator = 1,
4722     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4723     isPredicated = 1 in {
4724   def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4725                                                        i32imm:$amt1),
4726             "if (!$src1.new) dealloc_return:t",
4727             []>,
4728             Requires<[HasV4T]>;
4729 }
4730
4731
4732 // Load/Store with absolute addressing mode
4733 // memw(#u6)=Rt
4734
4735 multiclass ST_abs<string OpcStr> {
4736   let isPredicable = 1 in
4737   def _abs_V4 : STInst2<(outs),
4738             (ins globaladdress:$absaddr, IntRegs:$src),
4739             !strconcat(OpcStr, "(##$absaddr) = $src"),
4740             []>,
4741             Requires<[HasV4T]>;
4742
4743   let isPredicated = 1 in
4744   def _abs_cPt_V4 : STInst2<(outs),
4745             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4746             !strconcat("if ($src1)",
4747             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4748             []>,
4749             Requires<[HasV4T]>;
4750
4751   let isPredicated = 1 in
4752   def _abs_cNotPt_V4 : STInst2<(outs),
4753             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4754             !strconcat("if (!$src1)",
4755             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4756             []>,
4757             Requires<[HasV4T]>;
4758
4759   let isPredicated = 1 in
4760   def _abs_cdnPt_V4 : STInst2<(outs),
4761             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4762             !strconcat("if ($src1.new)",
4763             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4764             []>,
4765             Requires<[HasV4T]>;
4766
4767   let isPredicated = 1 in
4768   def _abs_cdnNotPt_V4 : STInst2<(outs),
4769             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4770             !strconcat("if (!$src1.new)",
4771             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4772             []>,
4773             Requires<[HasV4T]>;
4774
4775   def _abs_nv_V4 : STInst2<(outs),
4776             (ins globaladdress:$absaddr, IntRegs:$src),
4777             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4778             []>,
4779             Requires<[HasV4T]>;
4780
4781   let isPredicated = 1 in
4782   def _abs_cPt_nv_V4 : STInst2<(outs),
4783             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4784             !strconcat("if ($src1)",
4785             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4786             []>,
4787             Requires<[HasV4T]>;
4788
4789   let isPredicated = 1 in
4790   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4791             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4792             !strconcat("if (!$src1)",
4793             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4794             []>,
4795             Requires<[HasV4T]>;
4796
4797   let isPredicated = 1 in
4798   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4799             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4800             !strconcat("if ($src1.new)",
4801             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4802             []>,
4803             Requires<[HasV4T]>;
4804
4805   let isPredicated = 1 in
4806   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4807             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4808             !strconcat("if (!$src1.new)",
4809             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4810             []>,
4811             Requires<[HasV4T]>;
4812 }
4813
4814 let AddedComplexity = 30, isPredicable = 1 in
4815 def STrid_abs_V4 : STInst<(outs),
4816           (ins globaladdress:$absaddr, DoubleRegs:$src),
4817            "memd(##$absaddr) = $src",
4818           [(store (i64 DoubleRegs:$src),
4819                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
4820           Requires<[HasV4T]>;
4821
4822 let AddedComplexity = 30, isPredicated = 1 in
4823 def STrid_abs_cPt_V4 : STInst2<(outs),
4824           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4825           "if ($src1) memd(##$absaddr) = $src2",
4826           []>,
4827           Requires<[HasV4T]>;
4828
4829 let AddedComplexity = 30, isPredicated = 1 in
4830 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4831           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4832           "if (!$src1) memd(##$absaddr) = $src2",
4833           []>,
4834           Requires<[HasV4T]>;
4835
4836 let AddedComplexity = 30, isPredicated = 1 in
4837 def STrid_abs_cdnPt_V4 : STInst2<(outs),
4838           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4839           "if ($src1.new) memd(##$absaddr) = $src2",
4840           []>,
4841           Requires<[HasV4T]>;
4842
4843 let AddedComplexity = 30, isPredicated = 1 in
4844 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
4845           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4846           "if (!$src1.new) memd(##$absaddr) = $src2",
4847           []>,
4848           Requires<[HasV4T]>;
4849
4850 defm STrib : ST_abs<"memb">;
4851 defm STrih : ST_abs<"memh">;
4852 defm STriw : ST_abs<"memw">;
4853
4854 let Predicates = [HasV4T], AddedComplexity  = 30 in
4855 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
4856                         (HexagonCONST32 tglobaladdr:$absaddr)),
4857           (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4858
4859 let Predicates = [HasV4T], AddedComplexity  = 30 in
4860 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
4861                           (HexagonCONST32 tglobaladdr:$absaddr)),
4862           (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4863
4864 let Predicates = [HasV4T], AddedComplexity  = 30 in
4865 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
4866           (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4867
4868
4869 multiclass LD_abs<string OpcStr> {
4870   let isPredicable = 1 in
4871   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4872             (ins globaladdress:$absaddr),
4873             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
4874             []>,
4875             Requires<[HasV4T]>;
4876
4877   let isPredicated = 1 in
4878   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4879             (ins PredRegs:$src1, globaladdress:$absaddr),
4880             !strconcat("if ($src1) $dst = ",
4881             !strconcat(OpcStr, "(##$absaddr)")),
4882             []>,
4883             Requires<[HasV4T]>;
4884
4885   let isPredicated = 1 in
4886   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4887             (ins PredRegs:$src1, globaladdress:$absaddr),
4888             !strconcat("if (!$src1) $dst = ",
4889             !strconcat(OpcStr, "(##$absaddr)")),
4890             []>,
4891             Requires<[HasV4T]>;
4892
4893   let isPredicated = 1 in
4894   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4895             (ins PredRegs:$src1, globaladdress:$absaddr),
4896             !strconcat("if ($src1.new) $dst = ",
4897             !strconcat(OpcStr, "(##$absaddr)")),
4898             []>,
4899             Requires<[HasV4T]>;
4900
4901   let isPredicated = 1 in
4902   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4903             (ins PredRegs:$src1, globaladdress:$absaddr),
4904             !strconcat("if (!$src1.new) $dst = ",
4905             !strconcat(OpcStr, "(##$absaddr)")),
4906             []>,
4907             Requires<[HasV4T]>;
4908 }
4909
4910 let AddedComplexity = 30 in
4911 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
4912           (ins globaladdress:$absaddr),
4913           "$dst = memd(##$absaddr)",
4914           [(set (i64 DoubleRegs:$dst),
4915                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
4916           Requires<[HasV4T]>;
4917
4918 let AddedComplexity = 30, isPredicated = 1 in
4919 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4920           (ins PredRegs:$src1, globaladdress:$absaddr),
4921           "if ($src1) $dst = memd(##$absaddr)",
4922           []>,
4923           Requires<[HasV4T]>;
4924
4925 let AddedComplexity = 30, isPredicated = 1 in
4926 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4927           (ins PredRegs:$src1, globaladdress:$absaddr),
4928           "if (!$src1) $dst = memd(##$absaddr)",
4929           []>,
4930           Requires<[HasV4T]>;
4931
4932 let AddedComplexity = 30, isPredicated = 1 in
4933 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4934           (ins PredRegs:$src1, globaladdress:$absaddr),
4935           "if ($src1.new) $dst = memd(##$absaddr)",
4936           []>,
4937           Requires<[HasV4T]>;
4938
4939 let AddedComplexity = 30, isPredicated = 1 in
4940 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4941           (ins PredRegs:$src1, globaladdress:$absaddr),
4942           "if (!$src1.new) $dst = memd(##$absaddr)",
4943           []>,
4944           Requires<[HasV4T]>;
4945
4946 defm LDrib : LD_abs<"memb">;
4947 defm LDriub : LD_abs<"memub">;
4948 defm LDrih : LD_abs<"memh">;
4949 defm LDriuh : LD_abs<"memuh">;
4950 defm LDriw : LD_abs<"memw">;
4951
4952
4953 let Predicates = [HasV4T], AddedComplexity  = 30 in
4954 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
4955           (LDriw_abs_V4 tglobaladdr: $absaddr)>;
4956
4957 let Predicates = [HasV4T], AddedComplexity=30 in
4958 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4959           (LDrib_abs_V4 tglobaladdr:$absaddr)>;
4960
4961 let Predicates = [HasV4T], AddedComplexity=30 in
4962 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4963           (LDriub_abs_V4 tglobaladdr:$absaddr)>;
4964
4965 let Predicates = [HasV4T], AddedComplexity=30 in
4966 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4967           (LDrih_abs_V4 tglobaladdr:$absaddr)>;
4968
4969 let Predicates = [HasV4T], AddedComplexity=30 in
4970 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4971           (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
4972
4973 // Transfer global address into a register
4974 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
4975 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
4976            "$dst = ##$src1",
4977            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
4978            Requires<[HasV4T]>;
4979
4980 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4981 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4982                            (ins PredRegs:$src1, globaladdress:$src2),
4983            "if($src1) $dst = ##$src2",
4984            []>,
4985            Requires<[HasV4T]>;
4986
4987 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4988 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4989                               (ins PredRegs:$src1, globaladdress:$src2),
4990            "if(!$src1) $dst = ##$src2",
4991            []>,
4992            Requires<[HasV4T]>;
4993
4994 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4995 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4996                              (ins PredRegs:$src1, globaladdress:$src2),
4997            "if($src1.new) $dst = ##$src2",
4998            []>,
4999            Requires<[HasV4T]>;
5000
5001 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5002 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5003                                 (ins PredRegs:$src1, globaladdress:$src2),
5004            "if(!$src1.new) $dst = ##$src2",
5005            []>,
5006            Requires<[HasV4T]>;
5007
5008 let AddedComplexity = 50, Predicates = [HasV4T] in
5009 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
5010            (TFRI_V4 tglobaladdr:$src1)>;
5011
5012
5013 // Load - Indirect with long offset: These instructions take global address
5014 // as an operand
5015 let AddedComplexity = 10 in
5016 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
5017             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5018             "$dst=memd($src1<<#$src2+##$offset)",
5019             [(set (i64 DoubleRegs:$dst),
5020                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
5021                         (HexagonCONST32 tglobaladdr:$offset))))]>,
5022             Requires<[HasV4T]>;
5023
5024 let AddedComplexity = 10 in
5025 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
5026   def _lo_V4 : LDInst<(outs IntRegs:$dst),
5027             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5028             !strconcat("$dst = ",
5029             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
5030             [(set IntRegs:$dst,
5031                   (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
5032                           (HexagonCONST32 tglobaladdr:$offset)))))]>,
5033             Requires<[HasV4T]>;
5034 }
5035
5036 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
5037 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
5038 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
5039 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
5040 defm LDriw_ind : LD_indirect_lo<"memw", load>;
5041
5042 // Store - Indirect with long offset: These instructions take global address
5043 // as an operand
5044 let AddedComplexity = 10 in
5045 def STrid_ind_lo_V4 : STInst<(outs),
5046             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5047                  DoubleRegs:$src4),
5048             "memd($src1<<#$src2+#$src3) = $src4",
5049             [(store (i64 DoubleRegs:$src4),
5050                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
5051                       (HexagonCONST32 tglobaladdr:$src3)))]>,
5052              Requires<[HasV4T]>;
5053
5054 let AddedComplexity = 10 in
5055 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
5056   def _lo_V4 : STInst<(outs),
5057             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5058                  IntRegs:$src4),
5059             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
5060             [(OpNode (i32 IntRegs:$src4),
5061                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
5062                       (HexagonCONST32 tglobaladdr:$src3)))]>,
5063              Requires<[HasV4T]>;
5064 }
5065
5066 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
5067 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
5068 defm STriw_ind : ST_indirect_lo<"memw", store>;
5069
5070 // Store - absolute addressing mode: These instruction take constant
5071 // value as the extended operand
5072 multiclass ST_absimm<string OpcStr> {
5073   let isPredicable = 1 in
5074   def _abs_V4 : STInst2<(outs),
5075             (ins u6Imm:$src1, IntRegs:$src2),
5076             !strconcat(OpcStr, "(#$src1) = $src2"),
5077             []>,
5078             Requires<[HasV4T]>;
5079
5080   let isPredicated = 1 in
5081   def _abs_cPt_V4 : STInst2<(outs),
5082             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5083             !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5084             []>,
5085             Requires<[HasV4T]>;
5086
5087   let isPredicated = 1 in
5088   def _abs_cNotPt_V4 : STInst2<(outs),
5089             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5090             !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5091             []>,
5092             Requires<[HasV4T]>;
5093
5094   let isPredicated = 1 in
5095   def _abs_cdnPt_V4 : STInst2<(outs),
5096             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5097             !strconcat("if ($src1.new)",
5098             !strconcat(OpcStr, "(#$src2) = $src3")),
5099             []>,
5100             Requires<[HasV4T]>;
5101
5102   let isPredicated = 1 in
5103   def _abs_cdnNotPt_V4 : STInst2<(outs),
5104             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5105             !strconcat("if (!$src1.new)",
5106             !strconcat(OpcStr, "(#$src2) = $src3")),
5107             []>,
5108             Requires<[HasV4T]>;
5109
5110   def _abs_nv_V4 : STInst2<(outs),
5111             (ins u6Imm:$src1, IntRegs:$src2),
5112             !strconcat(OpcStr, "(#$src1) = $src2.new"),
5113             []>,
5114             Requires<[HasV4T]>;
5115
5116   let isPredicated = 1 in
5117   def _abs_cPt_nv_V4 : STInst2<(outs),
5118             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5119             !strconcat("if ($src1)",
5120             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5121             []>,
5122             Requires<[HasV4T]>;
5123
5124   let isPredicated = 1 in
5125   def _abs_cNotPt_nv_V4 : STInst2<(outs),
5126             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5127             !strconcat("if (!$src1)",
5128             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5129             []>,
5130             Requires<[HasV4T]>;
5131
5132   let isPredicated = 1 in
5133   def _abs_cdnPt_nv_V4 : STInst2<(outs),
5134             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5135             !strconcat("if ($src1.new)",
5136             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5137             []>,
5138             Requires<[HasV4T]>;
5139
5140   let isPredicated = 1 in
5141   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
5142             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5143             !strconcat("if (!$src1.new)",
5144             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5145             []>,
5146             Requires<[HasV4T]>;
5147 }
5148
5149 defm STrib_imm : ST_absimm<"memb">;
5150 defm STrih_imm : ST_absimm<"memh">;
5151 defm STriw_imm : ST_absimm<"memw">;
5152
5153 let Predicates = [HasV4T], AddedComplexity  = 30 in
5154 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
5155           (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5156
5157 let Predicates = [HasV4T], AddedComplexity  = 30 in
5158 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
5159           (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5160
5161 let Predicates = [HasV4T], AddedComplexity  = 30 in
5162 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
5163           (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5164
5165
5166 // Load - absolute addressing mode: These instruction take constant
5167 // value as the extended operand
5168
5169 multiclass LD_absimm<string OpcStr> {
5170   let isPredicable = 1 in
5171   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
5172             (ins u6Imm:$src),
5173             !strconcat("$dst = ",
5174             !strconcat(OpcStr, "(#$src)")),
5175             []>,
5176             Requires<[HasV4T]>;
5177
5178   let isPredicated = 1 in
5179   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
5180             (ins PredRegs:$src1, u6Imm:$src2),
5181             !strconcat("if ($src1) $dst = ",
5182             !strconcat(OpcStr, "(#$src2)")),
5183             []>,
5184             Requires<[HasV4T]>;
5185
5186   let isPredicated = 1 in
5187   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5188             (ins PredRegs:$src1, u6Imm:$src2),
5189             !strconcat("if (!$src1) $dst = ",
5190             !strconcat(OpcStr, "(#$src2)")),
5191             []>,
5192             Requires<[HasV4T]>;
5193
5194   let isPredicated = 1 in
5195   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
5196             (ins PredRegs:$src1, u6Imm:$src2),
5197             !strconcat("if ($src1.new) $dst = ",
5198             !strconcat(OpcStr, "(#$src2)")),
5199             []>,
5200             Requires<[HasV4T]>;
5201
5202   let isPredicated = 1 in
5203   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5204             (ins PredRegs:$src1, u6Imm:$src2),
5205             !strconcat("if (!$src1.new) $dst = ",
5206             !strconcat(OpcStr, "(#$src2)")),
5207             []>,
5208             Requires<[HasV4T]>;
5209 }
5210
5211 defm LDrib_imm : LD_absimm<"memb">;
5212 defm LDriub_imm : LD_absimm<"memub">;
5213 defm LDrih_imm : LD_absimm<"memh">;
5214 defm LDriuh_imm : LD_absimm<"memuh">;
5215 defm LDriw_imm : LD_absimm<"memw">;
5216
5217 let Predicates = [HasV4T], AddedComplexity  = 30 in
5218 def : Pat<(i32 (load u6ImmPred:$src)),
5219           (LDriw_imm_abs_V4 u6ImmPred:$src)>;
5220
5221 let Predicates = [HasV4T], AddedComplexity=30 in
5222 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
5223           (LDrib_imm_abs_V4 u6ImmPred:$src)>;
5224
5225 let Predicates = [HasV4T], AddedComplexity=30 in
5226 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
5227           (LDriub_imm_abs_V4 u6ImmPred:$src)>;
5228
5229 let Predicates = [HasV4T], AddedComplexity=30 in
5230 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
5231           (LDrih_imm_abs_V4 u6ImmPred:$src)>;
5232
5233 let Predicates = [HasV4T], AddedComplexity=30 in
5234 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
5235           (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
5236
5237
5238 // Indexed store double word - global address.
5239 // memw(Rs+#u6:2)=#S8
5240 let AddedComplexity = 10 in
5241 def STriw_offset_ext_V4 : STInst<(outs),
5242             (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
5243             "memw($src1+#$src2) = ##$src3",
5244             [(store (HexagonCONST32 tglobaladdr:$src3),
5245                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
5246             Requires<[HasV4T]>;
5247
5248
5249 // Indexed store double word - global address.
5250 // memw(Rs+#u6:2)=#S8
5251 let AddedComplexity = 10 in
5252 def STrih_offset_ext_V4 : STInst<(outs),
5253             (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
5254             "memh($src1+#$src2) = ##$src3",
5255             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
5256                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
5257             Requires<[HasV4T]>;