1 //===-- SPUFrameInfo.h - Top-level interface for Cell SPU Target -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation.
8 // See README.txt for details.
10 //===----------------------------------------------------------------------===//
12 // This file contains CellSPU frame information that doesn't fit anywhere else
15 //===----------------------------------------------------------------------===//
17 #if !defined(SPUFRAMEINFO_H)
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "SPURegisterInfo.h"
24 class SPUFrameInfo: public TargetFrameInfo {
25 const TargetMachine &TM;
26 std::pair<unsigned, int> LR[1];
29 SPUFrameInfo(const TargetMachine &tm);
31 //! Return a function's saved spill slots
33 For CellSPU, a function's saved spill slots is just the link register.
35 const std::pair<unsigned, int> *
36 getCalleeSaveSpillSlots(unsigned &NumEntries) const;
38 //! Stack slot size (16 bytes)
39 static const int stackSlotSize() {
42 //! Maximum frame offset representable by a signed 10-bit integer
44 This is the maximum frame offset that can be expressed as a 10-bit
45 integer, used in D-form addresses.
47 static const int maxFrameOffset() {
48 return ((1 << 9) - 1) * stackSlotSize();
50 //! Minimum frame offset representable by a signed 10-bit integer
51 static const int minFrameOffset() {
52 return -(1 << 9) * stackSlotSize();
54 //! Minimum frame size (enough to spill LR + SP)
55 static const int minStackSize() {
56 return (2 * stackSlotSize());
58 //! Frame size required to spill all registers plus frame info
59 static const int fullSpillSize() {
60 return (SPURegisterInfo::getNumArgRegs() * stackSlotSize());
62 //! Number of instructions required to overcome hint-for-branch latency
64 HBR (hint-for-branch) instructions can be inserted when, for example,
65 we know that a given function is going to be called, such as printf(),
66 in the control flow graph. HBRs are only inserted if a sufficient number
67 of instructions occurs between the HBR and the target. Currently, HBRs
68 take 6 cycles, ergo, the magic number 6.
70 static const int branchHintPenalty() {
76 #define SPUFRAMEINFO_H 1