1947e6567037bc5472bad4799bd66e4dd7a5ae04
[oota-llvm.git] / lib / Target / Alpha / AlphaTargetMachine.cpp
1 //===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Alpha.h"
14 #include "AlphaJITInfo.h"
15 #include "AlphaTargetAsmInfo.h"
16 #include "AlphaTargetMachine.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineRegistry.h"
20 #include "llvm/Support/FormattedStream.h"
21
22 using namespace llvm;
23
24 // Register the targets
25 static RegisterTarget<AlphaTargetMachine> X(TheAlphaTarget, "alpha", 
26                                             "Alpha [experimental]");
27
28 // Force static initialization.
29 extern "C" void LLVMInitializeAlphaTarget() { }
30
31 const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
32   return new AlphaTargetAsmInfo(*this);
33 }
34
35 AlphaTargetMachine::AlphaTargetMachine(const Target &T, const Module &M, 
36                                        const std::string &FS)
37   : LLVMTargetMachine(T),
38     DataLayout("e-f128:128:128"),
39     FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
40     JITInfo(*this),
41     Subtarget(M, FS),
42     TLInfo(*this) {
43   setRelocationModel(Reloc::PIC_);
44 }
45
46
47 //===----------------------------------------------------------------------===//
48 // Pass Pipeline Configuration
49 //===----------------------------------------------------------------------===//
50
51 bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
52                                          CodeGenOpt::Level OptLevel) {
53   PM.add(createAlphaISelDag(*this));
54   return false;
55 }
56 bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
57                                         CodeGenOpt::Level OptLevel) {
58   // Must run branch selection immediately preceding the asm printer
59   PM.add(createAlphaBranchSelectionPass());
60   PM.add(createAlphaLLRPPass(*this));
61   return false;
62 }
63 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
64                                         CodeGenOpt::Level OptLevel,
65                                         MachineCodeEmitter &MCE) {
66   PM.add(createAlphaCodeEmitterPass(*this, MCE));
67   return false;
68 }
69 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
70                                         CodeGenOpt::Level OptLevel,
71                                         JITCodeEmitter &JCE) {
72   PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
73   return false;
74 }
75 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
76                                         CodeGenOpt::Level OptLevel,
77                                         ObjectCodeEmitter &OCE) {
78   PM.add(createAlphaObjectCodeEmitterPass(*this, OCE));
79   return false;
80 }
81 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
82                                               CodeGenOpt::Level OptLevel,
83                                               MachineCodeEmitter &MCE) {
84   return addCodeEmitter(PM, OptLevel, MCE);
85 }
86 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
87                                               CodeGenOpt::Level OptLevel,
88                                               JITCodeEmitter &JCE) {
89   return addCodeEmitter(PM, OptLevel, JCE);
90 }
91 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
92                                               CodeGenOpt::Level OptLevel,
93                                               ObjectCodeEmitter &OCE) {
94   return addCodeEmitter(PM, OptLevel, OCE);
95 }
96