1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Module.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
30 /// AddLiveIn - This helper function adds the specified physical register to the
31 /// MachineFunction as a live in value. It also creates a corresponding virtual
33 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
34 TargetRegisterClass *RC) {
35 assert(RC->contains(PReg) && "Not the correct regclass!");
36 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
37 MF.getRegInfo().addLiveIn(PReg, VReg);
41 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
42 // Set up the TargetLowering object.
43 //I am having problems with shr n i8 1
44 setShiftAmountType(MVT::i64);
45 setBooleanContents(ZeroOrOneBooleanContent);
47 setUsesGlobalOffsetTable(true);
49 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
50 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
51 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
53 // We want to custom lower some of our intrinsics.
54 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
56 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
59 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
60 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
62 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
63 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
64 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
66 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
67 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
68 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
69 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
71 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
73 setOperationAction(ISD::FREM, MVT::f32, Expand);
74 setOperationAction(ISD::FREM, MVT::f64, Expand);
76 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
77 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
78 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
79 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
81 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
82 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
83 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
84 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
86 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
87 setOperationAction(ISD::ROTL , MVT::i64, Expand);
88 setOperationAction(ISD::ROTR , MVT::i64, Expand);
90 setOperationAction(ISD::SREM , MVT::i64, Custom);
91 setOperationAction(ISD::UREM , MVT::i64, Custom);
92 setOperationAction(ISD::SDIV , MVT::i64, Custom);
93 setOperationAction(ISD::UDIV , MVT::i64, Custom);
95 setOperationAction(ISD::ADDC , MVT::i64, Expand);
96 setOperationAction(ISD::ADDE , MVT::i64, Expand);
97 setOperationAction(ISD::SUBC , MVT::i64, Expand);
98 setOperationAction(ISD::SUBE , MVT::i64, Expand);
100 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
101 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
104 // We don't support sin/cos/sqrt/pow
105 setOperationAction(ISD::FSIN , MVT::f64, Expand);
106 setOperationAction(ISD::FCOS , MVT::f64, Expand);
107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
110 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
111 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
113 setOperationAction(ISD::FPOW , MVT::f32, Expand);
114 setOperationAction(ISD::FPOW , MVT::f64, Expand);
116 setOperationAction(ISD::SETCC, MVT::f32, Promote);
118 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
120 // We don't have line number support yet.
121 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
122 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
123 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
124 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
126 // Not implemented yet.
127 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
128 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
129 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
131 // We want to legalize GlobalAddress and ConstantPool and
132 // ExternalSymbols nodes into the appropriate instructions to
133 // materialize the address.
134 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
135 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
136 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
137 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
139 setOperationAction(ISD::VASTART, MVT::Other, Custom);
140 setOperationAction(ISD::VAEND, MVT::Other, Expand);
141 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
142 setOperationAction(ISD::VAARG, MVT::Other, Custom);
143 setOperationAction(ISD::VAARG, MVT::i32, Custom);
145 setOperationAction(ISD::RET, MVT::Other, Custom);
147 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
148 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
150 setStackPointerRegisterToSaveRestore(Alpha::R30);
152 addLegalFPImmediate(APFloat(+0.0)); //F31
153 addLegalFPImmediate(APFloat(+0.0f)); //F31
154 addLegalFPImmediate(APFloat(-0.0)); //-F31
155 addLegalFPImmediate(APFloat(-0.0f)); //-F31
158 setJumpBufAlignment(16);
160 computeRegisterProperties();
163 MVT AlphaTargetLowering::getSetCCResultType(MVT VT) const {
167 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
170 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
171 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
172 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
173 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
174 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
175 case AlphaISD::RelLit: return "Alpha::RelLit";
176 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
177 case AlphaISD::CALL: return "Alpha::CALL";
178 case AlphaISD::DivCall: return "Alpha::DivCall";
179 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
180 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
181 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
185 /// getFunctionAlignment - Return the Log2 alignment of this function.
186 unsigned AlphaTargetLowering::getFunctionAlignment(const Function *F) const {
190 static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
191 MVT PtrVT = Op.getValueType();
192 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
193 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
194 SDValue Zero = DAG.getConstant(0, PtrVT);
195 // FIXME there isn't really any debug info here
196 DebugLoc dl = Op.getDebugLoc();
198 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
199 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
200 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
204 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
205 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
207 //For now, just use variable size stack frame format
209 //In a standard call, the first six items are passed in registers $16
210 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
211 //of argument-to-register correspondence.) The remaining items are
212 //collected in a memory argument list that is a naturally aligned
213 //array of quadwords. In a standard call, this list, if present, must
214 //be passed at 0(SP).
215 //7 ... n 0(SP) ... (n-7)*8(SP)
223 static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
225 int &VarArgsOffset) {
226 MachineFunction &MF = DAG.getMachineFunction();
227 MachineFrameInfo *MFI = MF.getFrameInfo();
228 std::vector<SDValue> ArgValues;
229 SDValue Root = Op.getOperand(0);
230 DebugLoc dl = Op.getDebugLoc();
232 unsigned args_int[] = {
233 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
234 unsigned args_float[] = {
235 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
237 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
239 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
243 switch (ObjectVT.getSimpleVT()) {
245 assert(false && "Invalid value type!");
247 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
248 &Alpha::F8RCRegClass);
249 ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
252 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
253 &Alpha::F4RCRegClass);
254 ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
257 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
258 &Alpha::GPRCRegClass);
259 ArgVal = DAG.getCopyFromReg(Root, dl, args_int[ArgNo], MVT::i64);
263 // Create the frame index object for this incoming parameter...
264 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
266 // Create the SelectionDAG nodes corresponding to a load
267 //from this parameter
268 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
269 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
271 ArgValues.push_back(ArgVal);
274 // If the functions takes variable number of arguments, copy all regs to stack
275 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
277 VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
278 std::vector<SDValue> LS;
279 for (int i = 0; i < 6; ++i) {
280 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
281 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
282 SDValue argt = DAG.getCopyFromReg(Root, dl, args_int[i], MVT::i64);
283 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
284 if (i == 0) VarArgsBase = FI;
285 SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
286 LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
288 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
289 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
290 argt = DAG.getCopyFromReg(Root, dl, args_float[i], MVT::f64);
291 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
292 SDFI = DAG.getFrameIndex(FI, MVT::i64);
293 LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
296 //Set up a token factor with all the stack traffic
297 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
300 ArgValues.push_back(Root);
302 // Return the new list of results.
303 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
304 &ArgValues[0], ArgValues.size());
307 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
308 DebugLoc dl = Op.getDebugLoc();
309 SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), dl, Alpha::R26,
310 DAG.getNode(AlphaISD::GlobalRetAddr,
311 DebugLoc::getUnknownLoc(),
314 switch (Op.getNumOperands()) {
316 LLVM_UNREACHABLE("Do not know how to return this many arguments!");
319 //return SDValue(); // ret void is legal
321 MVT ArgVT = Op.getOperand(1).getValueType();
323 if (ArgVT.isInteger())
326 assert(ArgVT.isFloatingPoint());
329 Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
330 Op.getOperand(1), Copy.getValue(1));
331 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
332 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
336 MVT ArgVT = Op.getOperand(1).getValueType();
337 unsigned ArgReg1, ArgReg2;
338 if (ArgVT.isInteger()) {
342 assert(ArgVT.isFloatingPoint());
346 Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
347 Op.getOperand(1), Copy.getValue(1));
348 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
349 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
350 == DAG.getMachineFunction().getRegInfo().liveout_end())
351 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
352 Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
353 Op.getOperand(3), Copy.getValue(1));
354 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
355 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
356 == DAG.getMachineFunction().getRegInfo().liveout_end())
357 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
361 return DAG.getNode(AlphaISD::RET_FLAG, dl,
362 MVT::Other, Copy, Copy.getValue(1));
365 std::pair<SDValue, SDValue>
366 AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
367 bool RetSExt, bool RetZExt, bool isVarArg,
368 bool isInreg, unsigned NumFixedArgs,
369 unsigned CallingConv,
370 bool isTailCall, SDValue Callee,
371 ArgListTy &Args, SelectionDAG &DAG,
375 NumBytes = (Args.size() - 6) * 8;
377 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
378 std::vector<SDValue> args_to_use;
379 for (unsigned i = 0, e = Args.size(); i != e; ++i)
381 switch (getValueType(Args[i].Ty).getSimpleVT()) {
382 default: assert(0 && "Unexpected ValueType for argument!");
387 // Promote the integer to 64 bits. If the input type is signed use a
388 // sign extend, otherwise use a zero extend.
390 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, dl,
391 MVT::i64, Args[i].Node);
392 else if (Args[i].isZExt)
393 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, dl,
394 MVT::i64, Args[i].Node);
396 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Args[i].Node);
403 args_to_use.push_back(Args[i].Node);
406 std::vector<MVT> RetVals;
407 MVT RetTyVT = getValueType(RetTy);
408 MVT ActualRetTyVT = RetTyVT;
409 if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
410 ActualRetTyVT = MVT::i64;
412 if (RetTyVT != MVT::isVoid)
413 RetVals.push_back(ActualRetTyVT);
414 RetVals.push_back(MVT::Other);
416 std::vector<SDValue> Ops;
417 Ops.push_back(Chain);
418 Ops.push_back(Callee);
419 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
420 SDValue TheCall = DAG.getNode(AlphaISD::CALL, dl,
421 RetVals, &Ops[0], Ops.size());
422 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
423 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
424 DAG.getIntPtrConstant(0, true), SDValue());
425 SDValue RetVal = TheCall;
427 if (RetTyVT != ActualRetTyVT) {
428 ISD::NodeType AssertKind = ISD::DELETED_NODE;
430 AssertKind = ISD::AssertSext;
432 AssertKind = ISD::AssertZext;
434 if (AssertKind != ISD::DELETED_NODE)
435 RetVal = DAG.getNode(AssertKind, dl, MVT::i64, RetVal,
436 DAG.getValueType(RetTyVT));
438 RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
441 return std::make_pair(RetVal, Chain);
444 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
445 SDValue &DataPtr, SelectionDAG &DAG) {
446 Chain = N->getOperand(0);
447 SDValue VAListP = N->getOperand(1);
448 const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
449 DebugLoc dl = N->getDebugLoc();
451 SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0);
452 SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
453 DAG.getConstant(8, MVT::i64));
454 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
455 Tmp, NULL, 0, MVT::i32);
456 DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
457 if (N->getValueType(0).isFloatingPoint())
459 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
460 SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
461 DAG.getConstant(8*6, MVT::i64));
462 SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
463 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
464 DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
467 SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
468 DAG.getConstant(8, MVT::i64));
469 Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
473 /// LowerOperation - Provide custom lowering hooks for some operations.
475 SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
476 DebugLoc dl = Op.getDebugLoc();
477 switch (Op.getOpcode()) {
478 default: assert(0 && "Wasn't expecting to be able to lower this!");
479 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
483 case ISD::RET: return LowerRET(Op,DAG);
484 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
486 case ISD::INTRINSIC_WO_CHAIN: {
487 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
489 default: break; // Don't custom lower most intrinsics.
490 case Intrinsic::alpha_umulh:
491 return DAG.getNode(ISD::MULHU, dl, MVT::i64,
492 Op.getOperand(1), Op.getOperand(2));
496 case ISD::SINT_TO_FP: {
497 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
498 "Unhandled SINT_TO_FP type in custom expander!");
500 bool isDouble = Op.getValueType() == MVT::f64;
501 LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
502 SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
503 isDouble?MVT::f64:MVT::f32, LD);
506 case ISD::FP_TO_SINT: {
507 bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
508 SDValue src = Op.getOperand(0);
510 if (!isDouble) //Promote
511 src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
513 src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
515 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
517 case ISD::ConstantPool: {
518 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
519 Constant *C = CP->getConstVal();
520 SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
521 // FIXME there isn't really any debug info here
523 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
524 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
525 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
528 case ISD::GlobalTLSAddress:
529 assert(0 && "TLS not implemented for Alpha.");
530 case ISD::GlobalAddress: {
531 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
532 GlobalValue *GV = GSDN->getGlobal();
533 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
534 // FIXME there isn't really any debug info here
536 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
537 if (GV->hasLocalLinkage()) {
538 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
539 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
540 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
543 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
544 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
546 case ISD::ExternalSymbol: {
547 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
548 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
549 ->getSymbol(), MVT::i64),
550 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
555 //Expand only on constant case
556 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
557 MVT VT = Op.getNode()->getValueType(0);
558 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
559 BuildUDIV(Op.getNode(), DAG, NULL) :
560 BuildSDIV(Op.getNode(), DAG, NULL);
561 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1));
562 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
568 if (Op.getValueType().isInteger()) {
569 if (Op.getOperand(1).getOpcode() == ISD::Constant)
570 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
571 : BuildUDIV(Op.getNode(), DAG, NULL);
572 const char* opstr = 0;
573 switch (Op.getOpcode()) {
574 case ISD::UREM: opstr = "__remqu"; break;
575 case ISD::SREM: opstr = "__remq"; break;
576 case ISD::UDIV: opstr = "__divqu"; break;
577 case ISD::SDIV: opstr = "__divq"; break;
579 SDValue Tmp1 = Op.getOperand(0),
580 Tmp2 = Op.getOperand(1),
581 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
582 return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
587 SDValue Chain, DataPtr;
588 LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
591 if (Op.getValueType() == MVT::i32)
592 Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
595 Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
599 SDValue Chain = Op.getOperand(0);
600 SDValue DestP = Op.getOperand(1);
601 SDValue SrcP = Op.getOperand(2);
602 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
603 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
605 SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
606 SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
607 SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
608 DAG.getConstant(8, MVT::i64));
609 Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
610 NP, NULL,0, MVT::i32);
611 SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
612 DAG.getConstant(8, MVT::i64));
613 return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
616 SDValue Chain = Op.getOperand(0);
617 SDValue VAListP = Op.getOperand(1);
618 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
620 // vastart stores the address of the VarArgsBase and VarArgsOffset
621 SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
622 SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
623 SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
624 DAG.getConstant(8, MVT::i64));
625 return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
626 SA2, NULL, 0, MVT::i32);
628 case ISD::RETURNADDR:
629 return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
632 case ISD::FRAMEADDR: break;
638 void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
639 SmallVectorImpl<SDValue>&Results,
641 DebugLoc dl = N->getDebugLoc();
642 assert(N->getValueType(0) == MVT::i32 &&
643 N->getOpcode() == ISD::VAARG &&
644 "Unknown node to custom promote!");
646 SDValue Chain, DataPtr;
647 LowerVAARG(N, Chain, DataPtr, DAG);
648 SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0);
649 Results.push_back(Res);
650 Results.push_back(SDValue(Res.getNode(), 1));
656 /// getConstraintType - Given a constraint letter, return the type of
657 /// constraint it is for this target.
658 AlphaTargetLowering::ConstraintType
659 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
660 if (Constraint.size() == 1) {
661 switch (Constraint[0]) {
665 return C_RegisterClass;
668 return TargetLowering::getConstraintType(Constraint);
671 std::vector<unsigned> AlphaTargetLowering::
672 getRegClassForInlineAsmConstraint(const std::string &Constraint,
674 if (Constraint.size() == 1) {
675 switch (Constraint[0]) {
676 default: break; // Unknown constriant letter
678 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
679 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
680 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
681 Alpha::F9 , Alpha::F10, Alpha::F11,
682 Alpha::F12, Alpha::F13, Alpha::F14,
683 Alpha::F15, Alpha::F16, Alpha::F17,
684 Alpha::F18, Alpha::F19, Alpha::F20,
685 Alpha::F21, Alpha::F22, Alpha::F23,
686 Alpha::F24, Alpha::F25, Alpha::F26,
687 Alpha::F27, Alpha::F28, Alpha::F29,
688 Alpha::F30, Alpha::F31, 0);
690 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
691 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
692 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
693 Alpha::R9 , Alpha::R10, Alpha::R11,
694 Alpha::R12, Alpha::R13, Alpha::R14,
695 Alpha::R15, Alpha::R16, Alpha::R17,
696 Alpha::R18, Alpha::R19, Alpha::R20,
697 Alpha::R21, Alpha::R22, Alpha::R23,
698 Alpha::R24, Alpha::R25, Alpha::R26,
699 Alpha::R27, Alpha::R28, Alpha::R29,
700 Alpha::R30, Alpha::R31, 0);
704 return std::vector<unsigned>();
706 //===----------------------------------------------------------------------===//
707 // Other Lowering Code
708 //===----------------------------------------------------------------------===//
711 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
712 MachineBasicBlock *BB) const {
713 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
714 assert((MI->getOpcode() == Alpha::CAS32 ||
715 MI->getOpcode() == Alpha::CAS64 ||
716 MI->getOpcode() == Alpha::LAS32 ||
717 MI->getOpcode() == Alpha::LAS64 ||
718 MI->getOpcode() == Alpha::SWAP32 ||
719 MI->getOpcode() == Alpha::SWAP64) &&
720 "Unexpected instr type to insert");
722 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
723 MI->getOpcode() == Alpha::LAS32 ||
724 MI->getOpcode() == Alpha::SWAP32;
726 //Load locked store conditional for atomic ops take on the same form
729 //do stuff (maybe branch to exit)
731 //test sc and maybe branck to start
733 const BasicBlock *LLVM_BB = BB->getBasicBlock();
734 DebugLoc dl = MI->getDebugLoc();
735 MachineFunction::iterator It = BB;
738 MachineBasicBlock *thisMBB = BB;
739 MachineFunction *F = BB->getParent();
740 MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
741 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
743 sinkMBB->transferSuccessors(thisMBB);
745 F->insert(It, llscMBB);
746 F->insert(It, sinkMBB);
748 BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
750 unsigned reg_res = MI->getOperand(0).getReg(),
751 reg_ptr = MI->getOperand(1).getReg(),
752 reg_v2 = MI->getOperand(2).getReg(),
753 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
755 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
756 reg_res).addImm(0).addReg(reg_ptr);
757 switch (MI->getOpcode()) {
761 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
762 BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
763 .addReg(reg_v2).addReg(reg_res);
764 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
765 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
766 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
767 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
772 BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
773 .addReg(reg_res).addReg(reg_v2);
777 case Alpha::SWAP64: {
778 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
779 .addReg(reg_v2).addReg(reg_v2);
783 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
784 .addReg(reg_store).addImm(0).addReg(reg_ptr);
785 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
786 .addImm(0).addReg(reg_store).addMBB(llscMBB);
787 BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB);
789 thisMBB->addSuccessor(llscMBB);
790 llscMBB->addSuccessor(llscMBB);
791 llscMBB->addSuccessor(sinkMBB);
792 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
798 AlphaTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
799 // The Alpha target isn't yet aware of offsets.