1 //======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
25 const MachineFrameInfo *FFI = MF.getFrameInfo();
26 unsigned CFSize = FFI->getMaxCallFrameSize();
27 // It's not always a good idea to include the call frame as part of the
28 // stack frame. ARM (especially Thumb) has small immediate offset to
29 // address the stack frame. So a large call frame can cause poor codegen
30 // and may even makes it impossible to scavenge a register.
31 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
34 return !MF.getFrameInfo()->hasVarSizedObjects();
38 emitSPUpdate(MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator &MBBI,
40 const TargetInstrInfo &TII, DebugLoc dl,
41 const Thumb1RegisterInfo &MRI,
42 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
43 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
47 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
48 MachineBasicBlock &MBB = MF.front();
49 MachineBasicBlock::iterator MBBI = MBB.begin();
50 MachineFrameInfo *MFI = MF.getFrameInfo();
51 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
52 const Thumb1RegisterInfo *RegInfo =
53 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
54 const Thumb1InstrInfo &TII =
55 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
57 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
58 unsigned NumBytes = MFI->getStackSize();
59 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
60 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
61 unsigned FramePtr = RegInfo->getFrameRegister(MF);
62 unsigned BasePtr = RegInfo->getBaseRegister();
64 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
65 NumBytes = (NumBytes + 3) & ~3;
66 MFI->setStackSize(NumBytes);
68 // Determine the sizes of each callee-save spill areas and record which frame
69 // belongs to which callee-save spill areas.
70 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
71 int FramePtrSpillFI = 0;
74 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
75 MachineInstr::FrameSetup);
77 if (!AFI->hasStackFrame()) {
79 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
80 MachineInstr::FrameSetup);
84 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
85 unsigned Reg = CSI[i].getReg();
86 int FI = CSI[i].getFrameIdx();
95 AFI->addGPRCalleeSavedArea1Frame(FI);
103 FramePtrSpillFI = FI;
104 if (STI.isTargetDarwin()) {
105 AFI->addGPRCalleeSavedArea2Frame(FI);
108 AFI->addGPRCalleeSavedArea1Frame(FI);
113 AFI->addDPRCalleeSavedAreaFrame(FI);
118 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
120 if (MBBI != MBB.end())
121 dl = MBBI->getDebugLoc();
124 // Determine starting offsets of spill areas.
125 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
126 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
127 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
128 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
129 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
130 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
131 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
132 NumBytes = DPRCSOffset;
134 // Adjust FP so it point to the stack slot that contains the previous FP.
136 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
137 .addFrameIndex(FramePtrSpillFI).addImm(0)
138 .setMIFlags(MachineInstr::FrameSetup));
140 // If offset is > 508 then sp cannot be adjusted in a single instruction,
141 // try restoring from fp instead.
142 AFI->setShouldRestoreSPFromFP(true);
146 // Insert it after all the callee-save spills.
147 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
148 MachineInstr::FrameSetup);
150 if (STI.isTargetELF() && hasFP(MF))
151 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
152 AFI->getFramePtrSpillOffset());
154 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
155 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
156 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
158 if (RegInfo->needsStackRealignment(MF)) {
159 // We cannot use sp as source/dest register here, thus we're emitting the
160 // following sequence:
162 // lsrs r4, r4, Log2MaxAlign
163 // lsls r4, r4, Log2MaxAlign
165 unsigned MaxAlign = MFI->getMaxAlignment();
166 unsigned Log2MaxAlign = Log2_32(MaxAlign);
167 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
168 .addReg(ARM::SP, RegState::Kill));
169 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4))
170 .addReg(ARM::R4, RegState::Kill)
171 .addImm(Log2MaxAlign));
172 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4))
173 .addReg(ARM::R4, RegState::Kill)
174 .addImm(Log2MaxAlign));
175 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
176 .addReg(ARM::R4, RegState::Kill));
179 // If we need a base pointer, set it up here. It's whatever the value
180 // of the stack pointer is at this point. Any variable size objects
181 // will be allocated after this, so we can still use the base pointer
182 // to reference locals.
183 if (RegInfo->hasBasePointer(MF))
184 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
187 // If the frame has variable sized objects then the epilogue must restore
188 // the sp from fp. We can assume there's an FP here since hasFP already
189 // checks for hasVarSizedObjects.
190 if (MFI->hasVarSizedObjects())
191 AFI->setShouldRestoreSPFromFP(true);
194 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
195 for (unsigned i = 0; CSRegs[i]; ++i)
196 if (Reg == CSRegs[i])
201 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
202 if (MI->getOpcode() == ARM::tLDRspi &&
203 MI->getOperand(1).isFI() &&
204 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
206 else if (MI->getOpcode() == ARM::tPOP) {
207 // The first two operands are predicates. The last two are
208 // imp-def and imp-use of SP. Check everything in between.
209 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
210 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
217 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
218 MachineBasicBlock &MBB) const {
219 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
220 assert((MBBI->getOpcode() == ARM::tBX_RET ||
221 MBBI->getOpcode() == ARM::tPOP_RET) &&
222 "Can only insert epilog into returning blocks");
223 DebugLoc dl = MBBI->getDebugLoc();
224 MachineFrameInfo *MFI = MF.getFrameInfo();
225 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
226 const Thumb1RegisterInfo *RegInfo =
227 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
228 const Thumb1InstrInfo &TII =
229 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
231 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
232 int NumBytes = (int)MFI->getStackSize();
233 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
234 unsigned FramePtr = RegInfo->getFrameRegister(MF);
236 if (!AFI->hasStackFrame()) {
238 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
240 // Unwind MBBI to point to first LDR / VLDRD.
241 if (MBBI != MBB.begin()) {
244 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
245 if (!isCSRestore(MBBI, CSRegs))
249 // Move SP to start of FP callee save spill area.
250 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
251 AFI->getGPRCalleeSavedArea2Size() +
252 AFI->getDPRCalleeSavedAreaSize());
254 if (AFI->shouldRestoreSPFromFP()) {
255 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
256 // Reset SP based on frame pointer only if the stack frame extends beyond
257 // frame pointer stack slot, the target is ELF and the function has FP, or
258 // the target uses var sized objects.
260 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
261 "No scratch register to restore SP from FP!");
262 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
264 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
268 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
272 if (MBBI->getOpcode() == ARM::tBX_RET &&
273 &MBB.front() != MBBI &&
274 prior(MBBI)->getOpcode() == ARM::tPOP) {
275 MachineBasicBlock::iterator PMBBI = prior(MBBI);
276 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
278 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
283 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
284 // to LR, and we can't pop the value directly to the PC since
285 // we need to update the SP after popping the value. Therefore, we
286 // pop the old LR into R3 as a temporary.
288 // Move back past the callee-saved register restoration
289 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
291 // Epilogue for vararg functions: pop LR to R3 and branch off it.
292 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
293 .addReg(ARM::R3, RegState::Define);
295 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
297 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
298 .addReg(ARM::R3, RegState::Kill));
299 // erase the old tBX_RET instruction
304 bool Thumb1FrameLowering::
305 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
306 MachineBasicBlock::iterator MI,
307 const std::vector<CalleeSavedInfo> &CSI,
308 const TargetRegisterInfo *TRI) const {
313 MachineFunction &MF = *MBB.getParent();
314 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
316 if (MI != MBB.end()) DL = MI->getDebugLoc();
318 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
320 for (unsigned i = CSI.size(); i != 0; --i) {
321 unsigned Reg = CSI[i-1].getReg();
324 // Add the callee-saved register as live-in unless it's LR and
325 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
326 // then it's already added to the function and entry block live-in sets.
327 if (Reg == ARM::LR) {
328 MachineFunction &MF = *MBB.getParent();
329 if (MF.getFrameInfo()->isReturnAddressTaken() &&
330 MF.getRegInfo().isLiveIn(Reg))
337 MIB.addReg(Reg, getKillRegState(isKill));
339 MIB.setMIFlags(MachineInstr::FrameSetup);
343 bool Thumb1FrameLowering::
344 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
345 MachineBasicBlock::iterator MI,
346 const std::vector<CalleeSavedInfo> &CSI,
347 const TargetRegisterInfo *TRI) const {
351 MachineFunction &MF = *MBB.getParent();
352 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
353 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
355 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
356 DebugLoc DL = MI->getDebugLoc();
357 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
360 bool NumRegs = false;
361 for (unsigned i = CSI.size(); i != 0; --i) {
362 unsigned Reg = CSI[i-1].getReg();
363 if (Reg == ARM::LR) {
364 // Special epilogue for vararg functions. See emitEpilogue
368 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
371 MIB.addReg(Reg, getDefRegState(true));
375 // It's illegal to emit pop instruction without operands.
377 MBB.insert(MI, &*MIB);
379 MF.DeleteMachineInstr(MIB);