lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMBaseInfo.h"
  15 #include "ARMMCAsmInfo.h"
  16 #include "ARMMCTargetDesc.h"
  17 #include "InstPrinter/ARMInstPrinter.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCELFStreamer.h"
  21 #include "llvm/MC/MCInstrAnalysis.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/MC/MCStreamer.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28
  29 using namespace llvm;
  30
  31 #define GET_REGINFO_MC_DESC
  32 #include "ARMGenRegisterInfo.inc"
  33
  34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  35                                   std::string &Info) {
  36   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
  37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
  38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
  39       // Checks for the deprecated CP15ISB encoding:
  40       // mcr p15, #0, rX, c7, c5, #4
  41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
  42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
  43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
  44         Info = "deprecated since v7, use 'isb'";
  45         return true;
  46       }
  47
  48       // Checks for the deprecated CP15DSB encoding:
  49       // mcr p15, #0, rX, c7, c10, #4
  50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
  51         Info = "deprecated since v7, use 'dsb'";
  52         return true;
  53       }
  54     }
  55     // Checks for the deprecated CP15DMB encoding:
  56     // mcr p15, #0, rX, c7, c10, #5
  57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
  58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
  59       Info = "deprecated since v7, use 'dmb'";
  60       return true;
  61     }
  62   }
  63   return false;
  64 }
  65
  66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  67                                  std::string &Info) {
  68   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
  69       MI.getOperand(1).getImm() != 8) {
  70     Info = "applying IT instruction to more than one subsequent instruction is "
  71            "deprecated";
  72     return true;
  73   }
  74
  75   return false;
  76 }
  77
  78 static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  79                                        std::string &Info) {
  80   if (STI.getFeatureBits() & llvm::ARM::ModeThumb)
  81     return false;
  82
  83   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
  84   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
  85     assert(MI.getOperand(OI).isReg() && "expected register");
  86     if (MI.getOperand(OI).getReg() == ARM::SP ||
  87         MI.getOperand(OI).getReg() == ARM::PC) {
  88       Info = "use of SP or PC in the list is deprecated";
  89       return true;
  90     }
  91   }
  92   return false;
  93 }
  94
  95 #define GET_INSTRINFO_MC_DESC
  96 #include "ARMGenInstrInfo.inc"
  97
  98 #define GET_SUBTARGETINFO_MC_DESC
  99 #include "ARMGenSubtargetInfo.inc"
 100
 101
 102 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
 103   Triple triple(TT);
 104
 105   bool isThumb = triple.getArch() == Triple::thumb ||
 106                  triple.getArch() == Triple::thumbeb;
 107
 108   bool NoCPU = CPU == "generic" || CPU.empty();
 109   std::string ARMArchFeature;
 110   switch (triple.getSubArch()) {
 111   default:
 112     llvm_unreachable("invalid sub-architecture for ARM");
 113   case Triple::ARMSubArch_v8:
 114     if (NoCPU)
 115       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
 116       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
 117       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
 118       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
 119                        "+trustzone,+t2xtpk,+crypto,+crc";
 120     else
 121       // Use CPU to figure out the exact features
 122       ARMArchFeature = "+v8";
 123     break;
 124   case Triple::ARMSubArch_v7m:
 125     isThumb = true;
 126     if (NoCPU)
 127       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
 128       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
 129     else
 130       // Use CPU to figure out the exact features.
 131       ARMArchFeature = "+v7";
 132     break;
 133   case Triple::ARMSubArch_v7em:
 134     if (NoCPU)
 135       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
 136       //       FeatureT2XtPk, FeatureMClass
 137       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
 138     else
 139       // Use CPU to figure out the exact features.
 140       ARMArchFeature = "+v7";
 141     break;
 142   case Triple::ARMSubArch_v7s:
 143     if (NoCPU)
 144       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
 145       //      Swift
 146       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
 147     else
 148       // Use CPU to figure out the exact features.
 149       ARMArchFeature = "+v7";
 150     break;
 151   case Triple::ARMSubArch_v7:
 152     // v7 CPUs have lots of different feature sets. If no CPU is specified,
 153     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
 154     // the "minimum" feature set and use CPU string to figure out the exact
 155     // features.
 156     if (NoCPU)
 157       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
 158       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
 159     else
 160       // Use CPU to figure out the exact features.
 161       ARMArchFeature = "+v7";
 162     break;
 163   case Triple::ARMSubArch_v6t2:
 164     ARMArchFeature = "+v6t2";
 165     break;
 166   case Triple::ARMSubArch_v6m:
 167     isThumb = true;
 168     if (NoCPU)
 169       // v6m: FeatureNoARM, FeatureMClass
 170       ARMArchFeature = "+v6m,+noarm,+mclass";
 171     else
 172       ARMArchFeature = "+v6";
 173     break;
 174   case Triple::ARMSubArch_v6:
 175     ARMArchFeature = "+v6";
 176     break;
 177   case Triple::ARMSubArch_v5te:
 178     ARMArchFeature = "+v5te";
 179     break;
 180   case Triple::ARMSubArch_v5:
 181     ARMArchFeature = "+v5t";
 182     break;
 183   case Triple::ARMSubArch_v4t:
 184     ARMArchFeature = "+v4t";
 185     break;
 186   case Triple::NoSubArch:
 187     break;
 188   }
 189
 190   if (isThumb) {
 191     if (ARMArchFeature.empty())
 192       ARMArchFeature = "+thumb-mode";
 193     else
 194       ARMArchFeature += ",+thumb-mode";
 195   }
 196
 197   if (triple.isOSNaCl()) {
 198     if (ARMArchFeature.empty())
 199       ARMArchFeature = "+nacl-trap";
 200     else
 201       ARMArchFeature += ",+nacl-trap";
 202   }
 203
 204   return ARMArchFeature;
 205 }
 206
 207 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
 208                                                   StringRef FS) {
 209   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
 210   if (!FS.empty()) {
 211     if (!ArchFS.empty())
 212       ArchFS = ArchFS + "," + FS.str();
 213     else
 214       ArchFS = FS;
 215   }
 216
 217   MCSubtargetInfo *X = new MCSubtargetInfo();
 218   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 219   return X;
 220 }
 221
 222 static MCInstrInfo *createARMMCInstrInfo() {
 223   MCInstrInfo *X = new MCInstrInfo();
 224   InitARMMCInstrInfo(X);
 225   return X;
 226 }
 227
 228 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 229   MCRegisterInfo *X = new MCRegisterInfo();
 230   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
 231   return X;
 232 }
 233
 234 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
 235   Triple TheTriple(TT);
 236
 237   MCAsmInfo *MAI;
 238   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
 239     MAI = new ARMMCAsmInfoDarwin(TT);
 240   else if (TheTriple.isWindowsItaniumEnvironment())
 241     MAI = new ARMCOFFMCAsmInfoGNU();
 242   else if (TheTriple.isWindowsMSVCEnvironment())
 243     MAI = new ARMCOFFMCAsmInfoMicrosoft();
 244   else
 245     MAI = new ARMELFMCAsmInfo(TT);
 246
 247   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
 248   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 249
 250   return MAI;
 251 }
 252
 253 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 254                                              CodeModel::Model CM,
 255                                              CodeGenOpt::Level OL) {
 256   MCCodeGenInfo *X = new MCCodeGenInfo();
 257   if (RM == Reloc::Default) {
 258     Triple TheTriple(TT);
 259     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
 260     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
 261   }
 262   X->InitMCCodeGenInfo(RM, CM, OL);
 263   return X;
 264 }
 265
 266 // This is duplicated code. Refactor this.
 267 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
 268                                     MCContext &Ctx, MCAsmBackend &MAB,
 269                                     raw_ostream &OS, MCCodeEmitter *Emitter,
 270                                     const MCSubtargetInfo &STI, bool RelaxAll) {
 271   Triple TheTriple(TT);
 272
 273   switch (TheTriple.getObjectFormat()) {
 274   default: llvm_unreachable("unsupported object format");
 275   case Triple::MachO: {
 276     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
 277     new ARMTargetStreamer(*S);
 278     return S;
 279   }
 280   case Triple::COFF:
 281     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
 282     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
 283   case Triple::ELF:
 284     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
 285                                 TheTriple.getArch() == Triple::thumb);
 286   }
 287 }
 288
 289 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 290                                              unsigned SyntaxVariant,
 291                                              const MCAsmInfo &MAI,
 292                                              const MCInstrInfo &MII,
 293                                              const MCRegisterInfo &MRI,
 294                                              const MCSubtargetInfo &STI) {
 295   if (SyntaxVariant == 0)
 296     return new ARMInstPrinter(MAI, MII, MRI, STI);
 297   return nullptr;
 298 }
 299
 300 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
 301                                                    MCContext &Ctx) {
 302   Triple TheTriple(TT);
 303   if (TheTriple.isOSBinFormatMachO())
 304     return createARMMachORelocationInfo(Ctx);
 305   // Default to the stock relocation info.
 306   return llvm::createMCRelocationInfo(TT, Ctx);
 307 }
 308
 309 namespace {
 310
 311 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 312 public:
 313   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 314
 315   bool isUnconditionalBranch(const MCInst &Inst) const override {
 316     // BCCs with the "always" predicate are unconditional branches.
 317     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 318       return true;
 319     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 320   }
 321
 322   bool isConditionalBranch(const MCInst &Inst) const override {
 323     // BCCs with the "always" predicate are unconditional branches.
 324     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 325       return false;
 326     return MCInstrAnalysis::isConditionalBranch(Inst);
 327   }
 328
 329   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
 330                       uint64_t Size, uint64_t &Target) const override {
 331     // We only handle PCRel branches for now.
 332     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 333       return false;
 334
 335     int64_t Imm = Inst.getOperand(0).getImm();
 336     // FIXME: This is not right for thumb.
 337     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 338     return true;
 339   }
 340 };
 341
 342 }
 343
 344 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 345   return new ARMMCInstrAnalysis(Info);
 346 }
 347
 348 // Force static initialization.
 349 extern "C" void LLVMInitializeARMTargetMC() {
 350   // Register the MC asm info.
 351   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
 352   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
 353   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
 354   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
 355
 356   // Register the MC codegen info.
 357   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
 358   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
 359   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget,
 360                                         createARMMCCodeGenInfo);
 361   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget,
 362                                         createARMMCCodeGenInfo);
 363
 364   // Register the MC instruction info.
 365   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
 366   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
 367   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
 368   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
 369
 370   // Register the MC register info.
 371   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
 372   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
 373   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
 374   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
 375
 376   // Register the MC subtarget info.
 377   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
 378                                           ARM_MC::createARMMCSubtargetInfo);
 379   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
 380                                           ARM_MC::createARMMCSubtargetInfo);
 381   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
 382                                           ARM_MC::createARMMCSubtargetInfo);
 383   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
 384                                           ARM_MC::createARMMCSubtargetInfo);
 385
 386   // Register the MC instruction analyzer.
 387   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
 388                                           createARMMCInstrAnalysis);
 389   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
 390                                           createARMMCInstrAnalysis);
 391   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
 392                                           createARMMCInstrAnalysis);
 393   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
 394                                           createARMMCInstrAnalysis);
 395
 396   // Register the MC Code Emitter
 397   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
 398                                         createARMLEMCCodeEmitter);
 399   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
 400                                         createARMBEMCCodeEmitter);
 401   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
 402                                         createARMLEMCCodeEmitter);
 403   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
 404                                         createARMBEMCCodeEmitter);
 405
 406   // Register the asm backend.
 407   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
 408   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
 409   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
 410                                        createThumbLEAsmBackend);
 411   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
 412                                        createThumbBEAsmBackend);
 413
 414   // Register the object streamer.
 415   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
 416   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
 417   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
 418   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
 419
 420   // Register the asm streamer.
 421   TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
 422   TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
 423   TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
 424   TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
 425
 426   // Register the null streamer.
 427   TargetRegistry::RegisterNullStreamer(TheARMLETarget, createARMNullStreamer);
 428   TargetRegistry::RegisterNullStreamer(TheARMBETarget, createARMNullStreamer);
 429   TargetRegistry::RegisterNullStreamer(TheThumbLETarget, createARMNullStreamer);
 430   TargetRegistry::RegisterNullStreamer(TheThumbBETarget, createARMNullStreamer);
 431
 432   // Register the MCInstPrinter.
 433   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
 434   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
 435   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
 436                                         createARMMCInstPrinter);
 437   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
 438                                         createARMMCInstPrinter);
 439
 440   // Register the MC relocation info.
 441   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
 442                                            createARMMCRelocationInfo);
 443   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
 444                                            createARMMCRelocationInfo);
 445   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
 446                                            createARMMCRelocationInfo);
 447   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
 448                                            createARMMCRelocationInfo);
 449 }