1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
36 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39 // Checks for the deprecated CP15ISB encoding:
40 // mcr p15, #0, rX, c7, c5, #4
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44 Info = "deprecated since v7, use 'isb'";
48 // Checks for the deprecated CP15DSB encoding:
49 // mcr p15, #0, rX, c7, c10, #4
50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51 Info = "deprecated since v7, use 'dsb'";
55 // Checks for the deprecated CP15DMB encoding:
56 // mcr p15, #0, rX, c7, c10, #5
57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59 Info = "deprecated since v7, use 'dmb'";
66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
69 MI.getOperand(1).getImm() != 8) {
70 Info = "applying IT instruction to more than one subsequent instruction is "
78 static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
80 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
81 "cannot predicate thumb instructions");
83 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
84 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
85 assert(MI.getOperand(OI).isReg() && "expected register");
86 if (MI.getOperand(OI).getReg() == ARM::SP ||
87 MI.getOperand(OI).getReg() == ARM::PC) {
88 Info = "use of SP or PC in the list is deprecated";
95 static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
97 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
98 "cannot predicate thumb instructions");
100 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
101 bool ListContainsPC = false, ListContainsLR = false;
102 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
103 assert(MI.getOperand(OI).isReg() && "expected register");
104 switch (MI.getOperand(OI).getReg()) {
108 ListContainsLR = true;
111 ListContainsPC = true;
114 Info = "use of SP in the list is deprecated";
119 if (ListContainsPC && ListContainsLR) {
120 Info = "use of LR and PC simultaneously in the list is deprecated";
127 #define GET_INSTRINFO_MC_DESC
128 #include "ARMGenInstrInfo.inc"
130 #define GET_SUBTARGETINFO_MC_DESC
131 #include "ARMGenSubtargetInfo.inc"
134 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
137 bool isThumb = triple.getArch() == Triple::thumb ||
138 triple.getArch() == Triple::thumbeb;
140 bool NoCPU = CPU == "generic" || CPU.empty();
141 std::string ARMArchFeature;
142 switch (triple.getSubArch()) {
144 llvm_unreachable("invalid sub-architecture for ARM");
145 case Triple::ARMSubArch_v8:
147 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
148 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
149 // FeatureT2XtPk, FeatureCrypto, FeatureCRC
150 ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
151 "+trustzone,+t2xtpk,+crypto,+crc";
153 // Use CPU to figure out the exact features
154 ARMArchFeature = "+v8";
156 case Triple::ARMSubArch_v8_1a:
158 // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
159 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
160 // FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
161 ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
162 "+trustzone,+t2xtpk,+crypto,+crc";
164 // Use CPU to figure out the exact features
165 ARMArchFeature = "+v8.1a";
167 case Triple::ARMSubArch_v7m:
170 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
171 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
173 // Use CPU to figure out the exact features.
174 ARMArchFeature = "+v7";
176 case Triple::ARMSubArch_v7em:
178 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
179 // FeatureT2XtPk, FeatureMClass
180 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
182 // Use CPU to figure out the exact features.
183 ARMArchFeature = "+v7";
185 case Triple::ARMSubArch_v7s:
187 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
189 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
191 // Use CPU to figure out the exact features.
192 ARMArchFeature = "+v7";
194 case Triple::ARMSubArch_v7:
195 // v7 CPUs have lots of different feature sets. If no CPU is specified,
196 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
197 // the "minimum" feature set and use CPU string to figure out the exact
200 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
201 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
203 // Use CPU to figure out the exact features.
204 ARMArchFeature = "+v7";
206 case Triple::ARMSubArch_v6t2:
207 ARMArchFeature = "+v6t2";
209 case Triple::ARMSubArch_v6k:
210 ARMArchFeature = "+v6k";
212 case Triple::ARMSubArch_v6m:
215 // v6m: FeatureNoARM, FeatureMClass
216 ARMArchFeature = "+v6m,+noarm,+mclass";
218 ARMArchFeature = "+v6";
220 case Triple::ARMSubArch_v6:
221 ARMArchFeature = "+v6";
223 case Triple::ARMSubArch_v5te:
224 ARMArchFeature = "+v5te";
226 case Triple::ARMSubArch_v5:
227 ARMArchFeature = "+v5t";
229 case Triple::ARMSubArch_v4t:
230 ARMArchFeature = "+v4t";
232 case Triple::NoSubArch:
237 if (ARMArchFeature.empty())
238 ARMArchFeature = "+thumb-mode";
240 ARMArchFeature += ",+thumb-mode";
243 if (triple.isOSNaCl()) {
244 if (ARMArchFeature.empty())
245 ARMArchFeature = "+nacl-trap";
247 ARMArchFeature += ",+nacl-trap";
250 return ARMArchFeature;
253 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
255 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
258 ArchFS = (Twine(ArchFS) + "," + FS).str();
263 MCSubtargetInfo *X = new MCSubtargetInfo();
264 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
268 static MCInstrInfo *createARMMCInstrInfo() {
269 MCInstrInfo *X = new MCInstrInfo();
270 InitARMMCInstrInfo(X);
274 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
275 MCRegisterInfo *X = new MCRegisterInfo();
276 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
280 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
281 const Triple &TheTriple) {
283 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
284 MAI = new ARMMCAsmInfoDarwin(TheTriple);
285 else if (TheTriple.isWindowsItaniumEnvironment())
286 MAI = new ARMCOFFMCAsmInfoGNU();
287 else if (TheTriple.isWindowsMSVCEnvironment())
288 MAI = new ARMCOFFMCAsmInfoMicrosoft();
290 MAI = new ARMELFMCAsmInfo(TheTriple);
292 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
293 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
298 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
300 CodeGenOpt::Level OL) {
301 MCCodeGenInfo *X = new MCCodeGenInfo();
302 if (RM == Reloc::Default) {
303 Triple TheTriple(TT);
304 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
305 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
307 X->initMCCodeGenInfo(RM, CM, OL);
311 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
312 MCAsmBackend &MAB, raw_pwrite_stream &OS,
313 MCCodeEmitter *Emitter, bool RelaxAll) {
314 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
315 T.getArch() == Triple::thumb);
318 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
319 raw_pwrite_stream &OS,
320 MCCodeEmitter *Emitter, bool RelaxAll,
321 bool DWARFMustBeAtTheEnd) {
322 return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
325 static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
326 unsigned SyntaxVariant,
327 const MCAsmInfo &MAI,
328 const MCInstrInfo &MII,
329 const MCRegisterInfo &MRI) {
330 if (SyntaxVariant == 0)
331 return new ARMInstPrinter(MAI, MII, MRI);
335 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
337 if (TT.isOSBinFormatMachO())
338 return createARMMachORelocationInfo(Ctx);
339 // Default to the stock relocation info.
340 return llvm::createMCRelocationInfo(TT, Ctx);
345 class ARMMCInstrAnalysis : public MCInstrAnalysis {
347 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
349 bool isUnconditionalBranch(const MCInst &Inst) const override {
350 // BCCs with the "always" predicate are unconditional branches.
351 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
353 return MCInstrAnalysis::isUnconditionalBranch(Inst);
356 bool isConditionalBranch(const MCInst &Inst) const override {
357 // BCCs with the "always" predicate are unconditional branches.
358 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
360 return MCInstrAnalysis::isConditionalBranch(Inst);
363 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
364 uint64_t Size, uint64_t &Target) const override {
365 // We only handle PCRel branches for now.
366 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
369 int64_t Imm = Inst.getOperand(0).getImm();
370 // FIXME: This is not right for thumb.
371 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
378 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
379 return new ARMMCInstrAnalysis(Info);
382 // Force static initialization.
383 extern "C" void LLVMInitializeARMTargetMC() {
384 for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
385 &TheThumbBETarget}) {
386 // Register the MC asm info.
387 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
389 // Register the MC codegen info.
390 TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo);
392 // Register the MC instruction info.
393 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
395 // Register the MC register info.
396 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
398 // Register the MC subtarget info.
399 TargetRegistry::RegisterMCSubtargetInfo(*T,
400 ARM_MC::createARMMCSubtargetInfo);
402 // Register the MC instruction analyzer.
403 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
405 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
406 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
407 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
409 // Register the obj target streamer.
410 TargetRegistry::RegisterObjectTargetStreamer(*T,
411 createARMObjectTargetStreamer);
413 // Register the asm streamer.
414 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
416 // Register the null TargetStreamer.
417 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
419 // Register the MCInstPrinter.
420 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
422 // Register the MC relocation info.
423 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
426 // Register the MC Code Emitter
427 for (Target *T : {&TheARMLETarget, &TheThumbLETarget})
428 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
429 for (Target *T : {&TheARMBETarget, &TheThumbBETarget})
430 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
432 // Register the asm backend.
433 TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
434 TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
435 TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
436 createThumbLEAsmBackend);
437 TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
438 createThumbBEAsmBackend);