1 // The LLVM Compiler Infrastructure
3 // This file is distributed under the University of Illinois Open Source
4 // License. See LICENSE.TXT for details.
6 //===----------------------------------------------------------------------===//
8 // This file contains a printer that converts from our internal representation
9 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBuildAttrs.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Module.h"
22 #include "llvm/Assembly/Writer.h"
23 #include "llvm/CodeGen/AsmPrinter.h"
24 #include "llvm/CodeGen/DwarfWriter.h"
25 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCSectionMachO.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Target/TargetData.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Target/TargetRegistry.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/SmallString.h"
40 #include "llvm/ADT/Statistic.h"
41 #include "llvm/ADT/StringSet.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/Mangler.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/FormattedStream.h"
49 STATISTIC(EmittedInsts, "Number of machine instrs printed");
52 class ARMAsmPrinter : public AsmPrinter {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when printing asm code for different targets.
56 const ARMSubtarget *Subtarget;
58 /// AFI - Keep a pointer to ARMFunctionInfo for the current
62 /// MCP - Keep a pointer to constantpool entries of the current
64 const MachineConstantPool *MCP;
67 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
68 const MCAsmInfo *T, bool V)
69 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
70 Subtarget = &TM.getSubtarget<ARMSubtarget>();
73 virtual const char *getPassName() const {
74 return "ARM Assembly Printer";
77 void printOperand(const MachineInstr *MI, int OpNum,
78 const char *Modifier = 0);
79 void printSOImmOperand(const MachineInstr *MI, int OpNum);
80 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
81 void printSORegOperand(const MachineInstr *MI, int OpNum);
82 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
83 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
84 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
85 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
86 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
87 const char *Modifier = 0);
88 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
89 const char *Modifier = 0);
90 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
91 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
92 const char *Modifier = 0);
93 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
95 void printThumbITMask(const MachineInstr *MI, int OpNum);
96 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
97 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
99 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
100 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
101 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
102 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
104 void printT2SOOperand(const MachineInstr *MI, int OpNum);
105 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
106 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
107 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
108 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
109 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
111 void printPredicateOperand(const MachineInstr *MI, int OpNum);
112 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
113 void printPCLabel(const MachineInstr *MI, int OpNum);
114 void printRegisterList(const MachineInstr *MI, int OpNum);
115 void printCPInstOperand(const MachineInstr *MI, int OpNum,
116 const char *Modifier);
117 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
118 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
119 void printTBAddrMode(const MachineInstr *MI, int OpNum);
120 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
122 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
123 unsigned AsmVariant, const char *ExtraCode);
124 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
126 const char *ExtraCode);
128 void PrintGlobalVariable(const GlobalVariable* GVar);
129 void printInstruction(const MachineInstr *MI); // autogenerated.
130 static const char *getRegisterName(unsigned RegNo);
132 void printMachineInstruction(const MachineInstr *MI);
133 bool runOnMachineFunction(MachineFunction &F);
134 void EmitStartOfAsmFile(Module &M);
135 void EmitEndOfAsmFile(Module &M);
137 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
139 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
140 printDataDirective(MCPV->getType());
142 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
143 GlobalValue *GV = ACPV->getGV();
146 if (ACPV->isLSDA()) {
147 SmallString<16> LSDAName;
148 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
149 "_LSDA_" << getFunctionNumber();
150 Name = LSDAName.str();
152 bool isIndirect = Subtarget->isTargetDarwin() &&
153 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
155 Name = Mang->getMangledName(GV);
157 // FIXME: Remove this when Darwin transition to @GOT like syntax.
158 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
159 MCSymbol *Sym = OutContext.GetOrCreateSymbol(Name.c_str());
161 MachineModuleInfoMachO &MMIMachO =
162 MMI->getObjFileInfo<MachineModuleInfoMachO>();
163 const MCSymbol *&StubSym =
164 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
165 MMIMachO.getGVStubEntry(Sym);
167 SmallString<128> NameStr;
168 Mang->getNameWithPrefix(NameStr, GV, false);
169 StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
173 Name = Mang->makeNameProper(ACPV->getSymbol());
176 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
177 if (ACPV->getPCAdjustment() != 0) {
178 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
179 << ACPV->getLabelId()
180 << "+" << (unsigned)ACPV->getPCAdjustment();
181 if (ACPV->mustAddCurrentAddress())
188 void getAnalysisUsage(AnalysisUsage &AU) const {
189 AsmPrinter::getAnalysisUsage(AU);
190 AU.setPreservesAll();
191 AU.addRequired<MachineModuleInfo>();
192 AU.addRequired<DwarfWriter>();
195 } // end of anonymous namespace
197 #include "ARMGenAsmWriter.inc"
199 /// runOnMachineFunction - This uses the printInstruction()
200 /// method to print assembly for each instruction.
202 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
205 AFI = MF.getInfo<ARMFunctionInfo>();
206 MCP = MF.getConstantPool();
208 SetupMachineFunction(MF);
211 // NOTE: we don't print out constant pools here, they are handled as
216 // Print out labels for the function.
217 const Function *F = MF.getFunction();
218 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
220 switch (F->getLinkage()) {
221 default: llvm_unreachable("Unknown linkage type!");
222 case Function::PrivateLinkage:
223 case Function::InternalLinkage:
225 case Function::ExternalLinkage:
226 O << "\t.globl\t" << CurrentFnName << "\n";
228 case Function::LinkerPrivateLinkage:
229 case Function::WeakAnyLinkage:
230 case Function::WeakODRLinkage:
231 case Function::LinkOnceAnyLinkage:
232 case Function::LinkOnceODRLinkage:
233 if (Subtarget->isTargetDarwin()) {
234 O << "\t.globl\t" << CurrentFnName << "\n";
235 O << "\t.weak_definition\t" << CurrentFnName << "\n";
237 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
242 printVisibility(CurrentFnName, F->getVisibility());
244 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
245 if (AFI->isThumbFunction()) {
246 EmitAlignment(FnAlign, F, AFI->getAlign());
247 O << "\t.code\t16\n";
248 O << "\t.thumb_func";
249 if (Subtarget->isTargetDarwin())
250 O << "\t" << CurrentFnName;
253 EmitAlignment(FnAlign, F);
256 O << CurrentFnName << ":\n";
257 // Emit pre-function debug information.
258 DW->BeginFunction(&MF);
260 if (Subtarget->isTargetDarwin()) {
261 // If the function is empty, then we need to emit *something*. Otherwise,
262 // the function's label might be associated with something that it wasn't
263 // meant to be associated with. We emit a noop in this situation.
264 MachineFunction::iterator I = MF.begin();
266 if (++I == MF.end() && MF.front().empty())
270 // Print out code for the function.
271 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
273 // Print a label for the basic block.
274 if (I != MF.begin()) {
275 EmitBasicBlockStart(I);
277 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
279 // Print the assembly for the instruction.
280 printMachineInstruction(II);
284 if (MAI->hasDotTypeDotSizeDirective())
285 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
287 // Emit post-function debug information.
288 DW->EndFunction(&MF);
293 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
294 const char *Modifier) {
295 const MachineOperand &MO = MI->getOperand(OpNum);
296 switch (MO.getType()) {
297 case MachineOperand::MO_Register: {
298 unsigned Reg = MO.getReg();
299 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
300 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
301 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
302 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
304 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
306 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
307 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
308 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
309 &ARM::DPR_VFP2RegClass);
310 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
312 O << getRegisterName(Reg);
315 llvm_unreachable("not implemented");
318 case MachineOperand::MO_Immediate: {
319 int64_t Imm = MO.getImm();
322 if (strcmp(Modifier, "lo16") == 0)
324 else if (strcmp(Modifier, "hi16") == 0)
330 case MachineOperand::MO_MachineBasicBlock:
331 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
333 case MachineOperand::MO_GlobalAddress: {
334 bool isCallOp = Modifier && !strcmp(Modifier, "call");
335 GlobalValue *GV = MO.getGlobal();
336 O << Mang->getMangledName(GV);
338 printOffset(MO.getOffset());
340 if (isCallOp && Subtarget->isTargetELF() &&
341 TM.getRelocationModel() == Reloc::PIC_)
345 case MachineOperand::MO_ExternalSymbol: {
346 bool isCallOp = Modifier && !strcmp(Modifier, "call");
347 std::string Name = Mang->makeNameProper(MO.getSymbolName());
350 if (isCallOp && Subtarget->isTargetELF() &&
351 TM.getRelocationModel() == Reloc::PIC_)
355 case MachineOperand::MO_ConstantPoolIndex:
356 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
357 << '_' << MO.getIndex();
359 case MachineOperand::MO_JumpTableIndex:
360 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
361 << '_' << MO.getIndex();
364 O << "<unknown operand type>"; abort (); break;
368 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
369 const MCAsmInfo *MAI) {
370 // Break it up into two parts that make up a shifter immediate.
371 V = ARM_AM::getSOImmVal(V);
372 assert(V != -1 && "Not a valid so_imm value!");
374 unsigned Imm = ARM_AM::getSOImmValImm(V);
375 unsigned Rot = ARM_AM::getSOImmValRot(V);
377 // Print low-level immediate formation info, per
378 // A5.1.3: "Data-processing operands - Immediate".
380 O << "#" << Imm << ", " << Rot;
381 // Pretty printed version.
383 O << ' ' << MAI->getCommentString()
384 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
390 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
391 /// immediate in bits 0-7.
392 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
393 const MachineOperand &MO = MI->getOperand(OpNum);
394 assert(MO.isImm() && "Not a valid so_imm value!");
395 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
398 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
399 /// followed by an 'orr' to materialize.
400 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
401 const MachineOperand &MO = MI->getOperand(OpNum);
402 assert(MO.isImm() && "Not a valid so_imm value!");
403 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
404 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
405 printSOImm(O, V1, VerboseAsm, MAI);
407 printPredicateOperand(MI, 2);
413 printSOImm(O, V2, VerboseAsm, MAI);
416 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
417 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
419 // REG REG 0,SH_OPC - e.g. R5, ROR R3
420 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
421 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
422 const MachineOperand &MO1 = MI->getOperand(Op);
423 const MachineOperand &MO2 = MI->getOperand(Op+1);
424 const MachineOperand &MO3 = MI->getOperand(Op+2);
426 O << getRegisterName(MO1.getReg());
428 // Print the shift opc.
430 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
434 O << getRegisterName(MO2.getReg());
435 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
437 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
441 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
442 const MachineOperand &MO1 = MI->getOperand(Op);
443 const MachineOperand &MO2 = MI->getOperand(Op+1);
444 const MachineOperand &MO3 = MI->getOperand(Op+2);
446 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
447 printOperand(MI, Op);
451 O << "[" << getRegisterName(MO1.getReg());
454 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
456 << (char)ARM_AM::getAM2Op(MO3.getImm())
457 << ARM_AM::getAM2Offset(MO3.getImm());
463 << (char)ARM_AM::getAM2Op(MO3.getImm())
464 << getRegisterName(MO2.getReg());
466 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
468 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
473 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
474 const MachineOperand &MO1 = MI->getOperand(Op);
475 const MachineOperand &MO2 = MI->getOperand(Op+1);
478 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
479 assert(ImmOffs && "Malformed indexed load / store!");
481 << (char)ARM_AM::getAM2Op(MO2.getImm())
486 O << (char)ARM_AM::getAM2Op(MO2.getImm())
487 << getRegisterName(MO1.getReg());
489 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
491 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
495 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
496 const MachineOperand &MO1 = MI->getOperand(Op);
497 const MachineOperand &MO2 = MI->getOperand(Op+1);
498 const MachineOperand &MO3 = MI->getOperand(Op+2);
500 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
501 O << "[" << getRegisterName(MO1.getReg());
505 << (char)ARM_AM::getAM3Op(MO3.getImm())
506 << getRegisterName(MO2.getReg())
511 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
513 << (char)ARM_AM::getAM3Op(MO3.getImm())
518 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
519 const MachineOperand &MO1 = MI->getOperand(Op);
520 const MachineOperand &MO2 = MI->getOperand(Op+1);
523 O << (char)ARM_AM::getAM3Op(MO2.getImm())
524 << getRegisterName(MO1.getReg());
528 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
529 assert(ImmOffs && "Malformed indexed load / store!");
531 << (char)ARM_AM::getAM3Op(MO2.getImm())
535 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
536 const char *Modifier) {
537 const MachineOperand &MO1 = MI->getOperand(Op);
538 const MachineOperand &MO2 = MI->getOperand(Op+1);
539 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
540 if (Modifier && strcmp(Modifier, "submode") == 0) {
541 if (MO1.getReg() == ARM::SP) {
543 bool isLDM = (MI->getOpcode() == ARM::LDM ||
544 MI->getOpcode() == ARM::LDM_RET ||
545 MI->getOpcode() == ARM::t2LDM ||
546 MI->getOpcode() == ARM::t2LDM_RET);
547 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
549 O << ARM_AM::getAMSubModeStr(Mode);
550 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
551 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
552 if (Mode == ARM_AM::ia)
555 printOperand(MI, Op);
556 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
561 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
562 const char *Modifier) {
563 const MachineOperand &MO1 = MI->getOperand(Op);
564 const MachineOperand &MO2 = MI->getOperand(Op+1);
566 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
567 printOperand(MI, Op);
571 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
573 if (Modifier && strcmp(Modifier, "submode") == 0) {
574 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
575 if (MO1.getReg() == ARM::SP) {
576 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
577 MI->getOpcode() == ARM::FLDMS);
578 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
580 O << ARM_AM::getAMSubModeStr(Mode);
582 } else if (Modifier && strcmp(Modifier, "base") == 0) {
583 // Used for FSTM{D|S} and LSTM{D|S} operations.
584 O << getRegisterName(MO1.getReg());
585 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
590 O << "[" << getRegisterName(MO1.getReg());
592 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
594 << (char)ARM_AM::getAM5Op(MO2.getImm())
600 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
601 const MachineOperand &MO1 = MI->getOperand(Op);
602 const MachineOperand &MO2 = MI->getOperand(Op+1);
603 const MachineOperand &MO3 = MI->getOperand(Op+2);
605 // FIXME: No support yet for specifying alignment.
606 O << "[" << getRegisterName(MO1.getReg()) << "]";
608 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
609 if (MO2.getReg() == 0)
612 O << ", " << getRegisterName(MO2.getReg());
616 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
617 const char *Modifier) {
618 if (Modifier && strcmp(Modifier, "label") == 0) {
619 printPCLabel(MI, Op+1);
623 const MachineOperand &MO1 = MI->getOperand(Op);
624 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
625 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
629 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
630 const MachineOperand &MO = MI->getOperand(Op);
631 uint32_t v = ~MO.getImm();
632 int32_t lsb = CountTrailingZeros_32(v);
633 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
634 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
635 O << "#" << lsb << ", #" << width;
638 //===--------------------------------------------------------------------===//
641 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
642 // (3 - the number of trailing zeros) is the number of then / else.
643 unsigned Mask = MI->getOperand(Op).getImm();
644 unsigned NumTZ = CountTrailingZeros_32(Mask);
645 assert(NumTZ <= 3 && "Invalid IT mask!");
646 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
647 bool T = (Mask & (1 << Pos)) == 0;
656 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
657 const MachineOperand &MO1 = MI->getOperand(Op);
658 const MachineOperand &MO2 = MI->getOperand(Op+1);
659 O << "[" << getRegisterName(MO1.getReg());
660 O << ", " << getRegisterName(MO2.getReg()) << "]";
664 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
666 const MachineOperand &MO1 = MI->getOperand(Op);
667 const MachineOperand &MO2 = MI->getOperand(Op+1);
668 const MachineOperand &MO3 = MI->getOperand(Op+2);
670 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
671 printOperand(MI, Op);
675 O << "[" << getRegisterName(MO1.getReg());
677 O << ", " << getRegisterName(MO3.getReg());
678 else if (unsigned ImmOffs = MO2.getImm()) {
679 O << ", #" << ImmOffs;
687 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
688 printThumbAddrModeRI5Operand(MI, Op, 1);
691 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
692 printThumbAddrModeRI5Operand(MI, Op, 2);
695 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
696 printThumbAddrModeRI5Operand(MI, Op, 4);
699 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
700 const MachineOperand &MO1 = MI->getOperand(Op);
701 const MachineOperand &MO2 = MI->getOperand(Op+1);
702 O << "[" << getRegisterName(MO1.getReg());
703 if (unsigned ImmOffs = MO2.getImm())
704 O << ", #" << ImmOffs << " * 4";
708 //===--------------------------------------------------------------------===//
710 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
711 // register with shift forms.
713 // REG IMM, SH_OPC - e.g. R5, LSL #3
714 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
715 const MachineOperand &MO1 = MI->getOperand(OpNum);
716 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
718 unsigned Reg = MO1.getReg();
719 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
720 O << getRegisterName(Reg);
722 // Print the shift opc.
724 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
727 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
728 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
731 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
733 const MachineOperand &MO1 = MI->getOperand(OpNum);
734 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
736 O << "[" << getRegisterName(MO1.getReg());
738 unsigned OffImm = MO2.getImm();
739 if (OffImm) // Don't print +0.
740 O << ", #+" << OffImm;
744 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
746 const MachineOperand &MO1 = MI->getOperand(OpNum);
747 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
749 O << "[" << getRegisterName(MO1.getReg());
751 int32_t OffImm = (int32_t)MO2.getImm();
754 O << ", #-" << -OffImm;
756 O << ", #+" << OffImm;
760 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
762 const MachineOperand &MO1 = MI->getOperand(OpNum);
763 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
765 O << "[" << getRegisterName(MO1.getReg());
767 int32_t OffImm = (int32_t)MO2.getImm() / 4;
770 O << ", #-" << -OffImm << " * 4";
772 O << ", #+" << OffImm << " * 4";
776 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
778 const MachineOperand &MO1 = MI->getOperand(OpNum);
779 int32_t OffImm = (int32_t)MO1.getImm();
782 O << "#-" << -OffImm;
787 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
789 const MachineOperand &MO1 = MI->getOperand(OpNum);
790 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
791 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
793 O << "[" << getRegisterName(MO1.getReg());
795 assert(MO2.getReg() && "Invalid so_reg load / store address!");
796 O << ", " << getRegisterName(MO2.getReg());
798 unsigned ShAmt = MO3.getImm();
800 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
801 O << ", lsl #" << ShAmt;
807 //===--------------------------------------------------------------------===//
809 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
810 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
812 O << ARMCondCodeToString(CC);
815 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
816 unsigned Reg = MI->getOperand(OpNum).getReg();
818 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
823 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
824 int Id = (int)MI->getOperand(OpNum).getImm();
825 O << MAI->getPrivateGlobalPrefix() << "PC" << Id;
828 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
830 // Always skip the first operand, it's the optional (and implicit writeback).
831 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
832 if (MI->getOperand(i).isImplicit())
834 if ((int)i != OpNum+1) O << ", ";
840 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
841 const char *Modifier) {
842 assert(Modifier && "This operand only works with a modifier!");
843 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
845 if (!strcmp(Modifier, "label")) {
846 unsigned ID = MI->getOperand(OpNum).getImm();
847 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
848 << '_' << ID << ":\n";
850 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
851 unsigned CPI = MI->getOperand(OpNum).getIndex();
853 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
855 if (MCPE.isMachineConstantPoolEntry()) {
856 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
858 EmitGlobalConstant(MCPE.Val.ConstVal);
863 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
864 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
866 const MachineOperand &MO1 = MI->getOperand(OpNum);
867 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
868 unsigned JTI = MO1.getIndex();
869 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
870 << '_' << JTI << '_' << MO2.getImm() << ":\n";
872 const char *JTEntryDirective = MAI->getData32bitsDirective();
874 const MachineFunction *MF = MI->getParent()->getParent();
875 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
876 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
877 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
878 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
879 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
880 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
881 MachineBasicBlock *MBB = JTBBs[i];
882 bool isNew = JTSets.insert(MBB);
885 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
887 O << JTEntryDirective << ' ';
889 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
890 << '_' << JTI << '_' << MO2.getImm()
891 << "_set_" << MBB->getNumber();
892 else if (TM.getRelocationModel() == Reloc::PIC_) {
893 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
894 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
895 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
897 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
904 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
905 const MachineOperand &MO1 = MI->getOperand(OpNum);
906 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
907 unsigned JTI = MO1.getIndex();
908 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
909 << '_' << JTI << '_' << MO2.getImm() << ":\n";
911 const MachineFunction *MF = MI->getParent()->getParent();
912 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
913 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
914 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
915 bool ByteOffset = false, HalfWordOffset = false;
916 if (MI->getOpcode() == ARM::t2TBB)
918 else if (MI->getOpcode() == ARM::t2TBH)
919 HalfWordOffset = true;
921 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
922 MachineBasicBlock *MBB = JTBBs[i];
924 O << MAI->getData8bitsDirective();
925 else if (HalfWordOffset)
926 O << MAI->getData16bitsDirective();
927 if (ByteOffset || HalfWordOffset) {
929 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
930 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
931 << '_' << JTI << '_' << MO2.getImm() << ")/2";
934 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
940 // Make sure the instruction that follows TBB is 2-byte aligned.
941 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
942 if (ByteOffset && (JTBBs.size() & 1)) {
948 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
949 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
950 if (MI->getOpcode() == ARM::t2TBH)
955 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
956 O << MI->getOperand(OpNum).getImm();
959 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
960 unsigned AsmVariant, const char *ExtraCode){
961 // Does this asm operand have a single letter operand modifier?
962 if (ExtraCode && ExtraCode[0]) {
963 if (ExtraCode[1] != 0) return true; // Unknown modifier.
965 switch (ExtraCode[0]) {
966 default: return true; // Unknown modifier.
967 case 'a': // Print as a memory address.
968 if (MI->getOperand(OpNum).isReg()) {
969 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
973 case 'c': // Don't print "#" before an immediate operand.
974 if (!MI->getOperand(OpNum).isImm())
976 printNoHashImmediate(MI, OpNum);
978 case 'P': // Print a VFP double precision register.
979 printOperand(MI, OpNum);
982 if (TM.getTargetData()->isLittleEndian())
986 if (TM.getTargetData()->isBigEndian())
989 case 'H': // Write second word of DI / DF reference.
990 // Verify that this operand has two consecutive registers.
991 if (!MI->getOperand(OpNum).isReg() ||
992 OpNum+1 == MI->getNumOperands() ||
993 !MI->getOperand(OpNum+1).isReg())
995 ++OpNum; // Return the high-part.
999 printOperand(MI, OpNum);
1003 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1004 unsigned OpNum, unsigned AsmVariant,
1005 const char *ExtraCode) {
1006 if (ExtraCode && ExtraCode[0])
1007 return true; // Unknown modifier.
1009 const MachineOperand &MO = MI->getOperand(OpNum);
1010 assert(MO.isReg() && "unexpected inline asm memory operand");
1011 O << "[" << getRegisterName(MO.getReg()) << "]";
1015 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1018 int Opc = MI->getOpcode();
1019 if (Opc == ARM::CONSTPOOL_ENTRY)
1022 // Call the autogenerated instruction printer routines.
1023 processDebugLoc(MI, true);
1024 printInstruction(MI);
1025 if (VerboseAsm && !MI->getDebugLoc().isUnknown())
1028 processDebugLoc(MI, false);
1031 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1032 if (Subtarget->isTargetDarwin()) {
1033 Reloc::Model RelocM = TM.getRelocationModel();
1034 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1035 // Declare all the text sections up front (before the DWARF sections
1036 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1037 // them together at the beginning of the object file. This helps
1038 // avoid out-of-range branches that are due a fundamental limitation of
1039 // the way symbol offsets are encoded with the current Darwin ARM
1041 TargetLoweringObjectFileMachO &TLOFMacho =
1042 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1043 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1044 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1045 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1046 if (RelocM == Reloc::DynamicNoPIC) {
1047 const MCSection *sect =
1048 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1049 MCSectionMachO::S_SYMBOL_STUBS,
1050 12, SectionKind::getText());
1051 OutStreamer.SwitchSection(sect);
1053 const MCSection *sect =
1054 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1055 MCSectionMachO::S_SYMBOL_STUBS,
1056 16, SectionKind::getText());
1057 OutStreamer.SwitchSection(sect);
1062 // Use unified assembler syntax mode for Thumb.
1063 if (Subtarget->isThumb())
1064 O << "\t.syntax unified\n";
1066 // Emit ARM Build Attributes
1067 if (Subtarget->isTargetELF()) {
1069 std::string CPUString = Subtarget->getCPUString();
1070 if (CPUString != "generic")
1071 O << "\t.cpu " << CPUString << '\n';
1073 // FIXME: Emit FPU type
1074 if (Subtarget->hasVFP2())
1075 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1077 // Signal various FP modes.
1079 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1080 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1082 if (FiniteOnlyFPMath())
1083 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1085 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1087 // 8-bytes alignment stuff.
1088 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1089 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1091 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1092 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1093 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1094 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1096 // FIXME: Should we signal R9 usage?
1100 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1101 const TargetData *TD = TM.getTargetData();
1103 if (!GVar->hasInitializer()) // External global require no code
1106 // Check to see if this is a special global used by LLVM, if so, emit it.
1108 if (EmitSpecialLLVMGlobal(GVar)) {
1109 if (Subtarget->isTargetDarwin() &&
1110 TM.getRelocationModel() == Reloc::Static) {
1111 if (GVar->getName() == "llvm.global_ctors")
1112 O << ".reference .constructors_used\n";
1113 else if (GVar->getName() == "llvm.global_dtors")
1114 O << ".reference .destructors_used\n";
1119 std::string name = Mang->getMangledName(GVar);
1120 Constant *C = GVar->getInitializer();
1121 const Type *Type = C->getType();
1122 unsigned Size = TD->getTypeAllocSize(Type);
1123 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1124 bool isDarwin = Subtarget->isTargetDarwin();
1126 printVisibility(name, GVar->getVisibility());
1128 if (Subtarget->isTargetELF())
1129 O << "\t.type " << name << ",%object\n";
1131 const MCSection *TheSection =
1132 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1133 OutStreamer.SwitchSection(TheSection);
1135 // FIXME: get this stuff from section kind flags.
1136 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1137 // Don't put things that should go in the cstring section into "comm".
1138 !TheSection->getKind().isMergeableCString()) {
1139 if (GVar->hasExternalLinkage()) {
1140 if (const char *Directive = MAI->getZeroFillDirective()) {
1141 O << "\t.globl\t" << name << "\n";
1142 O << Directive << "__DATA, __common, " << name << ", "
1143 << Size << ", " << Align << "\n";
1148 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1149 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1152 if (GVar->hasLocalLinkage()) {
1153 O << MAI->getLCOMMDirective() << name << "," << Size
1155 } else if (GVar->hasCommonLinkage()) {
1156 O << MAI->getCOMMDirective() << name << "," << Size
1159 OutStreamer.SwitchSection(TheSection);
1160 O << "\t.globl " << name << '\n'
1161 << MAI->getWeakDefDirective() << name << '\n';
1162 EmitAlignment(Align, GVar);
1165 O << "\t\t\t\t" << MAI->getCommentString() << ' ';
1166 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1169 EmitGlobalConstant(C);
1172 } else if (MAI->getLCOMMDirective() != NULL) {
1173 if (GVar->hasLocalLinkage()) {
1174 O << MAI->getLCOMMDirective() << name << "," << Size;
1176 O << MAI->getCOMMDirective() << name << "," << Size;
1177 if (MAI->getCOMMDirectiveTakesAlignment())
1178 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1181 if (GVar->hasLocalLinkage())
1182 O << "\t.local\t" << name << "\n";
1183 O << MAI->getCOMMDirective() << name << "," << Size;
1184 if (MAI->getCOMMDirectiveTakesAlignment())
1185 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1188 O << "\t\t" << MAI->getCommentString() << " ";
1189 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1196 switch (GVar->getLinkage()) {
1197 case GlobalValue::CommonLinkage:
1198 case GlobalValue::LinkOnceAnyLinkage:
1199 case GlobalValue::LinkOnceODRLinkage:
1200 case GlobalValue::WeakAnyLinkage:
1201 case GlobalValue::WeakODRLinkage:
1202 case GlobalValue::LinkerPrivateLinkage:
1204 O << "\t.globl " << name << "\n"
1205 << "\t.weak_definition " << name << "\n";
1207 O << "\t.weak " << name << "\n";
1210 case GlobalValue::AppendingLinkage:
1211 // FIXME: appending linkage variables should go into a section of
1212 // their name or something. For now, just emit them as external.
1213 case GlobalValue::ExternalLinkage:
1214 O << "\t.globl " << name << "\n";
1216 case GlobalValue::PrivateLinkage:
1217 case GlobalValue::InternalLinkage:
1220 llvm_unreachable("Unknown linkage type!");
1223 EmitAlignment(Align, GVar);
1226 O << "\t\t\t\t" << MAI->getCommentString() << " ";
1227 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1230 if (MAI->hasDotTypeDotSizeDirective())
1231 O << "\t.size " << name << ", " << Size << "\n";
1233 EmitGlobalConstant(C);
1238 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1239 if (Subtarget->isTargetDarwin()) {
1240 // All darwin targets use mach-o.
1241 TargetLoweringObjectFileMachO &TLOFMacho =
1242 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1243 MachineModuleInfoMachO &MMIMacho =
1244 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1248 // Output non-lazy-pointers for external and common global variables.
1249 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1251 if (!Stubs.empty()) {
1252 // Switch with ".non_lazy_symbol_pointer" directive.
1253 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1255 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1256 Stubs[i].first->print(O, MAI);
1257 O << ":\n\t.indirect_symbol ";
1258 Stubs[i].second->print(O, MAI);
1259 O << "\n\t.long\t0\n";
1263 Stubs = MMIMacho.GetHiddenGVStubList();
1264 if (!Stubs.empty()) {
1265 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1267 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1268 Stubs[i].first->print(O, MAI);
1270 Stubs[i].second->print(O, MAI);
1275 // Funny Darwin hack: This flag tells the linker that no global symbols
1276 // contain code that falls through to other global symbols (e.g. the obvious
1277 // implementation of multiple entry points). If this doesn't occur, the
1278 // linker can safely perform dead code stripping. Since LLVM never
1279 // generates code that does this, it is always safe to set.
1280 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1284 // Force static initialization.
1285 extern "C" void LLVMInitializeARMAsmPrinter() {
1286 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1287 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);