1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCInstrItineraries.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
33 #define GET_SUBTARGETINFO_HEADER
34 #include "ARMGenSubtargetInfo.inc"
40 class ARMBaseTargetMachine;
42 class ARMSubtarget : public ARMGenSubtargetInfo {
44 enum ARMProcFamilyEnum {
45 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
46 CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexA53, CortexA57,
47 CortexA72, Krait, Swift
49 enum ARMProcClassEnum {
50 None, AClass, RClass, MClass
53 ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
54 ARMv5tej, ARMv6, ARMv6k, ARMv6z, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
55 ARMv7m, ARMv7em, ARMv8a, ARMv81a
58 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
59 ARMProcFamilyEnum ARMProcFamily;
61 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
62 ARMProcClassEnum ARMProcClass;
64 /// ARMArch - ARM architecture
67 /// HasV4TOps, HasV5TOps, HasV5TEOps,
68 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
69 /// Specify whether target support specific ARM ISA variants.
81 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
82 /// floating point ISAs are supported.
89 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
90 /// specified. Use the method useNEONForSinglePrecisionFP() to
91 /// determine if NEON should actually be used.
92 bool UseNEONForSinglePrecisionFP;
94 /// UseMulOps - True if non-microcoded fused integer multiply-add and
95 /// multiply-subtract instructions should be used.
98 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
99 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
102 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
103 /// forwarding to allow mul + mla being issued back to back.
104 bool HasVMLxForwarding;
106 /// SlowFPBrcc - True if floating point compare + branch is slow.
109 /// InThumbMode - True if compiling for Thumb, false for ARM.
112 /// UseSoftFloat - True if we're using software floating point features.
115 /// HasThumb2 - True if Thumb2 instructions are supported.
118 /// NoARM - True if subtarget does not support ARM mode execution.
121 /// ReserveR9 - True if R9 is not available as a general purpose register.
124 /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
125 /// 32-bit imms (including global addresses).
128 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
129 /// must be able to synthesize call stubs for interworking between ARM and
131 bool SupportsTailCall;
133 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
137 /// HasD16 - True if subtarget is limited to 16 double precision
138 /// FP registers for VFPv3.
141 /// HasHardwareDivide - True if subtarget supports [su]div
142 bool HasHardwareDivide;
144 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
145 bool HasHardwareDivideInARM;
147 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
149 bool HasT2ExtractPack;
151 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
155 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
156 /// over 16-bit ones.
159 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
160 /// that partially update CPSR and add false dependency on the previous
161 /// CPSR setting instruction.
162 bool AvoidCPSRPartialUpdate;
164 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
165 /// movs with shifter operand (i.e. asr, lsl, lsr).
166 bool AvoidMOVsShifterOperand;
168 /// HasRAS - Some processors perform return stack prediction. CodeGen should
169 /// avoid issue "normal" call instructions to callees which do not return.
172 /// HasMPExtension - True if the subtarget supports Multiprocessing
173 /// extension (ARMv7 only).
176 /// HasVirtualization - True if the subtarget supports the Virtualization
178 bool HasVirtualization;
180 /// FPOnlySP - If true, the floating point unit only supports single
184 /// If true, the processor supports the Performance Monitor Extensions. These
185 /// include a generic cycle-counter as well as more fine-grained (often
186 /// implementation-specific) events.
189 /// HasTrustZone - if true, processor supports TrustZone security extensions
192 /// HasCrypto - if true, processor supports Cryptography extensions
195 /// HasCRC - if true, processor supports CRC instructions
198 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
199 /// particularly effective at zeroing a VFP register.
200 bool HasZeroCycleZeroing;
202 /// StrictAlign - If true, the subtarget disallows unaligned memory
203 /// accesses for some types. For details, see
204 /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
207 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
208 /// blocks to conform to ARMv8 rule.
211 /// HasDSP - If true, the subtarget supports the DSP (saturating arith
212 /// and such) instructions.
215 /// NaCl TRAP instruction is generated instead of the regular TRAP.
218 /// Generate calls via indirect call instructions.
221 /// Target machine allowed unsafe FP math (such as use of NEON fp)
224 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
227 /// stackAlignment - The minimum alignment known to hold of the stack frame on
228 /// entry to the function and which must be maintained by every function.
229 unsigned stackAlignment;
231 /// CPUString - String name of used CPU.
232 std::string CPUString;
234 /// IsLittle - The target is Little Endian
237 /// TargetTriple - What processor and OS we're targeting.
240 /// SchedModel - Processor specific instruction costs.
241 MCSchedModel SchedModel;
243 /// Selected instruction itineraries (one entry per itinerary class.)
244 InstrItineraryData InstrItins;
246 /// Options passed via command line that could influence the target
247 const TargetOptions &Options;
249 const ARMBaseTargetMachine &TM;
252 /// This constructor initializes the data members to match that
253 /// of the specified triple.
255 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
256 const ARMBaseTargetMachine &TM, bool IsLittle);
258 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
259 /// that still makes it profitable to inline the call.
260 unsigned getMaxInlineSizeThreshold() const {
263 /// ParseSubtargetFeatures - Parses features string setting specified
264 /// subtarget options. Definition of function is auto generated by tblgen.
265 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
267 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
268 /// so that we can use initializer lists for subtarget initialization.
269 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
271 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
274 const ARMBaseInstrInfo *getInstrInfo() const override {
275 return InstrInfo.get();
277 const ARMTargetLowering *getTargetLowering() const override {
280 const ARMFrameLowering *getFrameLowering() const override {
281 return FrameLowering.get();
283 const ARMBaseRegisterInfo *getRegisterInfo() const override {
284 return &InstrInfo->getRegisterInfo();
288 ARMSelectionDAGInfo TSInfo;
289 // Either Thumb1FrameLowering or ARMFrameLowering.
290 std::unique_ptr<ARMFrameLowering> FrameLowering;
291 // Either Thumb1InstrInfo or Thumb2InstrInfo.
292 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
293 ARMTargetLowering TLInfo;
295 void initializeEnvironment();
296 void initSubtargetFeatures(StringRef CPU, StringRef FS);
297 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
300 void computeIssueWidth();
302 bool hasV4TOps() const { return HasV4TOps; }
303 bool hasV5TOps() const { return HasV5TOps; }
304 bool hasV5TEOps() const { return HasV5TEOps; }
305 bool hasV6Ops() const { return HasV6Ops; }
306 bool hasV6MOps() const { return HasV6MOps; }
307 bool hasV6KOps() const { return HasV6KOps; }
308 bool hasV6T2Ops() const { return HasV6T2Ops; }
309 bool hasV7Ops() const { return HasV7Ops; }
310 bool hasV8Ops() const { return HasV8Ops; }
311 bool hasV8_1aOps() const { return HasV8_1aOps; }
313 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
314 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
315 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
316 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
317 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
318 bool isSwift() const { return ARMProcFamily == Swift; }
319 bool isCortexM3() const { return CPUString == "cortex-m3"; }
320 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
321 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
322 bool isKrait() const { return ARMProcFamily == Krait; }
324 bool hasARMOps() const { return !NoARM; }
326 bool hasVFP2() const { return HasVFPv2; }
327 bool hasVFP3() const { return HasVFPv3; }
328 bool hasVFP4() const { return HasVFPv4; }
329 bool hasFPARMv8() const { return HasFPARMv8; }
330 bool hasNEON() const { return HasNEON; }
331 bool hasCrypto() const { return HasCrypto; }
332 bool hasCRC() const { return HasCRC; }
333 bool hasVirtualization() const { return HasVirtualization; }
334 bool useNEONForSinglePrecisionFP() const {
335 return hasNEON() && UseNEONForSinglePrecisionFP;
338 bool hasDivide() const { return HasHardwareDivide; }
339 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
340 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
341 bool hasDataBarrier() const { return HasDataBarrier; }
342 bool hasAnyDataBarrier() const {
343 return HasDataBarrier || (hasV6Ops() && !isThumb());
345 bool useMulOps() const { return UseMulOps; }
346 bool useFPVMLx() const { return !SlowFPVMLx; }
347 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
348 bool isFPBrccSlow() const { return SlowFPBrcc; }
349 bool isFPOnlySP() const { return FPOnlySP; }
350 bool hasPerfMon() const { return HasPerfMon; }
351 bool hasTrustZone() const { return HasTrustZone; }
352 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
353 bool prefers32BitThumb() const { return Pref32BitThumb; }
354 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
355 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
356 bool hasRAS() const { return HasRAS; }
357 bool hasMPExtension() const { return HasMPExtension; }
358 bool hasDSP() const { return HasDSP; }
359 bool useNaClTrap() const { return UseNaClTrap; }
360 bool useSjLjEH() const { return UseSjLjEH; }
361 bool genLongCalls() const { return GenLongCalls; }
363 bool hasFP16() const { return HasFP16; }
364 bool hasD16() const { return HasD16; }
366 const Triple &getTargetTriple() const { return TargetTriple; }
368 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
369 bool isTargetIOS() const { return TargetTriple.isiOS(); }
370 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
371 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
372 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
373 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
374 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
376 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
377 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
378 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
380 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
381 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
382 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
383 // even for GNUEABI, so we can make a distinction here and still conform to
384 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
385 // FIXME: The Darwin exception is temporary, while we move users to
386 // "*-*-*-macho" triples as quickly as possible.
387 bool isTargetAEABI() const {
388 return (TargetTriple.getEnvironment() == Triple::EABI ||
389 TargetTriple.getEnvironment() == Triple::EABIHF) &&
390 !isTargetDarwin() && !isTargetWindows();
392 bool isTargetGNUAEABI() const {
393 return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
394 TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
395 !isTargetDarwin() && !isTargetWindows();
398 // ARM Targets that support EHABI exception handling standard
399 // Darwin uses SjLj. Other targets might need more checks.
400 bool isTargetEHABICompatible() const {
401 return (TargetTriple.getEnvironment() == Triple::EABI ||
402 TargetTriple.getEnvironment() == Triple::GNUEABI ||
403 TargetTriple.getEnvironment() == Triple::EABIHF ||
404 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
405 isTargetAndroid()) &&
406 !isTargetDarwin() && !isTargetWindows();
409 bool isTargetHardFloat() const {
410 // FIXME: this is invalid for WindowsCE
411 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
412 TargetTriple.getEnvironment() == Triple::EABIHF ||
413 isTargetWindows() || isAAPCS16_ABI();
415 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
417 bool isAPCS_ABI() const;
418 bool isAAPCS_ABI() const;
419 bool isAAPCS16_ABI() const;
421 bool useSoftFloat() const { return UseSoftFloat; }
422 bool isThumb() const { return InThumbMode; }
423 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
424 bool isThumb2() const { return InThumbMode && HasThumb2; }
425 bool hasThumb2() const { return HasThumb2; }
426 bool isMClass() const { return ARMProcClass == MClass; }
427 bool isRClass() const { return ARMProcClass == RClass; }
428 bool isAClass() const { return ARMProcClass == AClass; }
430 bool isR9Reserved() const {
431 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
434 bool useStride4VFPs(const MachineFunction &MF) const;
436 bool useMovt(const MachineFunction &MF) const;
438 bool supportsTailCall() const { return SupportsTailCall; }
440 bool allowsUnalignedMem() const { return !StrictAlign; }
442 bool restrictIT() const { return RestrictIT; }
444 const std::string & getCPUString() const { return CPUString; }
446 bool isLittle() const { return IsLittle; }
448 unsigned getMispredictionPenalty() const;
450 /// This function returns true if the target has sincos() routine in its
451 /// compiler runtime or math libraries.
452 bool hasSinCos() const;
454 /// Returns true if machine scheduler should be enabled.
455 bool enableMachineScheduler() const override;
457 /// True for some subtargets at > -O0.
458 bool enablePostRAScheduler() const override;
460 // enableAtomicExpand- True if we need to expand our atomics.
461 bool enableAtomicExpand() const override;
463 /// getInstrItins - Return the instruction itineraries based on subtarget
465 const InstrItineraryData *getInstrItineraryData() const override {
469 /// getStackAlignment - Returns the minimum alignment known to hold of the
470 /// stack frame on entry to the function and which must be maintained by every
471 /// function for this subtarget.
472 unsigned getStackAlignment() const { return stackAlignment; }
474 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
476 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
478 /// True if fast-isel is used.
479 bool useFastISel() const;
481 } // End llvm namespace
483 #endif // ARMSUBTARGET_H