1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/GlobalValue.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_SUBTARGETINFO_TARGET_DESC
22 #define GET_SUBTARGETINFO_CTOR
23 #include "ARMGenSubtargetInfo.inc"
28 ReserveR9("arm-reserve-r9", cl::Hidden,
29 cl::desc("Reserve R9, making it unavailable as GPR"));
32 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
35 UseFusedMulOps("arm-use-mulops",
36 cl::init(true), cl::Hidden);
39 StrictAlign("arm-strict-align", cl::Hidden,
40 cl::desc("Disallow all unaligned memory accesses"));
42 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
43 const std::string &FS)
44 : ARMGenSubtargetInfo(TT, CPU, FS)
45 , ARMProcFamily(Others)
56 , UseNEONForSinglePrecisionFP(false)
57 , UseMulOps(UseFusedMulOps)
59 , HasVMLxForwarding(false)
65 , PostRAScheduler(false)
66 , IsR9Reserved(ReserveR9)
68 , SupportsTailCall(false)
71 , HasHardwareDivide(false)
72 , HasHardwareDivideInARM(false)
73 , HasT2ExtractPack(false)
74 , HasDataBarrier(false)
75 , Pref32BitThumb(false)
76 , AvoidCPSRPartialUpdate(false)
77 , AvoidMOVsShifterOperand(false)
79 , HasMPExtension(false)
81 , AllowsUnalignedMem(false)
87 , TargetABI(ARM_ABI_APCS) {
88 // Determine default and user specified characteristics
89 if (CPUString.empty())
90 CPUString = "generic";
92 // Insert the architecture feature derived from the target triple into the
93 // feature string. This is important for setting features that are implied
94 // based on the architecture version.
95 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString);
98 ArchFS = ArchFS + "," + FS;
102 ParseSubtargetFeatures(CPUString, ArchFS);
104 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
105 // ARM version or CPU and then remove this.
106 if (!HasV6T2Ops && hasThumb2())
107 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
109 // Keep a pointer to static instruction cost data for the specified CPU.
110 SchedModel = getSchedModelForCPU(CPUString);
112 // Initialize scheduling itinerary for the specified CPU.
113 InstrItins = getInstrItineraryForCPU(CPUString);
115 if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
116 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
117 // Darwin-EABI conforms to AACPS but not the rest of EABI.
118 TargetABI = ARM_ABI_AAPCS;
124 UseMovt = hasV6T2Ops();
126 IsR9Reserved = ReserveR9 | !HasV6Ops;
127 UseMovt = DarwinUseMOVT && hasV6T2Ops();
128 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
131 if (!isThumb() || hasThumb2())
132 PostRAScheduler = true;
134 // v6+ may or may not support unaligned mem access depending on the system
136 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
137 AllowsUnalignedMem = true;
140 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
142 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
143 Reloc::Model RelocM) const {
144 if (RelocM == Reloc::Static)
147 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
149 bool isDecl = GV->hasAvailableExternallyLinkage();
150 if (GV->isDeclaration() && !GV->isMaterializable())
153 if (!isTargetDarwin()) {
154 // Extra load is needed for all externally visible.
155 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
159 if (RelocM == Reloc::PIC_) {
160 // If this is a strong reference to a definition, it is definitely not
162 if (!isDecl && !GV->isWeakForLinker())
165 // Unless we have a symbol with hidden visibility, we have to go through a
166 // normal $non_lazy_ptr stub because this symbol might be resolved late.
167 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
170 // If symbol visibility is hidden, we have a stub for common symbol
171 // references and external declarations.
172 if (isDecl || GV->hasCommonLinkage())
173 // Hidden $non_lazy_ptr reference.
178 // If this is a strong reference to a definition, it is definitely not
180 if (!isDecl && !GV->isWeakForLinker())
183 // Unless we have a symbol with hidden visibility, we have to go through a
184 // normal $non_lazy_ptr stub because this symbol might be resolved late.
185 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
193 unsigned ARMSubtarget::getMispredictionPenalty() const {
194 return SchedModel->MispredictPenalty;
197 bool ARMSubtarget::enablePostRAScheduler(
198 CodeGenOpt::Level OptLevel,
199 TargetSubtargetInfo::AntiDepBreakMode& Mode,
200 RegClassVector& CriticalPathRCs) const {
201 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
202 CriticalPathRCs.clear();
203 CriticalPathRCs.push_back(&ARM::GPRRegClass);
204 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;