lib/Target/ARM/ARMRegisterInfo.h

   1 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the "Instituto Nokia de Tecnologia" and
   6 // is distributed under the University of Illinois Open Source
   7 // License. See LICENSE.TXT for details.
   8 //
   9 //===----------------------------------------------------------------------===//
  10 //
  11 // This file contains the ARM implementation of the MRegisterInfo class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef ARMREGISTERINFO_H
  16 #define ARMREGISTERINFO_H
  17
  18 #include "llvm/Target/MRegisterInfo.h"
  19 #include "ARMGenRegisterInfo.h.inc"
  20
  21 namespace llvm {
  22   class ARMSubtarget;
  23   class TargetInstrInfo;
  24   class Type;
  25
  26 struct ARMRegisterInfo : public ARMGenRegisterInfo {
  27   const TargetInstrInfo &TII;
  28   const ARMSubtarget &STI;
  29 private:
  30   /// FramePtr - ARM physical register used as frame ptr.
  31   unsigned FramePtr;
  32
  33 public:
  34   ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
  35
  36   /// getRegisterNumbering - Given the enum value for some register, e.g.
  37   /// ARM::LR, return the number that it corresponds to (e.g. 14).
  38   static unsigned getRegisterNumbering(unsigned RegEnum);
  39
  40   /// Code Generation virtual methods...
  41   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
  42                                  MachineBasicBlock::iterator MI,
  43                                  const std::vector<CalleeSavedInfo> &CSI) const;
  44
  45   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
  46                                    MachineBasicBlock::iterator MI,
  47                                  const std::vector<CalleeSavedInfo> &CSI) const;
  48
  49   void storeRegToStackSlot(MachineBasicBlock &MBB,
  50                            MachineBasicBlock::iterator MBBI,
  51                            unsigned SrcReg, bool isKill, int FrameIndex,
  52                            const TargetRegisterClass *RC) const;
  53
  54   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
  55                       SmallVectorImpl<MachineOperand> &Addr,
  56                       const TargetRegisterClass *RC,
  57                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
  58
  59   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  60                             MachineBasicBlock::iterator MBBI,
  61                             unsigned DestReg, int FrameIndex,
  62                             const TargetRegisterClass *RC) const;
  63
  64   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
  65                        SmallVectorImpl<MachineOperand> &Addr,
  66                        const TargetRegisterClass *RC,
  67                        SmallVectorImpl<MachineInstr*> &NewMIs) const;
  68
  69   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
  70                     unsigned DestReg, unsigned SrcReg,
  71                     const TargetRegisterClass *DestRC,
  72                     const TargetRegisterClass *SrcRC) const;
  73
  74   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
  75                      unsigned DestReg, const MachineInstr *Orig) const;
  76
  77   MachineInstr* foldMemoryOperand(MachineInstr* MI,
  78                                   SmallVectorImpl<unsigned> &Ops,
  79                                   int FrameIndex) const;
  80
  81   MachineInstr* foldMemoryOperand(MachineInstr* MI,
  82                                   SmallVectorImpl<unsigned> &Ops,
  83                                   MachineInstr* LoadMI) const {
  84     return 0;
  85   }
  86
  87   bool canFoldMemoryOperand(MachineInstr *MI,
  88                             SmallVectorImpl<unsigned> &Ops) const;
  89
  90   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
  91
  92   const TargetRegisterClass* const*
  93   getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
  94
  95   BitVector getReservedRegs(const MachineFunction &MF) const;
  96
  97   bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
  98
  99   bool requiresRegisterScavenging(const MachineFunction &MF) const;
 100
 101   bool hasFP(const MachineFunction &MF) const;
 102
 103   bool hasReservedCallFrame(MachineFunction &MF) const;
 104
 105   void eliminateCallFramePseudoInstr(MachineFunction &MF,
 106                                      MachineBasicBlock &MBB,
 107                                      MachineBasicBlock::iterator I) const;
 108
 109   void eliminateFrameIndex(MachineBasicBlock::iterator II,
 110                            int SPAdj, RegScavenger *RS = NULL) const;
 111
 112   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 113                                             RegScavenger *RS = NULL) const;
 114
 115   void emitPrologue(MachineFunction &MF) const;
 116   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 117
 118   // Debug information queries.
 119   unsigned getRARegister() const;
 120   unsigned getFrameRegister(MachineFunction &MF) const;
 121
 122   // Exception handling queries.
 123   unsigned getEHExceptionRegister() const;
 124   unsigned getEHHandlerRegister() const;
 125
 126   int getDwarfRegNum(unsigned RegNum, bool isEH) const;
 127 };
 128
 129 } // end namespace llvm
 130
 131 #endif