1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const ARMBaseInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 // Can be only subclassed.
56 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57 const ARMSubtarget &STI);
59 // Return the opcode that implements 'Op', or 0 if no opcode
60 unsigned getOpcode(int Op) const;
63 /// getRegisterNumbering - Given the enum value for some register, e.g.
64 /// ARM::LR, return the number that it corresponds to (e.g. 14). It
65 /// also returns true in isSPVFP if the register is a single precision
67 static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
69 /// Code Generation virtual methods...
70 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
72 BitVector getReservedRegs(const MachineFunction &MF) const;
74 /// getMatchingSuperRegClass - Return a subclass of the specified register
75 /// class A so that each register in it has a sub-register of the
76 /// specified sub-register index which is in the specified register class B.
77 virtual const TargetRegisterClass *
78 getMatchingSuperRegClass(const TargetRegisterClass *A,
79 const TargetRegisterClass *B, unsigned Idx) const;
81 /// canCombinedSubRegIndex - Given a register class and a list of sub-register
82 /// indices, return true if it's possible to combine the sub-register indices
83 /// into one that corresponds to a larger sub-register. Return the new sub-
84 /// register index by reference. Note the new index by be zero if the given
85 /// sub-registers combined to form the whole register.
86 virtual bool canCombinedSubRegIndex(const TargetRegisterClass *RC,
87 SmallVectorImpl<unsigned> &SubIndices,
88 unsigned &NewSubIdx) const;
90 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
92 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
93 getAllocationOrder(const TargetRegisterClass *RC,
94 unsigned HintType, unsigned HintReg,
95 const MachineFunction &MF) const;
97 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
98 const MachineFunction &MF) const;
100 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
101 MachineFunction &MF) const;
103 bool hasFP(const MachineFunction &MF) const;
105 bool canRealignStack(const MachineFunction &MF) const;
106 bool needsStackRealignment(const MachineFunction &MF) const;
108 bool cannotEliminateFrame(const MachineFunction &MF) const;
110 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
111 RegScavenger *RS = NULL) const;
113 // Debug information queries.
114 unsigned getRARegister() const;
115 unsigned getFrameRegister(const MachineFunction &MF) const;
116 int getFrameIndexReference(const MachineFunction &MF, int FI,
117 unsigned &FrameReg) const;
118 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
120 // Exception handling queries.
121 unsigned getEHExceptionRegister() const;
122 unsigned getEHHandlerRegister() const;
124 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
126 bool isLowRegister(unsigned Reg) const;
129 /// emitLoadConstPool - Emits a load from constpool to materialize the
130 /// specified immediate.
131 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator &MBBI,
134 unsigned DestReg, unsigned SubIdx,
136 ARMCC::CondCodes Pred = ARMCC::AL,
137 unsigned PredReg = 0) const;
139 /// Code Generation virtual methods...
140 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
142 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
144 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
146 virtual bool hasReservedCallFrame(MachineFunction &MF) const;
147 virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const;
149 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
150 MachineBasicBlock &MBB,
151 MachineBasicBlock::iterator I) const;
153 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
154 int SPAdj, FrameIndexValue *Value = NULL,
155 RegScavenger *RS = NULL) const;
157 virtual void emitPrologue(MachineFunction &MF) const;
158 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
161 unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
163 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
165 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
168 } // end namespace llvm