1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
50 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
58 llvm_unreachable("Unknown ARM register!");
59 case R0: case D0: case Q0: return 0;
60 case R1: case D1: case Q1: return 1;
61 case R2: case D2: case Q2: return 2;
62 case R3: case D3: case Q3: return 3;
63 case R4: case D4: case Q4: return 4;
64 case R5: case D5: case Q5: return 5;
65 case R6: case D6: case Q6: return 6;
66 case R7: case D7: case Q7: return 7;
67 case R8: case D8: case Q8: return 8;
68 case R9: case D9: case Q9: return 9;
69 case R10: case D10: case Q10: return 10;
70 case R11: case D11: case Q11: return 11;
71 case R12: case D12: case Q12: return 12;
72 case SP: case D13: case Q13: return 13;
73 case LR: case D14: case Q14: return 14;
74 case PC: case D15: case Q15: return 15;
93 case S0: case S1: case S2: case S3:
94 case S4: case S5: case S6: case S7:
95 case S8: case S9: case S10: case S11:
96 case S12: case S13: case S14: case S15:
97 case S16: case S17: case S18: case S19:
98 case S20: case S21: case S22: case S23:
99 case S24: case S25: case S26: case S27:
100 case S28: case S29: case S30: case S31: {
104 default: return 0; // Avoid compile time warning.
142 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143 const ARMSubtarget &sti)
144 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
150 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 static const unsigned CalleeSavedRegs[] = {
152 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
155 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
160 static const unsigned DarwinCalleeSavedRegs[] = {
161 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
164 ARM::R11, ARM::R10, ARM::R8,
166 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
170 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
173 const TargetRegisterClass* const *
174 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
175 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
176 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
180 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
185 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
186 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
188 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
190 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
195 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
196 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
197 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198 &ARM::GPRRegClass, &ARM::GPRRegClass,
200 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
205 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
206 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
207 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
208 &ARM::GPRRegClass, &ARM::GPRRegClass,
210 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
211 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
215 if (STI.isThumb1Only()) {
216 return STI.isTargetDarwin()
217 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
219 return STI.isTargetDarwin()
220 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
223 BitVector ARMBaseRegisterInfo::
224 getReservedRegs(const MachineFunction &MF) const {
225 // FIXME: avoid re-calculating this everytime.
226 BitVector Reserved(getNumRegs());
227 Reserved.set(ARM::SP);
228 Reserved.set(ARM::PC);
229 if (STI.isTargetDarwin() || hasFP(MF))
230 Reserved.set(FramePtr);
231 // Some targets reserve R9.
232 if (STI.isR9Reserved())
233 Reserved.set(ARM::R9);
237 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238 unsigned Reg) const {
246 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
250 return STI.isR9Reserved();
256 const TargetRegisterClass *
257 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258 const TargetRegisterClass *B,
259 unsigned SubIdx) const {
267 if (A->getSize() == 8) {
268 if (B == &ARM::SPR_8RegClass)
269 return &ARM::DPR_8RegClass;
270 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
271 if (A == &ARM::DPR_8RegClass)
273 return &ARM::DPR_VFP2RegClass;
276 if (A->getSize() == 16) {
277 if (B == &ARM::SPR_8RegClass)
278 return &ARM::QPR_8RegClass;
279 return &ARM::QPR_VFP2RegClass;
282 if (A->getSize() == 32) {
283 if (B == &ARM::SPR_8RegClass)
284 return 0; // Do not allow coalescing!
285 return &ARM::QQPR_VFP2RegClass;
288 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
289 return 0; // Do not allow coalescing!
296 if (A->getSize() == 16) {
297 if (B == &ARM::DPR_VFP2RegClass)
298 return &ARM::QPR_VFP2RegClass;
299 if (B == &ARM::DPR_8RegClass)
300 return 0; // Do not allow coalescing!
304 if (A->getSize() == 32) {
305 if (B == &ARM::DPR_VFP2RegClass)
306 return &ARM::QQPR_VFP2RegClass;
307 if (B == &ARM::DPR_8RegClass)
308 return 0; // Do not allow coalescing!
312 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
313 if (B != &ARM::DPRRegClass)
314 return 0; // Do not allow coalescing!
321 // D sub-registers of QQQQ registers.
322 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
324 return 0; // Do not allow coalescing!
330 if (A->getSize() == 32) {
331 if (B == &ARM::QPR_VFP2RegClass)
332 return &ARM::QQPR_VFP2RegClass;
333 if (B == &ARM::QPR_8RegClass)
334 return 0; // Do not allow coalescing!
338 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
339 if (B == &ARM::QPRRegClass)
341 return 0; // Do not allow coalescing!
345 // Q sub-registers of QQQQ registers.
346 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
348 return 0; // Do not allow coalescing!
354 const TargetRegisterClass *
355 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
356 return ARM::GPRRegisterClass;
359 /// getAllocationOrder - Returns the register allocation order for a specified
360 /// register class in the form of a pair of TargetRegisterClass iterators.
361 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
362 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
363 unsigned HintType, unsigned HintReg,
364 const MachineFunction &MF) const {
365 // Alternative register allocation orders when favoring even / odd registers
366 // of register pairs.
368 // No FP, R9 is available.
369 static const unsigned GPREven1[] = {
370 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
371 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
374 static const unsigned GPROdd1[] = {
375 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
376 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
380 // FP is R7, R9 is available.
381 static const unsigned GPREven2[] = {
382 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
383 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
386 static const unsigned GPROdd2[] = {
387 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
388 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
392 // FP is R11, R9 is available.
393 static const unsigned GPREven3[] = {
394 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
395 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
398 static const unsigned GPROdd3[] = {
399 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
400 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
404 // No FP, R9 is not available.
405 static const unsigned GPREven4[] = {
406 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
407 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
410 static const unsigned GPROdd4[] = {
411 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
412 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
416 // FP is R7, R9 is not available.
417 static const unsigned GPREven5[] = {
418 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
419 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
422 static const unsigned GPROdd5[] = {
423 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
424 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
428 // FP is R11, R9 is not available.
429 static const unsigned GPREven6[] = {
430 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
431 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
433 static const unsigned GPROdd6[] = {
434 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
435 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
439 if (HintType == ARMRI::RegPairEven) {
440 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
441 // It's no longer possible to fulfill this hint. Return the default
443 return std::make_pair(RC->allocation_order_begin(MF),
444 RC->allocation_order_end(MF));
446 if (!STI.isTargetDarwin() && !hasFP(MF)) {
447 if (!STI.isR9Reserved())
448 return std::make_pair(GPREven1,
449 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
451 return std::make_pair(GPREven4,
452 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
453 } else if (FramePtr == ARM::R7) {
454 if (!STI.isR9Reserved())
455 return std::make_pair(GPREven2,
456 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
458 return std::make_pair(GPREven5,
459 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
460 } else { // FramePtr == ARM::R11
461 if (!STI.isR9Reserved())
462 return std::make_pair(GPREven3,
463 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
465 return std::make_pair(GPREven6,
466 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
468 } else if (HintType == ARMRI::RegPairOdd) {
469 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
470 // It's no longer possible to fulfill this hint. Return the default
472 return std::make_pair(RC->allocation_order_begin(MF),
473 RC->allocation_order_end(MF));
475 if (!STI.isTargetDarwin() && !hasFP(MF)) {
476 if (!STI.isR9Reserved())
477 return std::make_pair(GPROdd1,
478 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
480 return std::make_pair(GPROdd4,
481 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
482 } else if (FramePtr == ARM::R7) {
483 if (!STI.isR9Reserved())
484 return std::make_pair(GPROdd2,
485 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
487 return std::make_pair(GPROdd5,
488 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
489 } else { // FramePtr == ARM::R11
490 if (!STI.isR9Reserved())
491 return std::make_pair(GPROdd3,
492 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
494 return std::make_pair(GPROdd6,
495 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
498 return std::make_pair(RC->allocation_order_begin(MF),
499 RC->allocation_order_end(MF));
502 /// ResolveRegAllocHint - Resolves the specified register allocation hint
503 /// to a physical register. Returns the physical register if it is successful.
505 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
506 const MachineFunction &MF) const {
507 if (Reg == 0 || !isPhysicalRegister(Reg))
511 else if (Type == (unsigned)ARMRI::RegPairOdd)
513 return getRegisterPairOdd(Reg, MF);
514 else if (Type == (unsigned)ARMRI::RegPairEven)
516 return getRegisterPairEven(Reg, MF);
521 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
522 MachineFunction &MF) const {
523 MachineRegisterInfo *MRI = &MF.getRegInfo();
524 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
525 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
526 Hint.first == (unsigned)ARMRI::RegPairEven) &&
527 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
528 // If 'Reg' is one of the even / odd register pair and it's now changed
529 // (e.g. coalesced) into a different register. The other register of the
530 // pair allocation hint must be updated to reflect the relationship
532 unsigned OtherReg = Hint.second;
533 Hint = MRI->getRegAllocationHint(OtherReg);
534 if (Hint.second == Reg)
535 // Make sure the pair has not already divorced.
536 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
540 /// hasFP - Return true if the specified function should have a dedicated frame
541 /// pointer register. This is true if the function has variable sized allocas
542 /// or if frame pointer elimination is disabled.
544 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
545 const MachineFrameInfo *MFI = MF.getFrameInfo();
546 return ((DisableFramePointerElim(MF) && MFI->hasCalls())||
547 needsStackRealignment(MF) ||
548 MFI->hasVarSizedObjects() ||
549 MFI->isFrameAddressTaken());
552 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
553 const MachineFrameInfo *MFI = MF.getFrameInfo();
554 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
555 return (RealignStack &&
556 !AFI->isThumb1OnlyFunction() &&
557 !MFI->hasVarSizedObjects());
560 bool ARMBaseRegisterInfo::
561 needsStackRealignment(const MachineFunction &MF) const {
562 const MachineFrameInfo *MFI = MF.getFrameInfo();
563 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
564 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
565 return (RealignStack &&
566 !AFI->isThumb1OnlyFunction() &&
567 (MFI->getMaxAlignment() > StackAlign) &&
568 !MFI->hasVarSizedObjects());
571 bool ARMBaseRegisterInfo::
572 cannotEliminateFrame(const MachineFunction &MF) const {
573 const MachineFrameInfo *MFI = MF.getFrameInfo();
574 if (DisableFramePointerElim(MF) && MFI->hasCalls())
576 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
577 || needsStackRealignment(MF);
580 /// estimateStackSize - Estimate and return the size of the frame.
581 static unsigned estimateStackSize(MachineFunction &MF) {
582 const MachineFrameInfo *FFI = MF.getFrameInfo();
584 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
585 int FixedOff = -FFI->getObjectOffset(i);
586 if (FixedOff > Offset) Offset = FixedOff;
588 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
589 if (FFI->isDeadObjectIndex(i))
591 Offset += FFI->getObjectSize(i);
592 unsigned Align = FFI->getObjectAlignment(i);
593 // Adjust to alignment boundary
594 Offset = (Offset+Align-1)/Align*Align;
596 return (unsigned)Offset;
599 /// estimateRSStackSizeLimit - Look at each instruction that references stack
600 /// frames and return the stack size limit beyond which some of these
601 /// instructions will require a scratch register during their expansion later.
603 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
604 unsigned Limit = (1 << 12) - 1;
605 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
606 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
608 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
609 if (!I->getOperand(i).isFI()) continue;
611 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
612 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
613 if (AddrMode == ARMII::AddrMode3 ||
614 AddrMode == ARMII::AddrModeT2_i8)
617 if (AddrMode == ARMII::AddrMode5 ||
618 AddrMode == ARMII::AddrModeT2_i8s4)
619 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
621 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
622 // When the stack offset is negative, we will end up using
623 // the i8 instructions instead.
626 if (AddrMode == ARMII::AddrMode6)
628 break; // At most one FI per instruction
637 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
638 RegScavenger *RS) const {
639 // This tells PEI to spill the FP as if it is any other callee-save register
640 // to take advantage the eliminateFrameIndex machinery. This also ensures it
641 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
642 // to combine multiple loads / stores.
643 bool CanEliminateFrame = true;
644 bool CS1Spilled = false;
645 bool LRSpilled = false;
646 unsigned NumGPRSpills = 0;
647 SmallVector<unsigned, 4> UnspilledCS1GPRs;
648 SmallVector<unsigned, 4> UnspilledCS2GPRs;
649 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
651 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
653 // FIXME: It will be better just to find spare register here.
654 if (needsStackRealignment(MF) &&
655 AFI->isThumb2Function())
656 MF.getRegInfo().setPhysRegUsed(ARM::R4);
658 // Spill LR if Thumb1 function uses variable length argument lists.
659 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
660 MF.getRegInfo().setPhysRegUsed(ARM::LR);
662 // Don't spill FP if the frame can be eliminated. This is determined
663 // by scanning the callee-save registers to see if any is used.
664 const unsigned *CSRegs = getCalleeSavedRegs();
665 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
666 for (unsigned i = 0; CSRegs[i]; ++i) {
667 unsigned Reg = CSRegs[i];
668 bool Spilled = false;
669 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
670 AFI->setCSRegisterIsSpilled(Reg);
672 CanEliminateFrame = false;
674 // Check alias registers too.
675 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
676 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
678 CanEliminateFrame = false;
683 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
684 CSRegClasses[i] == ARM::tGPRRegisterClass) {
688 if (!STI.isTargetDarwin()) {
695 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
710 if (!STI.isTargetDarwin()) {
711 UnspilledCS1GPRs.push_back(Reg);
721 UnspilledCS1GPRs.push_back(Reg);
724 UnspilledCS2GPRs.push_back(Reg);
731 bool ForceLRSpill = false;
732 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
733 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
734 // Force LR to be spilled if the Thumb function size is > 2048. This enables
735 // use of BL to implement far jump. If it turns out that it's not needed
736 // then the branch fix up path will undo it.
737 if (FnSize >= (1 << 11)) {
738 CanEliminateFrame = false;
743 // If any of the stack slot references may be out of range of an immediate
744 // offset, make sure a register (or a spill slot) is available for the
745 // register scavenger. Note that if we're indexing off the frame pointer, the
746 // effective stack size is 4 bytes larger since the FP points to the stack
747 // slot of the previous FP.
748 bool BigStack = RS &&
749 estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF);
751 bool ExtraCSSpill = false;
752 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
753 AFI->setHasStackFrame(true);
755 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
756 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
757 if (!LRSpilled && CS1Spilled) {
758 MF.getRegInfo().setPhysRegUsed(ARM::LR);
759 AFI->setCSRegisterIsSpilled(ARM::LR);
761 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
762 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
763 ForceLRSpill = false;
767 // Darwin ABI requires FP to point to the stack slot that contains the
769 if (STI.isTargetDarwin() || hasFP(MF)) {
770 MF.getRegInfo().setPhysRegUsed(FramePtr);
774 // If stack and double are 8-byte aligned and we are spilling an odd number
775 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
776 // the integer and double callee save areas.
777 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
778 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
779 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
780 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
781 unsigned Reg = UnspilledCS1GPRs[i];
782 // Don't spill high register if the function is thumb1
783 if (!AFI->isThumb1OnlyFunction() ||
784 isARMLowRegister(Reg) || Reg == ARM::LR) {
785 MF.getRegInfo().setPhysRegUsed(Reg);
786 AFI->setCSRegisterIsSpilled(Reg);
787 if (!isReservedReg(MF, Reg))
792 } else if (!UnspilledCS2GPRs.empty() &&
793 !AFI->isThumb1OnlyFunction()) {
794 unsigned Reg = UnspilledCS2GPRs.front();
795 MF.getRegInfo().setPhysRegUsed(Reg);
796 AFI->setCSRegisterIsSpilled(Reg);
797 if (!isReservedReg(MF, Reg))
802 // Estimate if we might need to scavenge a register at some point in order
803 // to materialize a stack offset. If so, either spill one additional
804 // callee-saved register or reserve a special spill slot to facilitate
805 // register scavenging. Thumb1 needs a spill slot for stack pointer
806 // adjustments also, even when the frame itself is small.
807 if (BigStack && !ExtraCSSpill) {
808 // If any non-reserved CS register isn't spilled, just spill one or two
809 // extra. That should take care of it!
810 unsigned NumExtras = TargetAlign / 4;
811 SmallVector<unsigned, 2> Extras;
812 while (NumExtras && !UnspilledCS1GPRs.empty()) {
813 unsigned Reg = UnspilledCS1GPRs.back();
814 UnspilledCS1GPRs.pop_back();
815 if (!isReservedReg(MF, Reg) &&
816 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
818 Extras.push_back(Reg);
822 // For non-Thumb1 functions, also check for hi-reg CS registers
823 if (!AFI->isThumb1OnlyFunction()) {
824 while (NumExtras && !UnspilledCS2GPRs.empty()) {
825 unsigned Reg = UnspilledCS2GPRs.back();
826 UnspilledCS2GPRs.pop_back();
827 if (!isReservedReg(MF, Reg)) {
828 Extras.push_back(Reg);
833 if (Extras.size() && NumExtras == 0) {
834 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
835 MF.getRegInfo().setPhysRegUsed(Extras[i]);
836 AFI->setCSRegisterIsSpilled(Extras[i]);
838 } else if (!AFI->isThumb1OnlyFunction()) {
839 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
840 // closest to SP or frame pointer.
841 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
842 MachineFrameInfo *MFI = MF.getFrameInfo();
843 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
851 MF.getRegInfo().setPhysRegUsed(ARM::LR);
852 AFI->setCSRegisterIsSpilled(ARM::LR);
853 AFI->setLRIsSpilledForFarJump(true);
857 unsigned ARMBaseRegisterInfo::getRARegister() const {
862 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
863 if (STI.isTargetDarwin() || hasFP(MF))
869 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
870 unsigned &FrameReg) const {
871 const MachineFrameInfo *MFI = MF.getFrameInfo();
872 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
873 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
874 bool isFixed = MFI->isFixedObjectIndex(FI);
877 if (AFI->isGPRCalleeSavedArea1Frame(FI))
878 Offset -= AFI->getGPRCalleeSavedArea1Offset();
879 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
880 Offset -= AFI->getGPRCalleeSavedArea2Offset();
881 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
882 Offset -= AFI->getDPRCalleeSavedAreaOffset();
883 else if (needsStackRealignment(MF)) {
884 // When dynamically realigning the stack, use the frame pointer for
885 // parameters, and the stack pointer for locals.
886 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
888 FrameReg = getFrameRegister(MF);
889 Offset -= AFI->getFramePtrSpillOffset();
891 } else if (hasFP(MF) && AFI->hasStackFrame()) {
892 if (isFixed || MFI->hasVarSizedObjects()) {
893 // Use frame pointer to reference fixed objects unless this is a
894 // frameless function.
895 FrameReg = getFrameRegister(MF);
896 Offset -= AFI->getFramePtrSpillOffset();
897 } else if (AFI->isThumb2Function()) {
898 // In Thumb2 mode, the negative offset is very limited.
899 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
900 if (FPOffset >= -255 && FPOffset < 0) {
901 FrameReg = getFrameRegister(MF);
911 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
914 return getFrameIndexReference(MF, FI, FrameReg);
917 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
918 llvm_unreachable("What is the exception register");
922 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
923 llvm_unreachable("What is the exception handler register");
927 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
928 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
931 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
932 const MachineFunction &MF) const {
935 // Return 0 if either register of the pair is a special register.
944 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
946 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
948 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1020 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1021 const MachineFunction &MF) const {
1024 // Return 0 if either register of the pair is a special register.
1033 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
1035 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1037 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1109 /// emitLoadConstPool - Emits a load from constpool to materialize the
1110 /// specified immediate.
1111 void ARMBaseRegisterInfo::
1112 emitLoadConstPool(MachineBasicBlock &MBB,
1113 MachineBasicBlock::iterator &MBBI,
1115 unsigned DestReg, unsigned SubIdx, int Val,
1116 ARMCC::CondCodes Pred,
1117 unsigned PredReg) const {
1118 MachineFunction &MF = *MBB.getParent();
1119 MachineConstantPool *ConstantPool = MF.getConstantPool();
1121 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1122 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1124 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1125 .addReg(DestReg, getDefRegState(true), SubIdx)
1126 .addConstantPoolIndex(Idx)
1127 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1130 bool ARMBaseRegisterInfo::
1131 requiresRegisterScavenging(const MachineFunction &MF) const {
1135 bool ARMBaseRegisterInfo::
1136 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1140 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1141 // not required, we reserve argument space for call sites in the function
1142 // immediately on entry to the current function. This eliminates the need for
1143 // add/sub sp brackets around call sites. Returns true if the call frame is
1144 // included as part of the stack frame.
1145 bool ARMBaseRegisterInfo::
1146 hasReservedCallFrame(MachineFunction &MF) const {
1147 const MachineFrameInfo *FFI = MF.getFrameInfo();
1148 unsigned CFSize = FFI->getMaxCallFrameSize();
1149 // It's not always a good idea to include the call frame as part of the
1150 // stack frame. ARM (especially Thumb) has small immediate offset to
1151 // address the stack frame. So a large call frame can cause poor codegen
1152 // and may even makes it impossible to scavenge a register.
1153 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1156 return !MF.getFrameInfo()->hasVarSizedObjects();
1159 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1160 // call frame pseudos can be simplified. Unlike most targets, having a FP
1161 // is not sufficient here since we still may reference some objects via SP
1162 // even when FP is available in Thumb2 mode.
1163 bool ARMBaseRegisterInfo::
1164 canSimplifyCallFramePseudos(MachineFunction &MF) const {
1165 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1169 emitSPUpdate(bool isARM,
1170 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1171 DebugLoc dl, const ARMBaseInstrInfo &TII,
1173 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1175 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1176 Pred, PredReg, TII);
1178 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1179 Pred, PredReg, TII);
1183 void ARMBaseRegisterInfo::
1184 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1185 MachineBasicBlock::iterator I) const {
1186 if (!hasReservedCallFrame(MF)) {
1187 // If we have alloca, convert as follows:
1188 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1189 // ADJCALLSTACKUP -> add, sp, sp, amount
1190 MachineInstr *Old = I;
1191 DebugLoc dl = Old->getDebugLoc();
1192 unsigned Amount = Old->getOperand(0).getImm();
1194 // We need to keep the stack aligned properly. To do this, we round the
1195 // amount of space needed for the outgoing arguments up to the next
1196 // alignment boundary.
1197 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1198 Amount = (Amount+Align-1)/Align*Align;
1200 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1201 assert(!AFI->isThumb1OnlyFunction() &&
1202 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1203 bool isARM = !AFI->isThumbFunction();
1205 // Replace the pseudo instruction with a new instruction...
1206 unsigned Opc = Old->getOpcode();
1207 int PIdx = Old->findFirstPredOperandIdx();
1208 ARMCC::CondCodes Pred = (PIdx == -1)
1209 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1210 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1211 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1212 unsigned PredReg = Old->getOperand(2).getReg();
1213 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1215 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1216 unsigned PredReg = Old->getOperand(3).getReg();
1217 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1218 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1226 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1227 int SPAdj, FrameIndexValue *Value,
1228 RegScavenger *RS) const {
1230 MachineInstr &MI = *II;
1231 MachineBasicBlock &MBB = *MI.getParent();
1232 MachineFunction &MF = *MBB.getParent();
1233 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1234 assert(!AFI->isThumb1OnlyFunction() &&
1235 "This eliminateFrameIndex does not support Thumb1!");
1237 while (!MI.getOperand(i).isFI()) {
1239 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1242 int FrameIndex = MI.getOperand(i).getIndex();
1245 int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1246 if (FrameReg != ARM::SP)
1250 // Special handling of dbg_value instructions.
1251 if (MI.isDebugValue()) {
1252 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1253 MI.getOperand(i+1).ChangeToImmediate(Offset);
1257 // Modify MI as necessary to handle as much of 'Offset' as possible
1259 if (!AFI->isThumbFunction())
1260 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1262 assert(AFI->isThumb2Function());
1263 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1268 // If we get here, the immediate doesn't fit into the instruction. We folded
1269 // as much as possible above, handle the rest, providing a register that is
1272 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1273 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1274 "This code isn't needed if offset already handled!");
1276 unsigned ScratchReg = 0;
1277 int PIdx = MI.findFirstPredOperandIdx();
1278 ARMCC::CondCodes Pred = (PIdx == -1)
1279 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1280 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1282 // Must be addrmode4/6.
1283 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1285 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1287 Value->first = FrameReg; // use the frame register as a kind indicator
1288 Value->second = Offset;
1290 if (!AFI->isThumbFunction())
1291 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1292 Offset, Pred, PredReg, TII);
1294 assert(AFI->isThumb2Function());
1295 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1296 Offset, Pred, PredReg, TII);
1298 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1299 if (!ReuseFrameIndexVals)
1305 /// Move iterator past the next bunch of callee save load / store ops for
1306 /// the particular spill area (1: integer area 1, 2: integer area 2,
1307 /// 3: fp area, 0: don't care).
1308 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1309 MachineBasicBlock::iterator &MBBI,
1310 int Opc1, int Opc2, unsigned Area,
1311 const ARMSubtarget &STI) {
1312 while (MBBI != MBB.end() &&
1313 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1314 MBBI->getOperand(1).isFI()) {
1317 unsigned Category = 0;
1318 switch (MBBI->getOperand(0).getReg()) {
1319 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1323 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1324 Category = STI.isTargetDarwin() ? 2 : 1;
1326 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1327 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1334 if (Done || Category != Area)
1342 void ARMBaseRegisterInfo::
1343 emitPrologue(MachineFunction &MF) const {
1344 MachineBasicBlock &MBB = MF.front();
1345 MachineBasicBlock::iterator MBBI = MBB.begin();
1346 MachineFrameInfo *MFI = MF.getFrameInfo();
1347 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1348 assert(!AFI->isThumb1OnlyFunction() &&
1349 "This emitPrologue does not support Thumb1!");
1350 bool isARM = !AFI->isThumbFunction();
1351 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1352 unsigned NumBytes = MFI->getStackSize();
1353 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1354 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1356 // Determine the sizes of each callee-save spill areas and record which frame
1357 // belongs to which callee-save spill areas.
1358 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1359 int FramePtrSpillFI = 0;
1361 // Allocate the vararg register save area. This is not counted in NumBytes.
1363 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1365 if (!AFI->hasStackFrame()) {
1367 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1371 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1372 unsigned Reg = CSI[i].getReg();
1373 int FI = CSI[i].getFrameIdx();
1380 if (Reg == FramePtr)
1381 FramePtrSpillFI = FI;
1382 AFI->addGPRCalleeSavedArea1Frame(FI);
1389 if (Reg == FramePtr)
1390 FramePtrSpillFI = FI;
1391 if (STI.isTargetDarwin()) {
1392 AFI->addGPRCalleeSavedArea2Frame(FI);
1395 AFI->addGPRCalleeSavedArea1Frame(FI);
1400 AFI->addDPRCalleeSavedAreaFrame(FI);
1405 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1406 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1407 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1409 // Set FP to point to the stack slot that contains the previous FP.
1410 // For Darwin, FP is R7, which has now been stored in spill area 1.
1411 // Otherwise, if this is not Darwin, all the callee-saved registers go
1412 // into spill area 1, including the FP in R11. In either case, it is
1413 // now safe to emit this assignment.
1414 if (STI.isTargetDarwin() || hasFP(MF)) {
1415 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1416 MachineInstrBuilder MIB =
1417 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1418 .addFrameIndex(FramePtrSpillFI).addImm(0);
1419 AddDefaultCC(AddDefaultPred(MIB));
1422 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1423 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1425 // Build the new SUBri to adjust SP for FP callee-save spill area.
1426 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1427 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1429 // Determine starting offsets of spill areas.
1430 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1431 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1432 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1433 if (STI.isTargetDarwin() || hasFP(MF))
1434 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1436 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1437 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1438 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1440 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1441 NumBytes = DPRCSOffset;
1443 // Adjust SP after all the callee-save spills.
1444 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1447 if (STI.isTargetELF() && hasFP(MF)) {
1448 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1449 AFI->getFramePtrSpillOffset());
1452 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1453 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1454 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1456 // If we need dynamic stack realignment, do it here.
1457 if (needsStackRealignment(MF)) {
1458 unsigned MaxAlign = MFI->getMaxAlignment();
1459 assert (!AFI->isThumb1OnlyFunction());
1460 if (!AFI->isThumbFunction()) {
1461 // Emit bic sp, sp, MaxAlign
1462 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1463 TII.get(ARM::BICri), ARM::SP)
1464 .addReg(ARM::SP, RegState::Kill)
1465 .addImm(MaxAlign-1)));
1467 // We cannot use sp as source/dest register here, thus we're emitting the
1468 // following sequence:
1470 // bic r4, r4, MaxAlign
1472 // FIXME: It will be better just to find spare register here.
1473 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1474 .addReg(ARM::SP, RegState::Kill);
1475 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1476 TII.get(ARM::t2BICri), ARM::R4)
1477 .addReg(ARM::R4, RegState::Kill)
1478 .addImm(MaxAlign-1)));
1479 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1480 .addReg(ARM::R4, RegState::Kill);
1485 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1486 for (unsigned i = 0; CSRegs[i]; ++i)
1487 if (Reg == CSRegs[i])
1492 static bool isCSRestore(MachineInstr *MI,
1493 const ARMBaseInstrInfo &TII,
1494 const unsigned *CSRegs) {
1495 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1496 MI->getOpcode() == (int)ARM::LDR ||
1497 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1498 MI->getOperand(1).isFI() &&
1499 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1502 void ARMBaseRegisterInfo::
1503 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1504 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1505 assert(MBBI->getDesc().isReturn() &&
1506 "Can only insert epilog into returning blocks");
1507 DebugLoc dl = MBBI->getDebugLoc();
1508 MachineFrameInfo *MFI = MF.getFrameInfo();
1509 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1510 assert(!AFI->isThumb1OnlyFunction() &&
1511 "This emitEpilogue does not support Thumb1!");
1512 bool isARM = !AFI->isThumbFunction();
1514 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1515 int NumBytes = (int)MFI->getStackSize();
1517 if (!AFI->hasStackFrame()) {
1519 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1521 // Unwind MBBI to point to first LDR / VLDRD.
1522 const unsigned *CSRegs = getCalleeSavedRegs();
1523 if (MBBI != MBB.begin()) {
1526 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1527 if (!isCSRestore(MBBI, TII, CSRegs))
1531 // Move SP to start of FP callee save spill area.
1532 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1533 AFI->getGPRCalleeSavedArea2Size() +
1534 AFI->getDPRCalleeSavedAreaSize());
1536 // Darwin ABI requires FP to point to the stack slot that contains the
1538 bool HasFP = hasFP(MF);
1539 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1540 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1541 // Reset SP based on frame pointer only if the stack frame extends beyond
1542 // frame pointer stack slot or target is ELF and the function has FP.
1544 AFI->getGPRCalleeSavedArea2Size() ||
1545 AFI->getDPRCalleeSavedAreaSize() ||
1546 AFI->getDPRCalleeSavedAreaOffset()) {
1549 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1552 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1557 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1559 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1561 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1565 } else if (NumBytes)
1566 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1568 // Move SP to start of integer callee save spill area 2.
1569 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1570 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1572 // Move SP to start of integer callee save spill area 1.
1573 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1574 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1576 // Move SP to SP upon entry to the function.
1577 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1578 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1582 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1585 #include "ARMGenRegisterInfo.inc"