1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMTargetObjectFile.h"
22 #include "InstPrinter/ARMInstPrinter.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "MCTargetDesc/ARMMCExpr.h"
25 #include "llvm/ADT/SetVector.h"
26 #include "llvm/ADT/SmallString.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/IR/Type.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCAssembler.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCInst.h"
41 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCObjectStreamer.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ARMBuildAttributes.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
61 std::unique_ptr<MCStreamer> Streamer)
62 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
63 InConstantPool(false) {}
65 void ARMAsmPrinter::EmitFunctionBodyEnd() {
66 // Make sure to terminate any constant pools that were at the end
70 InConstantPool = false;
71 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
74 void ARMAsmPrinter::EmitFunctionEntryLabel() {
75 if (AFI->isThumbFunction()) {
76 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
77 OutStreamer.EmitThumbFunc(CurrentFnSym);
80 OutStreamer.EmitLabel(CurrentFnSym);
83 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
84 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
85 assert(Size && "C++ constructor pointer had zero size!");
87 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
88 assert(GV && "C++ constructor pointer was not a GlobalValue!");
90 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
92 (Subtarget->isTargetELF()
93 ? MCSymbolRefExpr::VK_ARM_TARGET1
94 : MCSymbolRefExpr::VK_None),
97 OutStreamer.EmitValue(E, Size);
100 /// runOnMachineFunction - This uses the EmitInstruction()
101 /// method to print assembly for each instruction.
103 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
104 AFI = MF.getInfo<ARMFunctionInfo>();
105 MCP = MF.getConstantPool();
106 Subtarget = &MF.getSubtarget<ARMSubtarget>();
108 SetupMachineFunction(MF);
110 if (Subtarget->isTargetCOFF()) {
111 bool Internal = MF.getFunction()->hasInternalLinkage();
112 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
113 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
114 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
116 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
117 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
118 OutStreamer.EmitCOFFSymbolType(Type);
119 OutStreamer.EndCOFFSymbolDef();
122 // Have common code print out the function header with linkage info etc.
123 EmitFunctionHeader();
125 // Emit the rest of the function body.
128 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
129 // These are created per function, rather than per TU, since it's
130 // relatively easy to exceed the thumb branch range within a TU.
131 if (! ThumbIndirectPads.empty()) {
132 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
134 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
135 OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
136 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
137 .addReg(ThumbIndirectPads[i].first)
138 // Add predicate operands.
142 ThumbIndirectPads.clear();
145 // We didn't modify anything.
149 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
150 raw_ostream &O, const char *Modifier) {
151 const MachineOperand &MO = MI->getOperand(OpNum);
152 unsigned TF = MO.getTargetFlags();
154 switch (MO.getType()) {
155 default: llvm_unreachable("<unknown operand type>");
156 case MachineOperand::MO_Register: {
157 unsigned Reg = MO.getReg();
158 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
159 assert(!MO.getSubReg() && "Subregs should be eliminated!");
160 if(ARM::GPRPairRegClass.contains(Reg)) {
161 const MachineFunction &MF = *MI->getParent()->getParent();
162 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
163 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
165 O << ARMInstPrinter::getRegisterName(Reg);
168 case MachineOperand::MO_Immediate: {
169 int64_t Imm = MO.getImm();
171 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
172 (TF == ARMII::MO_LO16))
174 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
175 (TF == ARMII::MO_HI16))
180 case MachineOperand::MO_MachineBasicBlock:
181 O << *MO.getMBB()->getSymbol();
183 case MachineOperand::MO_GlobalAddress: {
184 const GlobalValue *GV = MO.getGlobal();
185 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
186 (TF & ARMII::MO_LO16))
188 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
189 (TF & ARMII::MO_HI16))
191 O << *GetARMGVSymbol(GV, TF);
193 printOffset(MO.getOffset(), O);
194 if (TF == ARMII::MO_PLT)
198 case MachineOperand::MO_ConstantPoolIndex:
199 O << *GetCPISymbol(MO.getIndex());
204 //===--------------------------------------------------------------------===//
206 MCSymbol *ARMAsmPrinter::
207 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
208 const DataLayout *DL = TM.getDataLayout();
209 SmallString<60> Name;
210 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
211 << getFunctionNumber() << '_' << uid << '_' << uid2;
212 return OutContext.GetOrCreateSymbol(Name.str());
216 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
217 const DataLayout *DL = TM.getDataLayout();
218 SmallString<60> Name;
219 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
220 << getFunctionNumber();
221 return OutContext.GetOrCreateSymbol(Name.str());
224 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
225 unsigned AsmVariant, const char *ExtraCode,
227 // Does this asm operand have a single letter operand modifier?
228 if (ExtraCode && ExtraCode[0]) {
229 if (ExtraCode[1] != 0) return true; // Unknown modifier.
231 switch (ExtraCode[0]) {
233 // See if this is a generic print operand
234 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
235 case 'a': // Print as a memory address.
236 if (MI->getOperand(OpNum).isReg()) {
238 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
243 case 'c': // Don't print "#" before an immediate operand.
244 if (!MI->getOperand(OpNum).isImm())
246 O << MI->getOperand(OpNum).getImm();
248 case 'P': // Print a VFP double precision register.
249 case 'q': // Print a NEON quad precision register.
250 printOperand(MI, OpNum, O);
252 case 'y': // Print a VFP single precision register as indexed double.
253 if (MI->getOperand(OpNum).isReg()) {
254 unsigned Reg = MI->getOperand(OpNum).getReg();
255 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
256 // Find the 'd' register that has this 's' register as a sub-register,
257 // and determine the lane number.
258 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
259 if (!ARM::DPRRegClass.contains(*SR))
261 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
262 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
267 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
268 if (!MI->getOperand(OpNum).isImm())
270 O << ~(MI->getOperand(OpNum).getImm());
272 case 'L': // The low 16 bits of an immediate constant.
273 if (!MI->getOperand(OpNum).isImm())
275 O << (MI->getOperand(OpNum).getImm() & 0xffff);
277 case 'M': { // A register range suitable for LDM/STM.
278 if (!MI->getOperand(OpNum).isReg())
280 const MachineOperand &MO = MI->getOperand(OpNum);
281 unsigned RegBegin = MO.getReg();
282 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
283 // already got the operands in registers that are operands to the
284 // inline asm statement.
286 if (ARM::GPRPairRegClass.contains(RegBegin)) {
287 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
288 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
289 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
290 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
292 O << ARMInstPrinter::getRegisterName(RegBegin);
294 // FIXME: The register allocator not only may not have given us the
295 // registers in sequence, but may not be in ascending registers. This
296 // will require changes in the register allocator that'll need to be
297 // propagated down here if the operands change.
298 unsigned RegOps = OpNum + 1;
299 while (MI->getOperand(RegOps).isReg()) {
301 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
309 case 'R': // The most significant register of a pair.
310 case 'Q': { // The least significant register of a pair.
313 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
314 if (!FlagsOP.isImm())
316 unsigned Flags = FlagsOP.getImm();
318 // This operand may not be the one that actually provides the register. If
319 // it's tied to a previous one then we should refer instead to that one
320 // for registers and their classes.
322 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
323 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
324 unsigned OpFlags = MI->getOperand(OpNum).getImm();
325 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
327 Flags = MI->getOperand(OpNum).getImm();
329 // Later code expects OpNum to be pointing at the register rather than
334 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
336 InlineAsm::hasRegClassConstraint(Flags, RC);
337 if (RC == ARM::GPRPairRegClassID) {
340 const MachineOperand &MO = MI->getOperand(OpNum);
343 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
344 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
345 ARM::gsub_0 : ARM::gsub_1);
346 O << ARMInstPrinter::getRegisterName(Reg);
351 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
352 if (RegOp >= MI->getNumOperands())
354 const MachineOperand &MO = MI->getOperand(RegOp);
357 unsigned Reg = MO.getReg();
358 O << ARMInstPrinter::getRegisterName(Reg);
362 case 'e': // The low doubleword register of a NEON quad register.
363 case 'f': { // The high doubleword register of a NEON quad register.
364 if (!MI->getOperand(OpNum).isReg())
366 unsigned Reg = MI->getOperand(OpNum).getReg();
367 if (!ARM::QPRRegClass.contains(Reg))
369 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
370 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
371 ARM::dsub_0 : ARM::dsub_1);
372 O << ARMInstPrinter::getRegisterName(SubReg);
376 // This modifier is not yet supported.
377 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
379 case 'H': { // The highest-numbered register of a pair.
380 const MachineOperand &MO = MI->getOperand(OpNum);
383 const MachineFunction &MF = *MI->getParent()->getParent();
384 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
385 unsigned Reg = MO.getReg();
386 if(!ARM::GPRPairRegClass.contains(Reg))
388 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
389 O << ARMInstPrinter::getRegisterName(Reg);
395 printOperand(MI, OpNum, O);
399 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
400 unsigned OpNum, unsigned AsmVariant,
401 const char *ExtraCode,
403 // Does this asm operand have a single letter operand modifier?
404 if (ExtraCode && ExtraCode[0]) {
405 if (ExtraCode[1] != 0) return true; // Unknown modifier.
407 switch (ExtraCode[0]) {
408 case 'A': // A memory operand for a VLD1/VST1 instruction.
409 default: return true; // Unknown modifier.
410 case 'm': // The base register of a memory operand.
411 if (!MI->getOperand(OpNum).isReg())
413 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
418 const MachineOperand &MO = MI->getOperand(OpNum);
419 assert(MO.isReg() && "unexpected inline asm memory operand");
420 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
424 static bool isThumb(const MCSubtargetInfo& STI) {
425 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
428 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
429 const MCSubtargetInfo *EndInfo) const {
430 // If either end mode is unknown (EndInfo == NULL) or different than
431 // the start mode, then restore the start mode.
432 const bool WasThumb = isThumb(StartInfo);
433 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
434 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
438 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
439 Triple TT(TM.getTargetTriple());
440 if (TT.isOSBinFormatMachO()) {
441 Reloc::Model RelocM = TM.getRelocationModel();
442 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
443 // Declare all the text sections up front (before the DWARF sections
444 // emitted by AsmPrinter::doInitialization) so the assembler will keep
445 // them together at the beginning of the object file. This helps
446 // avoid out-of-range branches that are due a fundamental limitation of
447 // the way symbol offsets are encoded with the current Darwin ARM
449 const TargetLoweringObjectFileMachO &TLOFMacho =
450 static_cast<const TargetLoweringObjectFileMachO &>(
451 getObjFileLowering());
453 // Collect the set of sections our functions will go into.
454 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
455 SmallPtrSet<const MCSection *, 8> > TextSections;
456 // Default text section comes first.
457 TextSections.insert(TLOFMacho.getTextSection());
458 // Now any user defined text sections from function attributes.
459 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
460 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
461 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
462 // Now the coalescable sections.
463 TextSections.insert(TLOFMacho.getTextCoalSection());
464 TextSections.insert(TLOFMacho.getConstTextCoalSection());
466 // Emit the sections in the .s file header to fix the order.
467 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
468 OutStreamer.SwitchSection(TextSections[i]);
470 if (RelocM == Reloc::DynamicNoPIC) {
471 const MCSection *sect =
472 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
473 MachO::S_SYMBOL_STUBS,
474 12, SectionKind::getText());
475 OutStreamer.SwitchSection(sect);
477 const MCSection *sect =
478 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
479 MachO::S_SYMBOL_STUBS,
480 16, SectionKind::getText());
481 OutStreamer.SwitchSection(sect);
483 const MCSection *StaticInitSect =
484 OutContext.getMachOSection("__TEXT", "__StaticInit",
486 MachO::S_ATTR_PURE_INSTRUCTIONS,
487 SectionKind::getText());
488 OutStreamer.SwitchSection(StaticInitSect);
491 // Compiling with debug info should not affect the code
492 // generation. Ensure the cstring section comes before the
493 // optional __DWARF secion. Otherwise, PC-relative loads would
494 // have to use different instruction sequences at "-g" in order to
495 // reach global data in the same object file.
496 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
499 // Use unified assembler syntax.
500 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
502 // Emit ARM Build Attributes
503 if (TT.isOSBinFormatELF())
506 // Use the triple's architecture and subarchitecture to determine
507 // if we're thumb for the purposes of the top level code16 assembler
509 bool isThumb = TT.getArch() == Triple::thumb ||
510 TT.getArch() == Triple::thumbeb ||
511 TT.getSubArch() == Triple::ARMSubArch_v7m ||
512 TT.getSubArch() == Triple::ARMSubArch_v6m;
513 if (!M.getModuleInlineAsm().empty() && isThumb)
514 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
518 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
519 MachineModuleInfoImpl::StubValueTy &MCSym) {
521 OutStreamer.EmitLabel(StubLabel);
522 // .indirect_symbol _foo
523 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
526 // External to current translation unit.
527 OutStreamer.EmitIntValue(0, 4/*size*/);
529 // Internal to current translation unit.
531 // When we place the LSDA into the TEXT section, the type info
532 // pointers need to be indirect and pc-rel. We accomplish this by
533 // using NLPs; however, sometimes the types are local to the file.
534 // We need to fill in the value for the NLP in those cases.
535 OutStreamer.EmitValue(
536 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
541 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
542 Triple TT(TM.getTargetTriple());
543 if (TT.isOSBinFormatMachO()) {
544 // All darwin targets use mach-o.
545 const TargetLoweringObjectFileMachO &TLOFMacho =
546 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
547 MachineModuleInfoMachO &MMIMacho =
548 MMI->getObjFileInfo<MachineModuleInfoMachO>();
550 // Output non-lazy-pointers for external and common global variables.
551 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
553 if (!Stubs.empty()) {
554 // Switch with ".non_lazy_symbol_pointer" directive.
555 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
558 for (auto &Stub : Stubs)
559 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
562 OutStreamer.AddBlankLine();
565 Stubs = MMIMacho.GetHiddenGVStubList();
566 if (!Stubs.empty()) {
567 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
570 for (auto &Stub : Stubs)
571 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
574 OutStreamer.AddBlankLine();
577 // Funny Darwin hack: This flag tells the linker that no global symbols
578 // contain code that falls through to other global symbols (e.g. the obvious
579 // implementation of multiple entry points). If this doesn't occur, the
580 // linker can safely perform dead code stripping. Since LLVM never
581 // generates code that does this, it is always safe to set.
582 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
585 // Emit a .data.rel section containing any stubs that were created.
586 if (TT.isOSBinFormatELF()) {
587 const TargetLoweringObjectFileELF &TLOFELF =
588 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
590 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
592 // Output stubs for external and common global variables.
593 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
594 if (!Stubs.empty()) {
595 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
596 const DataLayout *TD = TM.getDataLayout();
598 for (auto &stub: Stubs) {
599 OutStreamer.EmitLabel(stub.first);
600 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
601 TD->getPointerSize(0));
608 //===----------------------------------------------------------------------===//
609 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
611 // The following seem like one-off assembler flags, but they actually need
612 // to appear in the .ARM.attributes section in ELF.
613 // Instead of subclassing the MCELFStreamer, we do the work here.
615 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
616 const ARMSubtarget *Subtarget) {
618 return ARMBuildAttrs::v5TEJ;
620 if (Subtarget->hasV8Ops())
621 return ARMBuildAttrs::v8;
622 else if (Subtarget->hasV7Ops()) {
623 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
624 return ARMBuildAttrs::v7E_M;
625 return ARMBuildAttrs::v7;
626 } else if (Subtarget->hasV6T2Ops())
627 return ARMBuildAttrs::v6T2;
628 else if (Subtarget->hasV6MOps())
629 return ARMBuildAttrs::v6S_M;
630 else if (Subtarget->hasV6Ops())
631 return ARMBuildAttrs::v6;
632 else if (Subtarget->hasV5TEOps())
633 return ARMBuildAttrs::v5TE;
634 else if (Subtarget->hasV5TOps())
635 return ARMBuildAttrs::v5T;
636 else if (Subtarget->hasV4TOps())
637 return ARMBuildAttrs::v4T;
639 return ARMBuildAttrs::v4;
642 void ARMAsmPrinter::emitAttributes() {
643 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
644 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
646 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
648 ATS.switchVendor("aeabi");
650 // Compute ARM ELF Attributes based on the default subtarget that
651 // we'd have constructed. The existing ARM behavior isn't LTO clean
653 // FIXME: For ifunc related functions we could iterate over and look
654 // for a feature string that doesn't match the default one.
655 StringRef TT = TM.getTargetTriple();
656 StringRef CPU = TM.getTargetCPU();
657 StringRef FS = TM.getTargetFeatureString();
658 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
661 ArchFS = ArchFS + "," + FS.str();
665 const ARMBaseTargetMachine &ATM =
666 static_cast<const ARMBaseTargetMachine &>(TM);
667 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
669 std::string CPUString = STI.getCPUString();
671 // FIXME: remove krait check when GNU tools support krait cpu
672 if (CPUString != "generic" && CPUString != "krait")
673 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
675 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
677 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
678 // profile is not applicable (e.g. pre v7, or cross-profile code)".
679 if (STI.hasV7Ops()) {
680 if (STI.isAClass()) {
681 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
682 ARMBuildAttrs::ApplicationProfile);
683 } else if (STI.isRClass()) {
684 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
685 ARMBuildAttrs::RealTimeProfile);
686 } else if (STI.isMClass()) {
687 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
688 ARMBuildAttrs::MicroControllerProfile);
692 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
693 STI.hasARMOps() ? ARMBuildAttrs::Allowed
694 : ARMBuildAttrs::Not_Allowed);
695 if (STI.isThumb1Only()) {
696 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
697 } else if (STI.hasThumb2()) {
698 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
699 ARMBuildAttrs::AllowThumb32);
703 /* NEON is not exactly a VFP architecture, but GAS emit one of
704 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
705 if (STI.hasFPARMv8()) {
707 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
709 ATS.emitFPU(ARM::NEON_FP_ARMV8);
710 } else if (STI.hasVFP4())
711 ATS.emitFPU(ARM::NEON_VFPV4);
713 ATS.emitFPU(ARM::NEON);
714 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
716 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
717 ARMBuildAttrs::AllowNeonARMv8);
719 if (STI.hasFPARMv8())
720 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
721 // FPU, but there are two different names for it depending on the CPU.
722 ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
723 else if (STI.hasVFP4())
724 ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
725 else if (STI.hasVFP3())
726 ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
727 else if (STI.hasVFP2())
728 ATS.emitFPU(ARM::VFPV2);
731 if (TM.getRelocationModel() == Reloc::PIC_) {
732 // PIC specific attributes.
733 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
734 ARMBuildAttrs::AddressRWPCRel);
735 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
736 ARMBuildAttrs::AddressROPCRel);
737 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
738 ARMBuildAttrs::AddressGOT);
740 // Allow direct addressing of imported data for all other relocation models.
741 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
742 ARMBuildAttrs::AddressDirect);
745 // Signal various FP modes.
746 if (!TM.Options.UnsafeFPMath) {
747 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
748 ARMBuildAttrs::IEEEDenormals);
749 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
751 // If the user has permitted this code to choose the IEEE 754
752 // rounding at run-time, emit the rounding attribute.
753 if (TM.Options.HonorSignDependentRoundingFPMathOption)
754 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
756 if (!STI.hasVFP2()) {
757 // When the target doesn't have an FPU (by design or
758 // intention), the assumptions made on the software support
759 // mirror that of the equivalent hardware support *if it
760 // existed*. For v7 and better we indicate that denormals are
761 // flushed preserving sign, and for V6 we indicate that
762 // denormals are flushed to positive zero.
764 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
765 ARMBuildAttrs::PreserveFPSign);
766 } else if (STI.hasVFP3()) {
767 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
768 // the sign bit of the zero matches the sign bit of the input or
769 // result that is being flushed to zero.
770 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
771 ARMBuildAttrs::PreserveFPSign);
773 // For VFPv2 implementations it is implementation defined as
774 // to whether denormals are flushed to positive zero or to
775 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
776 // LLVM has chosen to flush this to positive zero (most likely for
777 // GCC compatibility), so that's the chosen value here (the
778 // absence of its emission implies zero).
781 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
782 // equivalent of GCC's -ffinite-math-only flag.
783 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
784 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
785 ARMBuildAttrs::Allowed);
787 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
788 ARMBuildAttrs::AllowIEE754);
790 if (STI.allowsUnalignedMem())
791 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
792 ARMBuildAttrs::Allowed);
794 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
795 ARMBuildAttrs::Not_Allowed);
797 // FIXME: add more flags to ARMBuildAttributes.h
798 // 8-bytes alignment stuff.
799 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
800 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
802 // ABI_HardFP_use attribute to indicate single precision FP.
803 if (STI.isFPOnlySP())
804 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
805 ARMBuildAttrs::HardFPSinglePrecision);
807 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
808 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
809 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
811 // FIXME: Should we signal R9 usage?
814 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
816 // FIXME: To support emitting this build attribute as GCC does, the
817 // -mfp16-format option and associated plumbing must be
818 // supported. For now the __fp16 type is exposed by default, so this
819 // attribute should be emitted with value 1.
820 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
821 ARMBuildAttrs::FP16FormatIEEE);
823 if (STI.hasMPExtension())
824 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
826 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
827 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
828 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
829 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
830 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
831 // otherwise, the default value (AllowDIVIfExists) applies.
832 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
833 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
836 if (const Module *SourceModule = MMI->getModule()) {
837 // ABI_PCS_wchar_t to indicate wchar_t width
838 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
839 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
840 SourceModule->getModuleFlag("wchar_size"))) {
841 int WCharWidth = WCharWidthValue->getZExtValue();
842 assert((WCharWidth == 2 || WCharWidth == 4) &&
843 "wchar_t width must be 2 or 4 bytes");
844 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
847 // ABI_enum_size to indicate enum width
848 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
849 // (all enums contain a value needing 32 bits to encode).
850 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
851 SourceModule->getModuleFlag("min_enum_size"))) {
852 int EnumWidth = EnumWidthValue->getZExtValue();
853 assert((EnumWidth == 1 || EnumWidth == 4) &&
854 "Minimum enum width must be 1 or 4 bytes");
855 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
856 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
861 // TODO: We currently only support either reserving the register, or treating
862 // it as another callee-saved register, but not as SB or a TLS pointer; It
863 // would instead be nicer to push this from the frontend as metadata, as we do
864 // for the wchar and enum size tags
865 if (STI.isR9Reserved())
866 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
868 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
870 if (STI.hasTrustZone() && STI.hasVirtualization())
871 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
872 ARMBuildAttrs::AllowTZVirtualization);
873 else if (STI.hasTrustZone())
874 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
875 ARMBuildAttrs::AllowTZ);
876 else if (STI.hasVirtualization())
877 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
878 ARMBuildAttrs::AllowVirtualization);
880 ATS.finishAttributeSection();
883 //===----------------------------------------------------------------------===//
885 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
886 unsigned LabelId, MCContext &Ctx) {
888 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
889 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
893 static MCSymbolRefExpr::VariantKind
894 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
896 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
897 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
898 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
899 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
900 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
901 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
903 llvm_unreachable("Invalid ARMCPModifier!");
906 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
907 unsigned char TargetFlags) {
908 if (Subtarget->isTargetMachO()) {
909 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
910 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
913 return getSymbol(GV);
915 // FIXME: Remove this when Darwin transition to @GOT like syntax.
916 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
917 MachineModuleInfoMachO &MMIMachO =
918 MMI->getObjFileInfo<MachineModuleInfoMachO>();
919 MachineModuleInfoImpl::StubValueTy &StubSym =
920 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
921 : MMIMachO.getGVStubEntry(MCSym);
922 if (!StubSym.getPointer())
923 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
924 !GV->hasInternalLinkage());
926 } else if (Subtarget->isTargetCOFF()) {
927 assert(Subtarget->isTargetWindows() &&
928 "Windows is the only supported COFF target");
930 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
932 return getSymbol(GV);
934 SmallString<128> Name;
936 getNameWithPrefix(Name, GV);
938 return OutContext.GetOrCreateSymbol(Name);
939 } else if (Subtarget->isTargetELF()) {
940 return getSymbol(GV);
942 llvm_unreachable("unexpected target");
946 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
947 const DataLayout *DL = TM.getDataLayout();
948 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
950 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
953 if (ACPV->isLSDA()) {
954 SmallString<128> Str;
955 raw_svector_ostream OS(Str);
956 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
957 MCSym = OutContext.GetOrCreateSymbol(OS.str());
958 } else if (ACPV->isBlockAddress()) {
959 const BlockAddress *BA =
960 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
961 MCSym = GetBlockAddressSymbol(BA);
962 } else if (ACPV->isGlobalValue()) {
963 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
965 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
966 // flag the global as MO_NONLAZY.
967 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
968 MCSym = GetARMGVSymbol(GV, TF);
969 } else if (ACPV->isMachineBasicBlock()) {
970 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
971 MCSym = MBB->getSymbol();
973 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
974 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
975 MCSym = GetExternalSymbolSymbol(Sym);
978 // Create an MCSymbol for the reference.
980 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
983 if (ACPV->getPCAdjustment()) {
984 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
988 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
990 MCBinaryExpr::CreateAdd(PCRelExpr,
991 MCConstantExpr::Create(ACPV->getPCAdjustment(),
994 if (ACPV->mustAddCurrentAddress()) {
995 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
996 // label, so just emit a local label end reference that instead.
997 MCSymbol *DotSym = OutContext.CreateTempSymbol();
998 OutStreamer.EmitLabel(DotSym);
999 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1000 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
1002 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
1004 OutStreamer.EmitValue(Expr, Size);
1007 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
1008 unsigned Opcode = MI->getOpcode();
1010 if (Opcode == ARM::BR_JTadd)
1012 else if (Opcode == ARM::BR_JTm)
1015 const MachineOperand &MO1 = MI->getOperand(OpNum);
1016 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1017 unsigned JTI = MO1.getIndex();
1019 // Emit a label for the jump table.
1020 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1021 OutStreamer.EmitLabel(JTISymbol);
1023 // Mark the jump table as data-in-code.
1024 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
1026 // Emit each entry of the table.
1027 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1028 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1029 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1031 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1032 MachineBasicBlock *MBB = JTBBs[i];
1033 // Construct an MCExpr for the entry. We want a value of the form:
1034 // (BasicBlockAddr - TableBeginAddr)
1036 // For example, a table with entries jumping to basic blocks BB0 and BB1
1039 // .word (LBB0 - LJTI_0_0)
1040 // .word (LBB1 - LJTI_0_0)
1041 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1043 if (TM.getRelocationModel() == Reloc::PIC_)
1044 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1047 // If we're generating a table of Thumb addresses in static relocation
1048 // model, we need to add one to keep interworking correctly.
1049 else if (AFI->isThumbFunction())
1050 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1052 OutStreamer.EmitValue(Expr, 4);
1054 // Mark the end of jump table data-in-code region.
1055 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1058 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1059 unsigned Opcode = MI->getOpcode();
1060 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1061 const MachineOperand &MO1 = MI->getOperand(OpNum);
1062 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1063 unsigned JTI = MO1.getIndex();
1065 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1066 OutStreamer.EmitLabel(JTISymbol);
1068 // Emit each entry of the table.
1069 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1070 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1071 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1072 unsigned OffsetWidth = 4;
1073 if (MI->getOpcode() == ARM::t2TBB_JT) {
1075 // Mark the jump table as data-in-code.
1076 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1077 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1079 // Mark the jump table as data-in-code.
1080 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1083 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1084 MachineBasicBlock *MBB = JTBBs[i];
1085 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1087 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1088 if (OffsetWidth == 4) {
1089 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
1090 .addExpr(MBBSymbolExpr)
1095 // Otherwise it's an offset from the dispatch instruction. Construct an
1096 // MCExpr for the entry. We want a value of the form:
1097 // (BasicBlockAddr - TableBeginAddr) / 2
1099 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1102 // .byte (LBB0 - LJTI_0_0) / 2
1103 // .byte (LBB1 - LJTI_0_0) / 2
1104 const MCExpr *Expr =
1105 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1106 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1108 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1110 OutStreamer.EmitValue(Expr, OffsetWidth);
1112 // Mark the end of jump table data-in-code region. 32-bit offsets use
1113 // actual branch instructions here, so we don't mark those as a data-region
1115 if (OffsetWidth != 4)
1116 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1119 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1120 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1121 "Only instruction which are involved into frame setup code are allowed");
1123 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
1124 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1125 const MachineFunction &MF = *MI->getParent()->getParent();
1126 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1127 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1129 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1130 unsigned Opc = MI->getOpcode();
1131 unsigned SrcReg, DstReg;
1133 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1134 // Two special cases:
1135 // 1) tPUSH does not have src/dst regs.
1136 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1137 // load. Yes, this is pretty fragile, but for now I don't see better
1139 SrcReg = DstReg = ARM::SP;
1141 SrcReg = MI->getOperand(1).getReg();
1142 DstReg = MI->getOperand(0).getReg();
1145 // Try to figure out the unwinding opcode out of src / dst regs.
1146 if (MI->mayStore()) {
1148 assert(DstReg == ARM::SP &&
1149 "Only stack pointer as a destination reg is supported");
1151 SmallVector<unsigned, 4> RegList;
1152 // Skip src & dst reg, and pred ops.
1153 unsigned StartOp = 2 + 2;
1154 // Use all the operands.
1155 unsigned NumOffset = 0;
1160 llvm_unreachable("Unsupported opcode for unwinding information");
1162 // Special case here: no src & dst reg, but two extra imp ops.
1163 StartOp = 2; NumOffset = 2;
1164 case ARM::STMDB_UPD:
1165 case ARM::t2STMDB_UPD:
1166 case ARM::VSTMDDB_UPD:
1167 assert(SrcReg == ARM::SP &&
1168 "Only stack pointer as a source reg is supported");
1169 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1171 const MachineOperand &MO = MI->getOperand(i);
1172 // Actually, there should never be any impdef stuff here. Skip it
1173 // temporary to workaround PR11902.
1174 if (MO.isImplicit())
1176 RegList.push_back(MO.getReg());
1179 case ARM::STR_PRE_IMM:
1180 case ARM::STR_PRE_REG:
1181 case ARM::t2STR_PRE:
1182 assert(MI->getOperand(2).getReg() == ARM::SP &&
1183 "Only stack pointer as a source reg is supported");
1184 RegList.push_back(SrcReg);
1187 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1188 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1190 // Changes of stack / frame pointer.
1191 if (SrcReg == ARM::SP) {
1196 llvm_unreachable("Unsupported opcode for unwinding information");
1202 Offset = -MI->getOperand(2).getImm();
1206 Offset = MI->getOperand(2).getImm();
1209 Offset = MI->getOperand(2).getImm()*4;
1213 Offset = -MI->getOperand(2).getImm()*4;
1215 case ARM::tLDRpci: {
1216 // Grab the constpool index and check, whether it corresponds to
1217 // original or cloned constpool entry.
1218 unsigned CPI = MI->getOperand(1).getIndex();
1219 const MachineConstantPool *MCP = MF.getConstantPool();
1220 if (CPI >= MCP->getConstants().size())
1221 CPI = AFI.getOriginalCPIdx(CPI);
1222 assert(CPI != -1U && "Invalid constpool index");
1224 // Derive the actual offset.
1225 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1226 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1227 // FIXME: Check for user, it should be "add" instruction!
1228 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1233 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1234 if (DstReg == FramePtr && FramePtr != ARM::SP)
1235 // Set-up of the frame pointer. Positive values correspond to "add"
1237 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1238 else if (DstReg == ARM::SP) {
1239 // Change of SP by an offset. Positive values correspond to "sub"
1241 ATS.emitPad(Offset);
1243 // Move of SP to a register. Positive values correspond to an "add"
1245 ATS.emitMovSP(DstReg, -Offset);
1248 } else if (DstReg == ARM::SP) {
1250 llvm_unreachable("Unsupported opcode for unwinding information");
1254 llvm_unreachable("Unsupported opcode for unwinding information");
1259 // Simple pseudo-instructions have their lowering (with expansion to real
1260 // instructions) auto-generated.
1261 #include "ARMGenMCPseudoLowering.inc"
1263 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1264 const DataLayout *DL = TM.getDataLayout();
1266 // If we just ended a constant pool, mark it as such.
1267 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1268 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1269 InConstantPool = false;
1272 // Emit unwinding stuff for frame-related instructions
1273 if (Subtarget->isTargetEHABICompatible() &&
1274 MI->getFlag(MachineInstr::FrameSetup))
1275 EmitUnwindingInstruction(MI);
1277 // Do any auto-generated pseudo lowerings.
1278 if (emitPseudoExpansionLowering(OutStreamer, MI))
1281 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1282 "Pseudo flag setting opcode should be expanded early");
1284 // Check for manual lowerings.
1285 unsigned Opc = MI->getOpcode();
1287 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1288 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1290 case ARM::tLEApcrel:
1291 case ARM::t2LEApcrel: {
1292 // FIXME: Need to also handle globals and externals
1293 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1294 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1295 ARM::t2LEApcrel ? ARM::t2ADR
1296 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1298 .addReg(MI->getOperand(0).getReg())
1299 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1300 // Add predicate operands.
1301 .addImm(MI->getOperand(2).getImm())
1302 .addReg(MI->getOperand(3).getReg()));
1305 case ARM::LEApcrelJT:
1306 case ARM::tLEApcrelJT:
1307 case ARM::t2LEApcrelJT: {
1308 MCSymbol *JTIPICSymbol =
1309 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1310 MI->getOperand(2).getImm());
1311 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1312 ARM::t2LEApcrelJT ? ARM::t2ADR
1313 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1315 .addReg(MI->getOperand(0).getReg())
1316 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1317 // Add predicate operands.
1318 .addImm(MI->getOperand(3).getImm())
1319 .addReg(MI->getOperand(4).getReg()));
1322 // Darwin call instructions are just normal call instructions with different
1323 // clobber semantics (they clobber R9).
1324 case ARM::BX_CALL: {
1325 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1328 // Add predicate operands.
1331 // Add 's' bit operand (always reg0 for this)
1334 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1335 .addReg(MI->getOperand(0).getReg()));
1338 case ARM::tBX_CALL: {
1339 if (Subtarget->hasV5TOps())
1340 llvm_unreachable("Expected BLX to be selected for v5t+");
1342 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1343 // that the saved lr has its LSB set correctly (the arch doesn't
1345 // So here we generate a bl to a small jump pad that does bx rN.
1346 // The jump pads are emitted after the function body.
1348 unsigned TReg = MI->getOperand(0).getReg();
1349 MCSymbol *TRegSym = nullptr;
1350 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1351 if (ThumbIndirectPads[i].first == TReg) {
1352 TRegSym = ThumbIndirectPads[i].second;
1358 TRegSym = OutContext.CreateTempSymbol();
1359 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1362 // Create a link-saving branch to the Reg Indirect Jump Pad.
1363 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
1364 // Predicate comes first here.
1365 .addImm(ARMCC::AL).addReg(0)
1366 .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
1369 case ARM::BMOVPCRX_CALL: {
1370 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1373 // Add predicate operands.
1376 // Add 's' bit operand (always reg0 for this)
1379 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1381 .addReg(MI->getOperand(0).getReg())
1382 // Add predicate operands.
1385 // Add 's' bit operand (always reg0 for this)
1389 case ARM::BMOVPCB_CALL: {
1390 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1393 // Add predicate operands.
1396 // Add 's' bit operand (always reg0 for this)
1399 const MachineOperand &Op = MI->getOperand(0);
1400 const GlobalValue *GV = Op.getGlobal();
1401 const unsigned TF = Op.getTargetFlags();
1402 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1403 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1404 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1406 // Add predicate operands.
1411 case ARM::MOVi16_ga_pcrel:
1412 case ARM::t2MOVi16_ga_pcrel: {
1414 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1415 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1417 unsigned TF = MI->getOperand(1).getTargetFlags();
1418 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1419 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1420 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1422 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1423 getFunctionNumber(),
1424 MI->getOperand(2).getImm(), OutContext);
1425 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1426 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1427 const MCExpr *PCRelExpr =
1428 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1429 MCBinaryExpr::CreateAdd(LabelSymExpr,
1430 MCConstantExpr::Create(PCAdj, OutContext),
1431 OutContext), OutContext), OutContext);
1432 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1434 // Add predicate operands.
1435 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1436 TmpInst.addOperand(MCOperand::CreateReg(0));
1437 // Add 's' bit operand (always reg0 for this)
1438 TmpInst.addOperand(MCOperand::CreateReg(0));
1439 EmitToStreamer(OutStreamer, TmpInst);
1442 case ARM::MOVTi16_ga_pcrel:
1443 case ARM::t2MOVTi16_ga_pcrel: {
1445 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1446 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1447 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1448 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1450 unsigned TF = MI->getOperand(2).getTargetFlags();
1451 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1452 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1453 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1455 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1456 getFunctionNumber(),
1457 MI->getOperand(3).getImm(), OutContext);
1458 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1459 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1460 const MCExpr *PCRelExpr =
1461 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1462 MCBinaryExpr::CreateAdd(LabelSymExpr,
1463 MCConstantExpr::Create(PCAdj, OutContext),
1464 OutContext), OutContext), OutContext);
1465 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1466 // Add predicate operands.
1467 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1468 TmpInst.addOperand(MCOperand::CreateReg(0));
1469 // Add 's' bit operand (always reg0 for this)
1470 TmpInst.addOperand(MCOperand::CreateReg(0));
1471 EmitToStreamer(OutStreamer, TmpInst);
1474 case ARM::tPICADD: {
1475 // This is a pseudo op for a label + instruction sequence, which looks like:
1478 // This adds the address of LPC0 to r0.
1481 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1482 getFunctionNumber(), MI->getOperand(2).getImm(),
1485 // Form and emit the add.
1486 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1487 .addReg(MI->getOperand(0).getReg())
1488 .addReg(MI->getOperand(0).getReg())
1490 // Add predicate operands.
1496 // This is a pseudo op for a label + instruction sequence, which looks like:
1499 // This adds the address of LPC0 to r0.
1502 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1503 getFunctionNumber(), MI->getOperand(2).getImm(),
1506 // Form and emit the add.
1507 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1508 .addReg(MI->getOperand(0).getReg())
1510 .addReg(MI->getOperand(1).getReg())
1511 // Add predicate operands.
1512 .addImm(MI->getOperand(3).getImm())
1513 .addReg(MI->getOperand(4).getReg())
1514 // Add 's' bit operand (always reg0 for this)
1525 case ARM::PICLDRSH: {
1526 // This is a pseudo op for a label + instruction sequence, which looks like:
1529 // The LCP0 label is referenced by a constant pool entry in order to get
1530 // a PC-relative address at the ldr instruction.
1533 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1534 getFunctionNumber(), MI->getOperand(2).getImm(),
1537 // Form and emit the load
1539 switch (MI->getOpcode()) {
1541 llvm_unreachable("Unexpected opcode!");
1542 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1543 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1544 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1545 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1546 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1547 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1548 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1549 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1551 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1552 .addReg(MI->getOperand(0).getReg())
1554 .addReg(MI->getOperand(1).getReg())
1556 // Add predicate operands.
1557 .addImm(MI->getOperand(3).getImm())
1558 .addReg(MI->getOperand(4).getReg()));
1562 case ARM::CONSTPOOL_ENTRY: {
1563 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1564 /// in the function. The first operand is the ID# for this instruction, the
1565 /// second is the index into the MachineConstantPool that this is, the third
1566 /// is the size in bytes of this constant pool entry.
1567 /// The required alignment is specified on the basic block holding this MI.
1568 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1569 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1571 // If this is the first entry of the pool, mark it.
1572 if (!InConstantPool) {
1573 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1574 InConstantPool = true;
1577 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1579 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1580 if (MCPE.isMachineConstantPoolEntry())
1581 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1583 EmitGlobalConstant(MCPE.Val.ConstVal);
1586 case ARM::t2BR_JT: {
1587 // Lower and emit the instruction itself, then the jump table following it.
1588 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1590 .addReg(MI->getOperand(0).getReg())
1591 // Add predicate operands.
1595 // Output the data for the jump table itself
1599 case ARM::t2TBB_JT: {
1600 // Lower and emit the instruction itself, then the jump table following it.
1601 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1603 .addReg(MI->getOperand(0).getReg())
1604 // Add predicate operands.
1608 // Output the data for the jump table itself
1610 // Make sure the next instruction is 2-byte aligned.
1614 case ARM::t2TBH_JT: {
1615 // Lower and emit the instruction itself, then the jump table following it.
1616 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1618 .addReg(MI->getOperand(0).getReg())
1619 // Add predicate operands.
1623 // Output the data for the jump table itself
1629 // Lower and emit the instruction itself, then the jump table following it.
1632 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1633 ARM::MOVr : ARM::tMOVr;
1634 TmpInst.setOpcode(Opc);
1635 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1636 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1637 // Add predicate operands.
1638 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1639 TmpInst.addOperand(MCOperand::CreateReg(0));
1640 // Add 's' bit operand (always reg0 for this)
1641 if (Opc == ARM::MOVr)
1642 TmpInst.addOperand(MCOperand::CreateReg(0));
1643 EmitToStreamer(OutStreamer, TmpInst);
1645 // Make sure the Thumb jump table is 4-byte aligned.
1646 if (Opc == ARM::tMOVr)
1649 // Output the data for the jump table itself
1654 // Lower and emit the instruction itself, then the jump table following it.
1657 if (MI->getOperand(1).getReg() == 0) {
1659 TmpInst.setOpcode(ARM::LDRi12);
1660 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1661 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1662 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1664 TmpInst.setOpcode(ARM::LDRrs);
1665 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1666 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1667 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1668 TmpInst.addOperand(MCOperand::CreateImm(0));
1670 // Add predicate operands.
1671 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1672 TmpInst.addOperand(MCOperand::CreateReg(0));
1673 EmitToStreamer(OutStreamer, TmpInst);
1675 // Output the data for the jump table itself
1679 case ARM::BR_JTadd: {
1680 // Lower and emit the instruction itself, then the jump table following it.
1681 // add pc, target, idx
1682 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1684 .addReg(MI->getOperand(0).getReg())
1685 .addReg(MI->getOperand(1).getReg())
1686 // Add predicate operands.
1689 // Add 's' bit operand (always reg0 for this)
1692 // Output the data for the jump table itself
1697 OutStreamer.EmitZeros(MI->getOperand(1).getImm());
1700 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1701 // FIXME: Remove this special case when they do.
1702 if (!Subtarget->isTargetMachO()) {
1703 //.long 0xe7ffdefe @ trap
1704 uint32_t Val = 0xe7ffdefeUL;
1705 OutStreamer.AddComment("trap");
1706 OutStreamer.EmitIntValue(Val, 4);
1711 case ARM::TRAPNaCl: {
1712 //.long 0xe7fedef0 @ trap
1713 uint32_t Val = 0xe7fedef0UL;
1714 OutStreamer.AddComment("trap");
1715 OutStreamer.EmitIntValue(Val, 4);
1719 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1720 // FIXME: Remove this special case when they do.
1721 if (!Subtarget->isTargetMachO()) {
1722 //.short 57086 @ trap
1723 uint16_t Val = 0xdefe;
1724 OutStreamer.AddComment("trap");
1725 OutStreamer.EmitIntValue(Val, 2);
1730 case ARM::t2Int_eh_sjlj_setjmp:
1731 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1732 case ARM::tInt_eh_sjlj_setjmp: {
1733 // Two incoming args: GPR:$src, GPR:$val
1736 // str $val, [$src, #4]
1741 unsigned SrcReg = MI->getOperand(0).getReg();
1742 unsigned ValReg = MI->getOperand(1).getReg();
1743 MCSymbol *Label = GetARMSJLJEHLabel();
1744 OutStreamer.AddComment("eh_setjmp begin");
1745 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1752 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1762 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1765 // The offset immediate is #4. The operand value is scaled by 4 for the
1766 // tSTR instruction.
1772 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1780 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1781 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1782 .addExpr(SymbolExpr)
1786 OutStreamer.AddComment("eh_setjmp end");
1787 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1795 OutStreamer.EmitLabel(Label);
1799 case ARM::Int_eh_sjlj_setjmp_nofp:
1800 case ARM::Int_eh_sjlj_setjmp: {
1801 // Two incoming args: GPR:$src, GPR:$val
1803 // str $val, [$src, #+4]
1807 unsigned SrcReg = MI->getOperand(0).getReg();
1808 unsigned ValReg = MI->getOperand(1).getReg();
1810 OutStreamer.AddComment("eh_setjmp begin");
1811 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1818 // 's' bit operand (always reg0 for this).
1821 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1829 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1835 // 's' bit operand (always reg0 for this).
1838 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1845 // 's' bit operand (always reg0 for this).
1848 OutStreamer.AddComment("eh_setjmp end");
1849 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1855 // 's' bit operand (always reg0 for this).
1859 case ARM::Int_eh_sjlj_longjmp: {
1860 // ldr sp, [$src, #8]
1861 // ldr $scratch, [$src, #4]
1864 unsigned SrcReg = MI->getOperand(0).getReg();
1865 unsigned ScratchReg = MI->getOperand(1).getReg();
1866 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1874 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1882 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1890 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1897 case ARM::tInt_eh_sjlj_longjmp: {
1898 // ldr $scratch, [$src, #8]
1900 // ldr $scratch, [$src, #4]
1903 unsigned SrcReg = MI->getOperand(0).getReg();
1904 unsigned ScratchReg = MI->getOperand(1).getReg();
1905 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1908 // The offset immediate is #8. The operand value is scaled by 4 for the
1909 // tLDR instruction.
1915 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1922 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1930 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1938 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1948 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1950 EmitToStreamer(OutStreamer, TmpInst);
1953 //===----------------------------------------------------------------------===//
1954 // Target Registry Stuff
1955 //===----------------------------------------------------------------------===//
1957 // Force static initialization.
1958 extern "C" void LLVMInitializeARMAsmPrinter() {
1959 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1960 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1961 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1962 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);