0f545ef466ef896a666c93f1419acc061ad737b2
[oota-llvm.git] / lib / Target / ARM / ARM.td
1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
16
17 include "llvm/Target/Target.td"
18
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
21 //
22
23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
24                                   "Thumb mode">;
25
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
28 //
29
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31                                    "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33                                    "Enable VFP3 instructions",
34                                    [FeatureVFP2]>;
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36                                    "Enable NEON instructions",
37                                    [FeatureVFP3]>;
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39                                      "Enable Thumb2 instructions">;
40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
41                                      "Does not support ARM mode execution",
42                                      [ModeThumb]>;
43 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
44                                      "Enable half-precision floating point">;
45 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46                                      "Enable VFP4 instructions",
47                                      [FeatureVFP3, FeatureFP16]>;
48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
49                                    "true", "Enable ARMv8 FP",
50                                    [FeatureVFP4]>;
51 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
52                                      "Restrict VFP3 to 16 double registers">;
53 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54                                      "Enable divide instructions">;
55 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
56                                         "HasHardwareDivideInARM", "true",
57                                       "Enable divide instructions in ARM mode">;
58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59                                  "Enable Thumb2 extract and pack instructions">;
60 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
61                                    "Has data barrier (dmb / dsb) instructions">;
62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63                                          "FP compare + branch is slow">;
64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65                           "Floating point unit supports single precision only">;
66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67                            "Enable support for Performance Monitor extensions">;
68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69                           "Enable support for TrustZone security extensions">;
70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
71                           "Enable support for Cryptography extensions",
72                           [FeatureNEON]>;
73 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
74                           "Enable support for CRC instructions">;
75
76 // Cyclone has preferred instructions for zeroing VFP registers, which can
77 // execute in 0 cycles.
78 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
79                                         "Has zero-cycle zeroing instructions">;
80
81 // Some processors have FP multiply-accumulate instructions that don't
82 // play nicely with other VFP / NEON instructions, and it's generally better
83 // to just not use them.
84 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
85                                          "Disable VFP / NEON MAC instructions">;
86
87 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
88 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
89                                        "HasVMLxForwarding", "true",
90                                        "Has multiplier accumulator forwarding">;
91
92 // Some processors benefit from using NEON instructions for scalar
93 // single-precision FP operations.
94 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
95                                         "true",
96                                         "Use NEON for single precision FP">;
97
98 // Disable 32-bit to 16-bit narrowing for experimentation.
99 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
100                                              "Prefer 32-bit Thumb instrs">;
101
102 /// Some instructions update CPSR partially, which can add false dependency for
103 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
104 /// mapped to a separate physical register. Avoid partial CPSR update for these
105 /// processors.
106 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
107                                                "AvoidCPSRPartialUpdate", "true",
108                                  "Avoid CPSR partial update for OOO execution">;
109
110 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
111                                             "AvoidMOVsShifterOperand", "true",
112                                 "Avoid movs instructions with shifter operand">;
113
114 // Some processors perform return stack prediction. CodeGen should avoid issue
115 // "normal" call instructions to callees which do not return.
116 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
117                                      "Has return address stack">;
118
119 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
120 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
121                                  "Supports v7 DSP instructions in Thumb2">;
122
123 // Multiprocessing extension.
124 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
125                                  "Supports Multiprocessing extension">;
126
127 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
128 def FeatureVirtualization : SubtargetFeature<"virtualization",
129                                  "HasVirtualization", "true",
130                                  "Supports Virtualization extension",
131                                  [FeatureHWDiv, FeatureHWDivARM]>;
132
133 // M-series ISA
134 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
135                                      "Is microcontroller profile ('M' series)">;
136
137 // R-series ISA
138 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
139                                      "Is realtime profile ('R' series)">;
140
141 // A-series ISA
142 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
143                                      "Is application profile ('A' series)">;
144
145 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
146 // See ARMInstrInfo.td for details.
147 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
148                                        "NaCl trap">;
149
150 // ARM ISAs.
151 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
152                                    "Support ARM v4T instructions">;
153 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
154                                    "Support ARM v5T instructions",
155                                    [HasV4TOps]>;
156 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
157                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
158                                    [HasV5TOps]>;
159 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
160                                    "Support ARM v6 instructions",
161                                    [HasV5TEOps]>;
162 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
163                                    "Support ARM v6M instructions",
164                                    [HasV6Ops]>;
165 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
166                                    "Support ARM v6k instructions",
167                                    [HasV6Ops]>;
168 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
169                                    "Support ARM v6t2 instructions",
170                                    [HasV6MOps, HasV6KOps, FeatureThumb2]>;
171 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
172                                    "Support ARM v7 instructions",
173                                    [HasV6T2Ops, FeaturePerfMon]>;
174 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
175                                    "Support ARM v8 instructions",
176                                    [HasV7Ops, FeatureVirtualization,
177                                     FeatureMP]>;
178
179 //===----------------------------------------------------------------------===//
180 // ARM Processors supported.
181 //
182
183 include "ARMSchedule.td"
184
185 // ARM processor families.
186 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
187                                    "Cortex-A5 ARM processors",
188                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
189                                     FeatureVMLxForwarding, FeatureT2XtPk,
190                                     FeatureTrustZone, FeatureMP]>;
191 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
192                                    "Cortex-A7 ARM processors",
193                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
194                                     FeatureVMLxForwarding, FeatureT2XtPk,
195                                     FeatureVFP4, FeatureMP,
196                                     FeatureHWDiv, FeatureHWDivARM,
197                                     FeatureTrustZone, FeatureVirtualization]>;
198 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
199                                    "Cortex-A8 ARM processors",
200                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
201                                     FeatureVMLxForwarding, FeatureT2XtPk,
202                                     FeatureTrustZone]>;
203 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
204                                    "Cortex-A9 ARM processors",
205                                    [FeatureVMLxForwarding,
206                                     FeatureT2XtPk, FeatureFP16,
207                                     FeatureAvoidPartialCPSR,
208                                     FeatureTrustZone]>;
209 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
210                                    "Swift ARM processors",
211                                    [FeatureNEONForFP, FeatureT2XtPk,
212                                     FeatureVFP4, FeatureMP, FeatureHWDiv,
213                                     FeatureHWDivARM, FeatureAvoidPartialCPSR,
214                                     FeatureAvoidMOVsShOp,
215                                     FeatureHasSlowFPVMLx, FeatureTrustZone]>;
216 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
217                                    "Cortex-A12 ARM processors",
218                                    [FeatureVMLxForwarding,
219                                     FeatureT2XtPk, FeatureVFP4,
220                                     FeatureHWDiv, FeatureHWDivARM,
221                                     FeatureAvoidPartialCPSR,
222                                     FeatureVirtualization,
223                                     FeatureTrustZone]>;
224
225
226 // FIXME: It has not been determined if A15 has these features.
227 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
228                                    "Cortex-A15 ARM processors",
229                                    [FeatureT2XtPk, FeatureVFP4,
230                                     FeatureMP, FeatureHWDiv, FeatureHWDivARM,
231                                     FeatureAvoidPartialCPSR,
232                                     FeatureTrustZone, FeatureVirtualization]>;
233
234 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
235                                    "Cortex-A17 ARM processors",
236                                    [FeatureVMLxForwarding,
237                                     FeatureT2XtPk, FeatureVFP4,
238                                     FeatureHWDiv, FeatureHWDivARM,
239                                     FeatureAvoidPartialCPSR,
240                                     FeatureVirtualization,
241                                     FeatureTrustZone]>;
242
243 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
244                                    "Cortex-A53 ARM processors",
245                                    [FeatureHWDiv, FeatureHWDivARM,
246                                     FeatureTrustZone, FeatureT2XtPk,
247                                     FeatureCrypto, FeatureCRC]>;
248
249 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
250                                    "Cortex-A57 ARM processors",
251                                    [FeatureHWDiv, FeatureHWDivARM,
252                                     FeatureTrustZone, FeatureT2XtPk,
253                                     FeatureCrypto, FeatureCRC]>;
254
255 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
256                                    "Cortex-R5 ARM processors",
257                                    [FeatureSlowFPBrcc,
258                                     FeatureHWDiv, FeatureHWDivARM,
259                                     FeatureHasSlowFPVMLx,
260                                     FeatureAvoidPartialCPSR,
261                                     FeatureT2XtPk]>;
262
263 // FIXME: krait has currently the same features as A9
264 // plus VFP4 and hardware division features.
265 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
266                                    "Qualcomm ARM processors",
267                                    [FeatureVMLxForwarding,
268                                     FeatureT2XtPk, FeatureFP16,
269                                     FeatureAvoidPartialCPSR,
270                                     FeatureTrustZone,
271                                     FeatureVFP4,
272                                     FeatureHWDiv,
273                                     FeatureHWDivARM]>;
274
275
276 class ProcNoItin<string Name, list<SubtargetFeature> Features>
277  : Processor<Name, NoItineraries, Features>;
278
279 // V4 Processors.
280 def : ProcNoItin<"generic",         []>;
281 def : ProcNoItin<"arm8",            []>;
282 def : ProcNoItin<"arm810",          []>;
283 def : ProcNoItin<"strongarm",       []>;
284 def : ProcNoItin<"strongarm110",    []>;
285 def : ProcNoItin<"strongarm1100",   []>;
286 def : ProcNoItin<"strongarm1110",   []>;
287
288 // V4T Processors.
289 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
290 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
291 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
292 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
293 def : ProcNoItin<"arm9",            [HasV4TOps]>;
294 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
295 def : ProcNoItin<"arm920",          [HasV4TOps]>;
296 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
297 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
298 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
299 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
300
301 // V5T Processors.
302 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
303 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
304
305 // V5TE Processors.
306 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
307 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
308 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
309 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
310 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
311 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
312 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
313 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
314 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
315 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
316
317 // V6 Processors.
318 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
319 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
320                                                        FeatureHasSlowFPVMLx]>;
321
322 // V6M Processors.
323 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
324                                                        FeatureDB, FeatureMClass]>;
325 def : Processor<"cortex-m0plus",    ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
326                                                        FeatureDB, FeatureMClass]>;
327 def : Processor<"cortex-m1",        ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
328                                                        FeatureDB, FeatureMClass]>;
329 def : Processor<"sc000",            ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
330                                                        FeatureDB, FeatureMClass]>;
331
332 // V6K Processors.
333 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6KOps]>;
334 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
335                                                        FeatureHasSlowFPVMLx]>;
336 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6KOps]>;
337 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
338                                                        FeatureHasSlowFPVMLx]>;
339
340 // V6T2 Processors.
341 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
342                                                        FeatureDSPThumb2]>;
343 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
344                                                        FeatureHasSlowFPVMLx,
345                                                        FeatureDSPThumb2]>;
346
347 // V7a Processors.
348 // FIXME: A5 has currently the same Schedule model as A8
349 def : ProcessorModel<"cortex-a5",   CortexA8Model,
350                                     [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
351                                      FeatureVFP4, FeatureDSPThumb2,
352                                      FeatureHasRAS, FeatureAClass]>;
353 def : ProcessorModel<"cortex-a7",   CortexA8Model,
354                                     [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
355                                      FeatureDSPThumb2, FeatureHasRAS,
356                                      FeatureAClass]>;
357 def : ProcessorModel<"cortex-a8",   CortexA8Model,
358                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
359                                      FeatureDSPThumb2, FeatureHasRAS,
360                                      FeatureAClass]>;
361 def : ProcessorModel<"cortex-a9",   CortexA9Model,
362                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
363                                      FeatureDSPThumb2, FeatureHasRAS, FeatureMP,
364                                      FeatureAClass]>;
365
366 // FIXME: A12 has currently the same Schedule model as A9
367 def : ProcessorModel<"cortex-a12", CortexA9Model,
368                                     [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
369                                      FeatureDSPThumb2, FeatureMP,
370                                      FeatureHasRAS, FeatureAClass]>;
371
372 // FIXME: A15 has currently the same ProcessorModel as A9.
373 def : ProcessorModel<"cortex-a15",   CortexA9Model,
374                                     [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
375                                      FeatureDSPThumb2, FeatureHasRAS,
376                                      FeatureAClass]>;
377
378 // FIXME: A17 has currently the same Schedule model as A9
379 def : ProcessorModel<"cortex-a17",  CortexA9Model,
380                                     [ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
381                                      FeatureDSPThumb2, FeatureMP,
382                                      FeatureHasRAS, FeatureAClass]>;
383
384 // FIXME: krait has currently the same Schedule model as A9
385 def : ProcessorModel<"krait",       CortexA9Model,
386                                     [ProcKrait, HasV7Ops,
387                                      FeatureNEON, FeatureDB,
388                                      FeatureDSPThumb2, FeatureHasRAS,
389                                      FeatureAClass]>;
390
391 // FIXME: R5 has currently the same ProcessorModel as A8.
392 def : ProcessorModel<"cortex-r5",   CortexA8Model,
393                                     [ProcR5, HasV7Ops, FeatureDB,
394                                      FeatureVFP3, FeatureDSPThumb2,
395                                      FeatureHasRAS, FeatureVFPOnlySP,
396                                      FeatureD16, FeatureRClass]>;
397
398 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
399 def : ProcessorModel<"cortex-r7",   CortexA8Model,
400                                     [ProcR5, HasV7Ops, FeatureDB,
401                                      FeatureVFP3, FeatureDSPThumb2,
402                                      FeatureHasRAS, FeatureVFPOnlySP,
403                                      FeatureD16, FeatureMP, FeatureRClass]>;
404
405 // V7M Processors.
406 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
407                                      FeatureThumb2, FeatureNoARM, FeatureDB,
408                                      FeatureHWDiv, FeatureMClass]>;
409 def : ProcNoItin<"sc300",           [HasV7Ops,
410                                      FeatureThumb2, FeatureNoARM, FeatureDB,
411                                      FeatureHWDiv, FeatureMClass]>;
412
413 // V7EM Processors.
414 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
415                                      FeatureThumb2, FeatureNoARM, FeatureDB,
416                                      FeatureHWDiv, FeatureDSPThumb2,
417                                      FeatureT2XtPk, FeatureVFP4,
418                                      FeatureVFPOnlySP, FeatureD16,
419                                      FeatureMClass]>;
420 def : ProcNoItin<"cortex-m7",       [HasV7Ops,
421                                      FeatureThumb2, FeatureNoARM, FeatureDB,
422                                      FeatureHWDiv, FeatureDSPThumb2,
423                                      FeatureT2XtPk, FeatureFPARMv8,
424                                      FeatureD16, FeatureMClass]>;
425
426
427 // Swift uArch Processors.
428 def : ProcessorModel<"swift",       SwiftModel,
429                                     [ProcSwift, HasV7Ops, FeatureNEON,
430                                      FeatureDB, FeatureDSPThumb2,
431                                      FeatureHasRAS, FeatureAClass]>;
432
433 // V8 Processors
434 def : ProcNoItin<"cortex-a53",      [ProcA53, HasV8Ops, FeatureAClass,
435                                     FeatureDB, FeatureFPARMv8,
436                                     FeatureNEON, FeatureDSPThumb2]>;
437 def : ProcNoItin<"cortex-a57",      [ProcA57, HasV8Ops, FeatureAClass,
438                                     FeatureDB, FeatureFPARMv8,
439                                     FeatureNEON, FeatureDSPThumb2]>;
440 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
441 def : ProcNoItin<"cortex-a72",      [ProcA57, HasV8Ops, FeatureAClass,
442                                     FeatureDB, FeatureFPARMv8,
443                                     FeatureNEON, FeatureDSPThumb2]>;
444
445 // Cyclone is very similar to swift
446 def : ProcessorModel<"cyclone",     SwiftModel,
447                                     [ProcSwift, HasV8Ops, HasV7Ops,
448                                      FeatureCrypto, FeatureFPARMv8,
449                                      FeatureDB,FeatureDSPThumb2,
450                                      FeatureHasRAS, FeatureZCZeroing]>;
451
452 //===----------------------------------------------------------------------===//
453 // Register File Description
454 //===----------------------------------------------------------------------===//
455
456 include "ARMRegisterInfo.td"
457
458 include "ARMCallingConv.td"
459
460 //===----------------------------------------------------------------------===//
461 // Instruction Descriptions
462 //===----------------------------------------------------------------------===//
463
464 include "ARMInstrInfo.td"
465
466 def ARMInstrInfo : InstrInfo;
467
468 //===----------------------------------------------------------------------===//
469 // Declare the target which we are implementing
470 //===----------------------------------------------------------------------===//
471
472 def ARM : Target {
473   // Pull in Instruction Info:
474   let InstructionSet = ARMInstrInfo;
475 }