lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

   1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief This file provides AMDGPU specific target descriptions.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AMDGPUMCTargetDesc.h"
  16 #include "AMDGPUMCAsmInfo.h"
  17 #include "AMDGPUTargetStreamer.h"
  18 #include "InstPrinter/AMDGPUInstPrinter.h"
  19 #include "SIDefines.h"
  20 #include "llvm/MC/MCCodeGenInfo.h"
  21 #include "llvm/MC/MCContext.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/MC/MCStreamer.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/MC/MachineLocation.h"
  27 #include "llvm/Support/ErrorHandling.h"
  28 #include "llvm/Support/TargetRegistry.h"
  29
  30 using namespace llvm;
  31
  32 #define GET_INSTRINFO_MC_DESC
  33 #include "AMDGPUGenInstrInfo.inc"
  34
  35 #define GET_SUBTARGETINFO_MC_DESC
  36 #include "AMDGPUGenSubtargetInfo.inc"
  37
  38 #define GET_REGINFO_MC_DESC
  39 #include "AMDGPUGenRegisterInfo.inc"
  40
  41 static MCInstrInfo *createAMDGPUMCInstrInfo() {
  42   MCInstrInfo *X = new MCInstrInfo();
  43   InitAMDGPUMCInstrInfo(X);
  44   return X;
  45 }
  46
  47 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const TargetTuple &TT) {
  48   MCRegisterInfo *X = new MCRegisterInfo();
  49   InitAMDGPUMCRegisterInfo(X, 0);
  50   return X;
  51 }
  52
  53 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(const TargetTuple &TT,
  54                                                     StringRef CPU,
  55                                                     StringRef FS) {
  56   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
  57 }
  58
  59 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const TargetTuple &TT,
  60                                                 Reloc::Model RM,
  61                                                 CodeModel::Model CM,
  62                                                 CodeGenOpt::Level OL) {
  63   MCCodeGenInfo *X = new MCCodeGenInfo();
  64   X->initMCCodeGenInfo(RM, CM, OL);
  65   return X;
  66 }
  67
  68 static MCInstPrinter *createAMDGPUMCInstPrinter(const TargetTuple &T,
  69                                                 unsigned SyntaxVariant,
  70                                                 const MCAsmInfo &MAI,
  71                                                 const MCInstrInfo &MII,
  72                                                 const MCRegisterInfo &MRI) {
  73   return new AMDGPUInstPrinter(MAI, MII, MRI);
  74 }
  75
  76 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
  77                                                       formatted_raw_ostream &OS,
  78                                                       MCInstPrinter *InstPrint,
  79                                                       bool isVerboseAsm) {
  80   return new AMDGPUTargetAsmStreamer(S, OS);
  81 }
  82
  83 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
  84                                                    MCStreamer &S,
  85                                                    const MCSubtargetInfo &STI) {
  86   return new AMDGPUTargetELFStreamer(S);
  87 }
  88
  89 extern "C" void LLVMInitializeAMDGPUTargetMC() {
  90   for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
  91     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
  92
  93     TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
  94     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
  95     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
  96     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
  97     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
  98     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
  99   }
 100
 101   // R600 specific registration
 102   TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
 103                                         createR600MCCodeEmitter);
 104
 105   // GCN specific registration
 106   TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
 107
 108   TargetRegistry::RegisterAsmTargetStreamer(TheGCNTarget,
 109                                             createAMDGPUAsmTargetStreamer);
 110   TargetRegistry::RegisterObjectTargetStreamer(TheGCNTarget,
 111                                               createAMDGPUObjectTargetStreamer);
 112 }