1 //===-- AMDIL.h - Top-level interface for AMDIL representation --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // This file contains the entry points for global functions defined in the LLVM
13 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Target/TargetMachine.h"
21 #define AMDIL_MAJOR_VERSION 2
22 #define AMDIL_MINOR_VERSION 0
23 #define AMDIL_REVISION_NUMBER 74
24 #define ARENA_SEGMENT_RESERVED_UAVS 12
25 #define DEFAULT_ARENA_UAV_ID 8
26 #define DEFAULT_RAW_UAV_ID 7
27 #define GLOBAL_RETURN_RAW_UAV_ID 11
28 #define HW_MAX_NUM_CB 8
29 #define MAX_NUM_UNIQUE_UAVS 8
30 #define OPENCL_MAX_NUM_ATOMIC_COUNTERS 8
31 #define OPENCL_MAX_READ_IMAGES 128
32 #define OPENCL_MAX_WRITE_IMAGES 8
33 #define OPENCL_MAX_SAMPLERS 16
35 // The next two values can never be zero, as zero is the ID that is
36 // used to assert against.
37 #define DEFAULT_LDS_ID 1
38 #define DEFAULT_GDS_ID 1
39 #define DEFAULT_SCRATCH_ID 1
40 #define DEFAULT_VEC_SLOTS 8
42 // SC->CAL version matchings.
43 #define CAL_VERSION_SC_150 1700
44 #define CAL_VERSION_SC_149 1700
45 #define CAL_VERSION_SC_148 1525
46 #define CAL_VERSION_SC_147 1525
47 #define CAL_VERSION_SC_146 1525
48 #define CAL_VERSION_SC_145 1451
49 #define CAL_VERSION_SC_144 1451
50 #define CAL_VERSION_SC_143 1441
51 #define CAL_VERSION_SC_142 1441
52 #define CAL_VERSION_SC_141 1420
53 #define CAL_VERSION_SC_140 1400
54 #define CAL_VERSION_SC_139 1387
55 #define CAL_VERSION_SC_138 1387
56 #define CAL_APPEND_BUFFER_SUPPORT 1340
57 #define CAL_VERSION_SC_137 1331
58 #define CAL_VERSION_SC_136 982
59 #define CAL_VERSION_SC_135 950
60 #define CAL_VERSION_GLOBAL_RETURN_BUFFER 990
62 #define OCL_DEVICE_RV710 0x0001
63 #define OCL_DEVICE_RV730 0x0002
64 #define OCL_DEVICE_RV770 0x0004
65 #define OCL_DEVICE_CEDAR 0x0008
66 #define OCL_DEVICE_REDWOOD 0x0010
67 #define OCL_DEVICE_JUNIPER 0x0020
68 #define OCL_DEVICE_CYPRESS 0x0040
69 #define OCL_DEVICE_CAICOS 0x0080
70 #define OCL_DEVICE_TURKS 0x0100
71 #define OCL_DEVICE_BARTS 0x0200
72 #define OCL_DEVICE_CAYMAN 0x0400
73 #define OCL_DEVICE_ALL 0x3FFF
75 /// The number of function ID's that are reserved for
76 /// internal compiler usage.
77 const unsigned int RESERVED_FUNCS = 1024;
79 #define AMDIL_OPT_LEVEL_DECL
80 #define AMDIL_OPT_LEVEL_VAR
81 #define AMDIL_OPT_LEVEL_VAR_NO_COMMA
84 class AMDILInstrPrinter;
91 /// Instruction selection passes.
93 createAMDILISelDag(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
95 createAMDILPeepholeOpt(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
99 createAMDILCFGPreparationPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
101 createAMDILCFGStructurizerPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
103 extern Target TheAMDILTarget;
104 extern Target TheAMDGPUTarget;
105 } // end namespace llvm;
107 #define GET_REGINFO_ENUM
108 #include "AMDGPUGenRegisterInfo.inc"
109 #define GET_INSTRINFO_ENUM
110 #include "AMDGPUGenInstrInfo.inc"
112 /// Include device information enumerations
113 #include "AMDILDeviceInfo.h"
116 /// OpenCL uses address spaces to differentiate between
117 /// various memory regions on the hardware. On the CPU
118 /// all of the address spaces point to the same memory,
119 /// however on the GPU, each address space points to
120 /// a seperate piece of memory that is unique from other
121 /// memory locations.
124 PRIVATE_ADDRESS = 0, // Address space for private memory.
125 GLOBAL_ADDRESS = 1, // Address space for global memory (RAT0, VTX0).
126 CONSTANT_ADDRESS = 2, // Address space for constant memory.
127 LOCAL_ADDRESS = 3, // Address space for local memory.
128 REGION_ADDRESS = 4, // Address space for region memory.
129 ADDRESS_NONE = 5, // Address space for unknown memory.
130 PARAM_D_ADDRESS = 6, // Address space for direct addressible parameter memory (CONST0)
131 PARAM_I_ADDRESS = 7, // Address space for indirect addressible parameter memory (VTX1)
132 USER_SGPR_ADDRESS = 8, // Address space for USER_SGPRS on SI
136 // This union/struct combination is an easy way to read out the
137 // exact bits that are needed.
138 typedef union ResourceRec {
140 #ifdef __BIG_ENDIAN__
141 unsigned short isImage : 1; // Reserved for future use/llvm.
142 unsigned short ResourceID : 10; // Flag to specify the resourece ID for
144 unsigned short HardwareInst : 1; // Flag to specify that this instruction
145 // is a hardware instruction.
146 unsigned short ConflictPtr : 1; // Flag to specify that the pointer has a
148 unsigned short ByteStore : 1; // Flag to specify if the op is a byte
150 unsigned short PointerPath : 1; // Flag to specify if the op is on the
152 unsigned short CacheableRead : 1; // Flag to specify if the read is
155 unsigned short CacheableRead : 1; // Flag to specify if the read is
157 unsigned short PointerPath : 1; // Flag to specify if the op is on the
159 unsigned short ByteStore : 1; // Flag to specify if the op is byte
161 unsigned short ConflictPtr : 1; // Flag to specify that the pointer has
163 unsigned short HardwareInst : 1; // Flag to specify that this instruction
164 // is a hardware instruction.
165 unsigned short ResourceID : 10; // Flag to specify the resource ID for
167 unsigned short isImage : 1; // Reserved for future use.
170 unsigned short u16all;
173 } // namespace AMDILAS
175 // Enums corresponding to AMDIL condition codes for IL. These
176 // values must be kept in sync with the ones in the .td file.
179 // AMDIL specific condition codes. These correspond to the IL_CC_*
180 // in AMDILInstrInfo.td and must be kept in the same order.
181 IL_CC_D_EQ = 0, // DEQ instruction.
182 IL_CC_D_GE = 1, // DGE instruction.
183 IL_CC_D_LT = 2, // DLT instruction.
184 IL_CC_D_NE = 3, // DNE instruction.
185 IL_CC_F_EQ = 4, // EQ instruction.
186 IL_CC_F_GE = 5, // GE instruction.
187 IL_CC_F_LT = 6, // LT instruction.
188 IL_CC_F_NE = 7, // NE instruction.
189 IL_CC_I_EQ = 8, // IEQ instruction.
190 IL_CC_I_GE = 9, // IGE instruction.
191 IL_CC_I_LT = 10, // ILT instruction.
192 IL_CC_I_NE = 11, // INE instruction.
193 IL_CC_U_GE = 12, // UGE instruction.
194 IL_CC_U_LT = 13, // ULE instruction.
195 // Pseudo IL Comparison instructions here.
196 IL_CC_F_GT = 14, // GT instruction.
200 IL_CC_F_LE = 18, // LE instruction
249 } // end namespace AMDILCC
250 } // end namespace llvm