1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the TargetInstrInfo class that is
11 // common to all AMD GPUs.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUInstrInfo.h"
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 AMDGPUInstrInfo::AMDGPUInstrInfo(AMDGPUTargetMachine &tm)
24 : AMDILInstrInfo(tm) { }
26 void AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
29 MachineRegisterInfo &MRI = MF.getRegInfo();
30 const AMDGPURegisterInfo & RI = getRegisterInfo();
32 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
33 MachineOperand &MO = MI.getOperand(i);
34 // Convert dst regclass to one that is supported by the ISA
35 if (MO.isReg() && MO.isDef()) {
36 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
37 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
38 const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);
42 MRI.setRegClass(MO.getReg(), newRegClass);