1 //===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
21 "Dump MachineInstrs in the CodeEmitter">;
23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
26 "Dump MachineInstrs in the CodeEmitter">;
28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
29 "EnableIRStructurizer",
31 "Disable IR Structurizer">;
33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
34 "EnablePromoteAlloca",
36 "Enable promote alloca pass">;
40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
43 "Disable the if conversion pass">;
45 def FeatureFP64 : SubtargetFeature<"fp64",
48 "Enable double precision operations">;
50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
53 "Enable double precision denormal handling",
56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
59 "Assuming f32 fma is at least as fast as mul + add",
62 // Some instructions do not support denormals despite this flag. Using
63 // fp32 denormals also causes instructions to run at the double
64 // precision rate for the device.
65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
68 "Enable single precision denormal handling">;
70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
73 "Specify if 64-bit addressing should be used">;
75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
78 "Older version of ALU instructions encoding">;
80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
83 "Specify use of dedicated vertex cache">;
85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
93 "GPU has CF_ALU bug">;
95 // XXX - This should probably be removed once enabled by default
96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
99 "Enable SI load/store optimizer pass">;
101 // Performance debugging feature. Allow using DS instruction immediate
102 // offsets even if the base pointer can't be proven to be base. On SI,
103 // base pointer values that won't give the same result as a 16-bit add
104 // are not safe to fold, but this will override the conservative test
105 // for the base pointer.
106 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <"unsafe-ds-offset-folding",
107 "EnableUnsafeDSOffsetFolding",
109 "Force using DS instruction immediate offsets on SI">;
111 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
114 "Force to generate flat instruction for global">;
116 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
119 "Support flat address space">;
121 def FeatureXNACK : SubtargetFeature<"xnack",
124 "Enable XNACK support">;
126 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
127 "EnableVGPRSpilling",
129 "Enable spilling of VGPRs to scratch memory">;
131 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
134 "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
136 def FeatureEnableHugeScratchBuffer : SubtargetFeature<"huge-scratch-buffer",
137 "EnableHugeScratchBuffer",
139 "Enable scratch buffer sizes greater than 128 GB">;
141 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
144 "Enable SI Machine Scheduler">;
146 class SubtargetFeatureFetchLimit <string Value> :
147 SubtargetFeature <"fetch"#Value,
150 "Limit the maximum number of fetches in a clause to "#Value>;
152 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
153 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
155 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
156 "wavefrontsize"#Value,
158 !cast<string>(Value),
159 "The number of threads per wavefront">;
161 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
162 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
163 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
165 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
166 "ldsbankcount"#Value,
168 !cast<string>(Value),
169 "The number of LDS banks per compute unit.">;
171 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
172 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
174 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
176 "isaver"#Major#"."#Minor#"."#Stepping,
178 "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
179 "Instruction set version number"
182 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
183 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
184 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
185 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
187 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
188 "localmemorysize"#Value,
190 !cast<string>(Value),
191 "The size of local memory in bytes">;
193 def FeatureGCN : SubtargetFeature<"gcn",
198 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
201 "Encoding format for SI and CI">;
203 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
206 "Encoding format for VI">;
208 def FeatureCIInsts : SubtargetFeature<"ci-insts",
211 "Additional intstructions for CI+">;
213 // Dummy feature used to disable assembler instructions.
214 def FeatureDisable : SubtargetFeature<"",
215 "FeatureDisable","true",
216 "Dummy feature to disable assembler"
219 class SubtargetFeatureGeneration <string Value,
220 list<SubtargetFeature> Implies> :
221 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
222 Value#" GPU generation", Implies>;
224 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
225 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
226 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
228 def FeatureR600 : SubtargetFeatureGeneration<"R600",
229 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
231 def FeatureR700 : SubtargetFeatureGeneration<"R700",
232 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
234 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
235 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
237 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
238 [FeatureFetchLimit16, FeatureWavefrontSize64,
239 FeatureLocalMemorySize32768]
242 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
243 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
244 FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
245 FeatureLDSBankCount32]>;
247 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
248 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
249 FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
250 FeatureGCN1Encoding, FeatureCIInsts]>;
252 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
253 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
254 FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
255 FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
257 //===----------------------------------------------------------------------===//
259 def AMDGPUInstrInfo : InstrInfo {
260 let guessInstructionProperties = 1;
261 let noNamedPositionallyEncodedOperands = 1;
264 def AMDGPUAsmParser : AsmParser {
265 // Some of the R600 registers have the same name, so this crashes.
266 // For example T0_XYZW and T0_XY both have the asm name T0.
267 let ShouldEmitMatchRegisterName = 0;
270 def AMDGPU : Target {
271 // Pull in Instruction Info:
272 let InstructionSet = AMDGPUInstrInfo;
273 let AssemblyParsers = [AMDGPUAsmParser];
276 // Dummy Instruction itineraries for pseudo instructions
277 def ALU_NULL : FuncUnit;
278 def NullALU : InstrItinClass;
280 //===----------------------------------------------------------------------===//
281 // Predicate helper class
282 //===----------------------------------------------------------------------===//
284 def TruePredicate : Predicate<"true">;
285 def isSICI : Predicate<
286 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
287 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
288 >, AssemblerPredicate<"FeatureGCN1Encoding">;
290 def isVI : Predicate <
291 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
292 AssemblerPredicate<"FeatureGCN3Encoding">;
294 class PredicateControl {
295 Predicate SubtargetPredicate;
296 Predicate SIAssemblerPredicate = isSICI;
297 Predicate VIAssemblerPredicate = isVI;
298 list<Predicate> AssemblerPredicates = [];
299 Predicate AssemblerPredicate = TruePredicate;
300 list<Predicate> OtherPredicates = [];
301 list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
306 // Include AMDGPU TD files
307 include "R600Schedule.td"
308 include "SISchedule.td"
309 include "Processors.td"
310 include "AMDGPUInstrInfo.td"
311 include "AMDGPUIntrinsics.td"
312 include "AMDGPURegisterInfo.td"
313 include "AMDGPUInstructions.td"
314 include "AMDGPUCallingConv.td"