lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

   1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides AArch64 specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18 #include <string>
  19
  20 namespace llvm {
  21 class formatted_raw_ostream;
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInstrInfo;
  26 class MCInstPrinter;
  27 class MCRegisterInfo;
  28 class MCObjectWriter;
  29 class MCStreamer;
  30 class MCSubtargetInfo;
  31 class MCTargetStreamer;
  32 class StringRef;
  33 class Target;
  34 class Triple;
  35 class raw_ostream;
  36
  37 extern Target TheAArch64leTarget;
  38 extern Target TheAArch64beTarget;
  39 extern Target TheARM64Target;
  40
  41 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
  42                                           const MCRegisterInfo &MRI,
  43                                           MCContext &Ctx);
  44 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
  45                                         const MCRegisterInfo &MRI, StringRef TT,
  46                                         StringRef CPU);
  47 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
  48                                         const MCRegisterInfo &MRI, StringRef TT,
  49                                         StringRef CPU);
  50
  51 MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
  52                                              bool IsLittleEndian);
  53
  54 MCObjectWriter *createAArch64MachObjectWriter(raw_ostream &OS, uint32_t CPUType,
  55                                               uint32_t CPUSubtype);
  56
  57 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
  58                                                  formatted_raw_ostream &OS,
  59                                                  MCInstPrinter *InstPrint,
  60                                                  bool isVerboseAsm);
  61
  62 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
  63                                                     const MCSubtargetInfo &STI);
  64
  65 } // End llvm namespace
  66
  67 // Defines symbolic names for AArch64 registers.  This defines a mapping from
  68 // register name to register number.
  69 //
  70 #define GET_REGINFO_ENUM
  71 #include "AArch64GenRegisterInfo.inc"
  72
  73 // Defines symbolic names for the AArch64 instructions.
  74 //
  75 #define GET_INSTRINFO_ENUM
  76 #include "AArch64GenInstrInfo.inc"
  77
  78 #define GET_SUBTARGETINFO_ENUM
  79 #include "AArch64GenSubtargetInfo.inc"
  80
  81 #endif