lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the functions necessary to decode AArch64 instruction
  11 // bitpatterns into MCInsts (with the help of TableGenerated information from
  12 // the instruction definitions).
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "arm-disassembler"
  17
  18 #include "AArch64.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64Subtarget.h"
  21 #include "Utils/AArch64BaseInfo.h"
  22 #include "llvm/MC/MCInst.h"
  23 #include "llvm/MC/MCInstrDesc.h"
  24 #include "llvm/MC/MCExpr.h"
  25 #include "llvm/MC/MCContext.h"
  26 #include "llvm/MC/MCDisassembler.h"
  27 #include "llvm/MC/MCFixedLenDisassembler.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MemoryObject.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32 #include "llvm/Support/raw_ostream.h"
  33
  34 using namespace llvm;
  35
  36 typedef MCDisassembler::DecodeStatus DecodeStatus;
  37
  38 namespace {
  39 /// AArch64 disassembler for all AArch64 platforms.
  40 class AArch64Disassembler : public MCDisassembler {
  41   OwningPtr<const MCRegisterInfo> RegInfo;
  42 public:
  43   /// Initializes the disassembler.
  44   ///
  45   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  46     : MCDisassembler(STI), RegInfo(Info) {
  47   }
  48
  49   ~AArch64Disassembler() {}
  50
  51   /// See MCDisassembler.
  52   DecodeStatus getInstruction(MCInst &instr,
  53                               uint64_t &size,
  54                               const MemoryObject &region,
  55                               uint64_t address,
  56                               raw_ostream &vStream,
  57                               raw_ostream &cStream) const;
  58
  59   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  60 };
  61
  62 }
  63
  64 // Forward-declarations used in the auto-generated files.
  65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                          uint64_t Address, const void *Decoder);
  67 static DecodeStatus
  68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                             uint64_t Address, const void *Decoder);
  70
  71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                          uint64_t Address, const void *Decoder);
  73 static DecodeStatus
  74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                             uint64_t Address, const void *Decoder);
  76
  77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                          uint64_t Address, const void *Decoder);
  79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  80                                          uint64_t Address, const void *Decoder);
  81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  82                                          uint64_t Address, const void *Decoder);
  83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  84                                          uint64_t Address, const void *Decoder);
  85 static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  86                                          uint64_t Address, const void *Decoder);
  87 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  88                                               unsigned RegNo, uint64_t Address,
  89                                               const void *Decoder);
  90 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst,
  91                                                 unsigned RegNo, uint64_t Address,
  92                                                 const void *Decoder);
  93
  94 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
  95                                                   unsigned RegNo,
  96                                                   uint64_t Address,
  97                                                   const void *Decoder);
  98
  99 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 103                                              uint64_t Address,
 104                                              const void *Decoder);
 105 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
 106                                                unsigned RegNo, uint64_t Address,
 107                                                const void *Decoder);
 108 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
 109                                                unsigned RegNo, uint64_t Address,
 110                                                const void *Decoder);
 111 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 112                                              uint64_t Address,
 113                                              const void *Decoder);
 114 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 115                                              uint64_t Address,
 116                                              const void *Decoder);
 117
 118 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 119                                                unsigned OptionHiS,
 120                                                uint64_t Address,
 121                                                const void *Decoder);
 122
 123
 124 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 125                                                unsigned Imm6Bits,
 126                                                uint64_t Address,
 127                                                const void *Decoder);
 128
 129 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 130                                                unsigned Imm6Bits,
 131                                                uint64_t Address,
 132                                                const void *Decoder);
 133
 134 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 135                                         unsigned RmBits,
 136                                         uint64_t Address,
 137                                         const void *Decoder);
 138
 139 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 140                                          uint64_t Address, const void *Decoder);
 141 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 142                                           uint64_t Address,
 143                                           const void *Decoder);
 144 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 145                                           uint64_t Address,
 146                                           const void *Decoder);
 147 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 148                                           uint64_t Address,
 149                                           const void *Decoder);
 150
 151 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
 152                                         uint64_t Address, const void *Decoder);
 153 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
 154                                          uint64_t Address,
 155                                          const void *Decoder);
 156 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
 157                                          uint64_t Address,
 158                                          const void *Decoder);
 159 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
 160                                          uint64_t Address,
 161                                          const void *Decoder);
 162
 163 template<int RegWidth>
 164 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 165                                              unsigned FullImm,
 166                                              uint64_t Address,
 167                                              const void *Decoder);
 168
 169 template<int RegWidth>
 170 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 171                                             unsigned Bits,
 172                                             uint64_t Address,
 173                                             const void *Decoder);
 174
 175 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 176                                            unsigned ShiftAmount,
 177                                            uint64_t Address,
 178                                            const void *Decoder);
 179 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 180 static DecodeStatus
 181 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 182                              uint64_t Address, const void *Decoder);
 183
 184 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 185                                             unsigned ShiftAmount,
 186                                             uint64_t Address,
 187                                             const void *Decoder);
 188 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 189                                               uint64_t Address,
 190                                               const void *Decoder);
 191
 192 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 193                                               uint64_t Address,
 194                                               const void *Decoder);
 195
 196 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 197                                               unsigned Insn,
 198                                               uint64_t Address,
 199                                               const void *Decoder);
 200
 201 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 202                                                        unsigned Val,
 203                                                        uint64_t Address,
 204                                                        const void *Decoder);
 205
 206 template<typename SomeNamedImmMapper>
 207 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 208                                           unsigned Val,
 209                                           uint64_t Address,
 210                                           const void *Decoder);
 211
 212 static DecodeStatus
 213 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 214                     llvm::MCInst &Inst, unsigned Val,
 215                     uint64_t Address, const void *Decoder);
 216
 217 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 218                                      unsigned Val,
 219                                      uint64_t Address,
 220                                      const void *Decoder);
 221
 222 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 223                                      unsigned Val,
 224                                      uint64_t Address,
 225                                      const void *Decoder);
 226
 227
 228 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 229                                                    unsigned Val,
 230                                                    uint64_t Address,
 231                                                    const void *Decoder);
 232
 233 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val,
 234                                                uint64_t Address,
 235                                                const void *Decoder);
 236
 237 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
 238                                                    uint64_t Address,
 239                                                    const void *Decoder);
 240
 241 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
 242                                           uint64_t Address,
 243                                           const void *Decoder);
 244
 245 static bool Check(DecodeStatus &Out, DecodeStatus In);
 246
 247 #include "AArch64GenDisassemblerTables.inc"
 248 #include "AArch64GenInstrInfo.inc"
 249
 250 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 251   switch (In) {
 252     case MCDisassembler::Success:
 253       // Out stays the same.
 254       return true;
 255     case MCDisassembler::SoftFail:
 256       Out = In;
 257       return true;
 258     case MCDisassembler::Fail:
 259       Out = In;
 260       return false;
 261   }
 262   llvm_unreachable("Invalid DecodeStatus!");
 263 }
 264
 265 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 266                                                  const MemoryObject &Region,
 267                                                  uint64_t Address,
 268                                                  raw_ostream &os,
 269                                                  raw_ostream &cs) const {
 270   CommentStream = &cs;
 271
 272   uint8_t bytes[4];
 273
 274   // We want to read exactly 4 bytes of data.
 275   if (Region.readBytes(Address, 4, bytes) == -1) {
 276     Size = 0;
 277     return MCDisassembler::Fail;
 278   }
 279
 280   // Encoded as a small-endian 32-bit word in the stream.
 281   uint32_t insn = (bytes[3] << 24) |
 282     (bytes[2] << 16) |
 283     (bytes[1] <<  8) |
 284     (bytes[0] <<  0);
 285
 286   // Calling the auto-generated decoder function.
 287   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 288                                           this, STI);
 289   if (result != MCDisassembler::Fail) {
 290     Size = 4;
 291     return result;
 292   }
 293
 294   MI.clear();
 295   Size = 0;
 296   return MCDisassembler::Fail;
 297 }
 298
 299 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 300   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 301   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 302 }
 303
 304 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 305                                         uint64_t Address, const void *Decoder) {
 306   if (RegNo > 31)
 307     return MCDisassembler::Fail;
 308
 309   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 310   Inst.addOperand(MCOperand::CreateReg(Register));
 311   return MCDisassembler::Success;
 312 }
 313
 314 static DecodeStatus
 315 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 316                             uint64_t Address, const void *Decoder) {
 317   if (RegNo > 31)
 318     return MCDisassembler::Fail;
 319
 320   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 321   Inst.addOperand(MCOperand::CreateReg(Register));
 322   return MCDisassembler::Success;
 323 }
 324
 325 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 326                                              uint64_t Address,
 327                                              const void *Decoder) {
 328   if (RegNo > 31)
 329     return MCDisassembler::Fail;
 330
 331   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 332   Inst.addOperand(MCOperand::CreateReg(Register));
 333   return MCDisassembler::Success;
 334 }
 335
 336 static DecodeStatus
 337 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 338                             uint64_t Address, const void *Decoder) {
 339   if (RegNo > 31)
 340     return MCDisassembler::Fail;
 341
 342   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 343   Inst.addOperand(MCOperand::CreateReg(Register));
 344   return MCDisassembler::Success;
 345 }
 346
 347 static DecodeStatus
 348 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 349                             uint64_t Address, const void *Decoder) {
 350   if (RegNo > 31)
 351     return MCDisassembler::Fail;
 352
 353   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 354   Inst.addOperand(MCOperand::CreateReg(Register));
 355   return MCDisassembler::Success;
 356 }
 357
 358 static DecodeStatus
 359 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 360                             uint64_t Address, const void *Decoder) {
 361   if (RegNo > 31)
 362     return MCDisassembler::Fail;
 363
 364   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 365   Inst.addOperand(MCOperand::CreateReg(Register));
 366   return MCDisassembler::Success;
 367 }
 368
 369
 370 static DecodeStatus
 371 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 372                             uint64_t Address, const void *Decoder) {
 373   if (RegNo > 31)
 374     return MCDisassembler::Fail;
 375
 376   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 377   Inst.addOperand(MCOperand::CreateReg(Register));
 378   return MCDisassembler::Success;
 379 }
 380
 381 static DecodeStatus
 382 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 383                             uint64_t Address, const void *Decoder) {
 384   if (RegNo > 31)
 385     return MCDisassembler::Fail;
 386
 387   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 388   Inst.addOperand(MCOperand::CreateReg(Register));
 389   return MCDisassembler::Success;
 390 }
 391
 392 static DecodeStatus
 393 DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 394                             uint64_t Address, const void *Decoder) {
 395   if (RegNo > 15)
 396     return MCDisassembler::Fail;
 397
 398   return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
 399 }
 400
 401 static DecodeStatus
 402 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 403                             uint64_t Address, const void *Decoder) {
 404   if (RegNo > 31)
 405     return MCDisassembler::Fail;
 406
 407   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 408   Inst.addOperand(MCOperand::CreateReg(Register));
 409   return MCDisassembler::Success;
 410 }
 411
 412 static DecodeStatus
 413 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 414                             uint64_t Address, const void *Decoder) {
 415   if (RegNo > 15)
 416     return MCDisassembler::Fail;
 417
 418   return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
 419 }
 420
 421 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
 422                                                   unsigned RegNo,
 423                                                   uint64_t Address,
 424                                                   const void *Decoder) {
 425   if (RegNo > 30)
 426     return MCDisassembler::Fail;
 427
 428   uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo);
 429   Inst.addOperand(MCOperand::CreateReg(Register));
 430   return MCDisassembler::Success;
 431 }
 432
 433 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo,
 434                                             unsigned RegID,
 435                                             const void *Decoder) {
 436   if (RegNo > 31)
 437     return MCDisassembler::Fail;
 438
 439   uint16_t Register = getReg(Decoder, RegID, RegNo);
 440   Inst.addOperand(MCOperand::CreateReg(Register));
 441   return MCDisassembler::Success;
 442 }
 443
 444 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 445                                              uint64_t Address,
 446                                              const void *Decoder) {
 447   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID,
 448                                  Decoder);
 449 }
 450
 451 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 452                                              uint64_t Address,
 453                                              const void *Decoder) {
 454   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID,
 455                                  Decoder);
 456 }
 457
 458 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
 459                                                unsigned RegNo, uint64_t Address,
 460                                                const void *Decoder) {
 461   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID,
 462                                  Decoder);
 463 }
 464
 465 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
 466                                                unsigned RegNo, uint64_t Address,
 467                                                const void *Decoder) {
 468   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID,
 469                                  Decoder);
 470 }
 471
 472 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 473                                              uint64_t Address,
 474                                              const void *Decoder) {
 475   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID,
 476                                  Decoder);
 477 }
 478
 479 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 480                                              uint64_t Address,
 481                                              const void *Decoder) {
 482   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID,
 483                                  Decoder);
 484 }
 485
 486 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 487                                                unsigned OptionHiS,
 488                                                uint64_t Address,
 489                                                const void *Decoder) {
 490   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 491   // S}. Hence we want to check bit 1.
 492   if (!(OptionHiS & 2))
 493     return MCDisassembler::Fail;
 494
 495   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 496   return MCDisassembler::Success;
 497 }
 498
 499 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 500                                                unsigned Imm6Bits,
 501                                                uint64_t Address,
 502                                                const void *Decoder) {
 503   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 504   // between 0 and 31.
 505   if (Imm6Bits > 31)
 506     return MCDisassembler::Fail;
 507
 508   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 509   return MCDisassembler::Success;
 510 }
 511
 512 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 513                                                unsigned Imm6Bits,
 514                                                uint64_t Address,
 515                                                const void *Decoder) {
 516   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 517   if (Imm6Bits < 32)
 518     return MCDisassembler::Fail;
 519
 520   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 521   return MCDisassembler::Success;
 522 }
 523
 524 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 525                                         unsigned RmBits,
 526                                         uint64_t Address,
 527                                         const void *Decoder) {
 528   // Any bits are valid in the instruction (they're architecturally ignored),
 529   // but a code generator should insert 0.
 530   Inst.addOperand(MCOperand::CreateImm(0));
 531   return MCDisassembler::Success;
 532 }
 533
 534 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 535                                          uint64_t Address,
 536                                          const void *Decoder) {
 537   Inst.addOperand(MCOperand::CreateImm(8 - Val));
 538   return MCDisassembler::Success;
 539 }
 540
 541 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 542                                           uint64_t Address,
 543                                           const void *Decoder) {
 544   Inst.addOperand(MCOperand::CreateImm(16 - Val));
 545   return MCDisassembler::Success;
 546 }
 547
 548 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 549                                           uint64_t Address,
 550                                           const void *Decoder) {
 551   Inst.addOperand(MCOperand::CreateImm(32 - Val));
 552   return MCDisassembler::Success;
 553 }
 554
 555 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 556                                           uint64_t Address,
 557                                           const void *Decoder) {
 558   Inst.addOperand(MCOperand::CreateImm(64 - Val));
 559   return MCDisassembler::Success;
 560 }
 561
 562 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
 563                                         uint64_t Address,
 564                                         const void *Decoder) {
 565   if (Val > 7)
 566     return MCDisassembler::Fail;
 567
 568   Inst.addOperand(MCOperand::CreateImm(Val));
 569   return MCDisassembler::Success;
 570 }
 571
 572 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
 573                                          uint64_t Address,
 574                                          const void *Decoder) {
 575   if (Val > 15)
 576     return MCDisassembler::Fail;
 577
 578   Inst.addOperand(MCOperand::CreateImm(Val));
 579   return MCDisassembler::Success;
 580 }
 581
 582 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
 583                                          uint64_t Address,
 584                                          const void *Decoder) {
 585   if (Val > 31)
 586     return MCDisassembler::Fail;
 587
 588   Inst.addOperand(MCOperand::CreateImm(Val));
 589   return MCDisassembler::Success;
 590 }
 591
 592 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
 593                                          uint64_t Address,
 594                                          const void *Decoder) {
 595   if (Val > 63)
 596     return MCDisassembler::Fail;
 597
 598   Inst.addOperand(MCOperand::CreateImm(Val));
 599   return MCDisassembler::Success;
 600 }
 601
 602 template<int RegWidth>
 603 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 604                                              unsigned FullImm,
 605                                              uint64_t Address,
 606                                              const void *Decoder) {
 607   unsigned Imm16 = FullImm & 0xffff;
 608   unsigned Shift = FullImm >> 16;
 609
 610   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 611
 612   Inst.addOperand(MCOperand::CreateImm(Imm16));
 613   Inst.addOperand(MCOperand::CreateImm(Shift));
 614   return MCDisassembler::Success;
 615 }
 616
 617 template<int RegWidth>
 618 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 619                                             unsigned Bits,
 620                                             uint64_t Address,
 621                                             const void *Decoder) {
 622   uint64_t Imm;
 623   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 624     return MCDisassembler::Fail;
 625
 626   Inst.addOperand(MCOperand::CreateImm(Bits));
 627   return MCDisassembler::Success;
 628 }
 629
 630
 631 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 632                                            unsigned ShiftAmount,
 633                                            uint64_t Address,
 634                                            const void *Decoder) {
 635   // Only values 0-4 are valid for this 3-bit field
 636   if (ShiftAmount > 4)
 637     return MCDisassembler::Fail;
 638
 639   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 640   return MCDisassembler::Success;
 641 }
 642
 643 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 644                                             unsigned ShiftAmount,
 645                                             uint64_t Address,
 646                                             const void *Decoder) {
 647   // Only values below 32 are valid for a 32-bit register
 648   if (ShiftAmount > 31)
 649     return MCDisassembler::Fail;
 650
 651   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 652   return MCDisassembler::Success;
 653 }
 654
 655 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 656                                               uint64_t Address,
 657                                               const void *Decoder) {
 658   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 659   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 660   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 661   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 662   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 663
 664   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 665   // out assertions that it thinks should never be hit.
 666   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 667   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 668
 669   if (!SF) {
 670     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 671     if (ImmR > 31 || ImmS > 31)
 672       return MCDisassembler::Fail;
 673   }
 674
 675   if (SF) {
 676     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 677     // BFM MCInsts use Rd as a source too.
 678     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 679     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 680   } else {
 681     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 682     // BFM MCInsts use Rd as a source too.
 683     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 684     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 685   }
 686
 687   // ASR and LSR have more specific patterns so they won't get here:
 688   assert(!(ImmS == 31 && !SF && Opc != BFM)
 689          && "shift should have used auto decode");
 690   assert(!(ImmS == 63 && SF && Opc != BFM)
 691          && "shift should have used auto decode");
 692
 693   // Extension instructions similarly:
 694   if (Opc == SBFM && ImmR == 0) {
 695     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 696     assert((ImmS != 31 || SF == 0) && "extension got here");
 697   } else if (Opc == UBFM && ImmR == 0) {
 698     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 699   }
 700
 701   if (Opc == UBFM) {
 702     // It might be a LSL instruction, which actually takes the shift amount
 703     // itself as an MCInst operand.
 704     if (SF && (ImmS + 1) % 64 == ImmR) {
 705       Inst.setOpcode(AArch64::LSLxxi);
 706       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 707       return MCDisassembler::Success;
 708     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 709       Inst.setOpcode(AArch64::LSLwwi);
 710       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 711       return MCDisassembler::Success;
 712     }
 713   }
 714
 715   // Otherwise it's definitely either an extract or an insert depending on which
 716   // of ImmR or ImmS is larger.
 717   unsigned ExtractOp, InsertOp;
 718   switch (Opc) {
 719   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 720   case SBFM:
 721     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 722     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 723     break;
 724   case BFM:
 725     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 726     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 727     break;
 728   case UBFM:
 729     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 730     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 731     break;
 732   }
 733
 734   // Otherwise it's a boring insert or extract
 735   Inst.addOperand(MCOperand::CreateImm(ImmR));
 736   Inst.addOperand(MCOperand::CreateImm(ImmS));
 737
 738
 739   if (ImmS < ImmR)
 740     Inst.setOpcode(InsertOp);
 741   else
 742     Inst.setOpcode(ExtractOp);
 743
 744   return MCDisassembler::Success;
 745 }
 746
 747 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 748                                               uint64_t Address,
 749                                               const void *Decoder) {
 750   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 751   // be 1 in assembly but has no other real manifestation.
 752   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 753   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 754   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 755
 756   if (IsToVec) {
 757     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 758     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 759   } else {
 760     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 761     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 762   }
 763
 764   // Add the lane
 765   Inst.addOperand(MCOperand::CreateImm(1));
 766
 767   return MCDisassembler::Success;
 768 }
 769
 770
 771 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 772                                               unsigned Insn,
 773                                               uint64_t Address,
 774                                               const void *Decoder) {
 775   DecodeStatus Result = MCDisassembler::Success;
 776   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 777   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 778   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 779   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 780   unsigned L = fieldFromInstruction(Insn, 22, 1);
 781   unsigned V = fieldFromInstruction(Insn, 26, 1);
 782   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 783
 784   // Not an official name, but it turns out that bit 23 distinguishes indexed
 785   // from non-indexed operations.
 786   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 787
 788   if (Indexed && L == 0) {
 789     // The MCInst for an indexed store has an out operand and 4 ins:
 790     //    Rn_wb, Rt, Rt2, Rn, Imm
 791     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 792   }
 793
 794   // You shouldn't load to the same register twice in an instruction...
 795   if (L && Rt == Rt2)
 796     Result = MCDisassembler::SoftFail;
 797
 798   // ... or do any operation that writes-back to a transfer register. But note
 799   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 800   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 801     Result = MCDisassembler::SoftFail;
 802
 803   // Exactly how we decode the MCInst's registers depends on the Opc and V
 804   // fields of the instruction. These also obviously determine the size of the
 805   // operation so we can fill in that information while we're at it.
 806   if (V) {
 807     // The instruction operates on the FP/SIMD registers
 808     switch (Opc) {
 809     default: return MCDisassembler::Fail;
 810     case 0:
 811       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 812       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 813       break;
 814     case 1:
 815       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 816       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 817       break;
 818     case 2:
 819       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 820       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 821       break;
 822     }
 823   } else {
 824     switch (Opc) {
 825     default: return MCDisassembler::Fail;
 826     case 0:
 827       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 828       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 829       break;
 830     case 1:
 831       assert(L && "unexpected \"store signed\" attempt");
 832       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 833       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 834       break;
 835     case 2:
 836       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 837       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 838       break;
 839     }
 840   }
 841
 842   if (Indexed && L == 1) {
 843     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 844     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 845     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 846   }
 847
 848
 849   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 850   Inst.addOperand(MCOperand::CreateImm(SImm7));
 851
 852   return Result;
 853 }
 854
 855 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 856                                                        uint32_t Val,
 857                                                        uint64_t Address,
 858                                                        const void *Decoder) {
 859   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 860   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 861   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 862   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 863
 864   DecodeStatus S = MCDisassembler::Success;
 865   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 866
 867   switch (MemSize) {
 868     case 2:
 869       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 870         return MCDisassembler::Fail;
 871       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 872         return MCDisassembler::Fail;
 873       break;
 874     case 3:
 875       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 876         return MCDisassembler::Fail;
 877       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 878         return MCDisassembler::Fail;
 879       break;
 880     default:
 881       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 882   }
 883
 884   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 885     return MCDisassembler::Fail;
 886
 887   return S;
 888 }
 889
 890 template<typename SomeNamedImmMapper>
 891 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 892                                           unsigned Val,
 893                                           uint64_t Address,
 894                                           const void *Decoder) {
 895   SomeNamedImmMapper Mapper;
 896   bool ValidNamed;
 897   Mapper.toString(Val, ValidNamed);
 898   if (ValidNamed || Mapper.validImm(Val)) {
 899     Inst.addOperand(MCOperand::CreateImm(Val));
 900     return MCDisassembler::Success;
 901   }
 902
 903   return MCDisassembler::Fail;
 904 }
 905
 906 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 907                                         llvm::MCInst &Inst,
 908                                         unsigned Val,
 909                                         uint64_t Address,
 910                                         const void *Decoder) {
 911   bool ValidNamed;
 912   Mapper.toString(Val, ValidNamed);
 913
 914   Inst.addOperand(MCOperand::CreateImm(Val));
 915
 916   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 917 }
 918
 919 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 920                                      unsigned Val,
 921                                      uint64_t Address,
 922                                      const void *Decoder) {
 923   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 924                              Decoder);
 925 }
 926
 927 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 928                                      unsigned Val,
 929                                      uint64_t Address,
 930                                      const void *Decoder) {
 931   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 932                              Decoder);
 933 }
 934
 935 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 936                                                    unsigned Insn,
 937                                                    uint64_t Address,
 938                                                    const void *Decoder) {
 939   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 940   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 941   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 942
 943   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 944   unsigned V = fieldFromInstruction(Insn, 26, 1);
 945   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 946
 947   if (Opc == 0 || (V == 1 && Opc == 2)) {
 948     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 949     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 950   }
 951
 952   if (V == 0 && (Opc == 2 || Size == 3)) {
 953     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 954   } else if (V == 0) {
 955     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 956   } else if (V == 1 && (Opc & 2)) {
 957     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 958   } else {
 959     switch (Size) {
 960     case 0:
 961       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 962       break;
 963     case 1:
 964       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 965       break;
 966     case 2:
 967       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 968       break;
 969     case 3:
 970       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 971       break;
 972     }
 973   }
 974
 975   if (Opc != 0 && (V != 1 || Opc != 2)) {
 976     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 977     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 978   }
 979
 980   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 981
 982   Inst.addOperand(MCOperand::CreateImm(Imm9));
 983
 984   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 985   // takes place at the architectural rather than encoding level:
 986   //
 987   // "STR xzr, [sp], #4" is perfectly valid.
 988   if (V == 0 && Rt == Rn && Rn != 31)
 989     return MCDisassembler::SoftFail;
 990   else
 991     return MCDisassembler::Success;
 992 }
 993
 994 static MCDisassembler *createAArch64Disassembler(const Target &T,
 995                                                  const MCSubtargetInfo &STI) {
 996   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 997 }
 998
 999 extern "C" void LLVMInitializeAArch64Disassembler() {
1000   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
1001                                          createAArch64Disassembler);
1002 }
1003
1004 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
1005 static DecodeStatus
1006 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
1007                              uint64_t Address, const void *Decoder) {
1008   bool IsLSL = false;
1009   if (Ext == A64SE::LSL)
1010     IsLSL = true;
1011   else if (Ext != A64SE::MSL)
1012     return MCDisassembler::Fail;
1013
1014   // MSL and LSLH accepts encoded shift amount 0 or 1.
1015   if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
1016     return MCDisassembler::Fail;
1017
1018   // LSL  accepts encoded shift amount 0, 1, 2 or 3.
1019   if (IsLSL && ShiftAmount > 3)
1020     return MCDisassembler::Fail;
1021
1022   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
1023   return MCDisassembler::Success;
1024 }
1025
1026 // Decode post-index vector load/store instructions.
1027 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last
1028 // operand is an immediate equal the the length of vector list in bytes,
1029 // or Rm is decoded to a GPR64noxzr register.
1030 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn,
1031                                                uint64_t Address,
1032                                                const void *Decoder) {
1033   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
1034   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1035   unsigned Rm = fieldFromInstruction(Insn, 16, 5);
1036   unsigned Opcode = fieldFromInstruction(Insn, 12, 4);
1037   unsigned IsLoad = fieldFromInstruction(Insn, 22, 1);
1038   // 0 for 64bit vector list, 1 for 128bit vector list
1039   unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1);
1040
1041   unsigned NumVecs;
1042   switch (Opcode) {
1043   case 0: // ld4/st4
1044   case 2: // ld1/st1 with 4 vectors
1045     NumVecs = 4; break;
1046   case 4: // ld3/st3
1047   case 6: // ld1/st1 with 3 vectors
1048     NumVecs = 3; break;
1049   case 7: // ld1/st1 with 1 vector
1050     NumVecs = 1; break;
1051   case 8:  // ld2/st2
1052   case 10: // ld1/st1 with 2 vectors
1053     NumVecs = 2; break;
1054   default:
1055     llvm_unreachable("Invalid opcode for post-index load/store instructions");
1056   }
1057
1058   // Decode vector list of 1/2/3/4 vectors for load instructions.
1059   if (IsLoad) {
1060     switch (NumVecs) {
1061     case 1:
1062       Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1063                   : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1064       break;
1065     case 2:
1066       Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1067                   : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1068       break;
1069     case 3:
1070       Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1071                   : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1072       break;
1073     case 4:
1074       Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1075                   : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1076       break;
1077     }
1078   }
1079
1080   // Decode write back register, which is equal to Rn.
1081   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1082   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1083
1084   if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte
1085     Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8)));
1086   else // Decode Rm
1087     DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1088
1089   // Decode vector list of 1/2/3/4 vectors for load instructions.
1090   if (!IsLoad) {
1091     switch (NumVecs) {
1092     case 1:
1093       Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1094                   : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1095       break;
1096     case 2:
1097       Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1098                   : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1099       break;
1100     case 3:
1101       Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1102                   : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1103       break;
1104     case 4:
1105       Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1106                   : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1107       break;
1108     }
1109   }
1110
1111   return MCDisassembler::Success;
1112 }
1113
1114 // Decode post-index vector load/store lane instructions.
1115 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last
1116 // operand is an immediate equal the the length of the changed bytes,
1117 // or Rm is decoded to a GPR64noxzr register.
1118 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
1119                                                    uint64_t Address,
1120                                                    const void *Decoder) {
1121   bool Is64bitVec = false;
1122   bool IsLoadDup = false;
1123   bool IsLoad = false;
1124   // The total number of bytes transferred.
1125   // TransferBytes = NumVecs * OneLaneBytes
1126   unsigned TransferBytes = 0;
1127   unsigned NumVecs = 0;
1128   unsigned Opc = Inst.getOpcode();
1129   switch (Opc) {
1130   case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register:
1131   case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register:
1132   case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register:
1133   case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: {
1134     switch (Opc) {
1135     case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register:
1136       TransferBytes = 1; break;
1137     case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register:
1138       TransferBytes = 2; break;
1139     case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register:
1140       TransferBytes = 4; break;
1141     case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register:
1142       TransferBytes = 8; break;
1143     }
1144     Is64bitVec = true;
1145     IsLoadDup = true;
1146     NumVecs = 1;
1147     break;
1148   }
1149
1150   case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register:
1151   case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register:
1152   case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register:
1153   case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: {
1154     switch (Opc) {
1155     case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register:
1156       TransferBytes = 1; break;
1157     case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register:
1158       TransferBytes = 2; break;
1159     case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register:
1160       TransferBytes = 4; break;
1161     case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register:
1162       TransferBytes = 8; break;
1163     }
1164     IsLoadDup = true;
1165     NumVecs = 1;
1166     break;
1167   }
1168
1169   case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register:
1170   case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register:
1171   case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register:
1172   case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: {
1173     switch (Opc) {
1174     case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register:
1175       TransferBytes = 2; break;
1176     case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register:
1177       TransferBytes = 4; break;
1178     case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register:
1179       TransferBytes = 8; break;
1180     case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register:
1181       TransferBytes = 16; break;
1182     }
1183     Is64bitVec = true;
1184     IsLoadDup = true;
1185     NumVecs = 2;
1186     break;
1187   }
1188
1189   case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register:
1190   case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register:
1191   case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register:
1192   case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: {
1193     switch (Opc) {
1194     case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register:
1195       TransferBytes = 2; break;
1196     case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register:
1197       TransferBytes = 4; break;
1198     case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register:
1199       TransferBytes = 8; break;
1200     case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register:
1201       TransferBytes = 16; break;
1202     }
1203     IsLoadDup = true;
1204     NumVecs = 2;
1205     break;
1206   }
1207
1208   case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register:
1209   case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register:
1210   case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register:
1211   case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: {
1212     switch (Opc) {
1213     case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register:
1214       TransferBytes = 3; break;
1215     case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register:
1216       TransferBytes = 6; break;
1217     case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register:
1218       TransferBytes = 12; break;
1219     case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register:
1220       TransferBytes = 24; break;
1221     }
1222     Is64bitVec = true;
1223     IsLoadDup = true;
1224     NumVecs = 3;
1225     break;
1226   }
1227
1228   case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register:
1229   case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_8H_register:
1230   case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_4S_register:
1231   case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: {
1232     switch (Opc) {
1233     case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register:
1234       TransferBytes = 3; break;
1235     case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_8H_register:
1236       TransferBytes = 6; break;
1237     case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_4S_register:
1238       TransferBytes = 12; break;
1239     case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register:
1240       TransferBytes = 24; break;
1241     }
1242     IsLoadDup = true;
1243     NumVecs = 3;
1244     break;
1245   }
1246
1247   case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register:
1248   case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register:
1249   case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register:
1250   case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: {
1251     switch (Opc) {
1252     case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register:
1253       TransferBytes = 4; break;
1254     case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register:
1255       TransferBytes = 8; break;
1256     case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register:
1257       TransferBytes = 16; break;
1258     case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register:
1259       TransferBytes = 32; break;
1260     }
1261     Is64bitVec = true;
1262     IsLoadDup = true;
1263     NumVecs = 4;
1264     break;
1265   }
1266
1267   case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register:
1268   case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_8H_register:
1269   case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_4S_register:
1270   case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: {
1271     switch (Opc) {
1272     case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register:
1273       TransferBytes = 4; break;
1274     case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_8H_register:
1275       TransferBytes = 8; break;
1276     case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_4S_register:
1277       TransferBytes = 16; break;
1278     case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register:
1279       TransferBytes = 32; break;
1280     }
1281     IsLoadDup = true;
1282     NumVecs = 4;
1283     break;
1284   }
1285
1286   case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register:
1287   case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register:
1288   case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register:
1289   case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: {
1290     switch (Opc) {
1291     case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register:
1292       TransferBytes = 1; break;
1293     case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register:
1294       TransferBytes = 2; break;
1295     case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register:
1296       TransferBytes = 4; break;
1297     case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register:
1298       TransferBytes = 8; break;
1299     }
1300     IsLoad = true;
1301     NumVecs = 1;
1302     break;
1303   }
1304
1305   case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register:
1306   case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register:
1307   case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register:
1308   case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: {
1309     switch (Opc) {
1310     case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register:
1311       TransferBytes = 2; break;
1312     case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register:
1313       TransferBytes = 4; break;
1314     case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register:
1315       TransferBytes = 8; break;
1316     case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register:
1317       TransferBytes = 16; break;
1318     }
1319     IsLoad = true;
1320     NumVecs = 2;
1321     break;
1322   }
1323
1324   case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register:
1325   case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register:
1326   case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register:
1327   case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: {
1328     switch (Opc) {
1329     case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register:
1330       TransferBytes = 3; break;
1331     case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register:
1332       TransferBytes = 6; break;
1333     case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register:
1334       TransferBytes = 12; break;
1335     case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register:
1336       TransferBytes = 24; break;
1337     }
1338     IsLoad = true;
1339     NumVecs = 3;
1340     break;
1341   }
1342
1343   case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
1344   case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
1345   case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
1346   case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
1347     switch (Opc) {
1348     case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
1349       TransferBytes = 4; break;
1350     case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
1351       TransferBytes = 8; break;
1352     case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
1353       TransferBytes = 16; break;
1354     case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
1355       TransferBytes = 32; break;
1356     }
1357     IsLoad = true;
1358     NumVecs = 4;
1359     break;
1360   }
1361
1362   case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register:
1363   case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register:
1364   case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register:
1365   case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: {
1366     switch (Opc) {
1367     case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register:
1368       TransferBytes = 1; break;
1369     case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register:
1370       TransferBytes = 2; break;
1371     case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register:
1372       TransferBytes = 4; break;
1373     case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register:
1374       TransferBytes = 8; break;
1375     }
1376     NumVecs = 1;
1377     break;
1378   }
1379
1380   case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register:
1381   case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register:
1382   case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register:
1383   case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: {
1384     switch (Opc) {
1385     case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register:
1386       TransferBytes = 2; break;
1387     case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register:
1388       TransferBytes = 4; break;
1389     case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register:
1390       TransferBytes = 8; break;
1391     case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register:
1392       TransferBytes = 16; break;
1393     }
1394     NumVecs = 2;
1395     break;
1396   }
1397
1398   case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register:
1399   case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register:
1400   case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register:
1401   case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: {
1402     switch (Opc) {
1403     case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register:
1404       TransferBytes = 3; break;
1405     case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register:
1406       TransferBytes = 6; break;
1407     case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register:
1408       TransferBytes = 12; break;
1409     case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register:
1410       TransferBytes = 24; break;
1411     }
1412     NumVecs = 3;
1413     break;
1414   }
1415
1416   case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register:
1417   case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register:
1418   case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register:
1419   case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: {
1420     switch (Opc) {
1421     case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register:
1422       TransferBytes = 4; break;
1423     case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register:
1424       TransferBytes = 8; break;
1425     case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register:
1426       TransferBytes = 16; break;
1427     case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register:
1428       TransferBytes = 32; break;
1429     }
1430     NumVecs = 4;
1431     break;
1432   }
1433
1434   default:
1435     return MCDisassembler::Fail;
1436   } // End of switch (Opc)
1437
1438   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
1439   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1440   unsigned Rm = fieldFromInstruction(Insn, 16, 5);
1441
1442   // Decode post-index of load duplicate lane
1443   if (IsLoadDup) {
1444     switch (NumVecs) {
1445     case 1:
1446       Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder)
1447                  : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1448       break;
1449     case 2:
1450       Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder)
1451                  : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1452       break;
1453     case 3:
1454       Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder)
1455                  : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1456       break;
1457     case 4:
1458       Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder)
1459                  : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1460     }
1461
1462     // Decode write back register, which is equal to Rn.
1463     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1464     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1465
1466     if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
1467       Inst.addOperand(MCOperand::CreateImm(TransferBytes));
1468     else // Decode Rm
1469       DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1470
1471     return MCDisassembler::Success;
1472   }
1473
1474   // Decode post-index of load/store lane
1475   // Loads have a vector list as output.
1476   if (IsLoad) {
1477     switch (NumVecs) {
1478     case 1:
1479       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1480       break;
1481     case 2:
1482       DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1483       break;
1484     case 3:
1485       DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1486       break;
1487     case 4:
1488       DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1489     }
1490   }
1491
1492   // Decode write back register, which is equal to Rn.
1493   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1494   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1495
1496   if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
1497     Inst.addOperand(MCOperand::CreateImm(TransferBytes));
1498   else // Decode Rm
1499     DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1500
1501   // Decode the source vector list.
1502   switch (NumVecs) {
1503   case 1:
1504     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1505     break;
1506   case 2:
1507     DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1508     break;
1509   case 3:
1510     DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1511     break;
1512   case 4:
1513     DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1514   }
1515
1516   // Decode lane
1517   unsigned Q = fieldFromInstruction(Insn, 30, 1);
1518   unsigned S = fieldFromInstruction(Insn, 10, 3);
1519   unsigned lane = 0;
1520   // Calculate the number of lanes by number of vectors and transfered bytes.
1521   // NumLanes = 16 bytes / bytes of each lane
1522   unsigned NumLanes = 16 / (TransferBytes / NumVecs);
1523   switch (NumLanes) {
1524   case 16: // A vector has 16 lanes, each lane is 1 bytes.
1525     lane = (Q << 3) | S;
1526     break;
1527   case 8:
1528     lane = (Q << 2) | (S >> 1);
1529     break;
1530   case 4:
1531     lane = (Q << 1) | (S >> 2);
1532     break;
1533   case 2:
1534     lane = Q;
1535     break;
1536   }
1537   Inst.addOperand(MCOperand::CreateImm(lane));
1538
1539   return MCDisassembler::Success;
1540 }
1541
1542 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
1543                                           uint64_t Address,
1544                                           const void *Decoder) {
1545   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
1546   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1547   unsigned size = fieldFromInstruction(Insn, 22, 2);
1548   unsigned Q = fieldFromInstruction(Insn, 30, 1);
1549
1550   DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
1551
1552   if(Q)
1553     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
1554   else
1555     DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
1556
1557   switch (size) {
1558   case 0:
1559     Inst.addOperand(MCOperand::CreateImm(8));
1560     break;
1561   case 1:
1562     Inst.addOperand(MCOperand::CreateImm(16));
1563     break;
1564   case 2:
1565     Inst.addOperand(MCOperand::CreateImm(32));
1566     break;
1567   default :
1568     return MCDisassembler::Fail;
1569   }
1570   return MCDisassembler::Success;
1571 }
1572