1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetFrameInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetLowering.h"
50 #include "llvm/Target/TargetMachine.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MathExtras.h"
56 #include "llvm/Support/Timer.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/ADT/Statistic.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
67 cl::desc("Enable verbose messages in the \"fast\" "
68 "instruction selector"));
70 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
71 cl::desc("Enable abort calls when \"fast\" instruction fails"));
73 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
74 cl::desc("Schedule copies of livein registers"),
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createFastDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 assert(TLI.getSchedulingPreference() ==
150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
151 return createBURRListDAGScheduler(IS, OptLevel);
155 // EmitInstrWithCustomInserter - This method should be implemented by targets
156 // that mark instructions with the 'usesCustomInserter' flag. These
157 // instructions are special in various ways, which require special support to
158 // insert. The specified MachineInstr is created but not inserted into any
159 // basic blocks, and this method is called to expand it into a sequence of
160 // instructions, potentially also creating new basic blocks and control flow.
161 // When new basic blocks are inserted and the edges from MBB to its successors
162 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
164 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
165 MachineBasicBlock *MBB,
166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
168 dbgs() << "If a target marks an instruction with "
169 "'usesCustomInserter', it must implement "
170 "TargetLowering::EmitInstrWithCustomInserter!";
176 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
177 /// physical register has only a single copy use, then coalesced the copy
179 static void EmitLiveInCopy(MachineBasicBlock *MBB,
180 MachineBasicBlock::iterator &InsertPos,
181 unsigned VirtReg, unsigned PhysReg,
182 const TargetRegisterClass *RC,
183 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
184 const MachineRegisterInfo &MRI,
185 const TargetRegisterInfo &TRI,
186 const TargetInstrInfo &TII) {
187 unsigned NumUses = 0;
188 MachineInstr *UseMI = NULL;
189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
190 UE = MRI.use_end(); UI != UE; ++UI) {
196 // If the number of uses is not one, or the use is not a move instruction,
197 // don't coalesce. Also, only coalesce away a virtual register to virtual
199 bool Coalesced = false;
200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
203 TargetRegisterInfo::isVirtualRegister(DstReg)) {
208 // Now find an ideal location to insert the copy.
209 MachineBasicBlock::iterator Pos = InsertPos;
210 while (Pos != MBB->begin()) {
211 MachineInstr *PrevMI = prior(Pos);
212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
213 // copyRegToReg might emit multiple instructions to do a copy.
214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
216 // This is what the BB looks like right now:
221 // We want to insert "r1025 = mov r1". Inserting this copy below the
222 // move to r1024 makes it impossible for that move to be coalesced.
229 break; // Woot! Found a good location.
233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
234 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
239 if (&*InsertPos == UseMI) ++InsertPos;
244 /// EmitLiveInCopies - If this is the first basic block in the function,
245 /// and if it has live ins that need to be copied into vregs, emit the
246 /// copies into the block.
247 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
248 const MachineRegisterInfo &MRI,
249 const TargetRegisterInfo &TRI,
250 const TargetInstrInfo &TII) {
251 if (SchedLiveInCopies) {
252 // Emit the copies at a heuristically-determined location in the block.
253 DenseMap<MachineInstr*, unsigned> CopyRegMap;
254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
256 E = MRI.livein_end(); LI != E; ++LI)
258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
260 RC, CopyRegMap, MRI, TRI, TII);
263 // Emit the copies into the top of the block.
264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
265 E = MRI.livein_end(); LI != E; ++LI)
267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
269 LI->second, LI->first, RC, RC);
270 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
276 //===----------------------------------------------------------------------===//
277 // SelectionDAGISel code
278 //===----------------------------------------------------------------------===//
280 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
282 FuncInfo(new FunctionLoweringInfo(TLI)),
283 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
290 SelectionDAGISel::~SelectionDAGISel() {
296 unsigned SelectionDAGISel::MakeReg(EVT VT) {
297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 MachineFunctionPass::getAnalysisUsage(AU);
308 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
309 Function &Fn = *mf.getFunction();
311 // Do some sanity-checking on the command-line options.
312 assert((!EnableFastISelVerbose || EnableFastISel) &&
313 "-fast-isel-verbose requires -fast-isel");
314 assert((!EnableFastISelAbort || EnableFastISel) &&
315 "-fast-isel-abort requires -fast-isel");
317 // Get alias analysis for load/store combining.
318 AA = &getAnalysis<AliasAnalysis>();
321 const TargetInstrInfo &TII = *TM.getInstrInfo();
322 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
325 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
328 RegInfo = &MF->getRegInfo();
329 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
332 FuncInfo->set(Fn, *MF, EnableFastISel);
335 SelectAllBasicBlocks(Fn, *MF, TII);
337 // If the first basic block in the function has live ins that need to be
338 // copied into vregs, emit the copies into the top of the block before
339 // emitting the code for the block.
340 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
342 // Add function live-ins to entry block live-in set.
343 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
344 E = RegInfo->livein_end(); I != E; ++I)
345 MF->begin()->addLiveIn(I->first);
348 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
349 "Not all catch info was assigned to a landing pad!");
357 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
358 /// attached with this instruction.
359 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
360 FastISel *FastIS, MachineFunction *MF) {
361 DebugLoc DL = I->getDebugLoc();
362 if (DL.isUnknown()) return;
364 SDB->setCurDebugLoc(DL);
367 FastIS->setCurDebugLoc(DL);
369 // If the function doesn't have a default debug location yet, set
370 // it. This is kind of a hack.
371 if (MF->getDefaultDebugLoc().isUnknown())
372 MF->setDefaultDebugLoc(DL);
375 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
376 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
377 SDB->setCurDebugLoc(DebugLoc());
379 FastIS->setCurDebugLoc(DebugLoc());
382 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
383 BasicBlock::iterator Begin,
384 BasicBlock::iterator End,
386 SDB->setCurrentBasicBlock(BB);
388 // Lower all of the non-terminator instructions. If a call is emitted
389 // as a tail call, cease emitting nodes for this block.
390 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
391 SetDebugLoc(I, SDB, 0, MF);
393 if (!isa<TerminatorInst>(I)) {
396 // Set the current debug location back to "unknown" so that it doesn't
397 // spuriously apply to subsequent instructions.
398 ResetDebugLoc(SDB, 0);
402 if (!SDB->HasTailCall) {
403 // Ensure that all instructions which are used outside of their defining
404 // blocks are available as virtual registers. Invoke is handled elsewhere.
405 for (BasicBlock::iterator I = Begin; I != End; ++I)
406 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
407 SDB->CopyToExportRegsIfNeeded(I);
409 // Handle PHI nodes in successor blocks.
410 if (End == LLVMBB->end()) {
411 HandlePHINodesInSuccessorBlocks(LLVMBB);
413 // Lower the terminator after the copies are emitted.
414 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
415 SDB->visit(*LLVMBB->getTerminator());
416 ResetDebugLoc(SDB, 0);
420 // Make sure the root of the DAG is up-to-date.
421 CurDAG->setRoot(SDB->getControlRoot());
423 // Final step, emit the lowered DAG as machine code.
425 HadTailCall = SDB->HasTailCall;
430 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
431 /// nodes from the worklist.
432 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
433 SmallVector<SDNode*, 128> &Worklist;
434 SmallPtrSet<SDNode*, 128> &InWorklist;
436 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
437 SmallPtrSet<SDNode*, 128> &inwl)
438 : Worklist(wl), InWorklist(inwl) {}
440 void RemoveFromWorklist(SDNode *N) {
441 if (!InWorklist.erase(N)) return;
443 SmallVector<SDNode*, 128>::iterator I =
444 std::find(Worklist.begin(), Worklist.end(), N);
445 assert(I != Worklist.end() && "Not in worklist");
447 *I = Worklist.back();
451 virtual void NodeDeleted(SDNode *N, SDNode *E) {
452 RemoveFromWorklist(N);
455 virtual void NodeUpdated(SDNode *N) {
461 /// TrivialTruncElim - Eliminate some trivial nops that can result from
462 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
463 static bool TrivialTruncElim(SDValue Op,
464 TargetLowering::TargetLoweringOpt &TLO) {
465 SDValue N0 = Op.getOperand(0);
466 EVT VT = Op.getValueType();
467 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
468 N0.getOpcode() == ISD::SIGN_EXTEND ||
469 N0.getOpcode() == ISD::ANY_EXTEND) &&
470 N0.getOperand(0).getValueType() == VT) {
471 return TLO.CombineTo(Op, N0.getOperand(0));
476 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
477 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
478 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
479 void SelectionDAGISel::ShrinkDemandedOps() {
480 SmallVector<SDNode*, 128> Worklist;
481 SmallPtrSet<SDNode*, 128> InWorklist;
483 // Add all the dag nodes to the worklist.
484 Worklist.reserve(CurDAG->allnodes_size());
485 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
486 E = CurDAG->allnodes_end(); I != E; ++I) {
487 Worklist.push_back(I);
488 InWorklist.insert(I);
491 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
492 while (!Worklist.empty()) {
493 SDNode *N = Worklist.pop_back_val();
496 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
497 // Deleting this node may make its operands dead, add them to the worklist
498 // if they aren't already there.
499 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
500 if (InWorklist.insert(N->getOperand(i).getNode()))
501 Worklist.push_back(N->getOperand(i).getNode());
503 CurDAG->DeleteNode(N);
507 // Run ShrinkDemandedOp on scalar binary operations.
508 if (N->getNumValues() != 1 ||
509 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
512 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
513 APInt Demanded = APInt::getAllOnesValue(BitWidth);
514 APInt KnownZero, KnownOne;
515 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
516 KnownZero, KnownOne, TLO) &&
517 (N->getOpcode() != ISD::TRUNCATE ||
518 !TrivialTruncElim(SDValue(N, 0), TLO)))
522 assert(!InWorklist.count(N) && "Already in worklist");
523 Worklist.push_back(N);
524 InWorklist.insert(N);
526 // Replace the old value with the new one.
527 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
528 TLO.Old.getNode()->dump(CurDAG);
529 errs() << "\nWith: ";
530 TLO.New.getNode()->dump(CurDAG);
533 if (InWorklist.insert(TLO.New.getNode()))
534 Worklist.push_back(TLO.New.getNode());
536 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
537 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
539 if (!TLO.Old.getNode()->use_empty()) continue;
541 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
543 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
544 if (OpNode->hasOneUse()) {
545 // Add OpNode to the end of the list to revisit.
546 DeadNodes.RemoveFromWorklist(OpNode);
547 Worklist.push_back(OpNode);
548 InWorklist.insert(OpNode);
552 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
553 CurDAG->DeleteNode(TLO.Old.getNode());
557 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
558 SmallPtrSet<SDNode*, 128> VisitedNodes;
559 SmallVector<SDNode*, 128> Worklist;
561 Worklist.push_back(CurDAG->getRoot().getNode());
568 SDNode *N = Worklist.pop_back_val();
570 // If we've already seen this node, ignore it.
571 if (!VisitedNodes.insert(N))
574 // Otherwise, add all chain operands to the worklist.
575 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
576 if (N->getOperand(i).getValueType() == MVT::Other)
577 Worklist.push_back(N->getOperand(i).getNode());
579 // If this is a CopyToReg with a vreg dest, process it.
580 if (N->getOpcode() != ISD::CopyToReg)
583 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
584 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
587 // Ignore non-scalar or non-integer values.
588 SDValue Src = N->getOperand(2);
589 EVT SrcVT = Src.getValueType();
590 if (!SrcVT.isInteger() || SrcVT.isVector())
593 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
594 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
595 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
597 // Only install this information if it tells us something.
598 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
599 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
600 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
601 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
602 FunctionLoweringInfo::LiveOutInfo &LOI =
603 FuncInfo->LiveOutRegInfo[DestReg];
604 LOI.NumSignBits = NumSignBits;
605 LOI.KnownOne = KnownOne;
606 LOI.KnownZero = KnownZero;
608 } while (!Worklist.empty());
611 void SelectionDAGISel::CodeGenAndEmitDAG() {
612 std::string GroupName;
613 if (TimePassesIsEnabled)
614 GroupName = "Instruction Selection and Scheduling";
615 std::string BlockName;
616 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
617 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
619 BlockName = MF->getFunction()->getNameStr() + ":" +
620 BB->getBasicBlock()->getNameStr();
622 DEBUG(dbgs() << "Initial selection DAG:\n");
623 DEBUG(CurDAG->dump());
625 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
627 // Run the DAG combiner in pre-legalize mode.
628 if (TimePassesIsEnabled) {
629 NamedRegionTimer T("DAG Combining 1", GroupName);
630 CurDAG->Combine(Unrestricted, *AA, OptLevel);
632 CurDAG->Combine(Unrestricted, *AA, OptLevel);
635 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
636 DEBUG(CurDAG->dump());
638 // Second step, hack on the DAG until it only uses operations and types that
639 // the target supports.
640 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
644 if (TimePassesIsEnabled) {
645 NamedRegionTimer T("Type Legalization", GroupName);
646 Changed = CurDAG->LegalizeTypes();
648 Changed = CurDAG->LegalizeTypes();
651 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
652 DEBUG(CurDAG->dump());
655 if (ViewDAGCombineLT)
656 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
658 // Run the DAG combiner in post-type-legalize mode.
659 if (TimePassesIsEnabled) {
660 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
661 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
663 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
666 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
667 DEBUG(CurDAG->dump());
670 if (TimePassesIsEnabled) {
671 NamedRegionTimer T("Vector Legalization", GroupName);
672 Changed = CurDAG->LegalizeVectors();
674 Changed = CurDAG->LegalizeVectors();
678 if (TimePassesIsEnabled) {
679 NamedRegionTimer T("Type Legalization 2", GroupName);
680 CurDAG->LegalizeTypes();
682 CurDAG->LegalizeTypes();
685 if (ViewDAGCombineLT)
686 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
688 // Run the DAG combiner in post-type-legalize mode.
689 if (TimePassesIsEnabled) {
690 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
691 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
693 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
696 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
697 DEBUG(CurDAG->dump());
700 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
702 if (TimePassesIsEnabled) {
703 NamedRegionTimer T("DAG Legalization", GroupName);
704 CurDAG->Legalize(OptLevel);
706 CurDAG->Legalize(OptLevel);
709 DEBUG(dbgs() << "Legalized selection DAG:\n");
710 DEBUG(CurDAG->dump());
712 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
714 // Run the DAG combiner in post-legalize mode.
715 if (TimePassesIsEnabled) {
716 NamedRegionTimer T("DAG Combining 2", GroupName);
717 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
719 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
722 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
723 DEBUG(CurDAG->dump());
725 if (OptLevel != CodeGenOpt::None) {
727 ComputeLiveOutVRegInfo();
730 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
732 // Third, instruction select all of the operations to machine code, adding the
733 // code to the MachineBasicBlock.
734 if (TimePassesIsEnabled) {
735 NamedRegionTimer T("Instruction Selection", GroupName);
736 DoInstructionSelection();
738 DoInstructionSelection();
741 DEBUG(dbgs() << "Selected selection DAG:\n");
742 DEBUG(CurDAG->dump());
744 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
746 // Schedule machine code.
747 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
748 if (TimePassesIsEnabled) {
749 NamedRegionTimer T("Instruction Scheduling", GroupName);
750 Scheduler->Run(CurDAG, BB, BB->end());
752 Scheduler->Run(CurDAG, BB, BB->end());
755 if (ViewSUnitDAGs) Scheduler->viewGraph();
757 // Emit machine code to BB. This can change 'BB' to the last block being
759 if (TimePassesIsEnabled) {
760 NamedRegionTimer T("Instruction Creation", GroupName);
761 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
763 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
766 // Free the scheduler state.
767 if (TimePassesIsEnabled) {
768 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
774 DEBUG(dbgs() << "Selected machine code:\n");
778 void SelectionDAGISel::DoInstructionSelection() {
779 DEBUG(errs() << "===== Instruction selection begins:\n");
783 // Select target instructions for the DAG.
785 // Number all nodes with a topological order and set DAGSize.
786 DAGSize = CurDAG->AssignTopologicalOrder();
788 // Create a dummy node (which is not added to allnodes), that adds
789 // a reference to the root node, preventing it from being deleted,
790 // and tracking any changes of the root.
791 HandleSDNode Dummy(CurDAG->getRoot());
792 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
795 // The AllNodes list is now topological-sorted. Visit the
796 // nodes by starting at the end of the list (the root of the
797 // graph) and preceding back toward the beginning (the entry
799 while (ISelPosition != CurDAG->allnodes_begin()) {
800 SDNode *Node = --ISelPosition;
801 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
802 // but there are currently some corner cases that it misses. Also, this
803 // makes it theoretically possible to disable the DAGCombiner.
804 if (Node->use_empty())
807 SDNode *ResNode = Select(Node);
809 // FIXME: This is pretty gross. 'Select' should be changed to not return
810 // anything at all and this code should be nuked with a tactical strike.
812 // If node should not be replaced, continue with the next one.
813 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
817 ReplaceUses(Node, ResNode);
819 // If after the replacement this node is not used any more,
820 // remove this dead node.
821 if (Node->use_empty()) { // Don't delete EntryToken, etc.
822 ISelUpdater ISU(ISelPosition);
823 CurDAG->RemoveDeadNode(Node, &ISU);
827 CurDAG->setRoot(Dummy.getValue());
829 DEBUG(errs() << "===== Instruction selection ends:\n");
831 PostprocessISelDAG();
835 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
837 const TargetInstrInfo &TII) {
838 // Initialize the Fast-ISel state, if needed.
839 FastISel *FastIS = 0;
841 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
842 FuncInfo->StaticAllocaMap
844 , FuncInfo->CatchInfoLost
848 // Iterate over all basic blocks in the function.
849 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
850 BasicBlock *LLVMBB = &*I;
851 BB = FuncInfo->MBBMap[LLVMBB];
853 BasicBlock::iterator const Begin = LLVMBB->begin();
854 BasicBlock::iterator const End = LLVMBB->end();
855 BasicBlock::iterator BI = Begin;
857 // Lower any arguments needed in this block if this is the entry block.
858 bool SuppressFastISel = false;
859 if (LLVMBB == &Fn.getEntryBlock()) {
860 LowerArguments(LLVMBB);
862 // If any of the arguments has the byval attribute, forgo
863 // fast-isel in the entry block.
866 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
868 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
869 if (EnableFastISelVerbose || EnableFastISelAbort)
870 dbgs() << "FastISel skips entry block due to byval argument\n";
871 SuppressFastISel = true;
877 if (BB->isLandingPad()) {
878 // Add a label to mark the beginning of the landing pad. Deletion of the
879 // landing pad can thus be detected via the MachineModuleInfo.
880 MCSymbol *Label = MF.getMMI().addLandingPad(BB);
882 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
883 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
885 // Mark exception register as live in.
886 unsigned Reg = TLI.getExceptionAddressRegister();
887 if (Reg) BB->addLiveIn(Reg);
889 // Mark exception selector register as live in.
890 Reg = TLI.getExceptionSelectorRegister();
891 if (Reg) BB->addLiveIn(Reg);
893 // FIXME: Hack around an exception handling flaw (PR1508): the personality
894 // function and list of typeids logically belong to the invoke (or, if you
895 // like, the basic block containing the invoke), and need to be associated
896 // with it in the dwarf exception handling tables. Currently however the
897 // information is provided by an intrinsic (eh.selector) that can be moved
898 // to unexpected places by the optimizers: if the unwind edge is critical,
899 // then breaking it can result in the intrinsics being in the successor of
900 // the landing pad, not the landing pad itself. This results
901 // in exceptions not being caught because no typeids are associated with
902 // the invoke. This may not be the only way things can go wrong, but it
903 // is the only way we try to work around for the moment.
904 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
906 if (Br && Br->isUnconditional()) { // Critical edge?
907 BasicBlock::iterator I, E;
908 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
909 if (isa<EHSelectorInst>(I))
913 // No catch info found - try to extract some from the successor.
914 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo);
918 // Before doing SelectionDAG ISel, see if FastISel has been requested.
919 if (FastIS && !SuppressFastISel) {
920 // Emit code for any incoming arguments. This must happen before
921 // beginning FastISel on the entry block.
922 if (LLVMBB == &Fn.getEntryBlock()) {
923 CurDAG->setRoot(SDB->getControlRoot());
927 FastIS->startNewBlock(BB);
928 // Do FastISel on as many instructions as possible.
929 for (; BI != End; ++BI) {
930 // Just before the terminator instruction, insert instructions to
931 // feed PHI nodes in successor blocks.
932 if (isa<TerminatorInst>(BI))
933 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
934 ++NumFastIselFailures;
935 ResetDebugLoc(SDB, FastIS);
936 if (EnableFastISelVerbose || EnableFastISelAbort) {
937 dbgs() << "FastISel miss: ";
940 assert(!EnableFastISelAbort &&
941 "FastISel didn't handle a PHI in a successor");
945 SetDebugLoc(BI, SDB, FastIS, &MF);
947 // Try to select the instruction with FastISel.
948 if (FastIS->SelectInstruction(BI)) {
949 ResetDebugLoc(SDB, FastIS);
953 // Clear out the debug location so that it doesn't carry over to
954 // unrelated instructions.
955 ResetDebugLoc(SDB, FastIS);
957 // Then handle certain instructions as single-LLVM-Instruction blocks.
958 if (isa<CallInst>(BI)) {
959 ++NumFastIselFailures;
960 if (EnableFastISelVerbose || EnableFastISelAbort) {
961 dbgs() << "FastISel missed call: ";
965 if (!BI->getType()->isVoidTy()) {
966 unsigned &R = FuncInfo->ValueMap[BI];
968 R = FuncInfo->CreateRegForValue(BI);
971 bool HadTailCall = false;
972 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
974 // If the call was emitted as a tail call, we're done with the block.
980 // If the instruction was codegen'd with multiple blocks,
981 // inform the FastISel object where to resume inserting.
982 FastIS->setCurrentBlock(BB);
986 // Otherwise, give up on FastISel for the rest of the block.
987 // For now, be a little lenient about non-branch terminators.
988 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
989 ++NumFastIselFailures;
990 if (EnableFastISelVerbose || EnableFastISelAbort) {
991 dbgs() << "FastISel miss: ";
994 if (EnableFastISelAbort)
995 // The "fast" selector couldn't handle something and bailed.
996 // For the purpose of debugging, just abort.
997 llvm_unreachable("FastISel didn't select the entire block");
1003 // Run SelectionDAG instruction selection on the remainder of the block
1004 // not handled by FastISel. If FastISel is not run, this is the entire
1008 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1018 SelectionDAGISel::FinishBasicBlock() {
1020 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1023 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1024 << SDB->PHINodesToUpdate.size() << "\n");
1025 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1026 dbgs() << "Node " << i << " : ("
1027 << SDB->PHINodesToUpdate[i].first
1028 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1030 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1031 // PHI nodes in successors.
1032 if (SDB->SwitchCases.empty() &&
1033 SDB->JTCases.empty() &&
1034 SDB->BitTestCases.empty()) {
1035 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1036 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1037 assert(PHI->isPHI() &&
1038 "This is not a machine PHI node that we are updating!");
1039 if (!BB->isSuccessor(PHI->getParent()))
1041 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1043 PHI->addOperand(MachineOperand::CreateMBB(BB));
1045 SDB->PHINodesToUpdate.clear();
1049 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1050 // Lower header first, if it wasn't already lowered
1051 if (!SDB->BitTestCases[i].Emitted) {
1052 // Set the current basic block to the mbb we wish to insert the code into
1053 BB = SDB->BitTestCases[i].Parent;
1054 SDB->setCurrentBasicBlock(BB);
1056 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1057 CurDAG->setRoot(SDB->getRoot());
1058 CodeGenAndEmitDAG();
1062 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1063 // Set the current basic block to the mbb we wish to insert the code into
1064 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1065 SDB->setCurrentBasicBlock(BB);
1068 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1069 SDB->BitTestCases[i].Reg,
1070 SDB->BitTestCases[i].Cases[j]);
1072 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1073 SDB->BitTestCases[i].Reg,
1074 SDB->BitTestCases[i].Cases[j]);
1077 CurDAG->setRoot(SDB->getRoot());
1078 CodeGenAndEmitDAG();
1083 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1084 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1085 MachineBasicBlock *PHIBB = PHI->getParent();
1086 assert(PHI->isPHI() &&
1087 "This is not a machine PHI node that we are updating!");
1088 // This is "default" BB. We have two jumps to it. From "header" BB and
1089 // from last "case" BB.
1090 if (PHIBB == SDB->BitTestCases[i].Default) {
1091 PHI->addOperand(MachineOperand::
1092 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1093 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1094 PHI->addOperand(MachineOperand::
1095 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1096 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1099 // One of "cases" BB.
1100 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1102 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1103 if (cBB->isSuccessor(PHIBB)) {
1104 PHI->addOperand(MachineOperand::
1105 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1106 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1111 SDB->BitTestCases.clear();
1113 // If the JumpTable record is filled in, then we need to emit a jump table.
1114 // Updating the PHI nodes is tricky in this case, since we need to determine
1115 // whether the PHI is a successor of the range check MBB or the jump table MBB
1116 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1117 // Lower header first, if it wasn't already lowered
1118 if (!SDB->JTCases[i].first.Emitted) {
1119 // Set the current basic block to the mbb we wish to insert the code into
1120 BB = SDB->JTCases[i].first.HeaderBB;
1121 SDB->setCurrentBasicBlock(BB);
1123 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1124 CurDAG->setRoot(SDB->getRoot());
1125 CodeGenAndEmitDAG();
1129 // Set the current basic block to the mbb we wish to insert the code into
1130 BB = SDB->JTCases[i].second.MBB;
1131 SDB->setCurrentBasicBlock(BB);
1133 SDB->visitJumpTable(SDB->JTCases[i].second);
1134 CurDAG->setRoot(SDB->getRoot());
1135 CodeGenAndEmitDAG();
1139 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1140 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1141 MachineBasicBlock *PHIBB = PHI->getParent();
1142 assert(PHI->isPHI() &&
1143 "This is not a machine PHI node that we are updating!");
1144 // "default" BB. We can go there only from header BB.
1145 if (PHIBB == SDB->JTCases[i].second.Default) {
1147 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1149 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1151 // JT BB. Just iterate over successors here
1152 if (BB->isSuccessor(PHIBB)) {
1154 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1155 PHI->addOperand(MachineOperand::CreateMBB(BB));
1159 SDB->JTCases.clear();
1161 // If the switch block involved a branch to one of the actual successors, we
1162 // need to update PHI nodes in that block.
1163 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1164 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1165 assert(PHI->isPHI() &&
1166 "This is not a machine PHI node that we are updating!");
1167 if (BB->isSuccessor(PHI->getParent())) {
1168 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1170 PHI->addOperand(MachineOperand::CreateMBB(BB));
1174 // If we generated any switch lowering information, build and codegen any
1175 // additional DAGs necessary.
1176 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1177 // Set the current basic block to the mbb we wish to insert the code into
1178 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1179 SDB->setCurrentBasicBlock(BB);
1182 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1183 CurDAG->setRoot(SDB->getRoot());
1184 CodeGenAndEmitDAG();
1186 // Handle any PHI nodes in successors of this chunk, as if we were coming
1187 // from the original BB before switch expansion. Note that PHI nodes can
1188 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1189 // handle them the right number of times.
1190 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1191 // If new BB's are created during scheduling, the edges may have been
1192 // updated. That is, the edge from ThisBB to BB may have been split and
1193 // BB's predecessor is now another block.
1194 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1195 SDB->EdgeMapping.find(BB);
1196 if (EI != SDB->EdgeMapping.end())
1197 ThisBB = EI->second;
1199 // BB may have been removed from the CFG if a branch was constant folded.
1200 if (ThisBB->isSuccessor(BB)) {
1201 for (MachineBasicBlock::iterator Phi = BB->begin();
1202 Phi != BB->end() && Phi->isPHI();
1204 // This value for this PHI node is recorded in PHINodesToUpdate.
1205 for (unsigned pn = 0; ; ++pn) {
1206 assert(pn != SDB->PHINodesToUpdate.size() &&
1207 "Didn't find PHI entry!");
1208 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1209 Phi->addOperand(MachineOperand::
1210 CreateReg(SDB->PHINodesToUpdate[pn].second,
1212 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1219 // Don't process RHS if same block as LHS.
1220 if (BB == SDB->SwitchCases[i].FalseBB)
1221 SDB->SwitchCases[i].FalseBB = 0;
1223 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1224 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1225 SDB->SwitchCases[i].FalseBB = 0;
1227 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1230 SDB->SwitchCases.clear();
1232 SDB->PHINodesToUpdate.clear();
1236 /// Create the scheduler. If a specific scheduler was specified
1237 /// via the SchedulerRegistry, use it, otherwise select the
1238 /// one preferred by the target.
1240 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1241 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1245 RegisterScheduler::setDefault(Ctor);
1248 return Ctor(this, OptLevel);
1251 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1252 return new ScheduleHazardRecognizer();
1255 //===----------------------------------------------------------------------===//
1256 // Helper functions used by the generated instruction selector.
1257 //===----------------------------------------------------------------------===//
1258 // Calls to these methods are generated by tblgen.
1260 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1261 /// the dag combiner simplified the 255, we still want to match. RHS is the
1262 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1263 /// specified in the .td file (e.g. 255).
1264 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1265 int64_t DesiredMaskS) const {
1266 const APInt &ActualMask = RHS->getAPIntValue();
1267 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1269 // If the actual mask exactly matches, success!
1270 if (ActualMask == DesiredMask)
1273 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1274 if (ActualMask.intersects(~DesiredMask))
1277 // Otherwise, the DAG Combiner may have proven that the value coming in is
1278 // either already zero or is not demanded. Check for known zero input bits.
1279 APInt NeededMask = DesiredMask & ~ActualMask;
1280 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1283 // TODO: check to see if missing bits are just not demanded.
1285 // Otherwise, this pattern doesn't match.
1289 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1290 /// the dag combiner simplified the 255, we still want to match. RHS is the
1291 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1292 /// specified in the .td file (e.g. 255).
1293 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1294 int64_t DesiredMaskS) const {
1295 const APInt &ActualMask = RHS->getAPIntValue();
1296 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1298 // If the actual mask exactly matches, success!
1299 if (ActualMask == DesiredMask)
1302 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1303 if (ActualMask.intersects(~DesiredMask))
1306 // Otherwise, the DAG Combiner may have proven that the value coming in is
1307 // either already zero or is not demanded. Check for known zero input bits.
1308 APInt NeededMask = DesiredMask & ~ActualMask;
1310 APInt KnownZero, KnownOne;
1311 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1313 // If all the missing bits in the or are already known to be set, match!
1314 if ((NeededMask & KnownOne) == NeededMask)
1317 // TODO: check to see if missing bits are just not demanded.
1319 // Otherwise, this pattern doesn't match.
1324 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1325 /// by tblgen. Others should not call it.
1326 void SelectionDAGISel::
1327 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1328 std::vector<SDValue> InOps;
1329 std::swap(InOps, Ops);
1331 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1332 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1333 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1335 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1336 if (InOps[e-1].getValueType() == MVT::Flag)
1337 --e; // Don't process a flag operand if it is here.
1340 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1341 if (!InlineAsm::isMemKind(Flags)) {
1342 // Just skip over this operand, copying the operands verbatim.
1343 Ops.insert(Ops.end(), InOps.begin()+i,
1344 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1345 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1347 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1348 "Memory operand with multiple values?");
1349 // Otherwise, this is a memory operand. Ask the target to select it.
1350 std::vector<SDValue> SelOps;
1351 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1352 report_fatal_error("Could not match memory address. Inline asm"
1355 // Add this to the output node.
1357 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1358 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1359 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1364 // Add the flag input back if present.
1365 if (e != InOps.size())
1366 Ops.push_back(InOps.back());
1369 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1372 static SDNode *findFlagUse(SDNode *N) {
1373 unsigned FlagResNo = N->getNumValues()-1;
1374 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1375 SDUse &Use = I.getUse();
1376 if (Use.getResNo() == FlagResNo)
1377 return Use.getUser();
1382 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1383 /// This function recursively traverses up the operand chain, ignoring
1385 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1386 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1387 bool IgnoreChains) {
1388 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1389 // greater than all of its (recursive) operands. If we scan to a point where
1390 // 'use' is smaller than the node we're scanning for, then we know we will
1393 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1394 // happen because we scan down to newly selected nodes in the case of flag
1396 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1399 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1400 // won't fail if we scan it again.
1401 if (!Visited.insert(Use))
1404 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1405 // Ignore chain uses, they are validated by HandleMergeInputChains.
1406 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1409 SDNode *N = Use->getOperand(i).getNode();
1411 if (Use == ImmedUse || Use == Root)
1412 continue; // We are not looking for immediate use.
1417 // Traverse up the operand chain.
1418 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1424 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1425 /// operand node N of U during instruction selection that starts at Root.
1426 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1427 SDNode *Root) const {
1428 if (OptLevel == CodeGenOpt::None) return false;
1429 return N.hasOneUse();
1432 /// IsLegalToFold - Returns true if the specific operand node N of
1433 /// U can be folded during instruction selection that starts at Root.
1434 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1435 bool IgnoreChains) const {
1436 if (OptLevel == CodeGenOpt::None) return false;
1438 // If Root use can somehow reach N through a path that that doesn't contain
1439 // U then folding N would create a cycle. e.g. In the following
1440 // diagram, Root can reach N through X. If N is folded into into Root, then
1441 // X is both a predecessor and a successor of U.
1452 // * indicates nodes to be folded together.
1454 // If Root produces a flag, then it gets (even more) interesting. Since it
1455 // will be "glued" together with its flag use in the scheduler, we need to
1456 // check if it might reach N.
1475 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1476 // (call it Fold), then X is a predecessor of FU and a successor of
1477 // Fold. But since Fold and FU are flagged together, this will create
1478 // a cycle in the scheduling graph.
1480 // If the node has flags, walk down the graph to the "lowest" node in the
1482 EVT VT = Root->getValueType(Root->getNumValues()-1);
1483 while (VT == MVT::Flag) {
1484 SDNode *FU = findFlagUse(Root);
1488 VT = Root->getValueType(Root->getNumValues()-1);
1490 // If our query node has a flag result with a use, we've walked up it. If
1491 // the user (which has already been selected) has a chain or indirectly uses
1492 // the chain, our WalkChainUsers predicate will not consider it. Because of
1493 // this, we cannot ignore chains in this predicate.
1494 IgnoreChains = false;
1498 SmallPtrSet<SDNode*, 16> Visited;
1499 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1502 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1503 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1504 SelectInlineAsmMemoryOperands(Ops);
1506 std::vector<EVT> VTs;
1507 VTs.push_back(MVT::Other);
1508 VTs.push_back(MVT::Flag);
1509 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1510 VTs, &Ops[0], Ops.size());
1512 return New.getNode();
1515 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1516 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1519 /// GetVBR - decode a vbr encoding whose top bit is set.
1520 ALWAYS_INLINE static uint64_t
1521 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1522 assert(Val >= 128 && "Not a VBR");
1523 Val &= 127; // Remove first vbr bit.
1528 NextBits = MatcherTable[Idx++];
1529 Val |= (NextBits&127) << Shift;
1531 } while (NextBits & 128);
1537 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1538 /// interior flag and chain results to use the new flag and chain results.
1539 void SelectionDAGISel::
1540 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1541 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1543 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1544 bool isMorphNodeTo) {
1545 SmallVector<SDNode*, 4> NowDeadNodes;
1547 ISelUpdater ISU(ISelPosition);
1549 // Now that all the normal results are replaced, we replace the chain and
1550 // flag results if present.
1551 if (!ChainNodesMatched.empty()) {
1552 assert(InputChain.getNode() != 0 &&
1553 "Matched input chains but didn't produce a chain");
1554 // Loop over all of the nodes we matched that produced a chain result.
1555 // Replace all the chain results with the final chain we ended up with.
1556 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1557 SDNode *ChainNode = ChainNodesMatched[i];
1559 // If this node was already deleted, don't look at it.
1560 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1563 // Don't replace the results of the root node if we're doing a
1565 if (ChainNode == NodeToMatch && isMorphNodeTo)
1568 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1569 if (ChainVal.getValueType() == MVT::Flag)
1570 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1571 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1572 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1574 // If the node became dead and we haven't already seen it, delete it.
1575 if (ChainNode->use_empty() &&
1576 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1577 NowDeadNodes.push_back(ChainNode);
1581 // If the result produces a flag, update any flag results in the matched
1582 // pattern with the flag result.
1583 if (InputFlag.getNode() != 0) {
1584 // Handle any interior nodes explicitly marked.
1585 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1586 SDNode *FRN = FlagResultNodesMatched[i];
1588 // If this node was already deleted, don't look at it.
1589 if (FRN->getOpcode() == ISD::DELETED_NODE)
1592 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1593 "Doesn't have a flag result");
1594 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1597 // If the node became dead and we haven't already seen it, delete it.
1598 if (FRN->use_empty() &&
1599 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1600 NowDeadNodes.push_back(FRN);
1604 if (!NowDeadNodes.empty())
1605 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1607 DEBUG(errs() << "ISEL: Match complete!\n");
1613 CR_LeadsToInteriorNode
1616 /// WalkChainUsers - Walk down the users of the specified chained node that is
1617 /// part of the pattern we're matching, looking at all of the users we find.
1618 /// This determines whether something is an interior node, whether we have a
1619 /// non-pattern node in between two pattern nodes (which prevent folding because
1620 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1621 /// between pattern nodes (in which case the TF becomes part of the pattern).
1623 /// The walk we do here is guaranteed to be small because we quickly get down to
1624 /// already selected nodes "below" us.
1626 WalkChainUsers(SDNode *ChainedNode,
1627 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1628 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1629 ChainResult Result = CR_Simple;
1631 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1632 E = ChainedNode->use_end(); UI != E; ++UI) {
1633 // Make sure the use is of the chain, not some other value we produce.
1634 if (UI.getUse().getValueType() != MVT::Other) continue;
1638 // If we see an already-selected machine node, then we've gone beyond the
1639 // pattern that we're selecting down into the already selected chunk of the
1641 if (User->isMachineOpcode() ||
1642 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1645 if (User->getOpcode() == ISD::CopyToReg ||
1646 User->getOpcode() == ISD::CopyFromReg ||
1647 User->getOpcode() == ISD::INLINEASM ||
1648 User->getOpcode() == ISD::EH_LABEL) {
1649 // If their node ID got reset to -1 then they've already been selected.
1650 // Treat them like a MachineOpcode.
1651 if (User->getNodeId() == -1)
1655 // If we have a TokenFactor, we handle it specially.
1656 if (User->getOpcode() != ISD::TokenFactor) {
1657 // If the node isn't a token factor and isn't part of our pattern, then it
1658 // must be a random chained node in between two nodes we're selecting.
1659 // This happens when we have something like:
1664 // Because we structurally match the load/store as a read/modify/write,
1665 // but the call is chained between them. We cannot fold in this case
1666 // because it would induce a cycle in the graph.
1667 if (!std::count(ChainedNodesInPattern.begin(),
1668 ChainedNodesInPattern.end(), User))
1669 return CR_InducesCycle;
1671 // Otherwise we found a node that is part of our pattern. For example in:
1675 // This would happen when we're scanning down from the load and see the
1676 // store as a user. Record that there is a use of ChainedNode that is
1677 // part of the pattern and keep scanning uses.
1678 Result = CR_LeadsToInteriorNode;
1679 InteriorChainedNodes.push_back(User);
1683 // If we found a TokenFactor, there are two cases to consider: first if the
1684 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1685 // uses of the TF are in our pattern) we just want to ignore it. Second,
1686 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1692 // | \ DAG's like cheese
1695 // [TokenFactor] [Op]
1702 // In this case, the TokenFactor becomes part of our match and we rewrite it
1703 // as a new TokenFactor.
1705 // To distinguish these two cases, do a recursive walk down the uses.
1706 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1708 // If the uses of the TokenFactor are just already-selected nodes, ignore
1709 // it, it is "below" our pattern.
1711 case CR_InducesCycle:
1712 // If the uses of the TokenFactor lead to nodes that are not part of our
1713 // pattern that are not selected, folding would turn this into a cycle,
1715 return CR_InducesCycle;
1716 case CR_LeadsToInteriorNode:
1717 break; // Otherwise, keep processing.
1720 // Okay, we know we're in the interesting interior case. The TokenFactor
1721 // is now going to be considered part of the pattern so that we rewrite its
1722 // uses (it may have uses that are not part of the pattern) with the
1723 // ultimate chain result of the generated code. We will also add its chain
1724 // inputs as inputs to the ultimate TokenFactor we create.
1725 Result = CR_LeadsToInteriorNode;
1726 ChainedNodesInPattern.push_back(User);
1727 InteriorChainedNodes.push_back(User);
1734 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1735 /// operation for when the pattern matched at least one node with a chains. The
1736 /// input vector contains a list of all of the chained nodes that we match. We
1737 /// must determine if this is a valid thing to cover (i.e. matching it won't
1738 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1739 /// be used as the input node chain for the generated nodes.
1741 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1742 SelectionDAG *CurDAG) {
1743 // Walk all of the chained nodes we've matched, recursively scanning down the
1744 // users of the chain result. This adds any TokenFactor nodes that are caught
1745 // in between chained nodes to the chained and interior nodes list.
1746 SmallVector<SDNode*, 3> InteriorChainedNodes;
1747 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1748 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1749 InteriorChainedNodes) == CR_InducesCycle)
1750 return SDValue(); // Would induce a cycle.
1753 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1754 // that we are interested in. Form our input TokenFactor node.
1755 SmallVector<SDValue, 3> InputChains;
1756 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1757 // Add the input chain of this node to the InputChains list (which will be
1758 // the operands of the generated TokenFactor) if it's not an interior node.
1759 SDNode *N = ChainNodesMatched[i];
1760 if (N->getOpcode() != ISD::TokenFactor) {
1761 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1764 // Otherwise, add the input chain.
1765 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1766 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1767 InputChains.push_back(InChain);
1771 // If we have a token factor, we want to add all inputs of the token factor
1772 // that are not part of the pattern we're matching.
1773 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1774 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1775 N->getOperand(op).getNode()))
1776 InputChains.push_back(N->getOperand(op));
1781 if (InputChains.size() == 1)
1782 return InputChains[0];
1783 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1784 MVT::Other, &InputChains[0], InputChains.size());
1787 /// MorphNode - Handle morphing a node in place for the selector.
1788 SDNode *SelectionDAGISel::
1789 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1790 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1791 // It is possible we're using MorphNodeTo to replace a node with no
1792 // normal results with one that has a normal result (or we could be
1793 // adding a chain) and the input could have flags and chains as well.
1794 // In this case we need to shift the operands down.
1795 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1796 // than the old isel though.
1797 int OldFlagResultNo = -1, OldChainResultNo = -1;
1799 unsigned NTMNumResults = Node->getNumValues();
1800 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1801 OldFlagResultNo = NTMNumResults-1;
1802 if (NTMNumResults != 1 &&
1803 Node->getValueType(NTMNumResults-2) == MVT::Other)
1804 OldChainResultNo = NTMNumResults-2;
1805 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1806 OldChainResultNo = NTMNumResults-1;
1808 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1809 // that this deletes operands of the old node that become dead.
1810 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1812 // MorphNodeTo can operate in two ways: if an existing node with the
1813 // specified operands exists, it can just return it. Otherwise, it
1814 // updates the node in place to have the requested operands.
1816 // If we updated the node in place, reset the node ID. To the isel,
1817 // this should be just like a newly allocated machine node.
1821 unsigned ResNumResults = Res->getNumValues();
1822 // Move the flag if needed.
1823 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1824 (unsigned)OldFlagResultNo != ResNumResults-1)
1825 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1826 SDValue(Res, ResNumResults-1));
1828 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1831 // Move the chain reference if needed.
1832 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1833 (unsigned)OldChainResultNo != ResNumResults-1)
1834 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1835 SDValue(Res, ResNumResults-1));
1837 // Otherwise, no replacement happened because the node already exists. Replace
1838 // Uses of the old node with the new one.
1840 CurDAG->ReplaceAllUsesWith(Node, Res);
1845 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1846 ALWAYS_INLINE static bool
1847 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1848 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1849 // Accept if it is exactly the same as a previously recorded node.
1850 unsigned RecNo = MatcherTable[MatcherIndex++];
1851 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1852 return N == RecordedNodes[RecNo];
1855 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1856 ALWAYS_INLINE static bool
1857 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1858 SelectionDAGISel &SDISel) {
1859 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1862 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1863 ALWAYS_INLINE static bool
1864 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1865 SelectionDAGISel &SDISel, SDNode *N) {
1866 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1869 ALWAYS_INLINE static bool
1870 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1872 uint16_t Opc = MatcherTable[MatcherIndex++];
1873 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1874 return N->getOpcode() == Opc;
1877 ALWAYS_INLINE static bool
1878 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1879 SDValue N, const TargetLowering &TLI) {
1880 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1881 if (N.getValueType() == VT) return true;
1883 // Handle the case when VT is iPTR.
1884 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1887 ALWAYS_INLINE static bool
1888 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1889 SDValue N, const TargetLowering &TLI,
1891 if (ChildNo >= N.getNumOperands())
1892 return false; // Match fails if out of range child #.
1893 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1897 ALWAYS_INLINE static bool
1898 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1900 return cast<CondCodeSDNode>(N)->get() ==
1901 (ISD::CondCode)MatcherTable[MatcherIndex++];
1904 ALWAYS_INLINE static bool
1905 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1906 SDValue N, const TargetLowering &TLI) {
1907 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1908 if (cast<VTSDNode>(N)->getVT() == VT)
1911 // Handle the case when VT is iPTR.
1912 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1915 ALWAYS_INLINE static bool
1916 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1918 int64_t Val = MatcherTable[MatcherIndex++];
1920 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1923 return C != 0 && C->getSExtValue() == Val;
1926 ALWAYS_INLINE static bool
1927 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1928 SDValue N, SelectionDAGISel &SDISel) {
1929 int64_t Val = MatcherTable[MatcherIndex++];
1931 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1933 if (N->getOpcode() != ISD::AND) return false;
1935 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1936 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1939 ALWAYS_INLINE static bool
1940 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1941 SDValue N, SelectionDAGISel &SDISel) {
1942 int64_t Val = MatcherTable[MatcherIndex++];
1944 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1946 if (N->getOpcode() != ISD::OR) return false;
1948 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1949 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1952 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1953 /// scope, evaluate the current node. If the current predicate is known to
1954 /// fail, set Result=true and return anything. If the current predicate is
1955 /// known to pass, set Result=false and return the MatcherIndex to continue
1956 /// with. If the current predicate is unknown, set Result=false and return the
1957 /// MatcherIndex to continue with.
1958 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1959 unsigned Index, SDValue N,
1960 bool &Result, SelectionDAGISel &SDISel,
1961 SmallVectorImpl<SDValue> &RecordedNodes){
1962 switch (Table[Index++]) {
1965 return Index-1; // Could not evaluate this predicate.
1966 case SelectionDAGISel::OPC_CheckSame:
1967 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1969 case SelectionDAGISel::OPC_CheckPatternPredicate:
1970 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1972 case SelectionDAGISel::OPC_CheckPredicate:
1973 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1975 case SelectionDAGISel::OPC_CheckOpcode:
1976 Result = !::CheckOpcode(Table, Index, N.getNode());
1978 case SelectionDAGISel::OPC_CheckType:
1979 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1981 case SelectionDAGISel::OPC_CheckChild0Type:
1982 case SelectionDAGISel::OPC_CheckChild1Type:
1983 case SelectionDAGISel::OPC_CheckChild2Type:
1984 case SelectionDAGISel::OPC_CheckChild3Type:
1985 case SelectionDAGISel::OPC_CheckChild4Type:
1986 case SelectionDAGISel::OPC_CheckChild5Type:
1987 case SelectionDAGISel::OPC_CheckChild6Type:
1988 case SelectionDAGISel::OPC_CheckChild7Type:
1989 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1990 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1992 case SelectionDAGISel::OPC_CheckCondCode:
1993 Result = !::CheckCondCode(Table, Index, N);
1995 case SelectionDAGISel::OPC_CheckValueType:
1996 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1998 case SelectionDAGISel::OPC_CheckInteger:
1999 Result = !::CheckInteger(Table, Index, N);
2001 case SelectionDAGISel::OPC_CheckAndImm:
2002 Result = !::CheckAndImm(Table, Index, N, SDISel);
2004 case SelectionDAGISel::OPC_CheckOrImm:
2005 Result = !::CheckOrImm(Table, Index, N, SDISel);
2012 /// FailIndex - If this match fails, this is the index to continue with.
2015 /// NodeStack - The node stack when the scope was formed.
2016 SmallVector<SDValue, 4> NodeStack;
2018 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2019 unsigned NumRecordedNodes;
2021 /// NumMatchedMemRefs - The number of matched memref entries.
2022 unsigned NumMatchedMemRefs;
2024 /// InputChain/InputFlag - The current chain/flag
2025 SDValue InputChain, InputFlag;
2027 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2028 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2031 SDNode *SelectionDAGISel::
2032 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2033 unsigned TableSize) {
2034 // FIXME: Should these even be selected? Handle these cases in the caller?
2035 switch (NodeToMatch->getOpcode()) {
2038 case ISD::EntryToken: // These nodes remain the same.
2039 case ISD::BasicBlock:
2041 //case ISD::VALUETYPE:
2042 //case ISD::CONDCODE:
2043 case ISD::HANDLENODE:
2044 case ISD::MDNODE_SDNODE:
2045 case ISD::TargetConstant:
2046 case ISD::TargetConstantFP:
2047 case ISD::TargetConstantPool:
2048 case ISD::TargetFrameIndex:
2049 case ISD::TargetExternalSymbol:
2050 case ISD::TargetBlockAddress:
2051 case ISD::TargetJumpTable:
2052 case ISD::TargetGlobalTLSAddress:
2053 case ISD::TargetGlobalAddress:
2054 case ISD::TokenFactor:
2055 case ISD::CopyFromReg:
2056 case ISD::CopyToReg:
2058 NodeToMatch->setNodeId(-1); // Mark selected.
2060 case ISD::AssertSext:
2061 case ISD::AssertZext:
2062 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2063 NodeToMatch->getOperand(0));
2065 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2066 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2069 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2071 // Set up the node stack with NodeToMatch as the only node on the stack.
2072 SmallVector<SDValue, 8> NodeStack;
2073 SDValue N = SDValue(NodeToMatch, 0);
2074 NodeStack.push_back(N);
2076 // MatchScopes - Scopes used when matching, if a match failure happens, this
2077 // indicates where to continue checking.
2078 SmallVector<MatchScope, 8> MatchScopes;
2080 // RecordedNodes - This is the set of nodes that have been recorded by the
2082 SmallVector<SDValue, 8> RecordedNodes;
2084 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2086 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2088 // These are the current input chain and flag for use when generating nodes.
2089 // Various Emit operations change these. For example, emitting a copytoreg
2090 // uses and updates these.
2091 SDValue InputChain, InputFlag;
2093 // ChainNodesMatched - If a pattern matches nodes that have input/output
2094 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2095 // which ones they are. The result is captured into this list so that we can
2096 // update the chain results when the pattern is complete.
2097 SmallVector<SDNode*, 3> ChainNodesMatched;
2098 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2100 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2101 NodeToMatch->dump(CurDAG);
2104 // Determine where to start the interpreter. Normally we start at opcode #0,
2105 // but if the state machine starts with an OPC_SwitchOpcode, then we
2106 // accelerate the first lookup (which is guaranteed to be hot) with the
2107 // OpcodeOffset table.
2108 unsigned MatcherIndex = 0;
2110 if (!OpcodeOffset.empty()) {
2111 // Already computed the OpcodeOffset table, just index into it.
2112 if (N.getOpcode() < OpcodeOffset.size())
2113 MatcherIndex = OpcodeOffset[N.getOpcode()];
2114 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2116 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2117 // Otherwise, the table isn't computed, but the state machine does start
2118 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2119 // is the first time we're selecting an instruction.
2122 // Get the size of this case.
2123 unsigned CaseSize = MatcherTable[Idx++];
2125 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2126 if (CaseSize == 0) break;
2128 // Get the opcode, add the index to the table.
2129 uint16_t Opc = MatcherTable[Idx++];
2130 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2131 if (Opc >= OpcodeOffset.size())
2132 OpcodeOffset.resize((Opc+1)*2);
2133 OpcodeOffset[Opc] = Idx;
2137 // Okay, do the lookup for the first opcode.
2138 if (N.getOpcode() < OpcodeOffset.size())
2139 MatcherIndex = OpcodeOffset[N.getOpcode()];
2143 assert(MatcherIndex < TableSize && "Invalid index");
2145 unsigned CurrentOpcodeIndex = MatcherIndex;
2147 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2150 // Okay, the semantics of this operation are that we should push a scope
2151 // then evaluate the first child. However, pushing a scope only to have
2152 // the first check fail (which then pops it) is inefficient. If we can
2153 // determine immediately that the first check (or first several) will
2154 // immediately fail, don't even bother pushing a scope for them.
2158 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2159 if (NumToSkip & 128)
2160 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2161 // Found the end of the scope with no match.
2162 if (NumToSkip == 0) {
2167 FailIndex = MatcherIndex+NumToSkip;
2169 unsigned MatcherIndexOfPredicate = MatcherIndex;
2170 (void)MatcherIndexOfPredicate; // silence warning.
2172 // If we can't evaluate this predicate without pushing a scope (e.g. if
2173 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2174 // push the scope and evaluate the full predicate chain.
2176 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2177 Result, *this, RecordedNodes);
2181 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2182 << "index " << MatcherIndexOfPredicate
2183 << ", continuing at " << FailIndex << "\n");
2184 ++NumDAGIselRetries;
2186 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2187 // move to the next case.
2188 MatcherIndex = FailIndex;
2191 // If the whole scope failed to match, bail.
2192 if (FailIndex == 0) break;
2194 // Push a MatchScope which indicates where to go if the first child fails
2196 MatchScope NewEntry;
2197 NewEntry.FailIndex = FailIndex;
2198 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2199 NewEntry.NumRecordedNodes = RecordedNodes.size();
2200 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2201 NewEntry.InputChain = InputChain;
2202 NewEntry.InputFlag = InputFlag;
2203 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2204 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2205 MatchScopes.push_back(NewEntry);
2208 case OPC_RecordNode:
2209 // Remember this node, it may end up being an operand in the pattern.
2210 RecordedNodes.push_back(N);
2213 case OPC_RecordChild0: case OPC_RecordChild1:
2214 case OPC_RecordChild2: case OPC_RecordChild3:
2215 case OPC_RecordChild4: case OPC_RecordChild5:
2216 case OPC_RecordChild6: case OPC_RecordChild7: {
2217 unsigned ChildNo = Opcode-OPC_RecordChild0;
2218 if (ChildNo >= N.getNumOperands())
2219 break; // Match fails if out of range child #.
2221 RecordedNodes.push_back(N->getOperand(ChildNo));
2224 case OPC_RecordMemRef:
2225 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2228 case OPC_CaptureFlagInput:
2229 // If the current node has an input flag, capture it in InputFlag.
2230 if (N->getNumOperands() != 0 &&
2231 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2232 InputFlag = N->getOperand(N->getNumOperands()-1);
2235 case OPC_MoveChild: {
2236 unsigned ChildNo = MatcherTable[MatcherIndex++];
2237 if (ChildNo >= N.getNumOperands())
2238 break; // Match fails if out of range child #.
2239 N = N.getOperand(ChildNo);
2240 NodeStack.push_back(N);
2244 case OPC_MoveParent:
2245 // Pop the current node off the NodeStack.
2246 NodeStack.pop_back();
2247 assert(!NodeStack.empty() && "Node stack imbalance!");
2248 N = NodeStack.back();
2252 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2254 case OPC_CheckPatternPredicate:
2255 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2257 case OPC_CheckPredicate:
2258 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2262 case OPC_CheckComplexPat: {
2263 unsigned CPNum = MatcherTable[MatcherIndex++];
2264 unsigned RecNo = MatcherTable[MatcherIndex++];
2265 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2266 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2271 case OPC_CheckOpcode:
2272 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2276 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2279 case OPC_SwitchOpcode: {
2280 unsigned CurNodeOpcode = N.getOpcode();
2281 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2284 // Get the size of this case.
2285 CaseSize = MatcherTable[MatcherIndex++];
2287 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2288 if (CaseSize == 0) break;
2290 uint16_t Opc = MatcherTable[MatcherIndex++];
2291 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2293 // If the opcode matches, then we will execute this case.
2294 if (CurNodeOpcode == Opc)
2297 // Otherwise, skip over this case.
2298 MatcherIndex += CaseSize;
2301 // If no cases matched, bail out.
2302 if (CaseSize == 0) break;
2304 // Otherwise, execute the case we found.
2305 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2306 << " to " << MatcherIndex << "\n");
2310 case OPC_SwitchType: {
2311 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2312 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2315 // Get the size of this case.
2316 CaseSize = MatcherTable[MatcherIndex++];
2318 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2319 if (CaseSize == 0) break;
2321 MVT::SimpleValueType CaseVT =
2322 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2323 if (CaseVT == MVT::iPTR)
2324 CaseVT = TLI.getPointerTy().SimpleTy;
2326 // If the VT matches, then we will execute this case.
2327 if (CurNodeVT == CaseVT)
2330 // Otherwise, skip over this case.
2331 MatcherIndex += CaseSize;
2334 // If no cases matched, bail out.
2335 if (CaseSize == 0) break;
2337 // Otherwise, execute the case we found.
2338 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2339 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2342 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2343 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2344 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2345 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2346 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2347 Opcode-OPC_CheckChild0Type))
2350 case OPC_CheckCondCode:
2351 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2353 case OPC_CheckValueType:
2354 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2356 case OPC_CheckInteger:
2357 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2359 case OPC_CheckAndImm:
2360 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2362 case OPC_CheckOrImm:
2363 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2366 case OPC_CheckFoldableChainNode: {
2367 assert(NodeStack.size() != 1 && "No parent node");
2368 // Verify that all intermediate nodes between the root and this one have
2370 bool HasMultipleUses = false;
2371 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2372 if (!NodeStack[i].hasOneUse()) {
2373 HasMultipleUses = true;
2376 if (HasMultipleUses) break;
2378 // Check to see that the target thinks this is profitable to fold and that
2379 // we can fold it without inducing cycles in the graph.
2380 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2382 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2383 NodeToMatch, true/*We validate our own chains*/))
2388 case OPC_EmitInteger: {
2389 MVT::SimpleValueType VT =
2390 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2391 int64_t Val = MatcherTable[MatcherIndex++];
2393 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2394 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2397 case OPC_EmitRegister: {
2398 MVT::SimpleValueType VT =
2399 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2400 unsigned RegNo = MatcherTable[MatcherIndex++];
2401 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2405 case OPC_EmitConvertToTarget: {
2406 // Convert from IMM/FPIMM to target version.
2407 unsigned RecNo = MatcherTable[MatcherIndex++];
2408 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2409 SDValue Imm = RecordedNodes[RecNo];
2411 if (Imm->getOpcode() == ISD::Constant) {
2412 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2413 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2414 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2415 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2416 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2419 RecordedNodes.push_back(Imm);
2423 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2424 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2425 // These are space-optimized forms of OPC_EmitMergeInputChains.
2426 assert(InputChain.getNode() == 0 &&
2427 "EmitMergeInputChains should be the first chain producing node");
2428 assert(ChainNodesMatched.empty() &&
2429 "Should only have one EmitMergeInputChains per match");
2431 // Read all of the chained nodes.
2432 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2433 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2434 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2436 // FIXME: What if other value results of the node have uses not matched
2438 if (ChainNodesMatched.back() != NodeToMatch &&
2439 !RecordedNodes[RecNo].hasOneUse()) {
2440 ChainNodesMatched.clear();
2444 // Merge the input chains if they are not intra-pattern references.
2445 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2447 if (InputChain.getNode() == 0)
2448 break; // Failed to merge.
2452 case OPC_EmitMergeInputChains: {
2453 assert(InputChain.getNode() == 0 &&
2454 "EmitMergeInputChains should be the first chain producing node");
2455 // This node gets a list of nodes we matched in the input that have
2456 // chains. We want to token factor all of the input chains to these nodes
2457 // together. However, if any of the input chains is actually one of the
2458 // nodes matched in this pattern, then we have an intra-match reference.
2459 // Ignore these because the newly token factored chain should not refer to
2461 unsigned NumChains = MatcherTable[MatcherIndex++];
2462 assert(NumChains != 0 && "Can't TF zero chains");
2464 assert(ChainNodesMatched.empty() &&
2465 "Should only have one EmitMergeInputChains per match");
2467 // Read all of the chained nodes.
2468 for (unsigned i = 0; i != NumChains; ++i) {
2469 unsigned RecNo = MatcherTable[MatcherIndex++];
2470 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2471 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2473 // FIXME: What if other value results of the node have uses not matched
2475 if (ChainNodesMatched.back() != NodeToMatch &&
2476 !RecordedNodes[RecNo].hasOneUse()) {
2477 ChainNodesMatched.clear();
2482 // If the inner loop broke out, the match fails.
2483 if (ChainNodesMatched.empty())
2486 // Merge the input chains if they are not intra-pattern references.
2487 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2489 if (InputChain.getNode() == 0)
2490 break; // Failed to merge.
2495 case OPC_EmitCopyToReg: {
2496 unsigned RecNo = MatcherTable[MatcherIndex++];
2497 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2498 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2500 if (InputChain.getNode() == 0)
2501 InputChain = CurDAG->getEntryNode();
2503 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2504 DestPhysReg, RecordedNodes[RecNo],
2507 InputFlag = InputChain.getValue(1);
2511 case OPC_EmitNodeXForm: {
2512 unsigned XFormNo = MatcherTable[MatcherIndex++];
2513 unsigned RecNo = MatcherTable[MatcherIndex++];
2514 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2515 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2520 case OPC_MorphNodeTo: {
2521 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2522 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2523 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2524 // Get the result VT list.
2525 unsigned NumVTs = MatcherTable[MatcherIndex++];
2526 SmallVector<EVT, 4> VTs;
2527 for (unsigned i = 0; i != NumVTs; ++i) {
2528 MVT::SimpleValueType VT =
2529 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2530 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2534 if (EmitNodeInfo & OPFL_Chain)
2535 VTs.push_back(MVT::Other);
2536 if (EmitNodeInfo & OPFL_FlagOutput)
2537 VTs.push_back(MVT::Flag);
2539 // This is hot code, so optimize the two most common cases of 1 and 2
2542 if (VTs.size() == 1)
2543 VTList = CurDAG->getVTList(VTs[0]);
2544 else if (VTs.size() == 2)
2545 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2547 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2549 // Get the operand list.
2550 unsigned NumOps = MatcherTable[MatcherIndex++];
2551 SmallVector<SDValue, 8> Ops;
2552 for (unsigned i = 0; i != NumOps; ++i) {
2553 unsigned RecNo = MatcherTable[MatcherIndex++];
2555 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2557 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2558 Ops.push_back(RecordedNodes[RecNo]);
2561 // If there are variadic operands to add, handle them now.
2562 if (EmitNodeInfo & OPFL_VariadicInfo) {
2563 // Determine the start index to copy from.
2564 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2565 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2566 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2567 "Invalid variadic node");
2568 // Copy all of the variadic operands, not including a potential flag
2570 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2572 SDValue V = NodeToMatch->getOperand(i);
2573 if (V.getValueType() == MVT::Flag) break;
2578 // If this has chain/flag inputs, add them.
2579 if (EmitNodeInfo & OPFL_Chain)
2580 Ops.push_back(InputChain);
2581 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2582 Ops.push_back(InputFlag);
2586 if (Opcode != OPC_MorphNodeTo) {
2587 // If this is a normal EmitNode command, just create the new node and
2588 // add the results to the RecordedNodes list.
2589 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2590 VTList, Ops.data(), Ops.size());
2592 // Add all the non-flag/non-chain results to the RecordedNodes list.
2593 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2594 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2595 RecordedNodes.push_back(SDValue(Res, i));
2599 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2603 // If the node had chain/flag results, update our notion of the current
2605 if (EmitNodeInfo & OPFL_FlagOutput) {
2606 InputFlag = SDValue(Res, VTs.size()-1);
2607 if (EmitNodeInfo & OPFL_Chain)
2608 InputChain = SDValue(Res, VTs.size()-2);
2609 } else if (EmitNodeInfo & OPFL_Chain)
2610 InputChain = SDValue(Res, VTs.size()-1);
2612 // If the OPFL_MemRefs flag is set on this node, slap all of the
2613 // accumulated memrefs onto it.
2615 // FIXME: This is vastly incorrect for patterns with multiple outputs
2616 // instructions that access memory and for ComplexPatterns that match
2618 if (EmitNodeInfo & OPFL_MemRefs) {
2619 MachineSDNode::mmo_iterator MemRefs =
2620 MF->allocateMemRefsArray(MatchedMemRefs.size());
2621 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2622 cast<MachineSDNode>(Res)
2623 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2627 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2628 << " node: "; Res->dump(CurDAG); errs() << "\n");
2630 // If this was a MorphNodeTo then we're completely done!
2631 if (Opcode == OPC_MorphNodeTo) {
2632 // Update chain and flag uses.
2633 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2634 InputFlag, FlagResultNodesMatched, true);
2641 case OPC_MarkFlagResults: {
2642 unsigned NumNodes = MatcherTable[MatcherIndex++];
2644 // Read and remember all the flag-result nodes.
2645 for (unsigned i = 0; i != NumNodes; ++i) {
2646 unsigned RecNo = MatcherTable[MatcherIndex++];
2648 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2650 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2651 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2656 case OPC_CompleteMatch: {
2657 // The match has been completed, and any new nodes (if any) have been
2658 // created. Patch up references to the matched dag to use the newly
2660 unsigned NumResults = MatcherTable[MatcherIndex++];
2662 for (unsigned i = 0; i != NumResults; ++i) {
2663 unsigned ResSlot = MatcherTable[MatcherIndex++];
2665 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2667 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2668 SDValue Res = RecordedNodes[ResSlot];
2670 assert(i < NodeToMatch->getNumValues() &&
2671 NodeToMatch->getValueType(i) != MVT::Other &&
2672 NodeToMatch->getValueType(i) != MVT::Flag &&
2673 "Invalid number of results to complete!");
2674 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2675 NodeToMatch->getValueType(i) == MVT::iPTR ||
2676 Res.getValueType() == MVT::iPTR ||
2677 NodeToMatch->getValueType(i).getSizeInBits() ==
2678 Res.getValueType().getSizeInBits()) &&
2679 "invalid replacement");
2680 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2683 // If the root node defines a flag, add it to the flag nodes to update
2685 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2686 FlagResultNodesMatched.push_back(NodeToMatch);
2688 // Update chain and flag uses.
2689 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2690 InputFlag, FlagResultNodesMatched, false);
2692 assert(NodeToMatch->use_empty() &&
2693 "Didn't replace all uses of the node?");
2695 // FIXME: We just return here, which interacts correctly with SelectRoot
2696 // above. We should fix this to not return an SDNode* anymore.
2701 // If the code reached this point, then the match failed. See if there is
2702 // another child to try in the current 'Scope', otherwise pop it until we
2703 // find a case to check.
2704 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2705 ++NumDAGIselRetries;
2707 if (MatchScopes.empty()) {
2708 CannotYetSelect(NodeToMatch);
2712 // Restore the interpreter state back to the point where the scope was
2714 MatchScope &LastScope = MatchScopes.back();
2715 RecordedNodes.resize(LastScope.NumRecordedNodes);
2717 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2718 N = NodeStack.back();
2720 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2721 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2722 MatcherIndex = LastScope.FailIndex;
2724 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2726 InputChain = LastScope.InputChain;
2727 InputFlag = LastScope.InputFlag;
2728 if (!LastScope.HasChainNodesMatched)
2729 ChainNodesMatched.clear();
2730 if (!LastScope.HasFlagResultNodesMatched)
2731 FlagResultNodesMatched.clear();
2733 // Check to see what the offset is at the new MatcherIndex. If it is zero
2734 // we have reached the end of this scope, otherwise we have another child
2735 // in the current scope to try.
2736 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2737 if (NumToSkip & 128)
2738 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2740 // If we have another child in this scope to match, update FailIndex and
2742 if (NumToSkip != 0) {
2743 LastScope.FailIndex = MatcherIndex+NumToSkip;
2747 // End of this scope, pop it and try the next child in the containing
2749 MatchScopes.pop_back();
2756 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2758 raw_string_ostream Msg(msg);
2759 Msg << "Cannot yet select: ";
2761 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2762 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2763 N->getOpcode() != ISD::INTRINSIC_VOID) {
2764 N->printrFull(Msg, CurDAG);
2766 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2768 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2769 if (iid < Intrinsic::num_intrinsics)
2770 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2771 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2772 Msg << "target intrinsic %" << TII->getName(iid);
2774 Msg << "unknown intrinsic #" << iid;
2776 report_fatal_error(Msg.str());
2779 char SelectionDAGISel::ID = 0;