1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetIntrinsicInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include "llvm/Target/TargetSubtargetInfo.h"
59 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
71 STATISTIC(NumFastIselFailLowerArguments,
72 "Number of entry blocks where fast isel failed to lower arguments");
76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
77 cl::desc("Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
89 // Standard binary operators...
90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
103 // Logical operators...
104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
108 // Memory instructions...
109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
117 // Convert instructions...
118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
131 // Other instructions...
132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
148 // Intrinsic instructions...
149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
170 cl::desc("Enable verbose messages in the \"fast\" "
171 "instruction selector"));
172 static cl::opt<int> EnableFastISelAbort(
173 "fast-isel-abort", cl::Hidden,
174 cl::desc("Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None ||
297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
298 TLI->getSchedulingPreference() == Sched::Source)
299 return createSourceListDAGScheduler(IS, OptLevel);
300 if (TLI->getSchedulingPreference() == Sched::RegPressure)
301 return createBURRListDAGScheduler(IS, OptLevel);
302 if (TLI->getSchedulingPreference() == Sched::Hybrid)
303 return createHybridListDAGScheduler(IS, OptLevel);
304 if (TLI->getSchedulingPreference() == Sched::VLIW)
305 return createVLIWDAGScheduler(IS, OptLevel);
306 assert(TLI->getSchedulingPreference() == Sched::ILP &&
307 "Unknown sched type!");
308 return createILPListDAGScheduler(IS, OptLevel);
312 // EmitInstrWithCustomInserter - This method should be implemented by targets
313 // that mark instructions with the 'usesCustomInserter' flag. These
314 // instructions are special in various ways, which require special support to
315 // insert. The specified MachineInstr is created but not inserted into any
316 // basic blocks, and this method is called to expand it into a sequence of
317 // instructions, potentially also creating new basic blocks and control flow.
318 // When new basic blocks are inserted and the edges from MBB to its successors
319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
323 MachineBasicBlock *MBB) const {
325 dbgs() << "If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
329 llvm_unreachable(nullptr);
332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
333 SDNode *Node) const {
334 assert(!MI->hasPostISelHook() &&
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
339 //===----------------------------------------------------------------------===//
340 // SelectionDAGISel code
341 //===----------------------------------------------------------------------===//
343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
344 CodeGenOpt::Level OL) :
345 MachineFunctionPass(ID), TM(tm),
346 FuncInfo(new FunctionLoweringInfo()),
347 CurDAG(new SelectionDAG(tm, OL)),
348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
355 initializeTargetLibraryInfoWrapperPassPass(
356 *PassRegistry::getPassRegistry());
359 SelectionDAGISel::~SelectionDAGISel() {
365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.addRequired<AliasAnalysis>();
367 AU.addPreserved<AliasAnalysis>();
368 AU.addRequired<GCModuleInfo>();
369 AU.addPreserved<GCModuleInfo>();
370 AU.addRequired<TargetLibraryInfoWrapperPass>();
371 if (UseMBPI && OptLevel != CodeGenOpt::None)
372 AU.addRequired<BranchProbabilityInfo>();
373 MachineFunctionPass::getAnalysisUsage(AU);
376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
377 /// may trap on it. In this case we have to split the edge so that the path
378 /// through the predecessor block that doesn't go to the phi block doesn't
379 /// execute the possibly trapping instruction.
381 /// This is required for correctness, so it must be done at -O0.
383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
384 // Loop for blocks with phi nodes.
385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
386 PHINode *PN = dyn_cast<PHINode>(BB->begin());
390 // For each block with a PHI node, check to see if any of the input values
391 // are potentially trapping constant expressions. Constant expressions are
392 // the only potentially trapping value that can occur as the argument to a
394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
397 if (!CE || !CE->canTrap()) continue;
399 // The only case we have to worry about is when the edge is critical.
400 // Since this block has a PHI Node, we assume it has multiple input
401 // edges: check to see if the pred has multiple successors.
402 BasicBlock *Pred = PN->getIncomingBlock(i);
403 if (Pred->getTerminator()->getNumSuccessors() == 1)
406 // Okay, we have to split this edge.
408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
416 // Do some sanity-checking on the command-line options.
417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
418 "-fast-isel-verbose requires -fast-isel");
419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
420 "-fast-isel-abort > 0 requires -fast-isel");
422 const Function &Fn = *mf.getFunction();
425 // Reset the target options before resetting the optimization
427 // FIXME: This is a horrible hack and should be processed via
428 // codegen looking at the optimization level explicitly when
429 // it wants to look at it.
430 TM.resetTargetOptions(Fn);
431 // Reset OptLevel to None for optnone functions.
432 CodeGenOpt::Level NewOptLevel = OptLevel;
433 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
434 NewOptLevel = CodeGenOpt::None;
435 OptLevelChanger OLC(*this, NewOptLevel);
437 TII = MF->getSubtarget().getInstrInfo();
438 TLI = MF->getSubtarget().getTargetLowering();
439 RegInfo = &MF->getRegInfo();
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
449 FuncInfo->set(Fn, *MF, CurDAG);
451 if (UseMBPI && OptLevel != CodeGenOpt::None)
452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
454 FuncInfo->BPI = nullptr;
456 SDB->init(GFI, *AA, LibInfo);
458 MF->setHasInlineAsm(false);
460 SelectAllBasicBlocks(Fn);
462 // If the first basic block in the function has live ins that need to be
463 // copied into vregs, emit the copies into the top of the block before
464 // emitting the code for the block.
465 MachineBasicBlock *EntryMBB = MF->begin();
466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
469 DenseMap<unsigned, unsigned> LiveInMap;
470 if (!FuncInfo->ArgDbgValues.empty())
471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
472 E = RegInfo->livein_end(); LI != E; ++LI)
474 LiveInMap.insert(std::make_pair(LI->first, LI->second));
476 // Insert DBG_VALUE instructions for function arguments to the entry block.
477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
479 bool hasFI = MI->getOperand(0).isFI();
481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
482 if (TargetRegisterInfo::isPhysicalRegister(Reg))
483 EntryMBB->insert(EntryMBB->begin(), MI);
485 MachineInstr *Def = RegInfo->getVRegDef(Reg);
487 MachineBasicBlock::iterator InsertPos = Def;
488 // FIXME: VR def may not be in entry block.
489 Def->getParent()->insert(std::next(InsertPos), MI);
491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
495 // If Reg is live-in then update debug info to track its copy in a vreg.
496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
497 if (LDI != LiveInMap.end()) {
498 assert(!hasFI && "There's no handling of frame pointer updating here yet "
500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
501 MachineBasicBlock::iterator InsertPos = Def;
502 const MDNode *Variable = MI->getDebugVariable();
503 const MDNode *Expr = MI->getDebugExpression();
504 DebugLoc DL = MI->getDebugLoc();
505 bool IsIndirect = MI->isIndirectDebugValue();
506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
507 assert(cast<MDLocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
509 // Def is never a terminator here, so it is ok to increment InsertPos.
510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
511 IsIndirect, LDI->second, Offset, Variable, Expr);
513 // If this vreg is directly copied into an exported register then
514 // that COPY instructions also need DBG_VALUE, if it is the only
515 // user of LDI->second.
516 MachineInstr *CopyUseMI = nullptr;
517 for (MachineRegisterInfo::use_instr_iterator
518 UI = RegInfo->use_instr_begin(LDI->second),
519 E = RegInfo->use_instr_end(); UI != E; ) {
520 MachineInstr *UseMI = &*(UI++);
521 if (UseMI->isDebugValue()) continue;
522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
523 CopyUseMI = UseMI; continue;
525 // Otherwise this is another use or second copy use.
526 CopyUseMI = nullptr; break;
529 // Use MI's debug location, which describes where Variable was
530 // declared, rather than whatever is attached to CopyUseMI.
531 MachineInstr *NewMI =
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
534 MachineBasicBlock::iterator Pos = CopyUseMI;
535 EntryMBB->insertAfter(Pos, NewMI);
540 // Determine if there are any calls in this machine function.
541 MachineFrameInfo *MFI = MF->getFrameInfo();
542 for (const auto &MBB : *MF) {
543 if (MFI->hasCalls() && MF->hasInlineAsm())
546 for (const auto &MI : MBB) {
547 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
548 if ((MCID.isCall() && !MCID.isReturn()) ||
549 MI.isStackAligningInlineAsm()) {
550 MFI->setHasCalls(true);
552 if (MI.isInlineAsm()) {
553 MF->setHasInlineAsm(true);
558 // Determine if there is a call to setjmp in the machine function.
559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
561 // Replace forward-declared registers with the registers containing
562 // the desired value.
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 for (DenseMap<unsigned, unsigned>::iterator
565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
567 unsigned From = I->first;
568 unsigned To = I->second;
569 // If To is also scheduled to be replaced, find what its ultimate
572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
576 // Make sure the new register has a sufficiently constrained register class.
577 if (TargetRegisterInfo::isVirtualRegister(From) &&
578 TargetRegisterInfo::isVirtualRegister(To))
579 MRI.constrainRegClass(To, MRI.getRegClass(From));
581 MRI.replaceRegWith(From, To);
584 // Freeze the set of reserved registers now that MachineFrameInfo has been
585 // set up. All the information required by getReservedRegs() should be
587 MRI.freezeReservedRegs(*MF);
589 // Release function-specific state. SDB and CurDAG are already cleared
593 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
594 DEBUG(MF->print(dbgs()));
599 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
600 BasicBlock::const_iterator End,
602 // Lower the instructions. If a call is emitted as a tail call, cease emitting
603 // nodes for this block.
604 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
607 // Make sure the root of the DAG is up-to-date.
608 CurDAG->setRoot(SDB->getControlRoot());
609 HadTailCall = SDB->HasTailCall;
612 // Final step, emit the lowered DAG as machine code.
616 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
617 SmallPtrSet<SDNode*, 128> VisitedNodes;
618 SmallVector<SDNode*, 128> Worklist;
620 Worklist.push_back(CurDAG->getRoot().getNode());
626 SDNode *N = Worklist.pop_back_val();
628 // If we've already seen this node, ignore it.
629 if (!VisitedNodes.insert(N).second)
632 // Otherwise, add all chain operands to the worklist.
633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
634 if (N->getOperand(i).getValueType() == MVT::Other)
635 Worklist.push_back(N->getOperand(i).getNode());
637 // If this is a CopyToReg with a vreg dest, process it.
638 if (N->getOpcode() != ISD::CopyToReg)
641 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
642 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
645 // Ignore non-scalar or non-integer values.
646 SDValue Src = N->getOperand(2);
647 EVT SrcVT = Src.getValueType();
648 if (!SrcVT.isInteger() || SrcVT.isVector())
651 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
652 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
653 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
654 } while (!Worklist.empty());
657 void SelectionDAGISel::CodeGenAndEmitDAG() {
658 std::string GroupName;
659 if (TimePassesIsEnabled)
660 GroupName = "Instruction Selection and Scheduling";
661 std::string BlockName;
662 int BlockNumber = -1;
664 bool MatchFilterBB = false; (void)MatchFilterBB;
666 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
667 FilterDAGBasicBlockName ==
668 FuncInfo->MBB->getBasicBlock()->getName().str());
671 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
672 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
676 BlockNumber = FuncInfo->MBB->getNumber();
678 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
680 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
681 << " '" << BlockName << "'\n"; CurDAG->dump());
683 if (ViewDAGCombine1 && MatchFilterBB)
684 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
686 // Run the DAG combiner in pre-legalize mode.
688 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
689 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
692 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
693 << " '" << BlockName << "'\n"; CurDAG->dump());
695 // Second step, hack on the DAG until it only uses operations and types that
696 // the target supports.
697 if (ViewLegalizeTypesDAGs && MatchFilterBB)
698 CurDAG->viewGraph("legalize-types input for " + BlockName);
702 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
703 Changed = CurDAG->LegalizeTypes();
706 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
709 CurDAG->NewNodesMustHaveLegalTypes = true;
712 if (ViewDAGCombineLT && MatchFilterBB)
713 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
715 // Run the DAG combiner in post-type-legalize mode.
717 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
718 TimePassesIsEnabled);
719 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
722 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
723 << " '" << BlockName << "'\n"; CurDAG->dump());
728 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
729 Changed = CurDAG->LegalizeVectors();
734 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
735 CurDAG->LegalizeTypes();
738 if (ViewDAGCombineLT && MatchFilterBB)
739 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
741 // Run the DAG combiner in post-type-legalize mode.
743 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
744 TimePassesIsEnabled);
745 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
748 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
749 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
752 if (ViewLegalizeDAGs && MatchFilterBB)
753 CurDAG->viewGraph("legalize input for " + BlockName);
756 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
760 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
761 << " '" << BlockName << "'\n"; CurDAG->dump());
763 if (ViewDAGCombine2 && MatchFilterBB)
764 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
766 // Run the DAG combiner in post-legalize mode.
768 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
769 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
772 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
773 << " '" << BlockName << "'\n"; CurDAG->dump());
775 if (OptLevel != CodeGenOpt::None)
776 ComputeLiveOutVRegInfo();
778 if (ViewISelDAGs && MatchFilterBB)
779 CurDAG->viewGraph("isel input for " + BlockName);
781 // Third, instruction select all of the operations to machine code, adding the
782 // code to the MachineBasicBlock.
784 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
785 DoInstructionSelection();
788 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
789 << " '" << BlockName << "'\n"; CurDAG->dump());
791 if (ViewSchedDAGs && MatchFilterBB)
792 CurDAG->viewGraph("scheduler input for " + BlockName);
794 // Schedule machine code.
795 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
797 NamedRegionTimer T("Instruction Scheduling", GroupName,
798 TimePassesIsEnabled);
799 Scheduler->Run(CurDAG, FuncInfo->MBB);
802 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
804 // Emit machine code to BB. This can change 'BB' to the last block being
806 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
808 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
810 // FuncInfo->InsertPt is passed by reference and set to the end of the
811 // scheduled instructions.
812 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
815 // If the block was split, make sure we update any references that are used to
816 // update PHI nodes later on.
817 if (FirstMBB != LastMBB)
818 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
820 // Free the scheduler state.
822 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
823 TimePassesIsEnabled);
827 // Free the SelectionDAG state, now that we're finished with it.
832 /// ISelUpdater - helper class to handle updates of the instruction selection
834 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
835 SelectionDAG::allnodes_iterator &ISelPosition;
837 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
838 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
840 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
841 /// deleted is the current ISelPosition node, update ISelPosition.
843 void NodeDeleted(SDNode *N, SDNode *E) override {
844 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
848 } // end anonymous namespace
850 void SelectionDAGISel::DoInstructionSelection() {
851 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
852 << FuncInfo->MBB->getNumber()
853 << " '" << FuncInfo->MBB->getName() << "'\n");
857 // Select target instructions for the DAG.
859 // Number all nodes with a topological order and set DAGSize.
860 DAGSize = CurDAG->AssignTopologicalOrder();
862 // Create a dummy node (which is not added to allnodes), that adds
863 // a reference to the root node, preventing it from being deleted,
864 // and tracking any changes of the root.
865 HandleSDNode Dummy(CurDAG->getRoot());
866 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
869 // Make sure that ISelPosition gets properly updated when nodes are deleted
870 // in calls made from this function.
871 ISelUpdater ISU(*CurDAG, ISelPosition);
873 // The AllNodes list is now topological-sorted. Visit the
874 // nodes by starting at the end of the list (the root of the
875 // graph) and preceding back toward the beginning (the entry
877 while (ISelPosition != CurDAG->allnodes_begin()) {
878 SDNode *Node = --ISelPosition;
879 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
880 // but there are currently some corner cases that it misses. Also, this
881 // makes it theoretically possible to disable the DAGCombiner.
882 if (Node->use_empty())
885 SDNode *ResNode = Select(Node);
887 // FIXME: This is pretty gross. 'Select' should be changed to not return
888 // anything at all and this code should be nuked with a tactical strike.
890 // If node should not be replaced, continue with the next one.
891 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
895 ReplaceUses(Node, ResNode);
898 // If after the replacement this node is not used any more,
899 // remove this dead node.
900 if (Node->use_empty()) // Don't delete EntryToken, etc.
901 CurDAG->RemoveDeadNode(Node);
904 CurDAG->setRoot(Dummy.getValue());
907 DEBUG(dbgs() << "===== Instruction selection ends:\n");
909 PostprocessISelDAG();
912 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
913 /// do other setup for EH landing-pad blocks.
914 void SelectionDAGISel::PrepareEHLandingPad() {
915 MachineBasicBlock *MBB = FuncInfo->MBB;
917 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
919 // Add a label to mark the beginning of the landing pad. Deletion of the
920 // landing pad can thus be detected via the MachineModuleInfo.
921 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
923 // Assign the call site to the landing pad's begin label.
924 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
926 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
927 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
930 // If this is an MSVC-style personality function, we need to split the landing
931 // pad into several BBs.
932 const BasicBlock *LLVMBB = MBB->getBasicBlock();
933 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
934 MF->getMMI().addPersonality(
935 MBB, cast<Function>(LPadInst->getPersonalityFn()->stripPointerCasts()));
936 EHPersonality Personality = MF->getMMI().getPersonalityType();
938 if (isMSVCEHPersonality(Personality)) {
939 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
940 const IntrinsicInst *Actions =
941 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
942 // Get all invoke BBs that unwind to this landingpad.
943 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
945 if (Actions && Actions->getIntrinsicID() == Intrinsic::eh_actions) {
946 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
947 // run WinEHPrepare, and we should remove this block from the machine CFG.
948 // Mark the targets of the indirectbr as landingpads instead.
949 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
950 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
951 // Add the edge from the invoke to the clause.
952 for (MachineBasicBlock *InvokeBB : InvokeBBs)
953 InvokeBB->addSuccessor(ClauseBB);
956 // Otherwise, we haven't done the preparation, and we need to invent some
957 // clause basic blocks that branch into the landingpad.
958 // FIXME: Remove this code once SEH preparation works.
960 // Make virtual registers and a series of labels that fill in values for
962 auto &RI = MF->getRegInfo();
963 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
965 // Emit separate machine basic blocks with separate labels for each clause
966 // before the main landing pad block.
967 MachineInstrBuilder SelectorPHI = BuildMI(
968 *MBB, MBB->begin(), SDB->getCurDebugLoc(),
969 TII->get(TargetOpcode::PHI), FuncInfo->ExceptionSelectorVirtReg);
970 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
971 // Skip filter clauses, we can't implement them.
972 if (LPadInst->isFilter(I))
975 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
976 MF->insert(MBB, ClauseBB);
978 // Add the edge from the invoke to the clause.
979 for (MachineBasicBlock *InvokeBB : InvokeBBs)
980 InvokeBB->addSuccessor(ClauseBB);
982 // Mark the clause as a landing pad or MI passes will delete it.
983 ClauseBB->setIsLandingPad();
985 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
987 // Start the BB with a label.
988 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
989 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
990 .addSym(ClauseLabel);
992 // Construct a simple BB that defines a register with the typeid
994 FuncInfo->MBB = ClauseBB;
995 FuncInfo->InsertPt = ClauseBB->end();
996 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
997 CurDAG->setRoot(SDB->getRoot());
1001 // Add the typeid virtual register to the phi in the main landing pad.
1002 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
1006 // Remove the edge from the invoke to the lpad.
1007 for (MachineBasicBlock *InvokeBB : InvokeBBs)
1008 InvokeBB->removeSuccessor(MBB);
1010 // Restore FuncInfo back to its previous state and select the main landing
1012 FuncInfo->MBB = MBB;
1013 FuncInfo->InsertPt = MBB->end();
1015 // Transfer EH state number assigned to the IR block to the MBB.
1016 if (Personality == EHPersonality::MSVC_CXX) {
1017 WinEHFuncInfo &FI = MF->getMMI().getWinEHFuncInfo(MF->getFunction());
1018 MF->getMMI().addWinEHState(MBB, FI.LandingPadStateMap[LPadInst]);
1023 // Mark exception register as live in.
1024 if (unsigned Reg = TLI->getExceptionPointerRegister())
1025 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
1027 // Mark exception selector register as live in.
1028 if (unsigned Reg = TLI->getExceptionSelectorRegister())
1029 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
1032 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1033 /// side-effect free and is either dead or folded into a generated instruction.
1034 /// Return false if it needs to be emitted.
1035 static bool isFoldedOrDeadInstruction(const Instruction *I,
1036 FunctionLoweringInfo *FuncInfo) {
1037 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1038 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1039 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1040 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1041 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1045 // Collect per Instruction statistics for fast-isel misses. Only those
1046 // instructions that cause the bail are accounted for. It does not account for
1047 // instructions higher in the block. Thus, summing the per instructions stats
1048 // will not add up to what is reported by NumFastIselFailures.
1049 static void collectFailStats(const Instruction *I) {
1050 switch (I->getOpcode()) {
1051 default: assert (0 && "<Invalid operator> ");
1054 case Instruction::Ret: NumFastIselFailRet++; return;
1055 case Instruction::Br: NumFastIselFailBr++; return;
1056 case Instruction::Switch: NumFastIselFailSwitch++; return;
1057 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1058 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1059 case Instruction::Resume: NumFastIselFailResume++; return;
1060 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1062 // Standard binary operators...
1063 case Instruction::Add: NumFastIselFailAdd++; return;
1064 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1065 case Instruction::Sub: NumFastIselFailSub++; return;
1066 case Instruction::FSub: NumFastIselFailFSub++; return;
1067 case Instruction::Mul: NumFastIselFailMul++; return;
1068 case Instruction::FMul: NumFastIselFailFMul++; return;
1069 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1070 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1071 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1072 case Instruction::URem: NumFastIselFailURem++; return;
1073 case Instruction::SRem: NumFastIselFailSRem++; return;
1074 case Instruction::FRem: NumFastIselFailFRem++; return;
1076 // Logical operators...
1077 case Instruction::And: NumFastIselFailAnd++; return;
1078 case Instruction::Or: NumFastIselFailOr++; return;
1079 case Instruction::Xor: NumFastIselFailXor++; return;
1081 // Memory instructions...
1082 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1083 case Instruction::Load: NumFastIselFailLoad++; return;
1084 case Instruction::Store: NumFastIselFailStore++; return;
1085 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1086 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1087 case Instruction::Fence: NumFastIselFailFence++; return;
1088 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1090 // Convert instructions...
1091 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1092 case Instruction::ZExt: NumFastIselFailZExt++; return;
1093 case Instruction::SExt: NumFastIselFailSExt++; return;
1094 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1095 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1096 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1097 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1098 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1099 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1100 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1101 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1102 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1104 // Other instructions...
1105 case Instruction::ICmp: NumFastIselFailICmp++; return;
1106 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1107 case Instruction::PHI: NumFastIselFailPHI++; return;
1108 case Instruction::Select: NumFastIselFailSelect++; return;
1109 case Instruction::Call: {
1110 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1111 switch (Intrinsic->getIntrinsicID()) {
1113 NumFastIselFailIntrinsicCall++; return;
1114 case Intrinsic::sadd_with_overflow:
1115 NumFastIselFailSAddWithOverflow++; return;
1116 case Intrinsic::uadd_with_overflow:
1117 NumFastIselFailUAddWithOverflow++; return;
1118 case Intrinsic::ssub_with_overflow:
1119 NumFastIselFailSSubWithOverflow++; return;
1120 case Intrinsic::usub_with_overflow:
1121 NumFastIselFailUSubWithOverflow++; return;
1122 case Intrinsic::smul_with_overflow:
1123 NumFastIselFailSMulWithOverflow++; return;
1124 case Intrinsic::umul_with_overflow:
1125 NumFastIselFailUMulWithOverflow++; return;
1126 case Intrinsic::frameaddress:
1127 NumFastIselFailFrameaddress++; return;
1128 case Intrinsic::sqrt:
1129 NumFastIselFailSqrt++; return;
1130 case Intrinsic::experimental_stackmap:
1131 NumFastIselFailStackMap++; return;
1132 case Intrinsic::experimental_patchpoint_void: // fall-through
1133 case Intrinsic::experimental_patchpoint_i64:
1134 NumFastIselFailPatchPoint++; return;
1137 NumFastIselFailCall++;
1140 case Instruction::Shl: NumFastIselFailShl++; return;
1141 case Instruction::LShr: NumFastIselFailLShr++; return;
1142 case Instruction::AShr: NumFastIselFailAShr++; return;
1143 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1144 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1145 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1146 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1147 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1148 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1149 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1154 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1155 // Initialize the Fast-ISel state, if needed.
1156 FastISel *FastIS = nullptr;
1157 if (TM.Options.EnableFastISel)
1158 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1160 // Iterate over all basic blocks in the function.
1161 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1162 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1163 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1164 const BasicBlock *LLVMBB = *I;
1166 if (OptLevel != CodeGenOpt::None) {
1167 bool AllPredsVisited = true;
1168 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1170 if (!FuncInfo->VisitedBBs.count(*PI)) {
1171 AllPredsVisited = false;
1176 if (AllPredsVisited) {
1177 for (BasicBlock::const_iterator I = LLVMBB->begin();
1178 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1179 FuncInfo->ComputePHILiveOutRegInfo(PN);
1181 for (BasicBlock::const_iterator I = LLVMBB->begin();
1182 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1183 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1186 FuncInfo->VisitedBBs.insert(LLVMBB);
1189 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1190 BasicBlock::const_iterator const End = LLVMBB->end();
1191 BasicBlock::const_iterator BI = End;
1193 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1194 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1196 // Setup an EH landing-pad block.
1197 FuncInfo->ExceptionPointerVirtReg = 0;
1198 FuncInfo->ExceptionSelectorVirtReg = 0;
1199 if (LLVMBB->isLandingPad())
1200 PrepareEHLandingPad();
1202 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1204 FastIS->startNewBlock();
1206 // Emit code for any incoming arguments. This must happen before
1207 // beginning FastISel on the entry block.
1208 if (LLVMBB == &Fn.getEntryBlock()) {
1211 // Lower any arguments needed in this block if this is the entry block.
1212 if (!FastIS->lowerArguments()) {
1213 // Fast isel failed to lower these arguments
1214 ++NumFastIselFailLowerArguments;
1215 if (EnableFastISelAbort > 1)
1216 report_fatal_error("FastISel didn't lower all arguments");
1218 // Use SelectionDAG argument lowering
1220 CurDAG->setRoot(SDB->getControlRoot());
1222 CodeGenAndEmitDAG();
1225 // If we inserted any instructions at the beginning, make a note of
1226 // where they are, so we can be sure to emit subsequent instructions
1228 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1229 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1231 FastIS->setLastLocalValue(nullptr);
1234 unsigned NumFastIselRemaining = std::distance(Begin, End);
1235 // Do FastISel on as many instructions as possible.
1236 for (; BI != Begin; --BI) {
1237 const Instruction *Inst = std::prev(BI);
1239 // If we no longer require this instruction, skip it.
1240 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1241 --NumFastIselRemaining;
1245 // Bottom-up: reset the insert pos at the top, after any local-value
1247 FastIS->recomputeInsertPt();
1249 // Try to select the instruction with FastISel.
1250 if (FastIS->selectInstruction(Inst)) {
1251 --NumFastIselRemaining;
1252 ++NumFastIselSuccess;
1253 // If fast isel succeeded, skip over all the folded instructions, and
1254 // then see if there is a load right before the selected instructions.
1255 // Try to fold the load if so.
1256 const Instruction *BeforeInst = Inst;
1257 while (BeforeInst != Begin) {
1258 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1259 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1262 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1263 BeforeInst->hasOneUse() &&
1264 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1265 // If we succeeded, don't re-select the load.
1266 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1267 --NumFastIselRemaining;
1268 ++NumFastIselSuccess;
1274 if (EnableFastISelVerbose2)
1275 collectFailStats(Inst);
1278 // Then handle certain instructions as single-LLVM-Instruction blocks.
1279 if (isa<CallInst>(Inst)) {
1281 if (EnableFastISelVerbose || EnableFastISelAbort) {
1282 dbgs() << "FastISel missed call: ";
1285 if (EnableFastISelAbort > 2)
1286 // FastISel selector couldn't handle something and bailed.
1287 // For the purpose of debugging, just abort.
1288 report_fatal_error("FastISel didn't select the entire block");
1290 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1291 unsigned &R = FuncInfo->ValueMap[Inst];
1293 R = FuncInfo->CreateRegs(Inst->getType());
1296 bool HadTailCall = false;
1297 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1298 SelectBasicBlock(Inst, BI, HadTailCall);
1300 // If the call was emitted as a tail call, we're done with the block.
1301 // We also need to delete any previously emitted instructions.
1303 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1308 // Recompute NumFastIselRemaining as Selection DAG instruction
1309 // selection may have handled the call, input args, etc.
1310 unsigned RemainingNow = std::distance(Begin, BI);
1311 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1312 NumFastIselRemaining = RemainingNow;
1316 bool ShouldAbort = EnableFastISelAbort;
1317 if (EnableFastISelVerbose || EnableFastISelAbort) {
1318 if (isa<TerminatorInst>(Inst)) {
1319 // Use a different message for terminator misses.
1320 dbgs() << "FastISel missed terminator: ";
1321 // Don't abort unless for terminator unless the level is really high
1322 ShouldAbort = (EnableFastISelAbort > 2);
1324 dbgs() << "FastISel miss: ";
1329 // FastISel selector couldn't handle something and bailed.
1330 // For the purpose of debugging, just abort.
1331 report_fatal_error("FastISel didn't select the entire block");
1333 NumFastIselFailures += NumFastIselRemaining;
1337 FastIS->recomputeInsertPt();
1339 // Lower any arguments needed in this block if this is the entry block.
1340 if (LLVMBB == &Fn.getEntryBlock()) {
1349 ++NumFastIselBlocks;
1352 // Run SelectionDAG instruction selection on the remainder of the block
1353 // not handled by FastISel. If FastISel is not run, this is the entire
1356 SelectBasicBlock(Begin, BI, HadTailCall);
1360 FuncInfo->PHINodesToUpdate.clear();
1364 SDB->clearDanglingDebugInfo();
1365 SDB->SPDescriptor.resetPerFunctionState();
1368 /// Given that the input MI is before a partial terminator sequence TSeq, return
1369 /// true if M + TSeq also a partial terminator sequence.
1371 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1372 /// lowering copy vregs into physical registers, which are then passed into
1373 /// terminator instructors so we can satisfy ABI constraints. A partial
1374 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1375 /// may be the whole terminator sequence).
1376 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1377 // If we do not have a copy or an implicit def, we return true if and only if
1378 // MI is a debug value.
1379 if (!MI->isCopy() && !MI->isImplicitDef())
1380 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1381 // physical registers if there is debug info associated with the terminator
1382 // of our mbb. We want to include said debug info in our terminator
1383 // sequence, so we return true in that case.
1384 return MI->isDebugValue();
1386 // We have left the terminator sequence if we are not doing one of the
1389 // 1. Copying a vreg into a physical register.
1390 // 2. Copying a vreg into a vreg.
1391 // 3. Defining a register via an implicit def.
1393 // OPI should always be a register definition...
1394 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1395 if (!OPI->isReg() || !OPI->isDef())
1398 // Defining any register via an implicit def is always ok.
1399 if (MI->isImplicitDef())
1402 // Grab the copy source...
1403 MachineInstr::const_mop_iterator OPI2 = OPI;
1405 assert(OPI2 != MI->operands_end()
1406 && "Should have a copy implying we should have 2 arguments.");
1408 // Make sure that the copy dest is not a vreg when the copy source is a
1409 // physical register.
1410 if (!OPI2->isReg() ||
1411 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1412 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1418 /// Find the split point at which to splice the end of BB into its success stack
1419 /// protector check machine basic block.
1421 /// On many platforms, due to ABI constraints, terminators, even before register
1422 /// allocation, use physical registers. This creates an issue for us since
1423 /// physical registers at this point can not travel across basic
1424 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1425 /// when they enter functions and moves them through a sequence of copies back
1426 /// into the physical registers right before the terminator creating a
1427 /// ``Terminator Sequence''. This function is searching for the beginning of the
1428 /// terminator sequence so that we can ensure that we splice off not just the
1429 /// terminator, but additionally the copies that move the vregs into the
1430 /// physical registers.
1431 static MachineBasicBlock::iterator
1432 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1433 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1435 if (SplitPoint == BB->begin())
1438 MachineBasicBlock::iterator Start = BB->begin();
1439 MachineBasicBlock::iterator Previous = SplitPoint;
1442 while (MIIsInTerminatorSequence(Previous)) {
1443 SplitPoint = Previous;
1444 if (Previous == Start)
1453 SelectionDAGISel::FinishBasicBlock() {
1455 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1456 << FuncInfo->PHINodesToUpdate.size() << "\n";
1457 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1458 dbgs() << "Node " << i << " : ("
1459 << FuncInfo->PHINodesToUpdate[i].first
1460 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1462 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1463 // PHI nodes in successors.
1464 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1465 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1466 assert(PHI->isPHI() &&
1467 "This is not a machine PHI node that we are updating!");
1468 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1470 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1473 // Handle stack protector.
1474 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1475 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1476 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1478 // Find the split point to split the parent mbb. At the same time copy all
1479 // physical registers used in the tail of parent mbb into virtual registers
1480 // before the split point and back into physical registers after the split
1481 // point. This prevents us needing to deal with Live-ins and many other
1482 // register allocation issues caused by us splitting the parent mbb. The
1483 // register allocator will clean up said virtual copies later on.
1484 MachineBasicBlock::iterator SplitPoint =
1485 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1487 // Splice the terminator of ParentMBB into SuccessMBB.
1488 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1492 // Add compare/jump on neq/jump to the parent BB.
1493 FuncInfo->MBB = ParentMBB;
1494 FuncInfo->InsertPt = ParentMBB->end();
1495 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1496 CurDAG->setRoot(SDB->getRoot());
1498 CodeGenAndEmitDAG();
1500 // CodeGen Failure MBB if we have not codegened it yet.
1501 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1502 if (!FailureMBB->size()) {
1503 FuncInfo->MBB = FailureMBB;
1504 FuncInfo->InsertPt = FailureMBB->end();
1505 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1506 CurDAG->setRoot(SDB->getRoot());
1508 CodeGenAndEmitDAG();
1511 // Clear the Per-BB State.
1512 SDB->SPDescriptor.resetPerBBState();
1515 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1516 // Lower header first, if it wasn't already lowered
1517 if (!SDB->BitTestCases[i].Emitted) {
1518 // Set the current basic block to the mbb we wish to insert the code into
1519 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1520 FuncInfo->InsertPt = FuncInfo->MBB->end();
1522 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1523 CurDAG->setRoot(SDB->getRoot());
1525 CodeGenAndEmitDAG();
1528 uint32_t UnhandledWeight = 0;
1529 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1530 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1532 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1533 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1534 // Set the current basic block to the mbb we wish to insert the code into
1535 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1536 FuncInfo->InsertPt = FuncInfo->MBB->end();
1539 SDB->visitBitTestCase(SDB->BitTestCases[i],
1540 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1542 SDB->BitTestCases[i].Reg,
1543 SDB->BitTestCases[i].Cases[j],
1546 SDB->visitBitTestCase(SDB->BitTestCases[i],
1547 SDB->BitTestCases[i].Default,
1549 SDB->BitTestCases[i].Reg,
1550 SDB->BitTestCases[i].Cases[j],
1554 CurDAG->setRoot(SDB->getRoot());
1556 CodeGenAndEmitDAG();
1560 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1562 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1563 MachineBasicBlock *PHIBB = PHI->getParent();
1564 assert(PHI->isPHI() &&
1565 "This is not a machine PHI node that we are updating!");
1566 // This is "default" BB. We have two jumps to it. From "header" BB and
1567 // from last "case" BB.
1568 if (PHIBB == SDB->BitTestCases[i].Default)
1569 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1570 .addMBB(SDB->BitTestCases[i].Parent)
1571 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1572 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1573 // One of "cases" BB.
1574 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1576 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1577 if (cBB->isSuccessor(PHIBB))
1578 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1582 SDB->BitTestCases.clear();
1584 // If the JumpTable record is filled in, then we need to emit a jump table.
1585 // Updating the PHI nodes is tricky in this case, since we need to determine
1586 // whether the PHI is a successor of the range check MBB or the jump table MBB
1587 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1588 // Lower header first, if it wasn't already lowered
1589 if (!SDB->JTCases[i].first.Emitted) {
1590 // Set the current basic block to the mbb we wish to insert the code into
1591 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1592 FuncInfo->InsertPt = FuncInfo->MBB->end();
1594 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1596 CurDAG->setRoot(SDB->getRoot());
1598 CodeGenAndEmitDAG();
1601 // Set the current basic block to the mbb we wish to insert the code into
1602 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1603 FuncInfo->InsertPt = FuncInfo->MBB->end();
1605 SDB->visitJumpTable(SDB->JTCases[i].second);
1606 CurDAG->setRoot(SDB->getRoot());
1608 CodeGenAndEmitDAG();
1611 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1613 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1614 MachineBasicBlock *PHIBB = PHI->getParent();
1615 assert(PHI->isPHI() &&
1616 "This is not a machine PHI node that we are updating!");
1617 // "default" BB. We can go there only from header BB.
1618 if (PHIBB == SDB->JTCases[i].second.Default)
1619 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1620 .addMBB(SDB->JTCases[i].first.HeaderBB);
1621 // JT BB. Just iterate over successors here
1622 if (FuncInfo->MBB->isSuccessor(PHIBB))
1623 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1626 SDB->JTCases.clear();
1628 // If we generated any switch lowering information, build and codegen any
1629 // additional DAGs necessary.
1630 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1631 // Set the current basic block to the mbb we wish to insert the code into
1632 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1633 FuncInfo->InsertPt = FuncInfo->MBB->end();
1635 // Determine the unique successors.
1636 SmallVector<MachineBasicBlock *, 2> Succs;
1637 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1638 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1639 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1641 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1642 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1643 CurDAG->setRoot(SDB->getRoot());
1645 CodeGenAndEmitDAG();
1647 // Remember the last block, now that any splitting is done, for use in
1648 // populating PHI nodes in successors.
1649 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1651 // Handle any PHI nodes in successors of this chunk, as if we were coming
1652 // from the original BB before switch expansion. Note that PHI nodes can
1653 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1654 // handle them the right number of times.
1655 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1656 FuncInfo->MBB = Succs[i];
1657 FuncInfo->InsertPt = FuncInfo->MBB->end();
1658 // FuncInfo->MBB may have been removed from the CFG if a branch was
1660 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1661 for (MachineBasicBlock::iterator
1662 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1663 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1664 MachineInstrBuilder PHI(*MF, MBBI);
1665 // This value for this PHI node is recorded in PHINodesToUpdate.
1666 for (unsigned pn = 0; ; ++pn) {
1667 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1668 "Didn't find PHI entry!");
1669 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1670 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1678 SDB->SwitchCases.clear();
1682 /// Create the scheduler. If a specific scheduler was specified
1683 /// via the SchedulerRegistry, use it, otherwise select the
1684 /// one preferred by the target.
1686 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1687 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1691 RegisterScheduler::setDefault(Ctor);
1694 return Ctor(this, OptLevel);
1697 //===----------------------------------------------------------------------===//
1698 // Helper functions used by the generated instruction selector.
1699 //===----------------------------------------------------------------------===//
1700 // Calls to these methods are generated by tblgen.
1702 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1703 /// the dag combiner simplified the 255, we still want to match. RHS is the
1704 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1705 /// specified in the .td file (e.g. 255).
1706 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1707 int64_t DesiredMaskS) const {
1708 const APInt &ActualMask = RHS->getAPIntValue();
1709 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1711 // If the actual mask exactly matches, success!
1712 if (ActualMask == DesiredMask)
1715 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1716 if (ActualMask.intersects(~DesiredMask))
1719 // Otherwise, the DAG Combiner may have proven that the value coming in is
1720 // either already zero or is not demanded. Check for known zero input bits.
1721 APInt NeededMask = DesiredMask & ~ActualMask;
1722 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1725 // TODO: check to see if missing bits are just not demanded.
1727 // Otherwise, this pattern doesn't match.
1731 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1732 /// the dag combiner simplified the 255, we still want to match. RHS is the
1733 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1734 /// specified in the .td file (e.g. 255).
1735 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1736 int64_t DesiredMaskS) const {
1737 const APInt &ActualMask = RHS->getAPIntValue();
1738 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1740 // If the actual mask exactly matches, success!
1741 if (ActualMask == DesiredMask)
1744 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1745 if (ActualMask.intersects(~DesiredMask))
1748 // Otherwise, the DAG Combiner may have proven that the value coming in is
1749 // either already zero or is not demanded. Check for known zero input bits.
1750 APInt NeededMask = DesiredMask & ~ActualMask;
1752 APInt KnownZero, KnownOne;
1753 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1755 // If all the missing bits in the or are already known to be set, match!
1756 if ((NeededMask & KnownOne) == NeededMask)
1759 // TODO: check to see if missing bits are just not demanded.
1761 // Otherwise, this pattern doesn't match.
1766 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1767 /// by tblgen. Others should not call it.
1768 void SelectionDAGISel::
1769 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1770 std::vector<SDValue> InOps;
1771 std::swap(InOps, Ops);
1773 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1774 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1775 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1776 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1778 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1779 if (InOps[e-1].getValueType() == MVT::Glue)
1780 --e; // Don't process a glue operand if it is here.
1783 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1784 if (!InlineAsm::isMemKind(Flags)) {
1785 // Just skip over this operand, copying the operands verbatim.
1786 Ops.insert(Ops.end(), InOps.begin()+i,
1787 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1788 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1790 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1791 "Memory operand with multiple values?");
1793 unsigned TiedToOperand;
1794 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1795 // We need the constraint ID from the operand this is tied to.
1796 unsigned CurOp = InlineAsm::Op_FirstOperand;
1797 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1798 for (; TiedToOperand; --TiedToOperand) {
1799 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1800 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1804 // Otherwise, this is a memory operand. Ask the target to select it.
1805 std::vector<SDValue> SelOps;
1806 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1807 InlineAsm::getMemoryConstraintID(Flags),
1809 report_fatal_error("Could not match memory address. Inline asm"
1812 // Add this to the output node.
1814 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1815 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1816 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1821 // Add the glue input back if present.
1822 if (e != InOps.size())
1823 Ops.push_back(InOps.back());
1826 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1829 static SDNode *findGlueUse(SDNode *N) {
1830 unsigned FlagResNo = N->getNumValues()-1;
1831 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1832 SDUse &Use = I.getUse();
1833 if (Use.getResNo() == FlagResNo)
1834 return Use.getUser();
1839 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1840 /// This function recursively traverses up the operand chain, ignoring
1842 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1843 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1844 bool IgnoreChains) {
1845 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1846 // greater than all of its (recursive) operands. If we scan to a point where
1847 // 'use' is smaller than the node we're scanning for, then we know we will
1850 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1851 // happen because we scan down to newly selected nodes in the case of glue
1853 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1856 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1857 // won't fail if we scan it again.
1858 if (!Visited.insert(Use).second)
1861 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1862 // Ignore chain uses, they are validated by HandleMergeInputChains.
1863 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1866 SDNode *N = Use->getOperand(i).getNode();
1868 if (Use == ImmedUse || Use == Root)
1869 continue; // We are not looking for immediate use.
1874 // Traverse up the operand chain.
1875 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1881 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1882 /// operand node N of U during instruction selection that starts at Root.
1883 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1884 SDNode *Root) const {
1885 if (OptLevel == CodeGenOpt::None) return false;
1886 return N.hasOneUse();
1889 /// IsLegalToFold - Returns true if the specific operand node N of
1890 /// U can be folded during instruction selection that starts at Root.
1891 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1892 CodeGenOpt::Level OptLevel,
1893 bool IgnoreChains) {
1894 if (OptLevel == CodeGenOpt::None) return false;
1896 // If Root use can somehow reach N through a path that that doesn't contain
1897 // U then folding N would create a cycle. e.g. In the following
1898 // diagram, Root can reach N through X. If N is folded into into Root, then
1899 // X is both a predecessor and a successor of U.
1910 // * indicates nodes to be folded together.
1912 // If Root produces glue, then it gets (even more) interesting. Since it
1913 // will be "glued" together with its glue use in the scheduler, we need to
1914 // check if it might reach N.
1933 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1934 // (call it Fold), then X is a predecessor of GU and a successor of
1935 // Fold. But since Fold and GU are glued together, this will create
1936 // a cycle in the scheduling graph.
1938 // If the node has glue, walk down the graph to the "lowest" node in the
1940 EVT VT = Root->getValueType(Root->getNumValues()-1);
1941 while (VT == MVT::Glue) {
1942 SDNode *GU = findGlueUse(Root);
1946 VT = Root->getValueType(Root->getNumValues()-1);
1948 // If our query node has a glue result with a use, we've walked up it. If
1949 // the user (which has already been selected) has a chain or indirectly uses
1950 // the chain, our WalkChainUsers predicate will not consider it. Because of
1951 // this, we cannot ignore chains in this predicate.
1952 IgnoreChains = false;
1956 SmallPtrSet<SDNode*, 16> Visited;
1957 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1960 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1961 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1962 SelectInlineAsmMemoryOperands(Ops);
1964 const EVT VTs[] = {MVT::Other, MVT::Glue};
1965 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1967 return New.getNode();
1971 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1973 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1974 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1976 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1977 SDValue New = CurDAG->getCopyFromReg(
1978 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1980 return New.getNode();
1984 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1986 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1987 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1988 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1989 Op->getOperand(2).getValueType());
1990 SDValue New = CurDAG->getCopyToReg(
1991 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1993 return New.getNode();
1998 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1999 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
2002 /// GetVBR - decode a vbr encoding whose top bit is set.
2003 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
2004 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
2005 assert(Val >= 128 && "Not a VBR");
2006 Val &= 127; // Remove first vbr bit.
2011 NextBits = MatcherTable[Idx++];
2012 Val |= (NextBits&127) << Shift;
2014 } while (NextBits & 128);
2020 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
2021 /// interior glue and chain results to use the new glue and chain results.
2022 void SelectionDAGISel::
2023 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
2024 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
2026 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
2027 bool isMorphNodeTo) {
2028 SmallVector<SDNode*, 4> NowDeadNodes;
2030 // Now that all the normal results are replaced, we replace the chain and
2031 // glue results if present.
2032 if (!ChainNodesMatched.empty()) {
2033 assert(InputChain.getNode() &&
2034 "Matched input chains but didn't produce a chain");
2035 // Loop over all of the nodes we matched that produced a chain result.
2036 // Replace all the chain results with the final chain we ended up with.
2037 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2038 SDNode *ChainNode = ChainNodesMatched[i];
2040 // If this node was already deleted, don't look at it.
2041 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2044 // Don't replace the results of the root node if we're doing a
2046 if (ChainNode == NodeToMatch && isMorphNodeTo)
2049 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2050 if (ChainVal.getValueType() == MVT::Glue)
2051 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2052 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2053 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2055 // If the node became dead and we haven't already seen it, delete it.
2056 if (ChainNode->use_empty() &&
2057 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2058 NowDeadNodes.push_back(ChainNode);
2062 // If the result produces glue, update any glue results in the matched
2063 // pattern with the glue result.
2064 if (InputGlue.getNode()) {
2065 // Handle any interior nodes explicitly marked.
2066 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2067 SDNode *FRN = GlueResultNodesMatched[i];
2069 // If this node was already deleted, don't look at it.
2070 if (FRN->getOpcode() == ISD::DELETED_NODE)
2073 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2074 "Doesn't have a glue result");
2075 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2078 // If the node became dead and we haven't already seen it, delete it.
2079 if (FRN->use_empty() &&
2080 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2081 NowDeadNodes.push_back(FRN);
2085 if (!NowDeadNodes.empty())
2086 CurDAG->RemoveDeadNodes(NowDeadNodes);
2088 DEBUG(dbgs() << "ISEL: Match complete!\n");
2094 CR_LeadsToInteriorNode
2097 /// WalkChainUsers - Walk down the users of the specified chained node that is
2098 /// part of the pattern we're matching, looking at all of the users we find.
2099 /// This determines whether something is an interior node, whether we have a
2100 /// non-pattern node in between two pattern nodes (which prevent folding because
2101 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2102 /// between pattern nodes (in which case the TF becomes part of the pattern).
2104 /// The walk we do here is guaranteed to be small because we quickly get down to
2105 /// already selected nodes "below" us.
2107 WalkChainUsers(const SDNode *ChainedNode,
2108 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2109 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2110 ChainResult Result = CR_Simple;
2112 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2113 E = ChainedNode->use_end(); UI != E; ++UI) {
2114 // Make sure the use is of the chain, not some other value we produce.
2115 if (UI.getUse().getValueType() != MVT::Other) continue;
2119 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2122 // If we see an already-selected machine node, then we've gone beyond the
2123 // pattern that we're selecting down into the already selected chunk of the
2125 unsigned UserOpcode = User->getOpcode();
2126 if (User->isMachineOpcode() ||
2127 UserOpcode == ISD::CopyToReg ||
2128 UserOpcode == ISD::CopyFromReg ||
2129 UserOpcode == ISD::INLINEASM ||
2130 UserOpcode == ISD::EH_LABEL ||
2131 UserOpcode == ISD::LIFETIME_START ||
2132 UserOpcode == ISD::LIFETIME_END) {
2133 // If their node ID got reset to -1 then they've already been selected.
2134 // Treat them like a MachineOpcode.
2135 if (User->getNodeId() == -1)
2139 // If we have a TokenFactor, we handle it specially.
2140 if (User->getOpcode() != ISD::TokenFactor) {
2141 // If the node isn't a token factor and isn't part of our pattern, then it
2142 // must be a random chained node in between two nodes we're selecting.
2143 // This happens when we have something like:
2148 // Because we structurally match the load/store as a read/modify/write,
2149 // but the call is chained between them. We cannot fold in this case
2150 // because it would induce a cycle in the graph.
2151 if (!std::count(ChainedNodesInPattern.begin(),
2152 ChainedNodesInPattern.end(), User))
2153 return CR_InducesCycle;
2155 // Otherwise we found a node that is part of our pattern. For example in:
2159 // This would happen when we're scanning down from the load and see the
2160 // store as a user. Record that there is a use of ChainedNode that is
2161 // part of the pattern and keep scanning uses.
2162 Result = CR_LeadsToInteriorNode;
2163 InteriorChainedNodes.push_back(User);
2167 // If we found a TokenFactor, there are two cases to consider: first if the
2168 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2169 // uses of the TF are in our pattern) we just want to ignore it. Second,
2170 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2176 // | \ DAG's like cheese
2179 // [TokenFactor] [Op]
2186 // In this case, the TokenFactor becomes part of our match and we rewrite it
2187 // as a new TokenFactor.
2189 // To distinguish these two cases, do a recursive walk down the uses.
2190 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2192 // If the uses of the TokenFactor are just already-selected nodes, ignore
2193 // it, it is "below" our pattern.
2195 case CR_InducesCycle:
2196 // If the uses of the TokenFactor lead to nodes that are not part of our
2197 // pattern that are not selected, folding would turn this into a cycle,
2199 return CR_InducesCycle;
2200 case CR_LeadsToInteriorNode:
2201 break; // Otherwise, keep processing.
2204 // Okay, we know we're in the interesting interior case. The TokenFactor
2205 // is now going to be considered part of the pattern so that we rewrite its
2206 // uses (it may have uses that are not part of the pattern) with the
2207 // ultimate chain result of the generated code. We will also add its chain
2208 // inputs as inputs to the ultimate TokenFactor we create.
2209 Result = CR_LeadsToInteriorNode;
2210 ChainedNodesInPattern.push_back(User);
2211 InteriorChainedNodes.push_back(User);
2218 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2219 /// operation for when the pattern matched at least one node with a chains. The
2220 /// input vector contains a list of all of the chained nodes that we match. We
2221 /// must determine if this is a valid thing to cover (i.e. matching it won't
2222 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2223 /// be used as the input node chain for the generated nodes.
2225 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2226 SelectionDAG *CurDAG) {
2227 // Walk all of the chained nodes we've matched, recursively scanning down the
2228 // users of the chain result. This adds any TokenFactor nodes that are caught
2229 // in between chained nodes to the chained and interior nodes list.
2230 SmallVector<SDNode*, 3> InteriorChainedNodes;
2231 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2232 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2233 InteriorChainedNodes) == CR_InducesCycle)
2234 return SDValue(); // Would induce a cycle.
2237 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2238 // that we are interested in. Form our input TokenFactor node.
2239 SmallVector<SDValue, 3> InputChains;
2240 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2241 // Add the input chain of this node to the InputChains list (which will be
2242 // the operands of the generated TokenFactor) if it's not an interior node.
2243 SDNode *N = ChainNodesMatched[i];
2244 if (N->getOpcode() != ISD::TokenFactor) {
2245 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2248 // Otherwise, add the input chain.
2249 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2250 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2251 InputChains.push_back(InChain);
2255 // If we have a token factor, we want to add all inputs of the token factor
2256 // that are not part of the pattern we're matching.
2257 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2258 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2259 N->getOperand(op).getNode()))
2260 InputChains.push_back(N->getOperand(op));
2264 if (InputChains.size() == 1)
2265 return InputChains[0];
2266 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2267 MVT::Other, InputChains);
2270 /// MorphNode - Handle morphing a node in place for the selector.
2271 SDNode *SelectionDAGISel::
2272 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2273 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2274 // It is possible we're using MorphNodeTo to replace a node with no
2275 // normal results with one that has a normal result (or we could be
2276 // adding a chain) and the input could have glue and chains as well.
2277 // In this case we need to shift the operands down.
2278 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2279 // than the old isel though.
2280 int OldGlueResultNo = -1, OldChainResultNo = -1;
2282 unsigned NTMNumResults = Node->getNumValues();
2283 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2284 OldGlueResultNo = NTMNumResults-1;
2285 if (NTMNumResults != 1 &&
2286 Node->getValueType(NTMNumResults-2) == MVT::Other)
2287 OldChainResultNo = NTMNumResults-2;
2288 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2289 OldChainResultNo = NTMNumResults-1;
2291 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2292 // that this deletes operands of the old node that become dead.
2293 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2295 // MorphNodeTo can operate in two ways: if an existing node with the
2296 // specified operands exists, it can just return it. Otherwise, it
2297 // updates the node in place to have the requested operands.
2299 // If we updated the node in place, reset the node ID. To the isel,
2300 // this should be just like a newly allocated machine node.
2304 unsigned ResNumResults = Res->getNumValues();
2305 // Move the glue if needed.
2306 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2307 (unsigned)OldGlueResultNo != ResNumResults-1)
2308 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2309 SDValue(Res, ResNumResults-1));
2311 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2314 // Move the chain reference if needed.
2315 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2316 (unsigned)OldChainResultNo != ResNumResults-1)
2317 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2318 SDValue(Res, ResNumResults-1));
2320 // Otherwise, no replacement happened because the node already exists. Replace
2321 // Uses of the old node with the new one.
2323 CurDAG->ReplaceAllUsesWith(Node, Res);
2328 /// CheckSame - Implements OP_CheckSame.
2329 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2330 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2332 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2333 // Accept if it is exactly the same as a previously recorded node.
2334 unsigned RecNo = MatcherTable[MatcherIndex++];
2335 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2336 return N == RecordedNodes[RecNo].first;
2339 /// CheckChildSame - Implements OP_CheckChildXSame.
2340 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2341 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2343 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2345 if (ChildNo >= N.getNumOperands())
2346 return false; // Match fails if out of range child #.
2347 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2351 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2352 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2353 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2354 const SelectionDAGISel &SDISel) {
2355 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2358 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2359 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2360 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2361 const SelectionDAGISel &SDISel, SDNode *N) {
2362 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2365 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2366 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2368 uint16_t Opc = MatcherTable[MatcherIndex++];
2369 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2370 return N->getOpcode() == Opc;
2373 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2374 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2375 SDValue N, const TargetLowering *TLI) {
2376 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2377 if (N.getValueType() == VT) return true;
2379 // Handle the case when VT is iPTR.
2380 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2383 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2384 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2385 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2386 if (ChildNo >= N.getNumOperands())
2387 return false; // Match fails if out of range child #.
2388 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2391 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2392 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2394 return cast<CondCodeSDNode>(N)->get() ==
2395 (ISD::CondCode)MatcherTable[MatcherIndex++];
2398 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2399 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2400 SDValue N, const TargetLowering *TLI) {
2401 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2402 if (cast<VTSDNode>(N)->getVT() == VT)
2405 // Handle the case when VT is iPTR.
2406 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2409 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2410 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2412 int64_t Val = MatcherTable[MatcherIndex++];
2414 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2416 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2417 return C && C->getSExtValue() == Val;
2420 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2421 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2422 SDValue N, unsigned ChildNo) {
2423 if (ChildNo >= N.getNumOperands())
2424 return false; // Match fails if out of range child #.
2425 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2428 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2429 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2430 SDValue N, const SelectionDAGISel &SDISel) {
2431 int64_t Val = MatcherTable[MatcherIndex++];
2433 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2435 if (N->getOpcode() != ISD::AND) return false;
2437 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2438 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2441 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2442 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2443 SDValue N, const SelectionDAGISel &SDISel) {
2444 int64_t Val = MatcherTable[MatcherIndex++];
2446 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2448 if (N->getOpcode() != ISD::OR) return false;
2450 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2451 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2454 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2455 /// scope, evaluate the current node. If the current predicate is known to
2456 /// fail, set Result=true and return anything. If the current predicate is
2457 /// known to pass, set Result=false and return the MatcherIndex to continue
2458 /// with. If the current predicate is unknown, set Result=false and return the
2459 /// MatcherIndex to continue with.
2460 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2461 unsigned Index, SDValue N,
2463 const SelectionDAGISel &SDISel,
2464 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2465 switch (Table[Index++]) {
2468 return Index-1; // Could not evaluate this predicate.
2469 case SelectionDAGISel::OPC_CheckSame:
2470 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2472 case SelectionDAGISel::OPC_CheckChild0Same:
2473 case SelectionDAGISel::OPC_CheckChild1Same:
2474 case SelectionDAGISel::OPC_CheckChild2Same:
2475 case SelectionDAGISel::OPC_CheckChild3Same:
2476 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2477 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2479 case SelectionDAGISel::OPC_CheckPatternPredicate:
2480 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2482 case SelectionDAGISel::OPC_CheckPredicate:
2483 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2485 case SelectionDAGISel::OPC_CheckOpcode:
2486 Result = !::CheckOpcode(Table, Index, N.getNode());
2488 case SelectionDAGISel::OPC_CheckType:
2489 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2491 case SelectionDAGISel::OPC_CheckChild0Type:
2492 case SelectionDAGISel::OPC_CheckChild1Type:
2493 case SelectionDAGISel::OPC_CheckChild2Type:
2494 case SelectionDAGISel::OPC_CheckChild3Type:
2495 case SelectionDAGISel::OPC_CheckChild4Type:
2496 case SelectionDAGISel::OPC_CheckChild5Type:
2497 case SelectionDAGISel::OPC_CheckChild6Type:
2498 case SelectionDAGISel::OPC_CheckChild7Type:
2499 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2501 SelectionDAGISel::OPC_CheckChild0Type);
2503 case SelectionDAGISel::OPC_CheckCondCode:
2504 Result = !::CheckCondCode(Table, Index, N);
2506 case SelectionDAGISel::OPC_CheckValueType:
2507 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2509 case SelectionDAGISel::OPC_CheckInteger:
2510 Result = !::CheckInteger(Table, Index, N);
2512 case SelectionDAGISel::OPC_CheckChild0Integer:
2513 case SelectionDAGISel::OPC_CheckChild1Integer:
2514 case SelectionDAGISel::OPC_CheckChild2Integer:
2515 case SelectionDAGISel::OPC_CheckChild3Integer:
2516 case SelectionDAGISel::OPC_CheckChild4Integer:
2517 Result = !::CheckChildInteger(Table, Index, N,
2518 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2520 case SelectionDAGISel::OPC_CheckAndImm:
2521 Result = !::CheckAndImm(Table, Index, N, SDISel);
2523 case SelectionDAGISel::OPC_CheckOrImm:
2524 Result = !::CheckOrImm(Table, Index, N, SDISel);
2532 /// FailIndex - If this match fails, this is the index to continue with.
2535 /// NodeStack - The node stack when the scope was formed.
2536 SmallVector<SDValue, 4> NodeStack;
2538 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2539 unsigned NumRecordedNodes;
2541 /// NumMatchedMemRefs - The number of matched memref entries.
2542 unsigned NumMatchedMemRefs;
2544 /// InputChain/InputGlue - The current chain/glue
2545 SDValue InputChain, InputGlue;
2547 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2548 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2551 /// \\brief A DAG update listener to keep the matching state
2552 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2553 /// change the DAG while matching. X86 addressing mode matcher is an example
2555 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2557 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2558 SmallVectorImpl<MatchScope> &MatchScopes;
2560 MatchStateUpdater(SelectionDAG &DAG,
2561 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2562 SmallVectorImpl<MatchScope> &MS) :
2563 SelectionDAG::DAGUpdateListener(DAG),
2564 RecordedNodes(RN), MatchScopes(MS) { }
2566 void NodeDeleted(SDNode *N, SDNode *E) override {
2567 // Some early-returns here to avoid the search if we deleted the node or
2568 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2569 // do, so it's unnecessary to update matching state at that point).
2570 // Neither of these can occur currently because we only install this
2571 // update listener during matching a complex patterns.
2572 if (!E || E->isMachineOpcode())
2574 // Performing linear search here does not matter because we almost never
2575 // run this code. You'd have to have a CSE during complex pattern
2577 for (auto &I : RecordedNodes)
2578 if (I.first.getNode() == N)
2581 for (auto &I : MatchScopes)
2582 for (auto &J : I.NodeStack)
2583 if (J.getNode() == N)
2589 SDNode *SelectionDAGISel::
2590 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2591 unsigned TableSize) {
2592 // FIXME: Should these even be selected? Handle these cases in the caller?
2593 switch (NodeToMatch->getOpcode()) {
2596 case ISD::EntryToken: // These nodes remain the same.
2597 case ISD::BasicBlock:
2599 case ISD::RegisterMask:
2600 case ISD::HANDLENODE:
2601 case ISD::MDNODE_SDNODE:
2602 case ISD::TargetConstant:
2603 case ISD::TargetConstantFP:
2604 case ISD::TargetConstantPool:
2605 case ISD::TargetFrameIndex:
2606 case ISD::TargetExternalSymbol:
2607 case ISD::TargetBlockAddress:
2608 case ISD::TargetJumpTable:
2609 case ISD::TargetGlobalTLSAddress:
2610 case ISD::TargetGlobalAddress:
2611 case ISD::TokenFactor:
2612 case ISD::CopyFromReg:
2613 case ISD::CopyToReg:
2615 case ISD::LIFETIME_START:
2616 case ISD::LIFETIME_END:
2617 NodeToMatch->setNodeId(-1); // Mark selected.
2619 case ISD::AssertSext:
2620 case ISD::AssertZext:
2621 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2622 NodeToMatch->getOperand(0));
2624 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2625 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2626 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2627 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2630 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2632 // Set up the node stack with NodeToMatch as the only node on the stack.
2633 SmallVector<SDValue, 8> NodeStack;
2634 SDValue N = SDValue(NodeToMatch, 0);
2635 NodeStack.push_back(N);
2637 // MatchScopes - Scopes used when matching, if a match failure happens, this
2638 // indicates where to continue checking.
2639 SmallVector<MatchScope, 8> MatchScopes;
2641 // RecordedNodes - This is the set of nodes that have been recorded by the
2642 // state machine. The second value is the parent of the node, or null if the
2643 // root is recorded.
2644 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2646 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2648 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2650 // These are the current input chain and glue for use when generating nodes.
2651 // Various Emit operations change these. For example, emitting a copytoreg
2652 // uses and updates these.
2653 SDValue InputChain, InputGlue;
2655 // ChainNodesMatched - If a pattern matches nodes that have input/output
2656 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2657 // which ones they are. The result is captured into this list so that we can
2658 // update the chain results when the pattern is complete.
2659 SmallVector<SDNode*, 3> ChainNodesMatched;
2660 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2662 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2663 NodeToMatch->dump(CurDAG);
2666 // Determine where to start the interpreter. Normally we start at opcode #0,
2667 // but if the state machine starts with an OPC_SwitchOpcode, then we
2668 // accelerate the first lookup (which is guaranteed to be hot) with the
2669 // OpcodeOffset table.
2670 unsigned MatcherIndex = 0;
2672 if (!OpcodeOffset.empty()) {
2673 // Already computed the OpcodeOffset table, just index into it.
2674 if (N.getOpcode() < OpcodeOffset.size())
2675 MatcherIndex = OpcodeOffset[N.getOpcode()];
2676 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2678 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2679 // Otherwise, the table isn't computed, but the state machine does start
2680 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2681 // is the first time we're selecting an instruction.
2684 // Get the size of this case.
2685 unsigned CaseSize = MatcherTable[Idx++];
2687 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2688 if (CaseSize == 0) break;
2690 // Get the opcode, add the index to the table.
2691 uint16_t Opc = MatcherTable[Idx++];
2692 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2693 if (Opc >= OpcodeOffset.size())
2694 OpcodeOffset.resize((Opc+1)*2);
2695 OpcodeOffset[Opc] = Idx;
2699 // Okay, do the lookup for the first opcode.
2700 if (N.getOpcode() < OpcodeOffset.size())
2701 MatcherIndex = OpcodeOffset[N.getOpcode()];
2705 assert(MatcherIndex < TableSize && "Invalid index");
2707 unsigned CurrentOpcodeIndex = MatcherIndex;
2709 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2712 // Okay, the semantics of this operation are that we should push a scope
2713 // then evaluate the first child. However, pushing a scope only to have
2714 // the first check fail (which then pops it) is inefficient. If we can
2715 // determine immediately that the first check (or first several) will
2716 // immediately fail, don't even bother pushing a scope for them.
2720 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2721 if (NumToSkip & 128)
2722 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2723 // Found the end of the scope with no match.
2724 if (NumToSkip == 0) {
2729 FailIndex = MatcherIndex+NumToSkip;
2731 unsigned MatcherIndexOfPredicate = MatcherIndex;
2732 (void)MatcherIndexOfPredicate; // silence warning.
2734 // If we can't evaluate this predicate without pushing a scope (e.g. if
2735 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2736 // push the scope and evaluate the full predicate chain.
2738 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2739 Result, *this, RecordedNodes);
2743 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2744 << "index " << MatcherIndexOfPredicate
2745 << ", continuing at " << FailIndex << "\n");
2746 ++NumDAGIselRetries;
2748 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2749 // move to the next case.
2750 MatcherIndex = FailIndex;
2753 // If the whole scope failed to match, bail.
2754 if (FailIndex == 0) break;
2756 // Push a MatchScope which indicates where to go if the first child fails
2758 MatchScope NewEntry;
2759 NewEntry.FailIndex = FailIndex;
2760 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2761 NewEntry.NumRecordedNodes = RecordedNodes.size();
2762 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2763 NewEntry.InputChain = InputChain;
2764 NewEntry.InputGlue = InputGlue;
2765 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2766 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2767 MatchScopes.push_back(NewEntry);
2770 case OPC_RecordNode: {
2771 // Remember this node, it may end up being an operand in the pattern.
2772 SDNode *Parent = nullptr;
2773 if (NodeStack.size() > 1)
2774 Parent = NodeStack[NodeStack.size()-2].getNode();
2775 RecordedNodes.push_back(std::make_pair(N, Parent));
2779 case OPC_RecordChild0: case OPC_RecordChild1:
2780 case OPC_RecordChild2: case OPC_RecordChild3:
2781 case OPC_RecordChild4: case OPC_RecordChild5:
2782 case OPC_RecordChild6: case OPC_RecordChild7: {
2783 unsigned ChildNo = Opcode-OPC_RecordChild0;
2784 if (ChildNo >= N.getNumOperands())
2785 break; // Match fails if out of range child #.
2787 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2791 case OPC_RecordMemRef:
2792 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2795 case OPC_CaptureGlueInput:
2796 // If the current node has an input glue, capture it in InputGlue.
2797 if (N->getNumOperands() != 0 &&
2798 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2799 InputGlue = N->getOperand(N->getNumOperands()-1);
2802 case OPC_MoveChild: {
2803 unsigned ChildNo = MatcherTable[MatcherIndex++];
2804 if (ChildNo >= N.getNumOperands())
2805 break; // Match fails if out of range child #.
2806 N = N.getOperand(ChildNo);
2807 NodeStack.push_back(N);
2811 case OPC_MoveParent:
2812 // Pop the current node off the NodeStack.
2813 NodeStack.pop_back();
2814 assert(!NodeStack.empty() && "Node stack imbalance!");
2815 N = NodeStack.back();
2819 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2822 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2823 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2824 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2825 Opcode-OPC_CheckChild0Same))
2829 case OPC_CheckPatternPredicate:
2830 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2832 case OPC_CheckPredicate:
2833 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2837 case OPC_CheckComplexPat: {
2838 unsigned CPNum = MatcherTable[MatcherIndex++];
2839 unsigned RecNo = MatcherTable[MatcherIndex++];
2840 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2842 // If target can modify DAG during matching, keep the matching state
2844 std::unique_ptr<MatchStateUpdater> MSU;
2845 if (ComplexPatternFuncMutatesDAG())
2846 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2849 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2850 RecordedNodes[RecNo].first, CPNum,
2855 case OPC_CheckOpcode:
2856 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2860 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2864 case OPC_SwitchOpcode: {
2865 unsigned CurNodeOpcode = N.getOpcode();
2866 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2869 // Get the size of this case.
2870 CaseSize = MatcherTable[MatcherIndex++];
2872 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2873 if (CaseSize == 0) break;
2875 uint16_t Opc = MatcherTable[MatcherIndex++];
2876 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2878 // If the opcode matches, then we will execute this case.
2879 if (CurNodeOpcode == Opc)
2882 // Otherwise, skip over this case.
2883 MatcherIndex += CaseSize;
2886 // If no cases matched, bail out.
2887 if (CaseSize == 0) break;
2889 // Otherwise, execute the case we found.
2890 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2891 << " to " << MatcherIndex << "\n");
2895 case OPC_SwitchType: {
2896 MVT CurNodeVT = N.getSimpleValueType();
2897 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2900 // Get the size of this case.
2901 CaseSize = MatcherTable[MatcherIndex++];
2903 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2904 if (CaseSize == 0) break;
2906 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2907 if (CaseVT == MVT::iPTR)
2908 CaseVT = TLI->getPointerTy();
2910 // If the VT matches, then we will execute this case.
2911 if (CurNodeVT == CaseVT)
2914 // Otherwise, skip over this case.
2915 MatcherIndex += CaseSize;
2918 // If no cases matched, bail out.
2919 if (CaseSize == 0) break;
2921 // Otherwise, execute the case we found.
2922 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2923 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2926 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2927 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2928 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2929 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2930 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2931 Opcode-OPC_CheckChild0Type))
2934 case OPC_CheckCondCode:
2935 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2937 case OPC_CheckValueType:
2938 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2941 case OPC_CheckInteger:
2942 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2944 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2945 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2946 case OPC_CheckChild4Integer:
2947 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2948 Opcode-OPC_CheckChild0Integer)) break;
2950 case OPC_CheckAndImm:
2951 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2953 case OPC_CheckOrImm:
2954 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2957 case OPC_CheckFoldableChainNode: {
2958 assert(NodeStack.size() != 1 && "No parent node");
2959 // Verify that all intermediate nodes between the root and this one have
2961 bool HasMultipleUses = false;
2962 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2963 if (!NodeStack[i].hasOneUse()) {
2964 HasMultipleUses = true;
2967 if (HasMultipleUses) break;
2969 // Check to see that the target thinks this is profitable to fold and that
2970 // we can fold it without inducing cycles in the graph.
2971 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2973 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2974 NodeToMatch, OptLevel,
2975 true/*We validate our own chains*/))
2980 case OPC_EmitInteger: {
2981 MVT::SimpleValueType VT =
2982 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2983 int64_t Val = MatcherTable[MatcherIndex++];
2985 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2986 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2987 CurDAG->getTargetConstant(Val, VT), nullptr));
2990 case OPC_EmitRegister: {
2991 MVT::SimpleValueType VT =
2992 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2993 unsigned RegNo = MatcherTable[MatcherIndex++];
2994 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2995 CurDAG->getRegister(RegNo, VT), nullptr));
2998 case OPC_EmitRegister2: {
2999 // For targets w/ more than 256 register names, the register enum
3000 // values are stored in two bytes in the matcher table (just like
3002 MVT::SimpleValueType VT =
3003 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3004 unsigned RegNo = MatcherTable[MatcherIndex++];
3005 RegNo |= MatcherTable[MatcherIndex++] << 8;
3006 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3007 CurDAG->getRegister(RegNo, VT), nullptr));
3011 case OPC_EmitConvertToTarget: {
3012 // Convert from IMM/FPIMM to target version.
3013 unsigned RecNo = MatcherTable[MatcherIndex++];
3014 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
3015 SDValue Imm = RecordedNodes[RecNo].first;
3017 if (Imm->getOpcode() == ISD::Constant) {
3018 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3019 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
3020 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3021 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3022 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
3025 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3029 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3030 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3031 // These are space-optimized forms of OPC_EmitMergeInputChains.
3032 assert(!InputChain.getNode() &&
3033 "EmitMergeInputChains should be the first chain producing node");
3034 assert(ChainNodesMatched.empty() &&
3035 "Should only have one EmitMergeInputChains per match");
3037 // Read all of the chained nodes.
3038 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3039 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3040 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3042 // FIXME: What if other value results of the node have uses not matched
3044 if (ChainNodesMatched.back() != NodeToMatch &&
3045 !RecordedNodes[RecNo].first.hasOneUse()) {
3046 ChainNodesMatched.clear();
3050 // Merge the input chains if they are not intra-pattern references.
3051 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3053 if (!InputChain.getNode())
3054 break; // Failed to merge.
3058 case OPC_EmitMergeInputChains: {
3059 assert(!InputChain.getNode() &&
3060 "EmitMergeInputChains should be the first chain producing node");
3061 // This node gets a list of nodes we matched in the input that have
3062 // chains. We want to token factor all of the input chains to these nodes
3063 // together. However, if any of the input chains is actually one of the
3064 // nodes matched in this pattern, then we have an intra-match reference.
3065 // Ignore these because the newly token factored chain should not refer to
3067 unsigned NumChains = MatcherTable[MatcherIndex++];
3068 assert(NumChains != 0 && "Can't TF zero chains");
3070 assert(ChainNodesMatched.empty() &&
3071 "Should only have one EmitMergeInputChains per match");
3073 // Read all of the chained nodes.
3074 for (unsigned i = 0; i != NumChains; ++i) {
3075 unsigned RecNo = MatcherTable[MatcherIndex++];
3076 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3077 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3079 // FIXME: What if other value results of the node have uses not matched
3081 if (ChainNodesMatched.back() != NodeToMatch &&
3082 !RecordedNodes[RecNo].first.hasOneUse()) {
3083 ChainNodesMatched.clear();
3088 // If the inner loop broke out, the match fails.
3089 if (ChainNodesMatched.empty())
3092 // Merge the input chains if they are not intra-pattern references.
3093 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3095 if (!InputChain.getNode())
3096 break; // Failed to merge.
3101 case OPC_EmitCopyToReg: {
3102 unsigned RecNo = MatcherTable[MatcherIndex++];
3103 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3104 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3106 if (!InputChain.getNode())
3107 InputChain = CurDAG->getEntryNode();
3109 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3110 DestPhysReg, RecordedNodes[RecNo].first,
3113 InputGlue = InputChain.getValue(1);
3117 case OPC_EmitNodeXForm: {
3118 unsigned XFormNo = MatcherTable[MatcherIndex++];
3119 unsigned RecNo = MatcherTable[MatcherIndex++];
3120 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3121 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3122 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3127 case OPC_MorphNodeTo: {
3128 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3129 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3130 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3131 // Get the result VT list.
3132 unsigned NumVTs = MatcherTable[MatcherIndex++];
3133 SmallVector<EVT, 4> VTs;
3134 for (unsigned i = 0; i != NumVTs; ++i) {
3135 MVT::SimpleValueType VT =
3136 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3137 if (VT == MVT::iPTR)
3138 VT = TLI->getPointerTy().SimpleTy;
3142 if (EmitNodeInfo & OPFL_Chain)
3143 VTs.push_back(MVT::Other);
3144 if (EmitNodeInfo & OPFL_GlueOutput)
3145 VTs.push_back(MVT::Glue);
3147 // This is hot code, so optimize the two most common cases of 1 and 2
3150 if (VTs.size() == 1)
3151 VTList = CurDAG->getVTList(VTs[0]);
3152 else if (VTs.size() == 2)
3153 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3155 VTList = CurDAG->getVTList(VTs);
3157 // Get the operand list.
3158 unsigned NumOps = MatcherTable[MatcherIndex++];
3159 SmallVector<SDValue, 8> Ops;
3160 for (unsigned i = 0; i != NumOps; ++i) {
3161 unsigned RecNo = MatcherTable[MatcherIndex++];
3163 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3165 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3166 Ops.push_back(RecordedNodes[RecNo].first);
3169 // If there are variadic operands to add, handle them now.
3170 if (EmitNodeInfo & OPFL_VariadicInfo) {
3171 // Determine the start index to copy from.
3172 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3173 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3174 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3175 "Invalid variadic node");
3176 // Copy all of the variadic operands, not including a potential glue
3178 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3180 SDValue V = NodeToMatch->getOperand(i);
3181 if (V.getValueType() == MVT::Glue) break;
3186 // If this has chain/glue inputs, add them.
3187 if (EmitNodeInfo & OPFL_Chain)
3188 Ops.push_back(InputChain);
3189 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3190 Ops.push_back(InputGlue);
3193 SDNode *Res = nullptr;
3194 if (Opcode != OPC_MorphNodeTo) {
3195 // If this is a normal EmitNode command, just create the new node and
3196 // add the results to the RecordedNodes list.
3197 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3200 // Add all the non-glue/non-chain results to the RecordedNodes list.
3201 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3202 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3203 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3207 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3208 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3210 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3211 // We will visit the equivalent node later.
3212 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3216 // If the node had chain/glue results, update our notion of the current
3218 if (EmitNodeInfo & OPFL_GlueOutput) {
3219 InputGlue = SDValue(Res, VTs.size()-1);
3220 if (EmitNodeInfo & OPFL_Chain)
3221 InputChain = SDValue(Res, VTs.size()-2);
3222 } else if (EmitNodeInfo & OPFL_Chain)
3223 InputChain = SDValue(Res, VTs.size()-1);
3225 // If the OPFL_MemRefs glue is set on this node, slap all of the
3226 // accumulated memrefs onto it.
3228 // FIXME: This is vastly incorrect for patterns with multiple outputs
3229 // instructions that access memory and for ComplexPatterns that match
3231 if (EmitNodeInfo & OPFL_MemRefs) {
3232 // Only attach load or store memory operands if the generated
3233 // instruction may load or store.
3234 const MCInstrDesc &MCID = TII->get(TargetOpc);
3235 bool mayLoad = MCID.mayLoad();
3236 bool mayStore = MCID.mayStore();
3238 unsigned NumMemRefs = 0;
3239 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3240 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3241 if ((*I)->isLoad()) {
3244 } else if ((*I)->isStore()) {
3252 MachineSDNode::mmo_iterator MemRefs =
3253 MF->allocateMemRefsArray(NumMemRefs);
3255 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3256 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3257 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3258 if ((*I)->isLoad()) {
3261 } else if ((*I)->isStore()) {
3269 cast<MachineSDNode>(Res)
3270 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3274 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3275 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3277 // If this was a MorphNodeTo then we're completely done!
3278 if (Opcode == OPC_MorphNodeTo) {
3279 // Update chain and glue uses.
3280 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3281 InputGlue, GlueResultNodesMatched, true);
3288 case OPC_MarkGlueResults: {
3289 unsigned NumNodes = MatcherTable[MatcherIndex++];
3291 // Read and remember all the glue-result nodes.
3292 for (unsigned i = 0; i != NumNodes; ++i) {
3293 unsigned RecNo = MatcherTable[MatcherIndex++];
3295 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3297 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3298 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3303 case OPC_CompleteMatch: {
3304 // The match has been completed, and any new nodes (if any) have been
3305 // created. Patch up references to the matched dag to use the newly
3307 unsigned NumResults = MatcherTable[MatcherIndex++];
3309 for (unsigned i = 0; i != NumResults; ++i) {
3310 unsigned ResSlot = MatcherTable[MatcherIndex++];
3312 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3314 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3315 SDValue Res = RecordedNodes[ResSlot].first;
3317 assert(i < NodeToMatch->getNumValues() &&
3318 NodeToMatch->getValueType(i) != MVT::Other &&
3319 NodeToMatch->getValueType(i) != MVT::Glue &&
3320 "Invalid number of results to complete!");
3321 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3322 NodeToMatch->getValueType(i) == MVT::iPTR ||
3323 Res.getValueType() == MVT::iPTR ||
3324 NodeToMatch->getValueType(i).getSizeInBits() ==
3325 Res.getValueType().getSizeInBits()) &&
3326 "invalid replacement");
3327 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3330 // If the root node defines glue, add it to the glue nodes to update list.
3331 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3332 GlueResultNodesMatched.push_back(NodeToMatch);
3334 // Update chain and glue uses.
3335 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3336 InputGlue, GlueResultNodesMatched, false);
3338 assert(NodeToMatch->use_empty() &&
3339 "Didn't replace all uses of the node?");
3341 // FIXME: We just return here, which interacts correctly with SelectRoot
3342 // above. We should fix this to not return an SDNode* anymore.
3347 // If the code reached this point, then the match failed. See if there is
3348 // another child to try in the current 'Scope', otherwise pop it until we
3349 // find a case to check.
3350 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3351 ++NumDAGIselRetries;
3353 if (MatchScopes.empty()) {
3354 CannotYetSelect(NodeToMatch);
3358 // Restore the interpreter state back to the point where the scope was
3360 MatchScope &LastScope = MatchScopes.back();
3361 RecordedNodes.resize(LastScope.NumRecordedNodes);
3363 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3364 N = NodeStack.back();
3366 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3367 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3368 MatcherIndex = LastScope.FailIndex;
3370 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3372 InputChain = LastScope.InputChain;
3373 InputGlue = LastScope.InputGlue;
3374 if (!LastScope.HasChainNodesMatched)
3375 ChainNodesMatched.clear();
3376 if (!LastScope.HasGlueResultNodesMatched)
3377 GlueResultNodesMatched.clear();
3379 // Check to see what the offset is at the new MatcherIndex. If it is zero
3380 // we have reached the end of this scope, otherwise we have another child
3381 // in the current scope to try.
3382 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3383 if (NumToSkip & 128)
3384 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3386 // If we have another child in this scope to match, update FailIndex and
3388 if (NumToSkip != 0) {
3389 LastScope.FailIndex = MatcherIndex+NumToSkip;
3393 // End of this scope, pop it and try the next child in the containing
3395 MatchScopes.pop_back();
3402 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3404 raw_string_ostream Msg(msg);
3405 Msg << "Cannot select: ";
3407 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3408 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3409 N->getOpcode() != ISD::INTRINSIC_VOID) {
3410 N->printrFull(Msg, CurDAG);
3411 Msg << "\nIn function: " << MF->getName();
3413 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3415 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3416 if (iid < Intrinsic::num_intrinsics)
3417 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3418 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3419 Msg << "target intrinsic %" << TII->getName(iid);
3421 Msg << "unknown intrinsic #" << iid;
3423 report_fatal_error(Msg.str());
3426 char SelectionDAGISel::ID = 0;