1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
17 #include "StatepointLowering.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
22 #include "llvm/IR/CallSite.h"
23 #include "llvm/IR/Statepoint.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetLowering.h"
31 class AddrSpaceCastInst;
39 class ExtractElementInst;
40 class ExtractValueInst;
47 class FunctionLoweringInfo;
48 class GetElementPtrInst;
54 class InsertElementInst;
55 class InsertValueInst;
58 class MachineBasicBlock;
60 class MachineRegisterInfo;
69 class ShuffleVectorInst;
74 class TargetLibraryInfo;
78 class UnreachableInst;
82 //===----------------------------------------------------------------------===//
83 /// SelectionDAGBuilder - This is the common target-independent lowering
84 /// implementation that is parameterized by a TargetLowering object.
86 class SelectionDAGBuilder {
87 /// CurInst - The current instruction being visited
88 const Instruction *CurInst;
90 DenseMap<const Value*, SDValue> NodeMap;
92 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
93 /// to preserve debug information for incoming arguments.
94 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
96 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
97 class DanglingDebugInfo {
98 const DbgValueInst* DI;
100 unsigned SDNodeOrder;
102 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
103 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
104 DI(di), dl(DL), SDNodeOrder(SDNO) { }
105 const DbgValueInst* getDI() { return DI; }
106 DebugLoc getdl() { return dl; }
107 unsigned getSDNodeOrder() { return SDNodeOrder; }
110 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
111 /// yet seen the referent. We defer handling these until we do see it.
112 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
115 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
116 /// them up and then emit token factor nodes when possible. This allows us to
117 /// get simple disambiguation between loads without worrying about alias
119 SmallVector<SDValue, 8> PendingLoads;
121 /// State used while lowering a statepoint sequence (gc_statepoint,
122 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
123 StatepointLoweringState StatepointLowering;
126 /// PendingExports - CopyToReg nodes that copy values to virtual registers
127 /// for export to other blocks need to be emitted before any terminator
128 /// instruction, but they have no other ordering requirements. We bunch them
129 /// up and the emit a single tokenfactor for them just before terminator
131 SmallVector<SDValue, 8> PendingExports;
133 /// SDNodeOrder - A unique monotonically increasing number used to order the
134 /// SDNodes we create.
135 unsigned SDNodeOrder;
137 /// Case - A struct to record the Value for a switch case, and the
138 /// case's target basic block.
140 const ConstantInt *Low;
141 const ConstantInt *High;
142 MachineBasicBlock* BB;
143 uint32_t ExtraWeight;
145 Case() : Low(nullptr), High(nullptr), BB(nullptr), ExtraWeight(0) { }
146 Case(const ConstantInt *low, const ConstantInt *high, MachineBasicBlock *bb,
147 uint32_t extraweight) : Low(low), High(high), BB(bb),
148 ExtraWeight(extraweight) { }
151 const APInt &rHigh = High->getValue();
152 const APInt &rLow = Low->getValue();
153 return (rHigh - rLow + 1ULL);
159 MachineBasicBlock* BB;
161 uint32_t ExtraWeight;
163 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
165 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
168 typedef std::vector<Case> CaseVector;
169 typedef std::vector<CaseBits> CaseBitsVector;
170 typedef CaseVector::iterator CaseItr;
171 typedef std::pair<CaseItr, CaseItr> CaseRange;
173 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
174 /// of conditional branches.
176 CaseRec(MachineBasicBlock *bb, const ConstantInt *lt, const ConstantInt *ge,
178 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
180 /// CaseBB - The MBB in which to emit the compare and branch
181 MachineBasicBlock *CaseBB;
182 /// LT, GE - If nonzero, we know the current case value must be less-than or
183 /// greater-than-or-equal-to these Constants.
184 const ConstantInt *LT;
185 const ConstantInt *GE;
186 /// Range - A pair of iterators representing the range of case values to be
187 /// processed at this point in the binary search tree.
191 typedef std::vector<CaseRec> CaseRecVector;
193 /// The comparison function for sorting the switch case values in the vector.
194 /// WARNING: Case ranges should be disjoint!
196 bool operator()(const Case &C1, const Case &C2) {
197 return C1.Low->getValue().slt(C2.High->getValue());
202 bool operator()(const CaseBits &C1, const CaseBits &C2) {
203 return C1.Bits > C2.Bits;
207 void Clusterify(CaseVector &Cases, const SwitchInst &SI);
209 /// CaseBlock - This structure is used to communicate between
210 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
211 /// blocks needed by multi-case switch statements.
213 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
214 const Value *cmpmiddle,
215 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
216 MachineBasicBlock *me,
217 uint32_t trueweight = 0, uint32_t falseweight = 0)
218 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
219 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
220 TrueWeight(trueweight), FalseWeight(falseweight) { }
222 // CC - the condition code to use for the case block's setcc node
225 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
226 // Emit by default LHS op RHS. MHS is used for range comparisons:
227 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
228 const Value *CmpLHS, *CmpMHS, *CmpRHS;
230 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
231 MachineBasicBlock *TrueBB, *FalseBB;
233 // ThisBB - the block into which to emit the code for the setcc and branches
234 MachineBasicBlock *ThisBB;
236 // TrueWeight/FalseWeight - branch weights.
237 uint32_t TrueWeight, FalseWeight;
241 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
242 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
244 /// Reg - the virtual register containing the index of the jump table entry
247 /// JTI - the JumpTableIndex for this jump table in the function.
249 /// MBB - the MBB into which to emit the code for the indirect jump.
250 MachineBasicBlock *MBB;
251 /// Default - the MBB of the default bb, which is a successor of the range
252 /// check MBB. This is when updating PHI nodes in successors.
253 MachineBasicBlock *Default;
255 struct JumpTableHeader {
256 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
258 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
262 MachineBasicBlock *HeaderBB;
265 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
268 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
270 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
272 MachineBasicBlock *ThisBB;
273 MachineBasicBlock *TargetBB;
274 uint32_t ExtraWeight;
277 typedef SmallVector<BitTestCase, 3> BitTestInfo;
279 struct BitTestBlock {
280 BitTestBlock(APInt F, APInt R, const Value* SV,
281 unsigned Rg, MVT RgVT, bool E,
282 MachineBasicBlock* P, MachineBasicBlock* D,
284 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
285 Parent(P), Default(D), Cases(std::move(C)) { }
292 MachineBasicBlock *Parent;
293 MachineBasicBlock *Default;
297 /// A class which encapsulates all of the information needed to generate a
298 /// stack protector check and signals to isel via its state being initialized
299 /// that a stack protector needs to be generated.
301 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
302 /// Protector Generation. The reason that it is placed here is for a lack of
303 /// other good places to stick it.
305 /// High Level Overview of SelectionDAG Stack Protector Generation:
307 /// Previously, generation of stack protectors was done exclusively in the
308 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
309 /// splitting basic blocks at the IR level to create the success/failure basic
310 /// blocks in the tail of the basic block in question. As a result of this,
311 /// calls that would have qualified for the sibling call optimization were no
312 /// longer eligible for optimization since said calls were no longer right in
313 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
316 /// Then it was noticed that since the sibling call optimization causes the
317 /// callee to reuse the caller's stack, if we could delay the generation of
318 /// the stack protector check until later in CodeGen after the sibling call
319 /// decision was made, we get both the tail call optimization and the stack
322 /// A few goals in solving this problem were:
324 /// 1. Preserve the architecture independence of stack protector generation.
326 /// 2. Preserve the normal IR level stack protector check for platforms like
327 /// OpenBSD for which we support platform-specific stack protector
330 /// The main problem that guided the present solution is that one can not
331 /// solve this problem in an architecture independent manner at the IR level
332 /// only. This is because:
334 /// 1. The decision on whether or not to perform a sibling call on certain
335 /// platforms (for instance i386) requires lower level information
336 /// related to available registers that can not be known at the IR level.
338 /// 2. Even if the previous point were not true, the decision on whether to
339 /// perform a tail call is done in LowerCallTo in SelectionDAG which
340 /// occurs after the Stack Protector Pass. As a result, one would need to
341 /// put the relevant callinst into the stack protector check success
342 /// basic block (where the return inst is placed) and then move it back
343 /// later at SelectionDAG/MI time before the stack protector check if the
344 /// tail call optimization failed. The MI level option was nixed
345 /// immediately since it would require platform-specific pattern
346 /// matching. The SelectionDAG level option was nixed because
347 /// SelectionDAG only processes one IR level basic block at a time
348 /// implying one could not create a DAG Combine to move the callinst.
350 /// To get around this problem a few things were realized:
352 /// 1. While one can not handle multiple IR level basic blocks at the
353 /// SelectionDAG Level, one can generate multiple machine basic blocks
354 /// for one IR level basic block. This is how we handle bit tests and
357 /// 2. At the MI level, tail calls are represented via a special return
358 /// MIInst called "tcreturn". Thus if we know the basic block in which we
359 /// wish to insert the stack protector check, we get the correct behavior
360 /// by always inserting the stack protector check right before the return
361 /// statement. This is a "magical transformation" since no matter where
362 /// the stack protector check intrinsic is, we always insert the stack
363 /// protector check code at the end of the BB.
365 /// Given the aforementioned constraints, the following solution was devised:
367 /// 1. On platforms that do not support SelectionDAG stack protector check
368 /// generation, allow for the normal IR level stack protector check
369 /// generation to continue.
371 /// 2. On platforms that do support SelectionDAG stack protector check
374 /// a. Use the IR level stack protector pass to decide if a stack
375 /// protector is required/which BB we insert the stack protector check
376 /// in by reusing the logic already therein. If we wish to generate a
377 /// stack protector check in a basic block, we place a special IR
378 /// intrinsic called llvm.stackprotectorcheck right before the BB's
379 /// returninst or if there is a callinst that could potentially be
380 /// sibling call optimized, before the call inst.
382 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
383 /// normally via SelectBasicBlock. In said process, when we visit the
384 /// stack protector check, we do not actually emit anything into the
385 /// BB. Instead, we just initialize the stack protector descriptor
386 /// class (which involves stashing information/creating the success
387 /// mbbb and the failure mbb if we have not created one for this
388 /// function yet) and export the guard variable that we are going to
391 /// c. After we finish selecting the basic block, in FinishBasicBlock if
392 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
393 /// initialized, we first find a splice point in the parent basic block
394 /// before the terminator and then splice the terminator of said basic
395 /// block into the success basic block. Then we code-gen a new tail for
396 /// the parent basic block consisting of the two loads, the comparison,
397 /// and finally two branches to the success/failure basic blocks. We
398 /// conclude by code-gening the failure basic block if we have not
399 /// code-gened it already (all stack protector checks we generate in
400 /// the same function, use the same failure basic block).
401 class StackProtectorDescriptor {
403 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
404 FailureMBB(nullptr), Guard(nullptr),
406 ~StackProtectorDescriptor() { }
408 /// Returns true if all fields of the stack protector descriptor are
409 /// initialized implying that we should/are ready to emit a stack protector.
410 bool shouldEmitStackProtector() const {
411 return ParentMBB && SuccessMBB && FailureMBB && Guard;
414 /// Initialize the stack protector descriptor structure for a new basic
416 void initialize(const BasicBlock *BB,
417 MachineBasicBlock *MBB,
418 const CallInst &StackProtCheckCall) {
419 // Make sure we are not initialized yet.
420 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
421 "already initialized!");
423 SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
424 FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
426 Guard = StackProtCheckCall.getArgOperand(0);
429 /// Reset state that changes when we handle different basic blocks.
431 /// This currently includes:
433 /// 1. The specific basic block we are generating a
434 /// stack protector for (ParentMBB).
436 /// 2. The successor machine basic block that will contain the tail of
437 /// parent mbb after we create the stack protector check (SuccessMBB). This
438 /// BB is visited only on stack protector check success.
439 void resetPerBBState() {
441 SuccessMBB = nullptr;
444 /// Reset state that only changes when we switch functions.
446 /// This currently includes:
448 /// 1. FailureMBB since we reuse the failure code path for all stack
449 /// protector checks created in an individual function.
451 /// 2.The guard variable since the guard variable we are checking against is
453 void resetPerFunctionState() {
454 FailureMBB = nullptr;
458 MachineBasicBlock *getParentMBB() { return ParentMBB; }
459 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
460 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
461 const Value *getGuard() { return Guard; }
463 unsigned getGuardReg() const { return GuardReg; }
464 void setGuardReg(unsigned R) { GuardReg = R; }
467 /// The basic block for which we are generating the stack protector.
469 /// As a result of stack protector generation, we will splice the
470 /// terminators of this basic block into the successor mbb SuccessMBB and
471 /// replace it with a compare/branch to the successor mbbs
472 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
474 MachineBasicBlock *ParentMBB;
476 /// A basic block visited on stack protector check success that contains the
477 /// terminators of ParentMBB.
478 MachineBasicBlock *SuccessMBB;
480 /// This basic block visited on stack protector check failure that will
481 /// contain a call to __stack_chk_fail().
482 MachineBasicBlock *FailureMBB;
484 /// The guard variable which we will compare against the stored value in the
485 /// stack protector stack slot.
488 /// The virtual register holding the stack guard value.
491 /// Add a successor machine basic block to ParentMBB. If the successor mbb
492 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
493 /// block will be created. Assign a large weight if IsLikely is true.
494 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
495 MachineBasicBlock *ParentMBB,
497 MachineBasicBlock *SuccMBB = nullptr);
501 const TargetMachine &TM;
503 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
504 /// nodes without a corresponding SDNode.
505 static const unsigned LowestSDNodeOrder = 1;
508 const DataLayout *DL;
510 const TargetLibraryInfo *LibInfo;
512 /// SwitchCases - Vector of CaseBlock structures used to communicate
513 /// SwitchInst code generation information.
514 std::vector<CaseBlock> SwitchCases;
515 /// JTCases - Vector of JumpTable structures used to communicate
516 /// SwitchInst code generation information.
517 std::vector<JumpTableBlock> JTCases;
518 /// BitTestCases - Vector of BitTestBlock structures used to communicate
519 /// SwitchInst code generation information.
520 std::vector<BitTestBlock> BitTestCases;
521 /// A StackProtectorDescriptor structure used to communicate stack protector
522 /// information in between SelectBasicBlock and FinishBasicBlock.
523 StackProtectorDescriptor SPDescriptor;
525 // Emit PHI-node-operand constants only once even if used by multiple
527 DenseMap<const Constant *, unsigned> ConstantsOut;
529 /// FuncInfo - Information about the function as a whole.
531 FunctionLoweringInfo &FuncInfo;
533 /// OptLevel - What optimization level we're generating code for.
535 CodeGenOpt::Level OptLevel;
537 /// GFI - Garbage collection metadata for the function.
540 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
541 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
543 /// HasTailCall - This is set to true if a call in the current
544 /// block has been translated as a tail call. In this case,
545 /// no subsequent DAG nodes should be created.
549 LLVMContext *Context;
551 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
552 CodeGenOpt::Level ol)
553 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
554 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
558 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
559 const TargetLibraryInfo *li);
561 /// clear - Clear out the current SelectionDAG and the associated
562 /// state and prepare this SelectionDAGBuilder object to be used
563 /// for a new block. This doesn't clear out information about
564 /// additional blocks that are needed to complete switch lowering
565 /// or PHI node updating; that information is cleared out as it is
569 /// clearDanglingDebugInfo - Clear the dangling debug information
570 /// map. This function is separated from the clear so that debug
571 /// information that is dangling in a basic block can be properly
572 /// resolved in a different basic block. This allows the
573 /// SelectionDAG to resolve dangling debug information attached
575 void clearDanglingDebugInfo();
577 /// getRoot - Return the current virtual root of the Selection DAG,
578 /// flushing any PendingLoad items. This must be done before emitting
579 /// a store or any other node that may need to be ordered after any
580 /// prior load instructions.
584 /// getControlRoot - Similar to getRoot, but instead of flushing all the
585 /// PendingLoad items, flush all the PendingExports items. It is necessary
586 /// to do this before emitting a terminator instruction.
588 SDValue getControlRoot();
590 SDLoc getCurSDLoc() const {
591 return SDLoc(CurInst, SDNodeOrder);
594 DebugLoc getCurDebugLoc() const {
595 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
598 unsigned getSDNodeOrder() const { return SDNodeOrder; }
600 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
602 void visit(const Instruction &I);
604 void visit(unsigned Opcode, const User &I);
606 /// getCopyFromRegs - If there was virtual register allocated for the value V
607 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
608 SDValue getCopyFromRegs(const Value *V, Type *Ty);
610 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
611 // generate the debug data structures now that we've seen its definition.
612 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
613 SDValue getValue(const Value *V);
614 SDValue getNonRegisterValue(const Value *V);
615 SDValue getValueImpl(const Value *V);
617 void setValue(const Value *V, SDValue NewN) {
618 SDValue &N = NodeMap[V];
619 assert(!N.getNode() && "Already set a value for this node!");
623 void removeValue(const Value *V) {
624 // This is to support hack in lowerCallFromStatepoint
625 // Should be removed when hack is resolved
629 void setUnusedArgValue(const Value *V, SDValue NewN) {
630 SDValue &N = UnusedArgNodeMap[V];
631 assert(!N.getNode() && "Already set a value for this node!");
635 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
636 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
637 MachineBasicBlock *SwitchBB, unsigned Opc,
638 uint32_t TW, uint32_t FW);
639 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
640 MachineBasicBlock *FBB,
641 MachineBasicBlock *CurBB,
642 MachineBasicBlock *SwitchBB,
643 uint32_t TW, uint32_t FW);
644 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
645 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
646 void CopyToExportRegsIfNeeded(const Value *V);
647 void ExportFromCurrentBlock(const Value *V);
648 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
649 MachineBasicBlock *LandingPad = nullptr);
651 std::pair<SDValue, SDValue> lowerCallOperands(
652 ImmutableCallSite CS,
656 bool UseVoidTy = false,
657 MachineBasicBlock *LandingPad = nullptr,
658 bool IsPatchPoint = false);
660 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
661 /// references that need to refer to the last resulting block.
662 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
664 // This function is responsible for the whole statepoint lowering process.
665 // It uniformly handles invoke and call statepoints.
666 void LowerStatepoint(ImmutableStatepoint Statepoint,
667 MachineBasicBlock *LandingPad = nullptr);
669 std::pair<SDValue, SDValue> lowerInvokable(
670 TargetLowering::CallLoweringInfo &CLI,
671 MachineBasicBlock *LandingPad);
673 // Terminator instructions.
674 void visitRet(const ReturnInst &I);
675 void visitBr(const BranchInst &I);
676 void visitSwitch(const SwitchInst &I);
677 void visitIndirectBr(const IndirectBrInst &I);
678 void visitUnreachable(const UnreachableInst &I);
680 // Helpers for visitSwitch
681 bool handleSmallSwitchRange(CaseRec& CR,
682 CaseRecVector& WorkList,
684 MachineBasicBlock* Default,
685 MachineBasicBlock *SwitchBB);
686 bool handleJTSwitchCase(CaseRec& CR,
687 CaseRecVector& WorkList,
689 MachineBasicBlock* Default,
690 MachineBasicBlock *SwitchBB);
691 bool handleBTSplitSwitchCase(CaseRec& CR,
692 CaseRecVector& WorkList,
694 MachineBasicBlock *SwitchBB);
695 void splitSwitchCase(CaseRec &CR, CaseItr Pivot, CaseRecVector &WorkList,
696 const Value *SV, MachineBasicBlock *SwitchBB);
697 bool handleBitTestsSwitchCase(CaseRec& CR,
698 CaseRecVector& WorkList,
700 MachineBasicBlock* Default,
701 MachineBasicBlock *SwitchBB);
703 uint32_t getEdgeWeight(const MachineBasicBlock *Src,
704 const MachineBasicBlock *Dst) const;
705 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
706 uint32_t Weight = 0);
708 void visitSwitchCase(CaseBlock &CB,
709 MachineBasicBlock *SwitchBB);
710 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
711 MachineBasicBlock *ParentBB);
712 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
713 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
714 void visitBitTestCase(BitTestBlock &BB,
715 MachineBasicBlock* NextMBB,
716 uint32_t BranchWeightToNext,
719 MachineBasicBlock *SwitchBB);
720 void visitJumpTable(JumpTable &JT);
721 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
722 MachineBasicBlock *SwitchBB);
723 unsigned visitLandingPadClauseBB(GlobalValue *ClauseGV,
724 MachineBasicBlock *LPadMBB);
727 // These all get lowered before this pass.
728 void visitInvoke(const InvokeInst &I);
729 void visitResume(const ResumeInst &I);
731 void visitBinary(const User &I, unsigned OpCode);
732 void visitShift(const User &I, unsigned Opcode);
733 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
734 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
735 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
736 void visitFSub(const User &I);
737 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
738 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
739 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
740 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
741 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
742 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
743 void visitSDiv(const User &I);
744 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
745 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
746 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
747 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
748 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
749 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
750 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
751 void visitICmp(const User &I);
752 void visitFCmp(const User &I);
753 // Visit the conversion instructions
754 void visitTrunc(const User &I);
755 void visitZExt(const User &I);
756 void visitSExt(const User &I);
757 void visitFPTrunc(const User &I);
758 void visitFPExt(const User &I);
759 void visitFPToUI(const User &I);
760 void visitFPToSI(const User &I);
761 void visitUIToFP(const User &I);
762 void visitSIToFP(const User &I);
763 void visitPtrToInt(const User &I);
764 void visitIntToPtr(const User &I);
765 void visitBitCast(const User &I);
766 void visitAddrSpaceCast(const User &I);
768 void visitExtractElement(const User &I);
769 void visitInsertElement(const User &I);
770 void visitShuffleVector(const User &I);
772 void visitExtractValue(const ExtractValueInst &I);
773 void visitInsertValue(const InsertValueInst &I);
774 void visitLandingPad(const LandingPadInst &I);
776 void visitGetElementPtr(const User &I);
777 void visitSelect(const User &I);
779 void visitAlloca(const AllocaInst &I);
780 void visitLoad(const LoadInst &I);
781 void visitStore(const StoreInst &I);
782 void visitMaskedLoad(const CallInst &I);
783 void visitMaskedStore(const CallInst &I);
784 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
785 void visitAtomicRMW(const AtomicRMWInst &I);
786 void visitFence(const FenceInst &I);
787 void visitPHI(const PHINode &I);
788 void visitCall(const CallInst &I);
789 bool visitMemCmpCall(const CallInst &I);
790 bool visitMemChrCall(const CallInst &I);
791 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
792 bool visitStrCmpCall(const CallInst &I);
793 bool visitStrLenCall(const CallInst &I);
794 bool visitStrNLenCall(const CallInst &I);
795 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
796 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
797 void visitAtomicLoad(const LoadInst &I);
798 void visitAtomicStore(const StoreInst &I);
800 void visitInlineAsm(ImmutableCallSite CS);
801 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
802 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
804 void visitVAStart(const CallInst &I);
805 void visitVAArg(const VAArgInst &I);
806 void visitVAEnd(const CallInst &I);
807 void visitVACopy(const CallInst &I);
808 void visitStackmap(const CallInst &I);
809 void visitPatchpoint(ImmutableCallSite CS,
810 MachineBasicBlock *LandingPad = nullptr);
812 // These three are implemented in StatepointLowering.cpp
813 void visitStatepoint(const CallInst &I);
814 void visitGCRelocate(const CallInst &I);
815 void visitGCResult(const CallInst &I);
817 void visitUserOp1(const Instruction &I) {
818 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
820 void visitUserOp2(const Instruction &I) {
821 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
824 void processIntegerCallValue(const Instruction &I,
825 SDValue Value, bool IsSigned);
827 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
829 /// EmitFuncArgumentDbgValue - If V is an function argument then create
830 /// corresponding DBG_VALUE machine instruction for it now. At the end of
831 /// instruction selection, they will be inserted to the entry BB.
832 bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, MDNode *Expr,
833 int64_t Offset, bool IsIndirect,
837 } // end namespace llvm