1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(),
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
525 bool Smaller = ValueVT.bitsLE(PartVT);
526 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
551 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
553 DAG.getConstant(i * (NumElements / NumIntermediates),
554 TLI.getVectorIdxTy()));
556 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
558 DAG.getConstant(i, TLI.getVectorIdxTy()));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 /// RegsForValue - This struct represents the registers (physical or virtual)
581 /// that a particular set of values is assigned, and the type information
582 /// about the value. The most common situation is to represent one value at a
583 /// time, but struct or array values are handled element-wise as multiple
584 /// values. The splitting of aggregates is performed recursively, so that we
585 /// never have aggregate-typed registers. The values at this point do not
586 /// necessarily have legal types, so each value may require one or more
587 /// registers of some legal type.
589 struct RegsForValue {
590 /// ValueVTs - The value types of the values, which may not be legal, and
591 /// may need be promoted or synthesized from one or more registers.
593 SmallVector<EVT, 4> ValueVTs;
595 /// RegVTs - The value types of the registers. This is the same size as
596 /// ValueVTs and it records, for each value, what the type of the assigned
597 /// register or registers are. (Individual values are never synthesized
598 /// from more than one type of register.)
600 /// With virtual registers, the contents of RegVTs is redundant with TLI's
601 /// getRegisterType member function, however when with physical registers
602 /// it is necessary to have a separate record of the types.
604 SmallVector<MVT, 4> RegVTs;
606 /// Regs - This list holds the registers assigned to the values.
607 /// Each legal or promoted value requires one register, and each
608 /// expanded value requires multiple registers.
610 SmallVector<unsigned, 4> Regs;
614 RegsForValue(const SmallVector<unsigned, 4> ®s,
615 MVT regvt, EVT valuevt)
616 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
618 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
619 unsigned Reg, Type *Ty) {
620 ComputeValueVTs(tli, Ty, ValueVTs);
622 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 EVT ValueVT = ValueVTs[Value];
624 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
625 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
626 for (unsigned i = 0; i != NumRegs; ++i)
627 Regs.push_back(Reg + i);
628 RegVTs.push_back(RegisterVT);
633 /// append - Add the specified values to this one.
634 void append(const RegsForValue &RHS) {
635 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
636 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
637 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
640 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
641 /// this value and returns the result as a ValueVTs value. This uses
642 /// Chain/Flag as the input and updates them for the output Chain/Flag.
643 /// If the Flag pointer is NULL, no flag is used.
644 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
646 SDValue &Chain, SDValue *Flag,
647 const Value *V = nullptr) const;
649 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
650 /// specified value into the registers specified by this object. This uses
651 /// Chain/Flag as the input and updates them for the output Chain/Flag.
652 /// If the Flag pointer is NULL, no flag is used.
654 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
655 SDValue *Flag, const Value *V,
656 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 if (NumZeroBits == RegSize) {
721 // The current value is a zero.
722 // Explicitly express that as it would be easier for
723 // optimizations to kick in.
724 Parts[i] = DAG.getConstant(0, RegisterVT);
728 // FIXME: We capture more information than the dag can represent. For
729 // now, just use the tightest assertzext/assertsext possible.
731 EVT FromVT(MVT::Other);
732 if (NumSignBits == RegSize)
733 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
734 else if (NumZeroBits >= RegSize-1)
735 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
736 else if (NumSignBits > RegSize-8)
737 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
738 else if (NumZeroBits >= RegSize-8)
739 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
740 else if (NumSignBits > RegSize-16)
741 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
742 else if (NumZeroBits >= RegSize-16)
743 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
744 else if (NumSignBits > RegSize-32)
745 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
746 else if (NumZeroBits >= RegSize-32)
747 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
751 // Add an assertion node.
752 assert(FromVT != MVT::Other);
753 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
754 RegisterVT, P, DAG.getValueType(FromVT));
757 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
758 NumRegs, RegisterVT, ValueVT, V);
763 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
766 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
767 /// specified value into the registers specified by this object. This uses
768 /// Chain/Flag as the input and updates them for the output Chain/Flag.
769 /// If the Flag pointer is NULL, no flag is used.
770 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
771 SDValue &Chain, SDValue *Flag, const Value *V,
772 ISD::NodeType PreferredExtendType) const {
773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
774 ISD::NodeType ExtendKind = PreferredExtendType;
776 // Get the list of the values's legal parts.
777 unsigned NumRegs = Regs.size();
778 SmallVector<SDValue, 8> Parts(NumRegs);
779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
780 EVT ValueVT = ValueVTs[Value];
781 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
782 MVT RegisterVT = RegVTs[Value];
784 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
785 ExtendKind = ISD::ZERO_EXTEND;
787 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
788 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
792 // Copy the parts into the registers.
793 SmallVector<SDValue, 8> Chains(NumRegs);
794 for (unsigned i = 0; i != NumRegs; ++i) {
797 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
800 *Flag = Part.getValue(1);
803 Chains[i] = Part.getValue(0);
806 if (NumRegs == 1 || Flag)
807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
808 // flagged to it. That is the CopyToReg nodes and the user are considered
809 // a single scheduling unit. If we create a TokenFactor and return it as
810 // chain, then the TokenFactor is both a predecessor (operand) of the
811 // user as well as a successor (the TF operands are flagged to the user).
812 // c1, f1 = CopyToReg
813 // c2, f2 = CopyToReg
814 // c3 = TokenFactor c1, c2
817 Chain = Chains[NumRegs-1];
819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
822 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
823 /// operand list. This adds the code marker and includes the number of
824 /// values added into it.
825 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
826 unsigned MatchingIdx,
828 std::vector<SDValue> &Ops) const {
829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
831 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
833 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
834 else if (!Regs.empty() &&
835 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
836 // Put the register class of the virtual registers in the flag word. That
837 // way, later passes can recompute register class constraints for inline
838 // assembly as well as normal instructions.
839 // Don't do this for tied operands that can use the regclass information
841 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
842 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
843 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
846 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
849 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 unsigned TheReg = Regs[Reg++];
856 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
858 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
859 // If we clobbered the stack pointer, MFI should know about it.
860 assert(DAG.getMachineFunction().getFrameInfo()->
861 hasInlineAsmWithSPAdjust());
867 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
868 const TargetLibraryInfo *li) {
872 DL = DAG.getTarget().getDataLayout();
873 Context = DAG.getContext();
874 LPadToCallSiteMap.clear();
877 /// clear - Clear out the current SelectionDAG and the associated
878 /// state and prepare this SelectionDAGBuilder object to be used
879 /// for a new block. This doesn't clear out information about
880 /// additional blocks that are needed to complete switch lowering
881 /// or PHI node updating; that information is cleared out as it is
883 void SelectionDAGBuilder::clear() {
885 UnusedArgNodeMap.clear();
886 PendingLoads.clear();
887 PendingExports.clear();
890 SDNodeOrder = LowestSDNodeOrder;
891 StatepointLowering.clear();
894 /// clearDanglingDebugInfo - Clear the dangling debug information
895 /// map. This function is separated from the clear so that debug
896 /// information that is dangling in a basic block can be properly
897 /// resolved in a different basic block. This allows the
898 /// SelectionDAG to resolve dangling debug information attached
900 void SelectionDAGBuilder::clearDanglingDebugInfo() {
901 DanglingDebugInfoMap.clear();
904 /// getRoot - Return the current virtual root of the Selection DAG,
905 /// flushing any PendingLoad items. This must be done before emitting
906 /// a store or any other node that may need to be ordered after any
907 /// prior load instructions.
909 SDValue SelectionDAGBuilder::getRoot() {
910 if (PendingLoads.empty())
911 return DAG.getRoot();
913 if (PendingLoads.size() == 1) {
914 SDValue Root = PendingLoads[0];
916 PendingLoads.clear();
920 // Otherwise, we have to make a token factor node.
921 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
923 PendingLoads.clear();
928 /// getControlRoot - Similar to getRoot, but instead of flushing all the
929 /// PendingLoad items, flush all the PendingExports items. It is necessary
930 /// to do this before emitting a terminator instruction.
932 SDValue SelectionDAGBuilder::getControlRoot() {
933 SDValue Root = DAG.getRoot();
935 if (PendingExports.empty())
938 // Turn all of the CopyToReg chains into one factored node.
939 if (Root.getOpcode() != ISD::EntryToken) {
940 unsigned i = 0, e = PendingExports.size();
941 for (; i != e; ++i) {
942 assert(PendingExports[i].getNode()->getNumOperands() > 1);
943 if (PendingExports[i].getNode()->getOperand(0) == Root)
944 break; // Don't add the root if we already indirectly depend on it.
948 PendingExports.push_back(Root);
951 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
953 PendingExports.clear();
958 void SelectionDAGBuilder::visit(const Instruction &I) {
959 // Set up outgoing PHI node register values before emitting the terminator.
960 if (isa<TerminatorInst>(&I))
961 HandlePHINodesInSuccessorBlocks(I.getParent());
967 visit(I.getOpcode(), I);
969 if (!isa<TerminatorInst>(&I) && !HasTailCall)
970 CopyToExportRegsIfNeeded(&I);
975 void SelectionDAGBuilder::visitPHI(const PHINode &) {
976 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
979 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
980 // Note: this doesn't use InstVisitor, because it has to work with
981 // ConstantExpr's in addition to instructions.
983 default: llvm_unreachable("Unknown instruction type encountered!");
984 // Build the switch statement using the Instruction.def file.
985 #define HANDLE_INST(NUM, OPCODE, CLASS) \
986 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
987 #include "llvm/IR/Instruction.def"
991 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
992 // generate the debug data structures now that we've seen its definition.
993 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
995 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
997 const DbgValueInst *DI = DDI.getDI();
998 DebugLoc dl = DDI.getdl();
999 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1000 MDNode *Variable = DI->getVariable();
1001 MDNode *Expr = DI->getExpression();
1002 uint64_t Offset = DI->getOffset();
1003 // A dbg.value for an alloca is always indirect.
1004 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1006 if (Val.getNode()) {
1007 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1009 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1010 IsIndirect, Offset, dl, DbgSDNodeOrder);
1011 DAG.AddDbgValue(SDV, Val.getNode(), false);
1014 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1015 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1019 /// getCopyFromRegs - If there was virtual register allocated for the value V
1020 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1021 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1022 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1029 SDValue Chain = DAG.getEntryNode();
1030 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1031 resolveDanglingDebugInfo(V, res);
1037 /// getValue - Return an SDValue for the given Value.
1038 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1039 // If we already have an SDValue for this value, use it. It's important
1040 // to do this first, so that we don't create a CopyFromReg if we already
1041 // have a regular SDValue.
1042 SDValue &N = NodeMap[V];
1043 if (N.getNode()) return N;
1045 // If there's a virtual register allocated and initialized for this
1047 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1048 if (copyFromReg.getNode()) {
1052 // Otherwise create a new SDValue and remember it.
1053 SDValue Val = getValueImpl(V);
1055 resolveDanglingDebugInfo(V, Val);
1059 /// getNonRegisterValue - Return an SDValue for the given Value, but
1060 /// don't look in FuncInfo.ValueMap for a virtual register.
1061 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1062 // If we already have an SDValue for this value, use it.
1063 SDValue &N = NodeMap[V];
1064 if (N.getNode()) return N;
1066 // Otherwise create a new SDValue and remember it.
1067 SDValue Val = getValueImpl(V);
1069 resolveDanglingDebugInfo(V, Val);
1073 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1074 /// Create an SDValue for the given value.
1075 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1078 if (const Constant *C = dyn_cast<Constant>(V)) {
1079 EVT VT = TLI.getValueType(V->getType(), true);
1081 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1082 return DAG.getConstant(*CI, VT);
1084 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1085 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1087 if (isa<ConstantPointerNull>(C)) {
1088 unsigned AS = V->getType()->getPointerAddressSpace();
1089 return DAG.getConstant(0, TLI.getPointerTy(AS));
1092 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1093 return DAG.getConstantFP(*CFP, VT);
1095 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1096 return DAG.getUNDEF(VT);
1098 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1099 visit(CE->getOpcode(), *CE);
1100 SDValue N1 = NodeMap[V];
1101 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1105 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1106 SmallVector<SDValue, 4> Constants;
1107 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1109 SDNode *Val = getValue(*OI).getNode();
1110 // If the operand is an empty aggregate, there are no values.
1112 // Add each leaf value from the operand to the Constants list
1113 // to form a flattened list of all the values.
1114 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1115 Constants.push_back(SDValue(Val, i));
1118 return DAG.getMergeValues(Constants, getCurSDLoc());
1121 if (const ConstantDataSequential *CDS =
1122 dyn_cast<ConstantDataSequential>(C)) {
1123 SmallVector<SDValue, 4> Ops;
1124 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1125 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1126 // Add each leaf value from the operand to the Constants list
1127 // to form a flattened list of all the values.
1128 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1129 Ops.push_back(SDValue(Val, i));
1132 if (isa<ArrayType>(CDS->getType()))
1133 return DAG.getMergeValues(Ops, getCurSDLoc());
1134 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1138 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1139 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1140 "Unknown struct or array constant!");
1142 SmallVector<EVT, 4> ValueVTs;
1143 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1144 unsigned NumElts = ValueVTs.size();
1146 return SDValue(); // empty struct
1147 SmallVector<SDValue, 4> Constants(NumElts);
1148 for (unsigned i = 0; i != NumElts; ++i) {
1149 EVT EltVT = ValueVTs[i];
1150 if (isa<UndefValue>(C))
1151 Constants[i] = DAG.getUNDEF(EltVT);
1152 else if (EltVT.isFloatingPoint())
1153 Constants[i] = DAG.getConstantFP(0, EltVT);
1155 Constants[i] = DAG.getConstant(0, EltVT);
1158 return DAG.getMergeValues(Constants, getCurSDLoc());
1161 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1162 return DAG.getBlockAddress(BA, VT);
1164 VectorType *VecTy = cast<VectorType>(V->getType());
1165 unsigned NumElements = VecTy->getNumElements();
1167 // Now that we know the number and type of the elements, get that number of
1168 // elements into the Ops array based on what kind of constant it is.
1169 SmallVector<SDValue, 16> Ops;
1170 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1171 for (unsigned i = 0; i != NumElements; ++i)
1172 Ops.push_back(getValue(CV->getOperand(i)));
1174 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1175 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1178 if (EltVT.isFloatingPoint())
1179 Op = DAG.getConstantFP(0, EltVT);
1181 Op = DAG.getConstant(0, EltVT);
1182 Ops.assign(NumElements, Op);
1185 // Create a BUILD_VECTOR node.
1186 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1189 // If this is a static alloca, generate it as the frameindex instead of
1191 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1192 DenseMap<const AllocaInst*, int>::iterator SI =
1193 FuncInfo.StaticAllocaMap.find(AI);
1194 if (SI != FuncInfo.StaticAllocaMap.end())
1195 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1198 // If this is an instruction which fast-isel has deferred, select it now.
1199 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1200 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1201 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1202 SDValue Chain = DAG.getEntryNode();
1203 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1206 llvm_unreachable("Can't get register for value!");
1209 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1211 SDValue Chain = getControlRoot();
1212 SmallVector<ISD::OutputArg, 8> Outs;
1213 SmallVector<SDValue, 8> OutVals;
1215 if (!FuncInfo.CanLowerReturn) {
1216 unsigned DemoteReg = FuncInfo.DemoteRegister;
1217 const Function *F = I.getParent()->getParent();
1219 // Emit a store of the return value through the virtual register.
1220 // Leave Outs empty so that LowerReturn won't try to load return
1221 // registers the usual way.
1222 SmallVector<EVT, 1> PtrValueVTs;
1223 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1226 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1227 SDValue RetOp = getValue(I.getOperand(0));
1229 SmallVector<EVT, 4> ValueVTs;
1230 SmallVector<uint64_t, 4> Offsets;
1231 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1232 unsigned NumValues = ValueVTs.size();
1234 SmallVector<SDValue, 4> Chains(NumValues);
1235 for (unsigned i = 0; i != NumValues; ++i) {
1236 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1237 RetPtr.getValueType(), RetPtr,
1238 DAG.getIntPtrConstant(Offsets[i]));
1240 DAG.getStore(Chain, getCurSDLoc(),
1241 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1242 // FIXME: better loc info would be nice.
1243 Add, MachinePointerInfo(), false, false, 0);
1246 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1247 MVT::Other, Chains);
1248 } else if (I.getNumOperands() != 0) {
1249 SmallVector<EVT, 4> ValueVTs;
1250 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1251 unsigned NumValues = ValueVTs.size();
1253 SDValue RetOp = getValue(I.getOperand(0));
1255 const Function *F = I.getParent()->getParent();
1257 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 ExtendKind = ISD::SIGN_EXTEND;
1261 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 ExtendKind = ISD::ZERO_EXTEND;
1265 LLVMContext &Context = F->getContext();
1266 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1269 for (unsigned j = 0; j != NumValues; ++j) {
1270 EVT VT = ValueVTs[j];
1272 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1273 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1275 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1276 MVT PartVT = TLI.getRegisterType(Context, VT);
1277 SmallVector<SDValue, 4> Parts(NumParts);
1278 getCopyToParts(DAG, getCurSDLoc(),
1279 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1280 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1282 // 'inreg' on function refers to return value
1283 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1287 // Propagate extension type if any
1288 if (ExtendKind == ISD::SIGN_EXTEND)
1290 else if (ExtendKind == ISD::ZERO_EXTEND)
1293 for (unsigned i = 0; i < NumParts; ++i) {
1294 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1295 VT, /*isfixed=*/true, 0, 0));
1296 OutVals.push_back(Parts[i]);
1302 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1303 CallingConv::ID CallConv =
1304 DAG.getMachineFunction().getFunction()->getCallingConv();
1305 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1306 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1308 // Verify that the target's LowerReturn behaved as expected.
1309 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1310 "LowerReturn didn't return a valid chain!");
1312 // Update the DAG with the new chain value resulting from return lowering.
1316 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1317 /// created for it, emit nodes to copy the value into the virtual
1319 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1321 if (V->getType()->isEmptyTy())
1324 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1325 if (VMI != FuncInfo.ValueMap.end()) {
1326 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1327 CopyValueToVirtualRegister(V, VMI->second);
1331 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1332 /// the current basic block, add it to ValueMap now so that we'll get a
1334 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1335 // No need to export constants.
1336 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1338 // Already exported?
1339 if (FuncInfo.isExportedInst(V)) return;
1341 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1342 CopyValueToVirtualRegister(V, Reg);
1345 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1346 const BasicBlock *FromBB) {
1347 // The operands of the setcc have to be in this block. We don't know
1348 // how to export them from some other block.
1349 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1350 // Can export from current BB.
1351 if (VI->getParent() == FromBB)
1354 // Is already exported, noop.
1355 return FuncInfo.isExportedInst(V);
1358 // If this is an argument, we can export it if the BB is the entry block or
1359 // if it is already exported.
1360 if (isa<Argument>(V)) {
1361 if (FromBB == &FromBB->getParent()->getEntryBlock())
1364 // Otherwise, can only export this if it is already exported.
1365 return FuncInfo.isExportedInst(V);
1368 // Otherwise, constants can always be exported.
1372 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1373 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1374 const MachineBasicBlock *Dst) const {
1375 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1378 const BasicBlock *SrcBB = Src->getBasicBlock();
1379 const BasicBlock *DstBB = Dst->getBasicBlock();
1380 return BPI->getEdgeWeight(SrcBB, DstBB);
1383 void SelectionDAGBuilder::
1384 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1385 uint32_t Weight /* = 0 */) {
1387 Weight = getEdgeWeight(Src, Dst);
1388 Src->addSuccessor(Dst, Weight);
1392 static bool InBlock(const Value *V, const BasicBlock *BB) {
1393 if (const Instruction *I = dyn_cast<Instruction>(V))
1394 return I->getParent() == BB;
1398 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1399 /// This function emits a branch and is used at the leaves of an OR or an
1400 /// AND operator tree.
1403 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1404 MachineBasicBlock *TBB,
1405 MachineBasicBlock *FBB,
1406 MachineBasicBlock *CurBB,
1407 MachineBasicBlock *SwitchBB,
1410 const BasicBlock *BB = CurBB->getBasicBlock();
1412 // If the leaf of the tree is a comparison, merge the condition into
1414 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1415 // The operands of the cmp have to be in this block. We don't know
1416 // how to export them from some other block. If this is the first block
1417 // of the sequence, no exporting is needed.
1418 if (CurBB == SwitchBB ||
1419 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1420 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1421 ISD::CondCode Condition;
1422 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1423 Condition = getICmpCondCode(IC->getPredicate());
1424 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1425 Condition = getFCmpCondCode(FC->getPredicate());
1426 if (TM.Options.NoNaNsFPMath)
1427 Condition = getFCmpCodeWithoutNaN(Condition);
1429 (void)Condition; // silence warning.
1430 llvm_unreachable("Unknown compare instruction");
1433 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1434 TBB, FBB, CurBB, TWeight, FWeight);
1435 SwitchCases.push_back(CB);
1440 // Create a CaseBlock record representing this branch.
1441 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1442 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1443 SwitchCases.push_back(CB);
1446 /// Scale down both weights to fit into uint32_t.
1447 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1448 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1449 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1450 NewTrue = NewTrue / Scale;
1451 NewFalse = NewFalse / Scale;
1454 /// FindMergedConditions - If Cond is an expression like
1455 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1456 MachineBasicBlock *TBB,
1457 MachineBasicBlock *FBB,
1458 MachineBasicBlock *CurBB,
1459 MachineBasicBlock *SwitchBB,
1460 unsigned Opc, uint32_t TWeight,
1462 // If this node is not part of the or/and tree, emit it as a branch.
1463 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1464 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1465 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1466 BOp->getParent() != CurBB->getBasicBlock() ||
1467 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1468 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1469 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1474 // Create TmpBB after CurBB.
1475 MachineFunction::iterator BBI = CurBB;
1476 MachineFunction &MF = DAG.getMachineFunction();
1477 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1478 CurBB->getParent()->insert(++BBI, TmpBB);
1480 if (Opc == Instruction::Or) {
1481 // Codegen X | Y as:
1490 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1491 // The requirement is that
1492 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1493 // = TrueProb for orignal BB.
1494 // Assuming the orignal weights are A and B, one choice is to set BB1's
1495 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1497 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1498 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1499 // TmpBB, but the math is more complicated.
1501 uint64_t NewTrueWeight = TWeight;
1502 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1503 ScaleWeights(NewTrueWeight, NewFalseWeight);
1504 // Emit the LHS condition.
1505 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1506 NewTrueWeight, NewFalseWeight);
1508 NewTrueWeight = TWeight;
1509 NewFalseWeight = 2 * (uint64_t)FWeight;
1510 ScaleWeights(NewTrueWeight, NewFalseWeight);
1511 // Emit the RHS condition into TmpBB.
1512 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1513 NewTrueWeight, NewFalseWeight);
1515 assert(Opc == Instruction::And && "Unknown merge op!");
1516 // Codegen X & Y as:
1524 // This requires creation of TmpBB after CurBB.
1526 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1527 // The requirement is that
1528 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1529 // = FalseProb for orignal BB.
1530 // Assuming the orignal weights are A and B, one choice is to set BB1's
1531 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1533 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1535 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1536 uint64_t NewFalseWeight = FWeight;
1537 ScaleWeights(NewTrueWeight, NewFalseWeight);
1538 // Emit the LHS condition.
1539 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1540 NewTrueWeight, NewFalseWeight);
1542 NewTrueWeight = 2 * (uint64_t)TWeight;
1543 NewFalseWeight = FWeight;
1544 ScaleWeights(NewTrueWeight, NewFalseWeight);
1545 // Emit the RHS condition into TmpBB.
1546 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1547 NewTrueWeight, NewFalseWeight);
1551 /// If the set of cases should be emitted as a series of branches, return true.
1552 /// If we should emit this as a bunch of and/or'd together conditions, return
1555 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1556 if (Cases.size() != 2) return true;
1558 // If this is two comparisons of the same values or'd or and'd together, they
1559 // will get folded into a single comparison, so don't emit two blocks.
1560 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1561 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1562 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1563 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1567 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1568 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1569 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1570 Cases[0].CC == Cases[1].CC &&
1571 isa<Constant>(Cases[0].CmpRHS) &&
1572 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1573 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1575 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1582 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1583 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1585 // Update machine-CFG edges.
1586 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1588 if (I.isUnconditional()) {
1589 // Update machine-CFG edges.
1590 BrMBB->addSuccessor(Succ0MBB);
1592 // If this is not a fall-through branch or optimizations are switched off,
1594 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1595 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1596 MVT::Other, getControlRoot(),
1597 DAG.getBasicBlock(Succ0MBB)));
1602 // If this condition is one of the special cases we handle, do special stuff
1604 const Value *CondVal = I.getCondition();
1605 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1607 // If this is a series of conditions that are or'd or and'd together, emit
1608 // this as a sequence of branches instead of setcc's with and/or operations.
1609 // As long as jumps are not expensive, this should improve performance.
1610 // For example, instead of something like:
1623 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1624 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1625 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1626 BOp->getOpcode() == Instruction::Or)) {
1627 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1628 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1629 getEdgeWeight(BrMBB, Succ1MBB));
1630 // If the compares in later blocks need to use values not currently
1631 // exported from this block, export them now. This block should always
1632 // be the first entry.
1633 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1635 // Allow some cases to be rejected.
1636 if (ShouldEmitAsBranches(SwitchCases)) {
1637 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1638 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1639 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1642 // Emit the branch for this block.
1643 visitSwitchCase(SwitchCases[0], BrMBB);
1644 SwitchCases.erase(SwitchCases.begin());
1648 // Okay, we decided not to do this, remove any inserted MBB's and clear
1650 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1651 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1653 SwitchCases.clear();
1657 // Create a CaseBlock record representing this branch.
1658 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1659 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1661 // Use visitSwitchCase to actually insert the fast branch sequence for this
1663 visitSwitchCase(CB, BrMBB);
1666 /// visitSwitchCase - Emits the necessary code to represent a single node in
1667 /// the binary search tree resulting from lowering a switch instruction.
1668 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1669 MachineBasicBlock *SwitchBB) {
1671 SDValue CondLHS = getValue(CB.CmpLHS);
1672 SDLoc dl = getCurSDLoc();
1674 // Build the setcc now.
1676 // Fold "(X == true)" to X and "(X == false)" to !X to
1677 // handle common cases produced by branch lowering.
1678 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1679 CB.CC == ISD::SETEQ)
1681 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1682 CB.CC == ISD::SETEQ) {
1683 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1684 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1686 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1688 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1690 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1691 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1693 SDValue CmpOp = getValue(CB.CmpMHS);
1694 EVT VT = CmpOp.getValueType();
1696 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1697 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1700 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1701 VT, CmpOp, DAG.getConstant(Low, VT));
1702 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1703 DAG.getConstant(High-Low, VT), ISD::SETULE);
1707 // Update successor info
1708 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1709 // TrueBB and FalseBB are always different unless the incoming IR is
1710 // degenerate. This only happens when running llc on weird IR.
1711 if (CB.TrueBB != CB.FalseBB)
1712 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1714 // If the lhs block is the next block, invert the condition so that we can
1715 // fall through to the lhs instead of the rhs block.
1716 if (CB.TrueBB == NextBlock(SwitchBB)) {
1717 std::swap(CB.TrueBB, CB.FalseBB);
1718 SDValue True = DAG.getConstant(1, Cond.getValueType());
1719 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1722 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1723 MVT::Other, getControlRoot(), Cond,
1724 DAG.getBasicBlock(CB.TrueBB));
1726 // Insert the false branch. Do this even if it's a fall through branch,
1727 // this makes it easier to do DAG optimizations which require inverting
1728 // the branch condition.
1729 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1730 DAG.getBasicBlock(CB.FalseBB));
1732 DAG.setRoot(BrCond);
1735 /// visitJumpTable - Emit JumpTable node in the current MBB
1736 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1737 // Emit the code for the jump table
1738 assert(JT.Reg != -1U && "Should lower JT Header first!");
1739 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1740 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1742 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1743 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1744 MVT::Other, Index.getValue(1),
1746 DAG.setRoot(BrJumpTable);
1749 /// visitJumpTableHeader - This function emits necessary code to produce index
1750 /// in the JumpTable from switch case.
1751 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1752 JumpTableHeader &JTH,
1753 MachineBasicBlock *SwitchBB) {
1754 // Subtract the lowest switch case value from the value being switched on and
1755 // conditional branch to default mbb if the result is greater than the
1756 // difference between smallest and largest cases.
1757 SDValue SwitchOp = getValue(JTH.SValue);
1758 EVT VT = SwitchOp.getValueType();
1759 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1760 DAG.getConstant(JTH.First, VT));
1762 // The SDNode we just created, which holds the value being switched on minus
1763 // the smallest case value, needs to be copied to a virtual register so it
1764 // can be used as an index into the jump table in a subsequent basic block.
1765 // This value may be smaller or larger than the target's pointer type, and
1766 // therefore require extension or truncating.
1767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1768 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1770 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1771 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1772 JumpTableReg, SwitchOp);
1773 JT.Reg = JumpTableReg;
1775 // Emit the range check for the jump table, and branch to the default block
1776 // for the switch statement if the value being switched on exceeds the largest
1777 // case in the switch.
1779 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1780 Sub.getValueType()),
1781 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1783 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1784 MVT::Other, CopyTo, CMP,
1785 DAG.getBasicBlock(JT.Default));
1787 // Avoid emitting unnecessary branches to the next block.
1788 if (JT.MBB != NextBlock(SwitchBB))
1789 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1790 DAG.getBasicBlock(JT.MBB));
1792 DAG.setRoot(BrCond);
1795 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1796 /// tail spliced into a stack protector check success bb.
1798 /// For a high level explanation of how this fits into the stack protector
1799 /// generation see the comment on the declaration of class
1800 /// StackProtectorDescriptor.
1801 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1802 MachineBasicBlock *ParentBB) {
1804 // First create the loads to the guard/stack slot for the comparison.
1805 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1806 EVT PtrTy = TLI.getPointerTy();
1808 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1809 int FI = MFI->getStackProtectorIndex();
1811 const Value *IRGuard = SPD.getGuard();
1812 SDValue GuardPtr = getValue(IRGuard);
1813 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1816 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1820 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1821 // guard value from the virtual register holding the value. Otherwise, emit a
1822 // volatile load to retrieve the stack guard value.
1823 unsigned GuardReg = SPD.getGuardReg();
1825 if (GuardReg && TLI.useLoadStackGuardNode())
1826 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1829 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1830 GuardPtr, MachinePointerInfo(IRGuard, 0),
1831 true, false, false, Align);
1833 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1835 MachinePointerInfo::getFixedStack(FI),
1836 true, false, false, Align);
1838 // Perform the comparison via a subtract/getsetcc.
1839 EVT VT = Guard.getValueType();
1840 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1843 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1844 Sub.getValueType()),
1845 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1847 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1848 // branch to failure MBB.
1849 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1850 MVT::Other, StackSlot.getOperand(0),
1851 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1852 // Otherwise branch to success MBB.
1853 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1855 DAG.getBasicBlock(SPD.getSuccessMBB()));
1860 /// Codegen the failure basic block for a stack protector check.
1862 /// A failure stack protector machine basic block consists simply of a call to
1863 /// __stack_chk_fail().
1865 /// For a high level explanation of how this fits into the stack protector
1866 /// generation see the comment on the declaration of class
1867 /// StackProtectorDescriptor.
1869 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1872 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1873 nullptr, 0, false, getCurSDLoc(), false, false).second;
1877 /// visitBitTestHeader - This function emits necessary code to produce value
1878 /// suitable for "bit tests"
1879 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1880 MachineBasicBlock *SwitchBB) {
1881 // Subtract the minimum value
1882 SDValue SwitchOp = getValue(B.SValue);
1883 EVT VT = SwitchOp.getValueType();
1884 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1885 DAG.getConstant(B.First, VT));
1888 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1890 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1891 Sub.getValueType()),
1892 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1894 // Determine the type of the test operands.
1895 bool UsePtrType = false;
1896 if (!TLI.isTypeLegal(VT))
1899 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1900 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1901 // Switch table case range are encoded into series of masks.
1902 // Just use pointer type, it's guaranteed to fit.
1908 VT = TLI.getPointerTy();
1909 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1912 B.RegVT = VT.getSimpleVT();
1913 B.Reg = FuncInfo.CreateReg(B.RegVT);
1914 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1917 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1919 addSuccessorWithWeight(SwitchBB, B.Default);
1920 addSuccessorWithWeight(SwitchBB, MBB);
1922 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1923 MVT::Other, CopyTo, RangeCmp,
1924 DAG.getBasicBlock(B.Default));
1926 // Avoid emitting unnecessary branches to the next block.
1927 if (MBB != NextBlock(SwitchBB))
1928 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1929 DAG.getBasicBlock(MBB));
1931 DAG.setRoot(BrRange);
1934 /// visitBitTestCase - this function produces one "bit test"
1935 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1936 MachineBasicBlock* NextMBB,
1937 uint32_t BranchWeightToNext,
1940 MachineBasicBlock *SwitchBB) {
1942 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1945 unsigned PopCount = countPopulation(B.Mask);
1946 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1947 if (PopCount == 1) {
1948 // Testing for a single bit; just compare the shift count with what it
1949 // would need to be to shift a 1 bit in that position.
1951 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1952 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1953 } else if (PopCount == BB.Range) {
1954 // There is only one zero bit in the range, test for it directly.
1956 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1957 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1959 // Make desired shift
1960 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1961 DAG.getConstant(1, VT), ShiftOp);
1963 // Emit bit tests and jumps
1964 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1965 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1966 Cmp = DAG.getSetCC(getCurSDLoc(),
1967 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1968 DAG.getConstant(0, VT), ISD::SETNE);
1971 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1972 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1973 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1974 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1976 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1977 MVT::Other, getControlRoot(),
1978 Cmp, DAG.getBasicBlock(B.TargetBB));
1980 // Avoid emitting unnecessary branches to the next block.
1981 if (NextMBB != NextBlock(SwitchBB))
1982 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1983 DAG.getBasicBlock(NextMBB));
1988 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1989 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1991 // Retrieve successors.
1992 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1993 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1995 const Value *Callee(I.getCalledValue());
1996 const Function *Fn = dyn_cast<Function>(Callee);
1997 if (isa<InlineAsm>(Callee))
1999 else if (Fn && Fn->isIntrinsic()) {
2000 switch (Fn->getIntrinsicID()) {
2002 llvm_unreachable("Cannot invoke this intrinsic");
2003 case Intrinsic::donothing:
2004 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2006 case Intrinsic::experimental_patchpoint_void:
2007 case Intrinsic::experimental_patchpoint_i64:
2008 visitPatchpoint(&I, LandingPad);
2010 case Intrinsic::experimental_gc_statepoint:
2011 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2015 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2017 // If the value of the invoke is used outside of its defining block, make it
2018 // available as a virtual register.
2019 // We already took care of the exported value for the statepoint instruction
2020 // during call to the LowerStatepoint.
2021 if (!isStatepoint(I)) {
2022 CopyToExportRegsIfNeeded(&I);
2025 // Update successor info
2026 addSuccessorWithWeight(InvokeMBB, Return);
2027 addSuccessorWithWeight(InvokeMBB, LandingPad);
2029 // Drop into normal successor.
2030 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2031 MVT::Other, getControlRoot(),
2032 DAG.getBasicBlock(Return)));
2035 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2036 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2039 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2040 assert(FuncInfo.MBB->isLandingPad() &&
2041 "Call to landingpad not in landing pad!");
2043 MachineBasicBlock *MBB = FuncInfo.MBB;
2044 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2045 AddLandingPadInfo(LP, MMI, MBB);
2047 // If there aren't registers to copy the values into (e.g., during SjLj
2048 // exceptions), then don't bother to create these DAG nodes.
2049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2050 if (TLI.getExceptionPointerRegister() == 0 &&
2051 TLI.getExceptionSelectorRegister() == 0)
2054 SmallVector<EVT, 2> ValueVTs;
2055 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2056 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2058 // Get the two live-in registers as SDValues. The physregs have already been
2059 // copied into virtual registers.
2061 if (FuncInfo.ExceptionPointerVirtReg) {
2062 Ops[0] = DAG.getZExtOrTrunc(
2063 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2064 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2065 getCurSDLoc(), ValueVTs[0]);
2067 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2069 Ops[1] = DAG.getZExtOrTrunc(
2070 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2071 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2072 getCurSDLoc(), ValueVTs[1]);
2075 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2076 DAG.getVTList(ValueVTs), Ops);
2081 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2082 MachineBasicBlock *LPadBB) {
2083 SDValue Chain = getControlRoot();
2085 // Get the typeid that we will dispatch on later.
2086 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2087 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2088 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2089 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2090 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2091 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2093 // Branch to the main landing pad block.
2094 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2095 ClauseMBB->addSuccessor(LPadBB);
2096 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2097 DAG.getBasicBlock(LPadBB)));
2101 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2102 /// small case ranges).
2103 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2104 CaseRecVector& WorkList,
2106 MachineBasicBlock *Default,
2107 MachineBasicBlock *SwitchBB) {
2108 // Size is the number of Cases represented by this range.
2109 size_t Size = CR.Range.second - CR.Range.first;
2113 // Get the MachineFunction which holds the current MBB. This is used when
2114 // inserting any additional MBBs necessary to represent the switch.
2115 MachineFunction *CurMF = FuncInfo.MF;
2117 // Figure out which block is immediately after the current one.
2118 MachineBasicBlock *NextMBB = nullptr;
2119 MachineFunction::iterator BBI = CR.CaseBB;
2120 if (++BBI != FuncInfo.MF->end())
2123 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2124 // If any two of the cases has the same destination, and if one value
2125 // is the same as the other, but has one bit unset that the other has set,
2126 // use bit manipulation to do two compares at once. For example:
2127 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2128 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2129 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2130 if (Size == 2 && CR.CaseBB == SwitchBB) {
2131 Case &Small = *CR.Range.first;
2132 Case &Big = *(CR.Range.second-1);
2134 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2135 const APInt& SmallValue = Small.Low->getValue();
2136 const APInt& BigValue = Big.Low->getValue();
2138 // Check that there is only one bit different.
2139 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2140 (SmallValue | BigValue) == BigValue) {
2141 // Isolate the common bit.
2142 APInt CommonBit = BigValue & ~SmallValue;
2143 assert((SmallValue | CommonBit) == BigValue &&
2144 CommonBit.countPopulation() == 1 && "Not a common bit?");
2146 SDValue CondLHS = getValue(SV);
2147 EVT VT = CondLHS.getValueType();
2148 SDLoc DL = getCurSDLoc();
2150 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2151 DAG.getConstant(CommonBit, VT));
2152 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2153 Or, DAG.getConstant(BigValue, VT),
2156 // Update successor info.
2157 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2158 addSuccessorWithWeight(SwitchBB, Small.BB,
2159 Small.ExtraWeight + Big.ExtraWeight);
2160 addSuccessorWithWeight(SwitchBB, Default,
2161 // The default destination is the first successor in IR.
2162 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2164 // Insert the true branch.
2165 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2166 getControlRoot(), Cond,
2167 DAG.getBasicBlock(Small.BB));
2169 // Insert the false branch.
2170 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2171 DAG.getBasicBlock(Default));
2173 DAG.setRoot(BrCond);
2179 // Order cases by weight so the most likely case will be checked first.
2180 uint32_t UnhandledWeights = 0;
2182 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2183 uint32_t IWeight = I->ExtraWeight;
2184 UnhandledWeights += IWeight;
2185 for (CaseItr J = CR.Range.first; J < I; ++J) {
2186 uint32_t JWeight = J->ExtraWeight;
2187 if (IWeight > JWeight)
2192 // Rearrange the case blocks so that the last one falls through if possible.
2193 Case &BackCase = *(CR.Range.second-1);
2194 if (Size > 1 && NextMBB && Default != NextMBB && BackCase.BB != NextMBB) {
2195 // The last case block won't fall through into 'NextMBB' if we emit the
2196 // branches in this order. See if rearranging a case value would help.
2197 // We start at the bottom as it's the case with the least weight.
2198 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2199 if (I->BB == NextMBB) {
2200 std::swap(*I, BackCase);
2205 // Create a CaseBlock record representing a conditional branch to
2206 // the Case's target mbb if the value being switched on SV is equal
2208 MachineBasicBlock *CurBlock = CR.CaseBB;
2209 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2210 MachineBasicBlock *FallThrough;
2212 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2213 CurMF->insert(BBI, FallThrough);
2215 // Put SV in a virtual register to make it available from the new blocks.
2216 ExportFromCurrentBlock(SV);
2218 // If the last case doesn't match, go to the default block.
2219 FallThrough = Default;
2222 const Value *RHS, *LHS, *MHS;
2224 if (I->High == I->Low) {
2225 // This is just small small case range :) containing exactly 1 case
2227 LHS = SV; RHS = I->High; MHS = nullptr;
2230 LHS = I->Low; MHS = SV; RHS = I->High;
2233 // The false weight should be sum of all un-handled cases.
2234 UnhandledWeights -= I->ExtraWeight;
2235 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2237 /* trueweight */ I->ExtraWeight,
2238 /* falseweight */ UnhandledWeights);
2240 // If emitting the first comparison, just call visitSwitchCase to emit the
2241 // code into the current block. Otherwise, push the CaseBlock onto the
2242 // vector to be later processed by SDISel, and insert the node's MBB
2243 // before the next MBB.
2244 if (CurBlock == SwitchBB)
2245 visitSwitchCase(CB, SwitchBB);
2247 SwitchCases.push_back(CB);
2249 CurBlock = FallThrough;
2255 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2256 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2257 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2260 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2261 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2262 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2263 return (LastExt - FirstExt + 1ULL);
2266 /// handleJTSwitchCase - Emit jumptable for current switch case range
2267 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2268 CaseRecVector &WorkList,
2270 MachineBasicBlock *Default,
2271 MachineBasicBlock *SwitchBB) {
2272 Case& FrontCase = *CR.Range.first;
2273 Case& BackCase = *(CR.Range.second-1);
2275 const APInt &First = FrontCase.Low->getValue();
2276 const APInt &Last = BackCase.High->getValue();
2278 APInt TSize(First.getBitWidth(), 0);
2279 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2283 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2286 APInt Range = ComputeRange(First, Last);
2287 // The density is TSize / Range. Require at least 40%.
2288 // It should not be possible for IntTSize to saturate for sane code, but make
2289 // sure we handle Range saturation correctly.
2290 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2291 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2292 if (IntTSize * 10 < IntRange * 4)
2295 DEBUG(dbgs() << "Lowering jump table\n"
2296 << "First entry: " << First << ". Last entry: " << Last << '\n'
2297 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2299 // Get the MachineFunction which holds the current MBB. This is used when
2300 // inserting any additional MBBs necessary to represent the switch.
2301 MachineFunction *CurMF = FuncInfo.MF;
2303 // Figure out which block is immediately after the current one.
2304 MachineFunction::iterator BBI = CR.CaseBB;
2307 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2309 // Create a new basic block to hold the code for loading the address
2310 // of the jump table, and jumping to it. Update successor information;
2311 // we will either branch to the default case for the switch, or the jump
2313 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2314 CurMF->insert(BBI, JumpTableBB);
2316 addSuccessorWithWeight(CR.CaseBB, Default);
2317 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2319 // Build a vector of destination BBs, corresponding to each target
2320 // of the jump table. If the value of the jump table slot corresponds to
2321 // a case statement, push the case's BB onto the vector, otherwise, push
2323 std::vector<MachineBasicBlock*> DestBBs;
2325 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2326 const APInt &Low = I->Low->getValue();
2327 const APInt &High = I->High->getValue();
2329 if (Low.sle(TEI) && TEI.sle(High)) {
2330 DestBBs.push_back(I->BB);
2334 DestBBs.push_back(Default);
2338 // Calculate weight for each unique destination in CR.
2339 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2341 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2342 DestWeights[I->BB] += I->ExtraWeight;
2345 // Update successor info. Add one edge to each unique successor.
2346 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2347 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2348 E = DestBBs.end(); I != E; ++I) {
2349 if (!SuccsHandled[(*I)->getNumber()]) {
2350 SuccsHandled[(*I)->getNumber()] = true;
2351 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2352 DestWeights.find(*I);
2353 addSuccessorWithWeight(JumpTableBB, *I,
2354 Itr != DestWeights.end() ? Itr->second : 0);
2358 // Create a jump table index for this jump table.
2359 unsigned JTEncoding = TLI.getJumpTableEncoding();
2360 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2361 ->createJumpTableIndex(DestBBs);
2363 // Set the jump table information so that we can codegen it as a second
2364 // MachineBasicBlock
2365 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2366 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2367 if (CR.CaseBB == SwitchBB)
2368 visitJumpTableHeader(JT, JTH, SwitchBB);
2370 JTCases.push_back(JumpTableBlock(JTH, JT));
2374 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2376 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2377 CaseRecVector& WorkList,
2379 MachineBasicBlock* SwitchBB) {
2380 Case& FrontCase = *CR.Range.first;
2381 Case& BackCase = *(CR.Range.second-1);
2383 // Size is the number of Cases represented by this range.
2384 unsigned Size = CR.Range.second - CR.Range.first;
2386 const APInt &First = FrontCase.Low->getValue();
2387 const APInt &Last = BackCase.High->getValue();
2389 CaseItr Pivot = CR.Range.first + Size/2;
2391 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2392 // (heuristically) allow us to emit JumpTable's later.
2393 APInt TSize(First.getBitWidth(), 0);
2394 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2398 APInt LSize = FrontCase.size();
2399 APInt RSize = TSize-LSize;
2400 DEBUG(dbgs() << "Selecting best pivot: \n"
2401 << "First: " << First << ", Last: " << Last <<'\n'
2402 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2404 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2406 const APInt &LEnd = I->High->getValue();
2407 const APInt &RBegin = J->Low->getValue();
2408 APInt Range = ComputeRange(LEnd, RBegin);
2409 assert((Range - 2ULL).isNonNegative() &&
2410 "Invalid case distance");
2411 // Use volatile double here to avoid excess precision issues on some hosts,
2412 // e.g. that use 80-bit X87 registers.
2413 // Only consider the density of sub-ranges that actually have sufficient
2414 // entries to be lowered as a jump table.
2415 volatile double LDensity =
2416 LSize.ult(TLI.getMinimumJumpTableEntries())
2418 : LSize.roundToDouble() / (LEnd - First + 1ULL).roundToDouble();
2419 volatile double RDensity =
2420 RSize.ult(TLI.getMinimumJumpTableEntries())
2422 : RSize.roundToDouble() / (Last - RBegin + 1ULL).roundToDouble();
2423 volatile double Metric = Range.logBase2() * (LDensity + RDensity);
2424 // Should always split in some non-trivial place
2425 DEBUG(dbgs() <<"=>Step\n"
2426 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2427 << "LDensity: " << LDensity
2428 << ", RDensity: " << RDensity << '\n'
2429 << "Metric: " << Metric << '\n');
2430 if (FMetric < Metric) {
2433 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2440 if (FMetric == 0 || !areJTsAllowed(TLI))
2441 Pivot = CR.Range.first + Size/2;
2442 splitSwitchCase(CR, Pivot, WorkList, SV, SwitchBB);
2446 void SelectionDAGBuilder::splitSwitchCase(CaseRec &CR, CaseItr Pivot,
2447 CaseRecVector &WorkList,
2449 MachineBasicBlock *SwitchBB) {
2450 // Get the MachineFunction which holds the current MBB. This is used when
2451 // inserting any additional MBBs necessary to represent the switch.
2452 MachineFunction *CurMF = FuncInfo.MF;
2454 // Figure out which block is immediately after the current one.
2455 MachineFunction::iterator BBI = CR.CaseBB;
2458 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2460 CaseRange LHSR(CR.Range.first, Pivot);
2461 CaseRange RHSR(Pivot, CR.Range.second);
2462 const ConstantInt *C = Pivot->Low;
2463 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2465 // We know that we branch to the LHS if the Value being switched on is
2466 // less than the Pivot value, C. We use this to optimize our binary
2467 // tree a bit, by recognizing that if SV is greater than or equal to the
2468 // LHS's Case Value, and that Case Value is exactly one less than the
2469 // Pivot's Value, then we can branch directly to the LHS's Target,
2470 // rather than creating a leaf node for it.
2471 if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE &&
2472 C->getValue() == (CR.GE->getValue() + 1LL)) {
2473 TrueBB = LHSR.first->BB;
2475 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2476 CurMF->insert(BBI, TrueBB);
2477 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2479 // Put SV in a virtual register to make it available from the new blocks.
2480 ExportFromCurrentBlock(SV);
2483 // Similar to the optimization above, if the Value being switched on is
2484 // known to be less than the Constant CR.LT, and the current Case Value
2485 // is CR.LT - 1, then we can branch directly to the target block for
2486 // the current Case Value, rather than emitting a RHS leaf node for it.
2487 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2488 RHSR.first->Low->getValue() == (CR.LT->getValue() - 1LL)) {
2489 FalseBB = RHSR.first->BB;
2491 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2492 CurMF->insert(BBI, FalseBB);
2493 WorkList.push_back(CaseRec(FalseBB, CR.LT, C, RHSR));
2495 // Put SV in a virtual register to make it available from the new blocks.
2496 ExportFromCurrentBlock(SV);
2499 // Create a CaseBlock record representing a conditional branch to
2500 // the LHS node if the value being switched on SV is less than C.
2501 // Otherwise, branch to LHS.
2502 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2504 if (CR.CaseBB == SwitchBB)
2505 visitSwitchCase(CB, SwitchBB);
2507 SwitchCases.push_back(CB);
2510 /// handleBitTestsSwitchCase - if current case range has few destination and
2511 /// range span less, than machine word bitwidth, encode case range into series
2512 /// of masks and emit bit tests with these masks.
2513 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2514 CaseRecVector& WorkList,
2516 MachineBasicBlock* Default,
2517 MachineBasicBlock* SwitchBB) {
2518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2519 EVT PTy = TLI.getPointerTy();
2520 unsigned IntPtrBits = PTy.getSizeInBits();
2522 Case& FrontCase = *CR.Range.first;
2523 Case& BackCase = *(CR.Range.second-1);
2525 // Get the MachineFunction which holds the current MBB. This is used when
2526 // inserting any additional MBBs necessary to represent the switch.
2527 MachineFunction *CurMF = FuncInfo.MF;
2529 // If target does not have legal shift left, do not emit bit tests at all.
2530 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2534 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2535 // Single case counts one, case range - two.
2536 numCmps += (I->Low == I->High ? 1 : 2);
2539 // Count unique destinations
2540 SmallSet<MachineBasicBlock*, 4> Dests;
2541 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2542 Dests.insert(I->BB);
2543 if (Dests.size() > 3)
2544 // Don't bother the code below, if there are too much unique destinations
2547 DEBUG(dbgs() << "Total number of unique destinations: "
2548 << Dests.size() << '\n'
2549 << "Total number of comparisons: " << numCmps << '\n');
2551 // Compute span of values.
2552 const APInt& minValue = FrontCase.Low->getValue();
2553 const APInt& maxValue = BackCase.High->getValue();
2554 APInt cmpRange = maxValue - minValue;
2556 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2557 << "Low bound: " << minValue << '\n'
2558 << "High bound: " << maxValue << '\n');
2560 if (cmpRange.uge(IntPtrBits) ||
2561 (!(Dests.size() == 1 && numCmps >= 3) &&
2562 !(Dests.size() == 2 && numCmps >= 5) &&
2563 !(Dests.size() >= 3 && numCmps >= 6)))
2566 DEBUG(dbgs() << "Emitting bit tests\n");
2567 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2569 // Optimize the case where all the case values fit in a
2570 // word without having to subtract minValue. In this case,
2571 // we can optimize away the subtraction.
2572 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2573 cmpRange = maxValue;
2575 lowBound = minValue;
2578 CaseBitsVector CasesBits;
2579 unsigned i, count = 0;
2581 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2582 MachineBasicBlock* Dest = I->BB;
2583 for (i = 0; i < count; ++i)
2584 if (Dest == CasesBits[i].BB)
2588 assert((count < 3) && "Too much destinations to test!");
2589 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2593 const APInt& lowValue = I->Low->getValue();
2594 const APInt& highValue = I->High->getValue();
2596 uint64_t lo = (lowValue - lowBound).getZExtValue();
2597 uint64_t hi = (highValue - lowBound).getZExtValue();
2598 CasesBits[i].ExtraWeight += I->ExtraWeight;
2600 for (uint64_t j = lo; j <= hi; j++) {
2601 CasesBits[i].Mask |= 1ULL << j;
2602 CasesBits[i].Bits++;
2606 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2610 // Figure out which block is immediately after the current one.
2611 MachineFunction::iterator BBI = CR.CaseBB;
2614 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2616 DEBUG(dbgs() << "Cases:\n");
2617 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2618 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2619 << ", Bits: " << CasesBits[i].Bits
2620 << ", BB: " << CasesBits[i].BB << '\n');
2622 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2623 CurMF->insert(BBI, CaseBB);
2624 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2626 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2628 // Put SV in a virtual register to make it available from the new blocks.
2629 ExportFromCurrentBlock(SV);
2632 BitTestBlock BTB(lowBound, cmpRange, SV,
2633 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2634 CR.CaseBB, Default, std::move(BTC));
2636 if (CR.CaseBB == SwitchBB)
2637 visitBitTestHeader(BTB, SwitchBB);
2639 BitTestCases.push_back(std::move(BTB));
2644 void SelectionDAGBuilder::Clusterify(CaseVector &Cases, const SwitchInst *SI) {
2645 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2647 // Extract cases from the switch and sort them.
2648 typedef std::pair<const ConstantInt*, unsigned> CasePair;
2649 std::vector<CasePair> Sorted;
2650 Sorted.reserve(SI->getNumCases());
2651 for (auto I : SI->cases())
2652 Sorted.push_back(std::make_pair(I.getCaseValue(), I.getSuccessorIndex()));
2653 std::sort(Sorted.begin(), Sorted.end(), [](CasePair a, CasePair b) {
2654 return a.first->getValue().slt(b.first->getValue());
2657 // Merge adjacent cases with the same destination, build Cases vector.
2658 assert(Cases.empty() && "Cases should be empty before Clusterify;");
2659 Cases.reserve(SI->getNumCases());
2660 MachineBasicBlock *PreviousSucc = nullptr;
2661 for (CasePair &CP : Sorted) {
2662 const ConstantInt *CaseVal = CP.first;
2663 unsigned SuccIndex = CP.second;
2664 MachineBasicBlock *Succ = FuncInfo.MBBMap[SI->getSuccessor(SuccIndex)];
2665 uint32_t Weight = BPI ? BPI->getEdgeWeight(SI->getParent(), SuccIndex) : 0;
2667 if (PreviousSucc == Succ &&
2668 (CaseVal->getValue() - Cases.back().High->getValue()) == 1) {
2669 // If this case has the same successor and is a neighbour, merge it into
2670 // the previous cluster.
2671 Cases.back().High = CaseVal;
2672 Cases.back().ExtraWeight += Weight;
2674 Cases.push_back(Case(CaseVal, CaseVal, Succ, Weight));
2677 PreviousSucc = Succ;
2682 for (auto &I : Cases)
2683 // A range counts double, since it requires two compares.
2684 numCmps += I.Low != I.High ? 2 : 1;
2686 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2687 << ". Total compares: " << numCmps << '\n';
2691 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2692 MachineBasicBlock *Last) {
2694 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2695 if (JTCases[i].first.HeaderBB == First)
2696 JTCases[i].first.HeaderBB = Last;
2698 // Update BitTestCases.
2699 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2700 if (BitTestCases[i].Parent == First)
2701 BitTestCases[i].Parent = Last;
2704 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2705 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2707 // Create a vector of Cases, sorted so that we can efficiently create a binary
2708 // search tree from them.
2710 Clusterify(Cases, &SI);
2712 // Get the default destination MBB.
2713 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2715 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2717 // Replace an unreachable default destination with the most popular case
2719 DenseMap<const BasicBlock *, unsigned> Popularity;
2720 unsigned MaxPop = 0;
2721 const BasicBlock *MaxBB = nullptr;
2722 for (auto I : SI.cases()) {
2723 const BasicBlock *BB = I.getCaseSuccessor();
2724 if (++Popularity[BB] > MaxPop) {
2725 MaxPop = Popularity[BB];
2733 Default = FuncInfo.MBBMap[MaxBB];
2735 // Remove cases that were pointing to the destination that is now the default.
2736 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2737 [&](const Case &C) { return C.BB == Default; }),
2741 // If there is only the default destination, go there directly.
2742 if (Cases.empty()) {
2743 // Update machine-CFG edges.
2744 SwitchMBB->addSuccessor(Default);
2746 // If this is not a fall-through branch, emit the branch.
2747 if (Default != NextBlock(SwitchMBB)) {
2748 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2749 getControlRoot(), DAG.getBasicBlock(Default)));
2754 // Get the Value to be switched on.
2755 const Value *SV = SI.getCondition();
2757 // Push the initial CaseRec onto the worklist
2758 CaseRecVector WorkList;
2759 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2760 CaseRange(Cases.begin(),Cases.end())));
2762 while (!WorkList.empty()) {
2763 // Grab a record representing a case range to process off the worklist
2764 CaseRec CR = WorkList.back();
2765 WorkList.pop_back();
2767 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2770 // If the range has few cases (two or less) emit a series of specific
2772 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2775 // If the switch has more than N blocks, and is at least 40% dense, and the
2776 // target supports indirect branches, then emit a jump table rather than
2777 // lowering the switch to a binary tree of conditional branches.
2778 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2779 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2782 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2783 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2784 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2788 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2789 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2791 // Update machine-CFG edges with unique successors.
2792 SmallSet<BasicBlock*, 32> Done;
2793 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2794 BasicBlock *BB = I.getSuccessor(i);
2795 bool Inserted = Done.insert(BB).second;
2799 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2800 addSuccessorWithWeight(IndirectBrMBB, Succ);
2803 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2804 MVT::Other, getControlRoot(),
2805 getValue(I.getAddress())));
2808 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2809 if (DAG.getTarget().Options.TrapUnreachable)
2810 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2813 void SelectionDAGBuilder::visitFSub(const User &I) {
2814 // -0.0 - X --> fneg
2815 Type *Ty = I.getType();
2816 if (isa<Constant>(I.getOperand(0)) &&
2817 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2818 SDValue Op2 = getValue(I.getOperand(1));
2819 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2820 Op2.getValueType(), Op2));
2824 visitBinary(I, ISD::FSUB);
2827 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2828 SDValue Op1 = getValue(I.getOperand(0));
2829 SDValue Op2 = getValue(I.getOperand(1));
2834 if (const OverflowingBinaryOperator *OFBinOp =
2835 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2836 nuw = OFBinOp->hasNoUnsignedWrap();
2837 nsw = OFBinOp->hasNoSignedWrap();
2839 if (const PossiblyExactOperator *ExactOp =
2840 dyn_cast<const PossiblyExactOperator>(&I))
2841 exact = ExactOp->isExact();
2843 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2844 Op1, Op2, nuw, nsw, exact);
2845 setValue(&I, BinNodeValue);
2848 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2849 SDValue Op1 = getValue(I.getOperand(0));
2850 SDValue Op2 = getValue(I.getOperand(1));
2853 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2855 // Coerce the shift amount to the right type if we can.
2856 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2857 unsigned ShiftSize = ShiftTy.getSizeInBits();
2858 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2859 SDLoc DL = getCurSDLoc();
2861 // If the operand is smaller than the shift count type, promote it.
2862 if (ShiftSize > Op2Size)
2863 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2865 // If the operand is larger than the shift count type but the shift
2866 // count type has enough bits to represent any shift value, truncate
2867 // it now. This is a common case and it exposes the truncate to
2868 // optimization early.
2869 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2870 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2871 // Otherwise we'll need to temporarily settle for some other convenient
2872 // type. Type legalization will make adjustments once the shiftee is split.
2874 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2881 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2883 if (const OverflowingBinaryOperator *OFBinOp =
2884 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2885 nuw = OFBinOp->hasNoUnsignedWrap();
2886 nsw = OFBinOp->hasNoSignedWrap();
2888 if (const PossiblyExactOperator *ExactOp =
2889 dyn_cast<const PossiblyExactOperator>(&I))
2890 exact = ExactOp->isExact();
2893 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2898 void SelectionDAGBuilder::visitSDiv(const User &I) {
2899 SDValue Op1 = getValue(I.getOperand(0));
2900 SDValue Op2 = getValue(I.getOperand(1));
2902 // Turn exact SDivs into multiplications.
2903 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2905 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2906 !isa<ConstantSDNode>(Op1) &&
2907 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2908 setValue(&I, DAG.getTargetLoweringInfo()
2909 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2911 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2915 void SelectionDAGBuilder::visitICmp(const User &I) {
2916 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2917 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2918 predicate = IC->getPredicate();
2919 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2920 predicate = ICmpInst::Predicate(IC->getPredicate());
2921 SDValue Op1 = getValue(I.getOperand(0));
2922 SDValue Op2 = getValue(I.getOperand(1));
2923 ISD::CondCode Opcode = getICmpCondCode(predicate);
2925 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2926 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2929 void SelectionDAGBuilder::visitFCmp(const User &I) {
2930 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2931 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2932 predicate = FC->getPredicate();
2933 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2934 predicate = FCmpInst::Predicate(FC->getPredicate());
2935 SDValue Op1 = getValue(I.getOperand(0));
2936 SDValue Op2 = getValue(I.getOperand(1));
2937 ISD::CondCode Condition = getFCmpCondCode(predicate);
2938 if (TM.Options.NoNaNsFPMath)
2939 Condition = getFCmpCodeWithoutNaN(Condition);
2940 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2941 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2944 void SelectionDAGBuilder::visitSelect(const User &I) {
2945 SmallVector<EVT, 4> ValueVTs;
2946 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2947 unsigned NumValues = ValueVTs.size();
2948 if (NumValues == 0) return;
2950 SmallVector<SDValue, 4> Values(NumValues);
2951 SDValue Cond = getValue(I.getOperand(0));
2952 SDValue TrueVal = getValue(I.getOperand(1));
2953 SDValue FalseVal = getValue(I.getOperand(2));
2954 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2955 ISD::VSELECT : ISD::SELECT;
2957 for (unsigned i = 0; i != NumValues; ++i)
2958 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2959 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2961 SDValue(TrueVal.getNode(),
2962 TrueVal.getResNo() + i),
2963 SDValue(FalseVal.getNode(),
2964 FalseVal.getResNo() + i));
2966 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2967 DAG.getVTList(ValueVTs), Values));
2970 void SelectionDAGBuilder::visitTrunc(const User &I) {
2971 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2972 SDValue N = getValue(I.getOperand(0));
2973 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2974 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2977 void SelectionDAGBuilder::visitZExt(const User &I) {
2978 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2979 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2980 SDValue N = getValue(I.getOperand(0));
2981 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2982 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2985 void SelectionDAGBuilder::visitSExt(const User &I) {
2986 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2987 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2988 SDValue N = getValue(I.getOperand(0));
2989 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2990 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2993 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2994 // FPTrunc is never a no-op cast, no need to check
2995 SDValue N = getValue(I.getOperand(0));
2996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2997 EVT DestVT = TLI.getValueType(I.getType());
2998 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
2999 DAG.getTargetConstant(0, TLI.getPointerTy())));
3002 void SelectionDAGBuilder::visitFPExt(const User &I) {
3003 // FPExt is never a no-op cast, no need to check
3004 SDValue N = getValue(I.getOperand(0));
3005 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3006 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3009 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3010 // FPToUI is never a no-op cast, no need to check
3011 SDValue N = getValue(I.getOperand(0));
3012 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3013 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3016 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3017 // FPToSI is never a no-op cast, no need to check
3018 SDValue N = getValue(I.getOperand(0));
3019 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3020 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3023 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3024 // UIToFP is never a no-op cast, no need to check
3025 SDValue N = getValue(I.getOperand(0));
3026 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3027 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3030 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3031 // SIToFP is never a no-op cast, no need to check
3032 SDValue N = getValue(I.getOperand(0));
3033 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3034 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3037 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3038 // What to do depends on the size of the integer and the size of the pointer.
3039 // We can either truncate, zero extend, or no-op, accordingly.
3040 SDValue N = getValue(I.getOperand(0));
3041 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3042 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3045 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3046 // What to do depends on the size of the integer and the size of the pointer.
3047 // We can either truncate, zero extend, or no-op, accordingly.
3048 SDValue N = getValue(I.getOperand(0));
3049 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3050 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3053 void SelectionDAGBuilder::visitBitCast(const User &I) {
3054 SDValue N = getValue(I.getOperand(0));
3055 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3057 // BitCast assures us that source and destination are the same size so this is
3058 // either a BITCAST or a no-op.
3059 if (DestVT != N.getValueType())
3060 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3061 DestVT, N)); // convert types.
3062 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3063 // might fold any kind of constant expression to an integer constant and that
3064 // is not what we are looking for. Only regcognize a bitcast of a genuine
3065 // constant integer as an opaque constant.
3066 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3067 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3070 setValue(&I, N); // noop cast.
3073 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3074 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3075 const Value *SV = I.getOperand(0);
3076 SDValue N = getValue(SV);
3077 EVT DestVT = TLI.getValueType(I.getType());
3079 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3080 unsigned DestAS = I.getType()->getPointerAddressSpace();
3082 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3083 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3088 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3090 SDValue InVec = getValue(I.getOperand(0));
3091 SDValue InVal = getValue(I.getOperand(1));
3092 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3093 getCurSDLoc(), TLI.getVectorIdxTy());
3094 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3095 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3098 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3100 SDValue InVec = getValue(I.getOperand(0));
3101 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3102 getCurSDLoc(), TLI.getVectorIdxTy());
3103 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3104 TLI.getValueType(I.getType()), InVec, InIdx));
3107 // Utility for visitShuffleVector - Return true if every element in Mask,
3108 // beginning from position Pos and ending in Pos+Size, falls within the
3109 // specified sequential range [L, L+Pos). or is undef.
3110 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3111 unsigned Pos, unsigned Size, int Low) {
3112 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3113 if (Mask[i] >= 0 && Mask[i] != Low)
3118 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3119 SDValue Src1 = getValue(I.getOperand(0));
3120 SDValue Src2 = getValue(I.getOperand(1));
3122 SmallVector<int, 8> Mask;
3123 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3124 unsigned MaskNumElts = Mask.size();
3126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3127 EVT VT = TLI.getValueType(I.getType());
3128 EVT SrcVT = Src1.getValueType();
3129 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3131 if (SrcNumElts == MaskNumElts) {
3132 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3137 // Normalize the shuffle vector since mask and vector length don't match.
3138 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3139 // Mask is longer than the source vectors and is a multiple of the source
3140 // vectors. We can use concatenate vector to make the mask and vectors
3142 if (SrcNumElts*2 == MaskNumElts) {
3143 // First check for Src1 in low and Src2 in high
3144 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3145 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3146 // The shuffle is concatenating two vectors together.
3147 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3151 // Then check for Src2 in low and Src1 in high
3152 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3153 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3154 // The shuffle is concatenating two vectors together.
3155 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3161 // Pad both vectors with undefs to make them the same length as the mask.
3162 unsigned NumConcat = MaskNumElts / SrcNumElts;
3163 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3164 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3165 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3167 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3168 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3172 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3173 getCurSDLoc(), VT, MOps1);
3174 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3175 getCurSDLoc(), VT, MOps2);
3177 // Readjust mask for new input vector length.
3178 SmallVector<int, 8> MappedOps;
3179 for (unsigned i = 0; i != MaskNumElts; ++i) {
3181 if (Idx >= (int)SrcNumElts)
3182 Idx -= SrcNumElts - MaskNumElts;
3183 MappedOps.push_back(Idx);
3186 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3191 if (SrcNumElts > MaskNumElts) {
3192 // Analyze the access pattern of the vector to see if we can extract
3193 // two subvectors and do the shuffle. The analysis is done by calculating
3194 // the range of elements the mask access on both vectors.
3195 int MinRange[2] = { static_cast<int>(SrcNumElts),
3196 static_cast<int>(SrcNumElts)};
3197 int MaxRange[2] = {-1, -1};
3199 for (unsigned i = 0; i != MaskNumElts; ++i) {
3205 if (Idx >= (int)SrcNumElts) {
3209 if (Idx > MaxRange[Input])
3210 MaxRange[Input] = Idx;
3211 if (Idx < MinRange[Input])
3212 MinRange[Input] = Idx;
3215 // Check if the access is smaller than the vector size and can we find
3216 // a reasonable extract index.
3217 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3219 int StartIdx[2]; // StartIdx to extract from
3220 for (unsigned Input = 0; Input < 2; ++Input) {
3221 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3222 RangeUse[Input] = 0; // Unused
3223 StartIdx[Input] = 0;
3227 // Find a good start index that is a multiple of the mask length. Then
3228 // see if the rest of the elements are in range.
3229 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3230 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3231 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3232 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3235 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3236 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3239 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3240 // Extract appropriate subvector and generate a vector shuffle
3241 for (unsigned Input = 0; Input < 2; ++Input) {
3242 SDValue &Src = Input == 0 ? Src1 : Src2;
3243 if (RangeUse[Input] == 0)
3244 Src = DAG.getUNDEF(VT);
3247 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3248 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3251 // Calculate new mask.
3252 SmallVector<int, 8> MappedOps;
3253 for (unsigned i = 0; i != MaskNumElts; ++i) {
3256 if (Idx < (int)SrcNumElts)
3259 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3261 MappedOps.push_back(Idx);
3264 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3270 // We can't use either concat vectors or extract subvectors so fall back to
3271 // replacing the shuffle with extract and build vector.
3272 // to insert and build vector.
3273 EVT EltVT = VT.getVectorElementType();
3274 EVT IdxVT = TLI.getVectorIdxTy();
3275 SmallVector<SDValue,8> Ops;
3276 for (unsigned i = 0; i != MaskNumElts; ++i) {
3281 Res = DAG.getUNDEF(EltVT);
3283 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3284 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3286 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3287 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3293 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3296 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3297 const Value *Op0 = I.getOperand(0);
3298 const Value *Op1 = I.getOperand(1);
3299 Type *AggTy = I.getType();
3300 Type *ValTy = Op1->getType();
3301 bool IntoUndef = isa<UndefValue>(Op0);
3302 bool FromUndef = isa<UndefValue>(Op1);
3304 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3307 SmallVector<EVT, 4> AggValueVTs;
3308 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3309 SmallVector<EVT, 4> ValValueVTs;
3310 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3312 unsigned NumAggValues = AggValueVTs.size();
3313 unsigned NumValValues = ValValueVTs.size();
3314 SmallVector<SDValue, 4> Values(NumAggValues);
3316 // Ignore an insertvalue that produces an empty object
3317 if (!NumAggValues) {
3318 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3322 SDValue Agg = getValue(Op0);
3324 // Copy the beginning value(s) from the original aggregate.
3325 for (; i != LinearIndex; ++i)
3326 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3327 SDValue(Agg.getNode(), Agg.getResNo() + i);
3328 // Copy values from the inserted value(s).
3330 SDValue Val = getValue(Op1);
3331 for (; i != LinearIndex + NumValValues; ++i)
3332 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3333 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3335 // Copy remaining value(s) from the original aggregate.
3336 for (; i != NumAggValues; ++i)
3337 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3338 SDValue(Agg.getNode(), Agg.getResNo() + i);
3340 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3341 DAG.getVTList(AggValueVTs), Values));
3344 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3345 const Value *Op0 = I.getOperand(0);
3346 Type *AggTy = Op0->getType();
3347 Type *ValTy = I.getType();
3348 bool OutOfUndef = isa<UndefValue>(Op0);
3350 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3353 SmallVector<EVT, 4> ValValueVTs;
3354 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3356 unsigned NumValValues = ValValueVTs.size();
3358 // Ignore a extractvalue that produces an empty object
3359 if (!NumValValues) {
3360 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3364 SmallVector<SDValue, 4> Values(NumValValues);
3366 SDValue Agg = getValue(Op0);
3367 // Copy out the selected value(s).
3368 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3369 Values[i - LinearIndex] =
3371 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3372 SDValue(Agg.getNode(), Agg.getResNo() + i);
3374 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3375 DAG.getVTList(ValValueVTs), Values));
3378 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3379 Value *Op0 = I.getOperand(0);
3380 // Note that the pointer operand may be a vector of pointers. Take the scalar
3381 // element which holds a pointer.
3382 Type *Ty = Op0->getType()->getScalarType();
3383 unsigned AS = Ty->getPointerAddressSpace();
3384 SDValue N = getValue(Op0);
3386 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3388 const Value *Idx = *OI;
3389 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3390 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3393 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3394 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3395 DAG.getConstant(Offset, N.getValueType()));
3398 Ty = StTy->getElementType(Field);
3400 Ty = cast<SequentialType>(Ty)->getElementType();
3401 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
3402 unsigned PtrSize = PtrTy.getSizeInBits();
3403 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3405 // If this is a constant subscript, handle it quickly.
3406 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
3409 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3410 SDValue OffsVal = DAG.getConstant(Offs, PtrTy);
3411 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal);
3415 // N = N + Idx * ElementSize;
3416 SDValue IdxN = getValue(Idx);
3418 // If the index is smaller or larger than intptr_t, truncate or extend
3420 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3422 // If this is a multiply by a power of two, turn it into a shl
3423 // immediately. This is a very common case.
3424 if (ElementSize != 1) {
3425 if (ElementSize.isPowerOf2()) {
3426 unsigned Amt = ElementSize.logBase2();
3427 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3428 N.getValueType(), IdxN,
3429 DAG.getConstant(Amt, IdxN.getValueType()));
3431 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3432 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3433 N.getValueType(), IdxN, Scale);
3437 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3438 N.getValueType(), N, IdxN);
3445 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3446 // If this is a fixed sized alloca in the entry block of the function,
3447 // allocate it statically on the stack.
3448 if (FuncInfo.StaticAllocaMap.count(&I))
3449 return; // getValue will auto-populate this.
3451 Type *Ty = I.getAllocatedType();
3452 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3453 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3455 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3458 SDValue AllocSize = getValue(I.getArraySize());
3460 EVT IntPtr = TLI.getPointerTy();
3461 if (AllocSize.getValueType() != IntPtr)
3462 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3464 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3466 DAG.getConstant(TySize, IntPtr));
3468 // Handle alignment. If the requested alignment is less than or equal to
3469 // the stack alignment, ignore it. If the size is greater than or equal to
3470 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3471 unsigned StackAlign =
3472 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3473 if (Align <= StackAlign)
3476 // Round the size of the allocation up to the stack alignment size
3477 // by add SA-1 to the size.
3478 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3479 AllocSize.getValueType(), AllocSize,
3480 DAG.getIntPtrConstant(StackAlign-1));
3482 // Mask out the low bits for alignment purposes.
3483 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3484 AllocSize.getValueType(), AllocSize,
3485 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3487 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3488 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3489 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3491 DAG.setRoot(DSA.getValue(1));
3493 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3496 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3498 return visitAtomicLoad(I);
3500 const Value *SV = I.getOperand(0);
3501 SDValue Ptr = getValue(SV);
3503 Type *Ty = I.getType();
3505 bool isVolatile = I.isVolatile();
3506 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3507 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3508 unsigned Alignment = I.getAlignment();
3511 I.getAAMetadata(AAInfo);
3512 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3515 SmallVector<EVT, 4> ValueVTs;
3516 SmallVector<uint64_t, 4> Offsets;
3517 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3518 unsigned NumValues = ValueVTs.size();
3523 bool ConstantMemory = false;
3524 if (isVolatile || NumValues > MaxParallelChains)
3525 // Serialize volatile loads with other side effects.
3527 else if (AA->pointsToConstantMemory(
3528 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3529 // Do not serialize (non-volatile) loads of constant memory with anything.
3530 Root = DAG.getEntryNode();
3531 ConstantMemory = true;
3533 // Do not serialize non-volatile loads against each other.
3534 Root = DAG.getRoot();
3538 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3540 SmallVector<SDValue, 4> Values(NumValues);
3541 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3543 EVT PtrVT = Ptr.getValueType();
3544 unsigned ChainI = 0;
3545 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3546 // Serializing loads here may result in excessive register pressure, and
3547 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3548 // could recover a bit by hoisting nodes upward in the chain by recognizing
3549 // they are side-effect free or do not alias. The optimizer should really
3550 // avoid this case by converting large object/array copies to llvm.memcpy
3551 // (MaxParallelChains should always remain as failsafe).
3552 if (ChainI == MaxParallelChains) {
3553 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3554 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3555 makeArrayRef(Chains.data(), ChainI));
3559 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3561 DAG.getConstant(Offsets[i], PtrVT));
3562 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3563 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3564 isNonTemporal, isInvariant, Alignment, AAInfo,
3568 Chains[ChainI] = L.getValue(1);
3571 if (!ConstantMemory) {
3572 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3573 makeArrayRef(Chains.data(), ChainI));
3577 PendingLoads.push_back(Chain);
3580 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3581 DAG.getVTList(ValueVTs), Values));
3584 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3586 return visitAtomicStore(I);
3588 const Value *SrcV = I.getOperand(0);
3589 const Value *PtrV = I.getOperand(1);
3591 SmallVector<EVT, 4> ValueVTs;
3592 SmallVector<uint64_t, 4> Offsets;
3593 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3594 ValueVTs, &Offsets);
3595 unsigned NumValues = ValueVTs.size();
3599 // Get the lowered operands. Note that we do this after
3600 // checking if NumResults is zero, because with zero results
3601 // the operands won't have values in the map.
3602 SDValue Src = getValue(SrcV);
3603 SDValue Ptr = getValue(PtrV);
3605 SDValue Root = getRoot();
3606 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3608 EVT PtrVT = Ptr.getValueType();
3609 bool isVolatile = I.isVolatile();
3610 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3611 unsigned Alignment = I.getAlignment();
3614 I.getAAMetadata(AAInfo);
3616 unsigned ChainI = 0;
3617 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3618 // See visitLoad comments.
3619 if (ChainI == MaxParallelChains) {
3620 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3621 makeArrayRef(Chains.data(), ChainI));
3625 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3626 DAG.getConstant(Offsets[i], PtrVT));
3627 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3628 SDValue(Src.getNode(), Src.getResNo() + i),
3629 Add, MachinePointerInfo(PtrV, Offsets[i]),
3630 isVolatile, isNonTemporal, Alignment, AAInfo);
3631 Chains[ChainI] = St;
3634 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3635 makeArrayRef(Chains.data(), ChainI));
3636 DAG.setRoot(StoreNode);
3639 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3640 SDLoc sdl = getCurSDLoc();
3642 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3643 Value *PtrOperand = I.getArgOperand(1);
3644 SDValue Ptr = getValue(PtrOperand);
3645 SDValue Src0 = getValue(I.getArgOperand(0));
3646 SDValue Mask = getValue(I.getArgOperand(3));
3647 EVT VT = Src0.getValueType();
3648 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3650 Alignment = DAG.getEVTAlignment(VT);
3653 I.getAAMetadata(AAInfo);
3655 MachineMemOperand *MMO =
3656 DAG.getMachineFunction().
3657 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3658 MachineMemOperand::MOStore, VT.getStoreSize(),
3660 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3662 DAG.setRoot(StoreNode);
3663 setValue(&I, StoreNode);
3666 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3667 SDLoc sdl = getCurSDLoc();
3669 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3670 Value *PtrOperand = I.getArgOperand(0);
3671 SDValue Ptr = getValue(PtrOperand);
3672 SDValue Src0 = getValue(I.getArgOperand(3));
3673 SDValue Mask = getValue(I.getArgOperand(2));
3675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3676 EVT VT = TLI.getValueType(I.getType());
3677 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3679 Alignment = DAG.getEVTAlignment(VT);
3682 I.getAAMetadata(AAInfo);
3683 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3685 SDValue InChain = DAG.getRoot();
3686 if (AA->pointsToConstantMemory(
3687 AliasAnalysis::Location(PtrOperand,
3688 AA->getTypeStoreSize(I.getType()),
3690 // Do not serialize (non-volatile) loads of constant memory with anything.
3691 InChain = DAG.getEntryNode();
3694 MachineMemOperand *MMO =
3695 DAG.getMachineFunction().
3696 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3697 MachineMemOperand::MOLoad, VT.getStoreSize(),
3698 Alignment, AAInfo, Ranges);
3700 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3702 SDValue OutChain = Load.getValue(1);
3703 DAG.setRoot(OutChain);
3707 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3708 SDLoc dl = getCurSDLoc();
3709 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3710 AtomicOrdering FailureOrder = I.getFailureOrdering();
3711 SynchronizationScope Scope = I.getSynchScope();
3713 SDValue InChain = getRoot();
3715 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3716 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3717 SDValue L = DAG.getAtomicCmpSwap(
3718 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3719 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3720 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3721 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3723 SDValue OutChain = L.getValue(2);
3726 DAG.setRoot(OutChain);
3729 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3730 SDLoc dl = getCurSDLoc();
3732 switch (I.getOperation()) {
3733 default: llvm_unreachable("Unknown atomicrmw operation");
3734 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3735 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3736 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3737 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3738 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3739 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3740 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3741 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3742 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3743 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3744 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3746 AtomicOrdering Order = I.getOrdering();
3747 SynchronizationScope Scope = I.getSynchScope();
3749 SDValue InChain = getRoot();
3752 DAG.getAtomic(NT, dl,
3753 getValue(I.getValOperand()).getSimpleValueType(),
3755 getValue(I.getPointerOperand()),
3756 getValue(I.getValOperand()),
3757 I.getPointerOperand(),
3758 /* Alignment=*/ 0, Order, Scope);
3760 SDValue OutChain = L.getValue(1);
3763 DAG.setRoot(OutChain);
3766 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3767 SDLoc dl = getCurSDLoc();
3768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3771 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3772 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3773 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3776 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3777 SDLoc dl = getCurSDLoc();
3778 AtomicOrdering Order = I.getOrdering();
3779 SynchronizationScope Scope = I.getSynchScope();
3781 SDValue InChain = getRoot();
3783 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3784 EVT VT = TLI.getValueType(I.getType());
3786 if (I.getAlignment() < VT.getSizeInBits() / 8)
3787 report_fatal_error("Cannot generate unaligned atomic load");
3789 MachineMemOperand *MMO =
3790 DAG.getMachineFunction().
3791 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3792 MachineMemOperand::MOVolatile |
3793 MachineMemOperand::MOLoad,
3795 I.getAlignment() ? I.getAlignment() :
3796 DAG.getEVTAlignment(VT));
3798 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3800 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3801 getValue(I.getPointerOperand()), MMO,
3804 SDValue OutChain = L.getValue(1);
3807 DAG.setRoot(OutChain);
3810 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3811 SDLoc dl = getCurSDLoc();
3813 AtomicOrdering Order = I.getOrdering();
3814 SynchronizationScope Scope = I.getSynchScope();
3816 SDValue InChain = getRoot();
3818 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3819 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3821 if (I.getAlignment() < VT.getSizeInBits() / 8)
3822 report_fatal_error("Cannot generate unaligned atomic store");
3825 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3827 getValue(I.getPointerOperand()),
3828 getValue(I.getValueOperand()),
3829 I.getPointerOperand(), I.getAlignment(),
3832 DAG.setRoot(OutChain);
3835 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3837 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3838 unsigned Intrinsic) {
3839 bool HasChain = !I.doesNotAccessMemory();
3840 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3842 // Build the operand list.
3843 SmallVector<SDValue, 8> Ops;
3844 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3846 // We don't need to serialize loads against other loads.
3847 Ops.push_back(DAG.getRoot());
3849 Ops.push_back(getRoot());
3853 // Info is set by getTgtMemInstrinsic
3854 TargetLowering::IntrinsicInfo Info;
3855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3856 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3858 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3859 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3860 Info.opc == ISD::INTRINSIC_W_CHAIN)
3861 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3863 // Add all operands of the call to the operand list.
3864 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3865 SDValue Op = getValue(I.getArgOperand(i));
3869 SmallVector<EVT, 4> ValueVTs;
3870 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3873 ValueVTs.push_back(MVT::Other);
3875 SDVTList VTs = DAG.getVTList(ValueVTs);
3879 if (IsTgtIntrinsic) {
3880 // This is target intrinsic that touches memory
3881 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3882 VTs, Ops, Info.memVT,
3883 MachinePointerInfo(Info.ptrVal, Info.offset),
3884 Info.align, Info.vol,
3885 Info.readMem, Info.writeMem, Info.size);
3886 } else if (!HasChain) {
3887 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3888 } else if (!I.getType()->isVoidTy()) {
3889 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3891 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3895 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3897 PendingLoads.push_back(Chain);
3902 if (!I.getType()->isVoidTy()) {
3903 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3904 EVT VT = TLI.getValueType(PTy);
3905 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3908 setValue(&I, Result);
3912 /// GetSignificand - Get the significand and build it into a floating-point
3913 /// number with exponent of 1:
3915 /// Op = (Op & 0x007fffff) | 0x3f800000;
3917 /// where Op is the hexadecimal representation of floating point value.
3919 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3920 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3921 DAG.getConstant(0x007fffff, MVT::i32));
3922 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3923 DAG.getConstant(0x3f800000, MVT::i32));
3924 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3927 /// GetExponent - Get the exponent:
3929 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3931 /// where Op is the hexadecimal representation of floating point value.
3933 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3935 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3936 DAG.getConstant(0x7f800000, MVT::i32));
3937 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3938 DAG.getConstant(23, TLI.getPointerTy()));
3939 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3940 DAG.getConstant(127, MVT::i32));
3941 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3944 /// getF32Constant - Get 32-bit floating point constant.
3946 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3947 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3951 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3952 SelectionDAG &DAG) {
3953 // IntegerPartOfX = ((int32_t)(t0);
3954 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3956 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3957 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3958 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3960 // IntegerPartOfX <<= 23;
3961 IntegerPartOfX = DAG.getNode(
3962 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3963 DAG.getConstant(23, DAG.getTargetLoweringInfo().getPointerTy()));
3965 SDValue TwoToFractionalPartOfX;
3966 if (LimitFloatPrecision <= 6) {
3967 // For floating-point precision of 6:
3969 // TwoToFractionalPartOfX =
3971 // (0.735607626f + 0.252464424f * x) * x;
3973 // error 0.0144103317, which is 6 bits
3974 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3975 getF32Constant(DAG, 0x3e814304));
3976 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3977 getF32Constant(DAG, 0x3f3c50c8));
3978 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3979 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3980 getF32Constant(DAG, 0x3f7f5e7e));
3981 } else if (LimitFloatPrecision <= 12) {
3982 // For floating-point precision of 12:
3984 // TwoToFractionalPartOfX =
3987 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3989 // error 0.000107046256, which is 13 to 14 bits
3990 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3991 getF32Constant(DAG, 0x3da235e3));
3992 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3993 getF32Constant(DAG, 0x3e65b8f3));
3994 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3995 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3996 getF32Constant(DAG, 0x3f324b07));
3997 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3998 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3999 getF32Constant(DAG, 0x3f7ff8fd));
4000 } else { // LimitFloatPrecision <= 18
4001 // For floating-point precision of 18:
4003 // TwoToFractionalPartOfX =
4007 // (0.554906021e-1f +
4008 // (0.961591928e-2f +
4009 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4010 // error 2.47208000*10^(-7), which is better than 18 bits
4011 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4012 getF32Constant(DAG, 0x3924b03e));
4013 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4014 getF32Constant(DAG, 0x3ab24b87));
4015 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4016 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4017 getF32Constant(DAG, 0x3c1d8c17));
4018 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4019 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4020 getF32Constant(DAG, 0x3d634a1d));
4021 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4022 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4023 getF32Constant(DAG, 0x3e75fe14));
4024 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4025 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4026 getF32Constant(DAG, 0x3f317234));
4027 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4028 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4029 getF32Constant(DAG, 0x3f800000));
4032 // Add the exponent into the result in integer domain.
4033 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4034 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4035 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4038 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4039 /// limited-precision mode.
4040 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4041 const TargetLowering &TLI) {
4042 if (Op.getValueType() == MVT::f32 &&
4043 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4045 // Put the exponent in the right bit position for later addition to the
4048 // #define LOG2OFe 1.4426950f
4049 // t0 = Op * LOG2OFe
4050 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4051 getF32Constant(DAG, 0x3fb8aa3b));
4052 return getLimitedPrecisionExp2(t0, dl, DAG);
4055 // No special expansion.
4056 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4059 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4060 /// limited-precision mode.
4061 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4062 const TargetLowering &TLI) {
4063 if (Op.getValueType() == MVT::f32 &&
4064 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4065 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4067 // Scale the exponent by log(2) [0.69314718f].
4068 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4069 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4070 getF32Constant(DAG, 0x3f317218));
4072 // Get the significand and build it into a floating-point number with
4074 SDValue X = GetSignificand(DAG, Op1, dl);
4076 SDValue LogOfMantissa;
4077 if (LimitFloatPrecision <= 6) {
4078 // For floating-point precision of 6:
4082 // (1.4034025f - 0.23903021f * x) * x;
4084 // error 0.0034276066, which is better than 8 bits
4085 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4086 getF32Constant(DAG, 0xbe74c456));
4087 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4088 getF32Constant(DAG, 0x3fb3a2b1));
4089 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4090 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4091 getF32Constant(DAG, 0x3f949a29));
4092 } else if (LimitFloatPrecision <= 12) {
4093 // For floating-point precision of 12:
4099 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4101 // error 0.000061011436, which is 14 bits
4102 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4103 getF32Constant(DAG, 0xbd67b6d6));
4104 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4105 getF32Constant(DAG, 0x3ee4f4b8));
4106 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4107 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4108 getF32Constant(DAG, 0x3fbc278b));
4109 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4110 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4111 getF32Constant(DAG, 0x40348e95));
4112 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4113 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4114 getF32Constant(DAG, 0x3fdef31a));
4115 } else { // LimitFloatPrecision <= 18
4116 // For floating-point precision of 18:
4124 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4126 // error 0.0000023660568, which is better than 18 bits
4127 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4128 getF32Constant(DAG, 0xbc91e5ac));
4129 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4130 getF32Constant(DAG, 0x3e4350aa));
4131 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4132 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4133 getF32Constant(DAG, 0x3f60d3e3));
4134 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4135 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4136 getF32Constant(DAG, 0x4011cdf0));
4137 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4138 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4139 getF32Constant(DAG, 0x406cfd1c));
4140 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4141 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4142 getF32Constant(DAG, 0x408797cb));
4143 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4144 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4145 getF32Constant(DAG, 0x4006dcab));
4148 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4151 // No special expansion.
4152 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4155 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4156 /// limited-precision mode.
4157 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4158 const TargetLowering &TLI) {
4159 if (Op.getValueType() == MVT::f32 &&
4160 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4161 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4163 // Get the exponent.
4164 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4166 // Get the significand and build it into a floating-point number with
4168 SDValue X = GetSignificand(DAG, Op1, dl);
4170 // Different possible minimax approximations of significand in
4171 // floating-point for various degrees of accuracy over [1,2].
4172 SDValue Log2ofMantissa;
4173 if (LimitFloatPrecision <= 6) {
4174 // For floating-point precision of 6:
4176 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4178 // error 0.0049451742, which is more than 7 bits
4179 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4180 getF32Constant(DAG, 0xbeb08fe0));
4181 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4182 getF32Constant(DAG, 0x40019463));
4183 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4184 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4185 getF32Constant(DAG, 0x3fd6633d));
4186 } else if (LimitFloatPrecision <= 12) {
4187 // For floating-point precision of 12:
4193 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4195 // error 0.0000876136000, which is better than 13 bits
4196 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4197 getF32Constant(DAG, 0xbda7262e));
4198 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4199 getF32Constant(DAG, 0x3f25280b));
4200 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4201 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4202 getF32Constant(DAG, 0x4007b923));
4203 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4204 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4205 getF32Constant(DAG, 0x40823e2f));
4206 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4207 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4208 getF32Constant(DAG, 0x4020d29c));
4209 } else { // LimitFloatPrecision <= 18
4210 // For floating-point precision of 18:
4219 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4221 // error 0.0000018516, which is better than 18 bits
4222 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4223 getF32Constant(DAG, 0xbcd2769e));
4224 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4225 getF32Constant(DAG, 0x3e8ce0b9));
4226 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4227 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4228 getF32Constant(DAG, 0x3fa22ae7));
4229 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4230 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4231 getF32Constant(DAG, 0x40525723));
4232 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4233 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4234 getF32Constant(DAG, 0x40aaf200));
4235 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4236 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4237 getF32Constant(DAG, 0x40c39dad));
4238 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4239 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4240 getF32Constant(DAG, 0x4042902c));
4243 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4246 // No special expansion.
4247 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4250 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4251 /// limited-precision mode.
4252 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4253 const TargetLowering &TLI) {
4254 if (Op.getValueType() == MVT::f32 &&
4255 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4256 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4258 // Scale the exponent by log10(2) [0.30102999f].
4259 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4260 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4261 getF32Constant(DAG, 0x3e9a209a));
4263 // Get the significand and build it into a floating-point number with
4265 SDValue X = GetSignificand(DAG, Op1, dl);
4267 SDValue Log10ofMantissa;
4268 if (LimitFloatPrecision <= 6) {
4269 // For floating-point precision of 6:
4271 // Log10ofMantissa =
4273 // (0.60948995f - 0.10380950f * x) * x;
4275 // error 0.0014886165, which is 6 bits
4276 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4277 getF32Constant(DAG, 0xbdd49a13));
4278 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4279 getF32Constant(DAG, 0x3f1c0789));
4280 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4281 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4282 getF32Constant(DAG, 0x3f011300));
4283 } else if (LimitFloatPrecision <= 12) {
4284 // For floating-point precision of 12:
4286 // Log10ofMantissa =
4289 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4291 // error 0.00019228036, which is better than 12 bits
4292 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4293 getF32Constant(DAG, 0x3d431f31));
4294 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4295 getF32Constant(DAG, 0x3ea21fb2));
4296 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4297 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4298 getF32Constant(DAG, 0x3f6ae232));
4299 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4300 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4301 getF32Constant(DAG, 0x3f25f7c3));
4302 } else { // LimitFloatPrecision <= 18
4303 // For floating-point precision of 18:
4305 // Log10ofMantissa =
4310 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4312 // error 0.0000037995730, which is better than 18 bits
4313 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4314 getF32Constant(DAG, 0x3c5d51ce));
4315 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4316 getF32Constant(DAG, 0x3e00685a));
4317 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4318 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4319 getF32Constant(DAG, 0x3efb6798));
4320 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4321 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4322 getF32Constant(DAG, 0x3f88d192));
4323 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4324 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4325 getF32Constant(DAG, 0x3fc4316c));
4326 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4327 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4328 getF32Constant(DAG, 0x3f57ce70));
4331 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4334 // No special expansion.
4335 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4338 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4339 /// limited-precision mode.
4340 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4341 const TargetLowering &TLI) {
4342 if (Op.getValueType() == MVT::f32 &&
4343 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4344 return getLimitedPrecisionExp2(Op, dl, DAG);
4346 // No special expansion.
4347 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4350 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4351 /// limited-precision mode with x == 10.0f.
4352 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4353 SelectionDAG &DAG, const TargetLowering &TLI) {
4354 bool IsExp10 = false;
4355 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4356 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4357 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4359 IsExp10 = LHSC->isExactlyValue(Ten);
4364 // Put the exponent in the right bit position for later addition to the
4367 // #define LOG2OF10 3.3219281f
4368 // t0 = Op * LOG2OF10;
4369 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4370 getF32Constant(DAG, 0x40549a78));
4371 return getLimitedPrecisionExp2(t0, dl, DAG);
4374 // No special expansion.
4375 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4379 /// ExpandPowI - Expand a llvm.powi intrinsic.
4380 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4381 SelectionDAG &DAG) {
4382 // If RHS is a constant, we can expand this out to a multiplication tree,
4383 // otherwise we end up lowering to a call to __powidf2 (for example). When
4384 // optimizing for size, we only want to do this if the expansion would produce
4385 // a small number of multiplies, otherwise we do the full expansion.
4386 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4387 // Get the exponent as a positive value.
4388 unsigned Val = RHSC->getSExtValue();
4389 if ((int)Val < 0) Val = -Val;
4391 // powi(x, 0) -> 1.0
4393 return DAG.getConstantFP(1.0, LHS.getValueType());
4395 const Function *F = DAG.getMachineFunction().getFunction();
4396 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
4397 // If optimizing for size, don't insert too many multiplies. This
4398 // inserts up to 5 multiplies.
4399 countPopulation(Val) + Log2_32(Val) < 7) {
4400 // We use the simple binary decomposition method to generate the multiply
4401 // sequence. There are more optimal ways to do this (for example,
4402 // powi(x,15) generates one more multiply than it should), but this has
4403 // the benefit of being both really simple and much better than a libcall.
4404 SDValue Res; // Logically starts equal to 1.0
4405 SDValue CurSquare = LHS;
4409 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4411 Res = CurSquare; // 1.0*CurSquare.
4414 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4415 CurSquare, CurSquare);
4419 // If the original was negative, invert the result, producing 1/(x*x*x).
4420 if (RHSC->getSExtValue() < 0)
4421 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4422 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4427 // Otherwise, expand to a libcall.
4428 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4431 // getTruncatedArgReg - Find underlying register used for an truncated
4433 static unsigned getTruncatedArgReg(const SDValue &N) {
4434 if (N.getOpcode() != ISD::TRUNCATE)
4437 const SDValue &Ext = N.getOperand(0);
4438 if (Ext.getOpcode() == ISD::AssertZext ||
4439 Ext.getOpcode() == ISD::AssertSext) {
4440 const SDValue &CFR = Ext.getOperand(0);
4441 if (CFR.getOpcode() == ISD::CopyFromReg)
4442 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4443 if (CFR.getOpcode() == ISD::TRUNCATE)
4444 return getTruncatedArgReg(CFR);
4449 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4450 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4451 /// At the end of instruction selection, they will be inserted to the entry BB.
4452 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4454 MDNode *Expr, int64_t Offset,
4457 const Argument *Arg = dyn_cast<Argument>(V);
4461 MachineFunction &MF = DAG.getMachineFunction();
4462 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4464 // Ignore inlined function arguments here.
4465 DIVariable DV(Variable);
4466 if (DV.isInlinedFnArgument(MF.getFunction()))
4469 Optional<MachineOperand> Op;
4470 // Some arguments' frame index is recorded during argument lowering.
4471 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4472 Op = MachineOperand::CreateFI(FI);
4474 if (!Op && N.getNode()) {
4476 if (N.getOpcode() == ISD::CopyFromReg)
4477 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4479 Reg = getTruncatedArgReg(N);
4480 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4481 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4482 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4487 Op = MachineOperand::CreateReg(Reg, false);
4491 // Check if ValueMap has reg number.
4492 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4493 if (VMI != FuncInfo.ValueMap.end())
4494 Op = MachineOperand::CreateReg(VMI->second, false);
4497 if (!Op && N.getNode())
4498 // Check if frame index is available.
4499 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4500 if (FrameIndexSDNode *FINode =
4501 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4502 Op = MachineOperand::CreateFI(FINode->getIndex());
4508 FuncInfo.ArgDbgValues.push_back(
4509 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4510 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4512 FuncInfo.ArgDbgValues.push_back(
4513 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4516 .addMetadata(Variable)
4517 .addMetadata(Expr));
4522 // VisualStudio defines setjmp as _setjmp
4523 #if defined(_MSC_VER) && defined(setjmp) && \
4524 !defined(setjmp_undefined_for_msvc)
4525 # pragma push_macro("setjmp")
4527 # define setjmp_undefined_for_msvc
4530 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4531 /// we want to emit this as a call to a named external function, return the name
4532 /// otherwise lower it and return null.
4534 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4536 SDLoc sdl = getCurSDLoc();
4537 DebugLoc dl = getCurDebugLoc();
4540 switch (Intrinsic) {
4542 // By default, turn this into a target intrinsic node.
4543 visitTargetIntrinsic(I, Intrinsic);
4545 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4546 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4547 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4548 case Intrinsic::returnaddress:
4549 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4550 getValue(I.getArgOperand(0))));
4552 case Intrinsic::frameaddress:
4553 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4554 getValue(I.getArgOperand(0))));
4556 case Intrinsic::read_register: {
4557 Value *Reg = I.getArgOperand(0);
4559 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4560 EVT VT = TLI.getValueType(I.getType());
4561 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4564 case Intrinsic::write_register: {
4565 Value *Reg = I.getArgOperand(0);
4566 Value *RegValue = I.getArgOperand(1);
4567 SDValue Chain = getValue(RegValue).getOperand(0);
4569 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4570 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4571 RegName, getValue(RegValue)));
4574 case Intrinsic::setjmp:
4575 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4576 case Intrinsic::longjmp:
4577 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4578 case Intrinsic::memcpy: {
4579 // FIXME: this definition of "user defined address space" is x86-specific
4580 // Assert for address < 256 since we support only user defined address
4582 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4584 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4586 "Unknown address space");
4587 SDValue Op1 = getValue(I.getArgOperand(0));
4588 SDValue Op2 = getValue(I.getArgOperand(1));
4589 SDValue Op3 = getValue(I.getArgOperand(2));
4590 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4592 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4593 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4594 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4595 MachinePointerInfo(I.getArgOperand(0)),
4596 MachinePointerInfo(I.getArgOperand(1))));
4599 case Intrinsic::memset: {
4600 // FIXME: this definition of "user defined address space" is x86-specific
4601 // Assert for address < 256 since we support only user defined address
4603 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4605 "Unknown address space");
4606 SDValue Op1 = getValue(I.getArgOperand(0));
4607 SDValue Op2 = getValue(I.getArgOperand(1));
4608 SDValue Op3 = getValue(I.getArgOperand(2));
4609 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4611 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4612 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4613 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4614 MachinePointerInfo(I.getArgOperand(0))));
4617 case Intrinsic::memmove: {
4618 // FIXME: this definition of "user defined address space" is x86-specific
4619 // Assert for address < 256 since we support only user defined address
4621 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4623 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4625 "Unknown address space");
4626 SDValue Op1 = getValue(I.getArgOperand(0));
4627 SDValue Op2 = getValue(I.getArgOperand(1));
4628 SDValue Op3 = getValue(I.getArgOperand(2));
4629 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4631 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4632 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4633 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4634 MachinePointerInfo(I.getArgOperand(0)),
4635 MachinePointerInfo(I.getArgOperand(1))));
4638 case Intrinsic::dbg_declare: {
4639 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4640 MDNode *Variable = DI.getVariable();
4641 MDNode *Expression = DI.getExpression();
4642 const Value *Address = DI.getAddress();
4643 DIVariable DIVar(Variable);
4644 assert((!DIVar || DIVar.isVariable()) &&
4645 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4646 if (!Address || !DIVar) {
4647 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4651 // Check if address has undef value.
4652 if (isa<UndefValue>(Address) ||
4653 (Address->use_empty() && !isa<Argument>(Address))) {
4654 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4658 SDValue &N = NodeMap[Address];
4659 if (!N.getNode() && isa<Argument>(Address))
4660 // Check unused arguments map.
4661 N = UnusedArgNodeMap[Address];
4664 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4665 Address = BCI->getOperand(0);
4666 // Parameters are handled specially.
4668 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4669 isa<Argument>(Address));
4671 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4673 if (isParameter && !AI) {
4674 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4676 // Byval parameter. We have a frame index at this point.
4677 SDV = DAG.getFrameIndexDbgValue(
4678 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4680 // Address is an argument, so try to emit its dbg value using
4681 // virtual register info from the FuncInfo.ValueMap.
4682 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4686 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4687 true, 0, dl, SDNodeOrder);
4689 // Can't do anything with other non-AI cases yet.
4690 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4691 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4692 DEBUG(Address->dump());
4695 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4697 // If Address is an argument then try to emit its dbg value using
4698 // virtual register info from the FuncInfo.ValueMap.
4699 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4701 // If variable is pinned by a alloca in dominating bb then
4702 // use StaticAllocaMap.
4703 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4704 if (AI->getParent() != DI.getParent()) {
4705 DenseMap<const AllocaInst*, int>::iterator SI =
4706 FuncInfo.StaticAllocaMap.find(AI);
4707 if (SI != FuncInfo.StaticAllocaMap.end()) {
4708 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4709 0, dl, SDNodeOrder);
4710 DAG.AddDbgValue(SDV, nullptr, false);
4715 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4720 case Intrinsic::dbg_value: {
4721 const DbgValueInst &DI = cast<DbgValueInst>(I);
4722 DIVariable DIVar(DI.getVariable());
4723 assert((!DIVar || DIVar.isVariable()) &&
4724 "Variable in DbgValueInst should be either null or a DIVariable.");
4728 MDNode *Variable = DI.getVariable();
4729 MDNode *Expression = DI.getExpression();
4730 uint64_t Offset = DI.getOffset();
4731 const Value *V = DI.getValue();
4736 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4737 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4739 DAG.AddDbgValue(SDV, nullptr, false);
4741 // Do not use getValue() in here; we don't want to generate code at
4742 // this point if it hasn't been done yet.
4743 SDValue N = NodeMap[V];
4744 if (!N.getNode() && isa<Argument>(V))
4745 // Check unused arguments map.
4746 N = UnusedArgNodeMap[V];
4748 // A dbg.value for an alloca is always indirect.
4749 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4750 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4752 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4753 IsIndirect, Offset, dl, SDNodeOrder);
4754 DAG.AddDbgValue(SDV, N.getNode(), false);
4756 } else if (!V->use_empty() ) {
4757 // Do not call getValue(V) yet, as we don't want to generate code.
4758 // Remember it for later.
4759 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4760 DanglingDebugInfoMap[V] = DDI;
4762 // We may expand this to cover more cases. One case where we have no
4763 // data available is an unreferenced parameter.
4764 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4768 // Build a debug info table entry.
4769 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4770 V = BCI->getOperand(0);
4771 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4772 // Don't handle byval struct arguments or VLAs, for example.
4774 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4775 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4778 DenseMap<const AllocaInst*, int>::iterator SI =
4779 FuncInfo.StaticAllocaMap.find(AI);
4780 if (SI == FuncInfo.StaticAllocaMap.end())
4781 return nullptr; // VLAs.
4785 case Intrinsic::eh_typeid_for: {
4786 // Find the type id for the given typeinfo.
4787 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4788 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4789 Res = DAG.getConstant(TypeID, MVT::i32);
4794 case Intrinsic::eh_return_i32:
4795 case Intrinsic::eh_return_i64:
4796 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4797 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4800 getValue(I.getArgOperand(0)),
4801 getValue(I.getArgOperand(1))));
4803 case Intrinsic::eh_unwind_init:
4804 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4806 case Intrinsic::eh_dwarf_cfa: {
4807 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4808 TLI.getPointerTy());
4809 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4810 CfaArg.getValueType(),
4811 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4812 CfaArg.getValueType()),
4814 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4815 DAG.getConstant(0, TLI.getPointerTy()));
4816 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4820 case Intrinsic::eh_sjlj_callsite: {
4821 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4822 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4823 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4824 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4826 MMI.setCurrentCallSite(CI->getZExtValue());
4829 case Intrinsic::eh_sjlj_functioncontext: {
4830 // Get and store the index of the function context.
4831 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4833 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4834 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4835 MFI->setFunctionContextIndex(FI);
4838 case Intrinsic::eh_sjlj_setjmp: {
4841 Ops[1] = getValue(I.getArgOperand(0));
4842 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4843 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4844 setValue(&I, Op.getValue(0));
4845 DAG.setRoot(Op.getValue(1));
4848 case Intrinsic::eh_sjlj_longjmp: {
4849 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4850 getRoot(), getValue(I.getArgOperand(0))));
4854 case Intrinsic::masked_load:
4857 case Intrinsic::masked_store:
4858 visitMaskedStore(I);
4860 case Intrinsic::x86_mmx_pslli_w:
4861 case Intrinsic::x86_mmx_pslli_d:
4862 case Intrinsic::x86_mmx_pslli_q:
4863 case Intrinsic::x86_mmx_psrli_w:
4864 case Intrinsic::x86_mmx_psrli_d:
4865 case Intrinsic::x86_mmx_psrli_q:
4866 case Intrinsic::x86_mmx_psrai_w:
4867 case Intrinsic::x86_mmx_psrai_d: {
4868 SDValue ShAmt = getValue(I.getArgOperand(1));
4869 if (isa<ConstantSDNode>(ShAmt)) {
4870 visitTargetIntrinsic(I, Intrinsic);
4873 unsigned NewIntrinsic = 0;
4874 EVT ShAmtVT = MVT::v2i32;
4875 switch (Intrinsic) {
4876 case Intrinsic::x86_mmx_pslli_w:
4877 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4879 case Intrinsic::x86_mmx_pslli_d:
4880 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4882 case Intrinsic::x86_mmx_pslli_q:
4883 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4885 case Intrinsic::x86_mmx_psrli_w:
4886 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4888 case Intrinsic::x86_mmx_psrli_d:
4889 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4891 case Intrinsic::x86_mmx_psrli_q:
4892 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4894 case Intrinsic::x86_mmx_psrai_w:
4895 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4897 case Intrinsic::x86_mmx_psrai_d:
4898 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4900 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4903 // The vector shift intrinsics with scalars uses 32b shift amounts but
4904 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4906 // We must do this early because v2i32 is not a legal type.
4909 ShOps[1] = DAG.getConstant(0, MVT::i32);
4910 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4911 EVT DestVT = TLI.getValueType(I.getType());
4912 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4913 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4914 DAG.getConstant(NewIntrinsic, MVT::i32),
4915 getValue(I.getArgOperand(0)), ShAmt);
4919 case Intrinsic::convertff:
4920 case Intrinsic::convertfsi:
4921 case Intrinsic::convertfui:
4922 case Intrinsic::convertsif:
4923 case Intrinsic::convertuif:
4924 case Intrinsic::convertss:
4925 case Intrinsic::convertsu:
4926 case Intrinsic::convertus:
4927 case Intrinsic::convertuu: {
4928 ISD::CvtCode Code = ISD::CVT_INVALID;
4929 switch (Intrinsic) {
4930 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4931 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4932 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4933 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4934 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4935 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4936 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4937 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4938 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4939 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4941 EVT DestVT = TLI.getValueType(I.getType());
4942 const Value *Op1 = I.getArgOperand(0);
4943 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4944 DAG.getValueType(DestVT),
4945 DAG.getValueType(getValue(Op1).getValueType()),
4946 getValue(I.getArgOperand(1)),
4947 getValue(I.getArgOperand(2)),
4952 case Intrinsic::powi:
4953 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4954 getValue(I.getArgOperand(1)), DAG));
4956 case Intrinsic::log:
4957 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4959 case Intrinsic::log2:
4960 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4962 case Intrinsic::log10:
4963 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4965 case Intrinsic::exp:
4966 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4968 case Intrinsic::exp2:
4969 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4971 case Intrinsic::pow:
4972 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4973 getValue(I.getArgOperand(1)), DAG, TLI));
4975 case Intrinsic::sqrt:
4976 case Intrinsic::fabs:
4977 case Intrinsic::sin:
4978 case Intrinsic::cos:
4979 case Intrinsic::floor:
4980 case Intrinsic::ceil:
4981 case Intrinsic::trunc:
4982 case Intrinsic::rint:
4983 case Intrinsic::nearbyint:
4984 case Intrinsic::round: {
4986 switch (Intrinsic) {
4987 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4988 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4989 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4990 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4991 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4992 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4993 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4994 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4995 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4996 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4997 case Intrinsic::round: Opcode = ISD::FROUND; break;
5000 setValue(&I, DAG.getNode(Opcode, sdl,
5001 getValue(I.getArgOperand(0)).getValueType(),
5002 getValue(I.getArgOperand(0))));
5005 case Intrinsic::minnum:
5006 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5007 getValue(I.getArgOperand(0)).getValueType(),
5008 getValue(I.getArgOperand(0)),
5009 getValue(I.getArgOperand(1))));
5011 case Intrinsic::maxnum:
5012 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5013 getValue(I.getArgOperand(0)).getValueType(),
5014 getValue(I.getArgOperand(0)),
5015 getValue(I.getArgOperand(1))));
5017 case Intrinsic::copysign:
5018 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5019 getValue(I.getArgOperand(0)).getValueType(),
5020 getValue(I.getArgOperand(0)),
5021 getValue(I.getArgOperand(1))));
5023 case Intrinsic::fma:
5024 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5025 getValue(I.getArgOperand(0)).getValueType(),
5026 getValue(I.getArgOperand(0)),
5027 getValue(I.getArgOperand(1)),
5028 getValue(I.getArgOperand(2))));
5030 case Intrinsic::fmuladd: {
5031 EVT VT = TLI.getValueType(I.getType());
5032 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5033 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5034 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5035 getValue(I.getArgOperand(0)).getValueType(),
5036 getValue(I.getArgOperand(0)),
5037 getValue(I.getArgOperand(1)),
5038 getValue(I.getArgOperand(2))));
5040 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5041 getValue(I.getArgOperand(0)).getValueType(),
5042 getValue(I.getArgOperand(0)),
5043 getValue(I.getArgOperand(1)));
5044 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5045 getValue(I.getArgOperand(0)).getValueType(),
5047 getValue(I.getArgOperand(2)));
5052 case Intrinsic::convert_to_fp16:
5053 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5054 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5055 getValue(I.getArgOperand(0)),
5056 DAG.getTargetConstant(0, MVT::i32))));
5058 case Intrinsic::convert_from_fp16:
5060 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5061 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5062 getValue(I.getArgOperand(0)))));
5064 case Intrinsic::pcmarker: {
5065 SDValue Tmp = getValue(I.getArgOperand(0));
5066 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5069 case Intrinsic::readcyclecounter: {
5070 SDValue Op = getRoot();
5071 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5072 DAG.getVTList(MVT::i64, MVT::Other), Op);
5074 DAG.setRoot(Res.getValue(1));
5077 case Intrinsic::bswap:
5078 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5079 getValue(I.getArgOperand(0)).getValueType(),
5080 getValue(I.getArgOperand(0))));
5082 case Intrinsic::cttz: {
5083 SDValue Arg = getValue(I.getArgOperand(0));
5084 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5085 EVT Ty = Arg.getValueType();
5086 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5090 case Intrinsic::ctlz: {
5091 SDValue Arg = getValue(I.getArgOperand(0));
5092 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5093 EVT Ty = Arg.getValueType();
5094 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5098 case Intrinsic::ctpop: {
5099 SDValue Arg = getValue(I.getArgOperand(0));
5100 EVT Ty = Arg.getValueType();
5101 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5104 case Intrinsic::stacksave: {
5105 SDValue Op = getRoot();
5106 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5107 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5109 DAG.setRoot(Res.getValue(1));
5112 case Intrinsic::stackrestore: {
5113 Res = getValue(I.getArgOperand(0));
5114 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5117 case Intrinsic::stackprotector: {
5118 // Emit code into the DAG to store the stack guard onto the stack.
5119 MachineFunction &MF = DAG.getMachineFunction();
5120 MachineFrameInfo *MFI = MF.getFrameInfo();
5121 EVT PtrTy = TLI.getPointerTy();
5122 SDValue Src, Chain = getRoot();
5123 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5124 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5126 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5127 // global variable __stack_chk_guard.
5129 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5130 if (BC->getOpcode() == Instruction::BitCast)
5131 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5133 if (GV && TLI.useLoadStackGuardNode()) {
5134 // Emit a LOAD_STACK_GUARD node.
5135 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5137 MachinePointerInfo MPInfo(GV);
5138 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5139 unsigned Flags = MachineMemOperand::MOLoad |
5140 MachineMemOperand::MOInvariant;
5141 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5142 PtrTy.getSizeInBits() / 8,
5143 DAG.getEVTAlignment(PtrTy));
5144 Node->setMemRefs(MemRefs, MemRefs + 1);
5146 // Copy the guard value to a virtual register so that it can be
5147 // retrieved in the epilogue.
5148 Src = SDValue(Node, 0);
5149 const TargetRegisterClass *RC =
5150 TLI.getRegClassFor(Src.getSimpleValueType());
5151 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5153 SPDescriptor.setGuardReg(Reg);
5154 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5156 Src = getValue(I.getArgOperand(0)); // The guard's value.
5159 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5161 int FI = FuncInfo.StaticAllocaMap[Slot];
5162 MFI->setStackProtectorIndex(FI);
5164 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5166 // Store the stack protector onto the stack.
5167 Res = DAG.getStore(Chain, sdl, Src, FIN,
5168 MachinePointerInfo::getFixedStack(FI),
5174 case Intrinsic::objectsize: {
5175 // If we don't know by now, we're never going to know.
5176 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5178 assert(CI && "Non-constant type in __builtin_object_size?");
5180 SDValue Arg = getValue(I.getCalledValue());
5181 EVT Ty = Arg.getValueType();
5184 Res = DAG.getConstant(-1ULL, Ty);
5186 Res = DAG.getConstant(0, Ty);
5191 case Intrinsic::annotation:
5192 case Intrinsic::ptr_annotation:
5193 // Drop the intrinsic, but forward the value
5194 setValue(&I, getValue(I.getOperand(0)));
5196 case Intrinsic::assume:
5197 case Intrinsic::var_annotation:
5198 // Discard annotate attributes and assumptions
5201 case Intrinsic::init_trampoline: {
5202 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5206 Ops[1] = getValue(I.getArgOperand(0));
5207 Ops[2] = getValue(I.getArgOperand(1));
5208 Ops[3] = getValue(I.getArgOperand(2));
5209 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5210 Ops[5] = DAG.getSrcValue(F);
5212 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5217 case Intrinsic::adjust_trampoline: {
5218 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5220 getValue(I.getArgOperand(0))));
5223 case Intrinsic::gcroot:
5225 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5226 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5228 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5229 GFI->addStackRoot(FI->getIndex(), TypeMap);
5232 case Intrinsic::gcread:
5233 case Intrinsic::gcwrite:
5234 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5235 case Intrinsic::flt_rounds:
5236 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5239 case Intrinsic::expect: {
5240 // Just replace __builtin_expect(exp, c) with EXP.
5241 setValue(&I, getValue(I.getArgOperand(0)));
5245 case Intrinsic::debugtrap:
5246 case Intrinsic::trap: {
5247 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5248 if (TrapFuncName.empty()) {
5249 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5250 ISD::TRAP : ISD::DEBUGTRAP;
5251 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5254 TargetLowering::ArgListTy Args;
5256 TargetLowering::CallLoweringInfo CLI(DAG);
5257 CLI.setDebugLoc(sdl).setChain(getRoot())
5258 .setCallee(CallingConv::C, I.getType(),
5259 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5260 std::move(Args), 0);
5262 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5263 DAG.setRoot(Result.second);
5267 case Intrinsic::uadd_with_overflow:
5268 case Intrinsic::sadd_with_overflow:
5269 case Intrinsic::usub_with_overflow:
5270 case Intrinsic::ssub_with_overflow:
5271 case Intrinsic::umul_with_overflow:
5272 case Intrinsic::smul_with_overflow: {
5274 switch (Intrinsic) {
5275 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5276 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5277 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5278 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5279 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5280 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5281 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5283 SDValue Op1 = getValue(I.getArgOperand(0));
5284 SDValue Op2 = getValue(I.getArgOperand(1));
5286 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5287 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5290 case Intrinsic::prefetch: {
5292 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5294 Ops[1] = getValue(I.getArgOperand(0));
5295 Ops[2] = getValue(I.getArgOperand(1));
5296 Ops[3] = getValue(I.getArgOperand(2));
5297 Ops[4] = getValue(I.getArgOperand(3));
5298 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5299 DAG.getVTList(MVT::Other), Ops,
5300 EVT::getIntegerVT(*Context, 8),
5301 MachinePointerInfo(I.getArgOperand(0)),
5303 false, /* volatile */
5305 rw==1)); /* write */
5308 case Intrinsic::lifetime_start:
5309 case Intrinsic::lifetime_end: {
5310 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5311 // Stack coloring is not enabled in O0, discard region information.
5312 if (TM.getOptLevel() == CodeGenOpt::None)
5315 SmallVector<Value *, 4> Allocas;
5316 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5318 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5319 E = Allocas.end(); Object != E; ++Object) {
5320 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5322 // Could not find an Alloca.
5323 if (!LifetimeObject)
5326 // First check that the Alloca is static, otherwise it won't have a
5327 // valid frame index.
5328 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5329 if (SI == FuncInfo.StaticAllocaMap.end())
5332 int FI = SI->second;
5336 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5337 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5339 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5344 case Intrinsic::invariant_start:
5345 // Discard region information.
5346 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5348 case Intrinsic::invariant_end:
5349 // Discard region information.
5351 case Intrinsic::stackprotectorcheck: {
5352 // Do not actually emit anything for this basic block. Instead we initialize
5353 // the stack protector descriptor and export the guard variable so we can
5354 // access it in FinishBasicBlock.
5355 const BasicBlock *BB = I.getParent();
5356 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5357 ExportFromCurrentBlock(SPDescriptor.getGuard());
5359 // Flush our exports since we are going to process a terminator.
5360 (void)getControlRoot();
5363 case Intrinsic::clear_cache:
5364 return TLI.getClearCacheBuiltinName();
5365 case Intrinsic::donothing:
5368 case Intrinsic::experimental_stackmap: {
5372 case Intrinsic::experimental_patchpoint_void:
5373 case Intrinsic::experimental_patchpoint_i64: {
5374 visitPatchpoint(&I);
5377 case Intrinsic::experimental_gc_statepoint: {
5381 case Intrinsic::experimental_gc_result_int:
5382 case Intrinsic::experimental_gc_result_float:
5383 case Intrinsic::experimental_gc_result_ptr:
5384 case Intrinsic::experimental_gc_result: {
5388 case Intrinsic::experimental_gc_relocate: {
5392 case Intrinsic::instrprof_increment:
5393 llvm_unreachable("instrprof failed to lower an increment");
5395 case Intrinsic::frameescape: {
5396 MachineFunction &MF = DAG.getMachineFunction();
5397 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5399 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
5400 // is the same on all targets.
5401 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5403 cast<AllocaInst>(I.getArgOperand(Idx)->stripPointerCasts());
5404 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5405 "can only escape static allocas");
5406 int FI = FuncInfo.StaticAllocaMap[Slot];
5407 MCSymbol *FrameAllocSym =
5408 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(MF.getName(),
5410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5411 TII->get(TargetOpcode::FRAME_ALLOC))
5412 .addSym(FrameAllocSym)
5419 case Intrinsic::framerecover: {
5420 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
5421 MachineFunction &MF = DAG.getMachineFunction();
5422 MVT PtrVT = TLI.getPointerTy(0);
5424 // Get the symbol that defines the frame offset.
5425 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5426 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5427 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5428 MCSymbol *FrameAllocSym =
5429 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(Fn->getName(),
5432 // Create a TargetExternalSymbol for the label to avoid any target lowering
5433 // that would make this PC relative.
5434 StringRef Name = FrameAllocSym->getName();
5435 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
5436 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5438 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5440 // Add the offset to the FP.
5441 Value *FP = I.getArgOperand(1);
5442 SDValue FPVal = getValue(FP);
5443 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5448 case Intrinsic::eh_begincatch:
5449 case Intrinsic::eh_endcatch:
5450 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5454 std::pair<SDValue, SDValue>
5455 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5456 MachineBasicBlock *LandingPad) {
5457 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5458 MCSymbol *BeginLabel = nullptr;
5461 // Insert a label before the invoke call to mark the try range. This can be
5462 // used to detect deletion of the invoke via the MachineModuleInfo.
5463 BeginLabel = MMI.getContext().CreateTempSymbol();
5465 // For SjLj, keep track of which landing pads go with which invokes
5466 // so as to maintain the ordering of pads in the LSDA.
5467 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5468 if (CallSiteIndex) {
5469 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5470 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5472 // Now that the call site is handled, stop tracking it.
5473 MMI.setCurrentCallSite(0);
5476 // Both PendingLoads and PendingExports must be flushed here;
5477 // this call might not return.
5479 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5481 CLI.setChain(getRoot());
5483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5484 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5486 assert((CLI.IsTailCall || Result.second.getNode()) &&
5487 "Non-null chain expected with non-tail call!");
5488 assert((Result.second.getNode() || !Result.first.getNode()) &&
5489 "Null value expected with tail call!");
5491 if (!Result.second.getNode()) {
5492 // As a special case, a null chain means that a tail call has been emitted
5493 // and the DAG root is already updated.
5496 // Since there's no actual continuation from this block, nothing can be
5497 // relying on us setting vregs for them.
5498 PendingExports.clear();
5500 DAG.setRoot(Result.second);
5504 // Insert a label at the end of the invoke call to mark the try range. This
5505 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5506 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5507 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5509 // Inform MachineModuleInfo of range.
5510 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5516 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5518 MachineBasicBlock *LandingPad) {
5519 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5520 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5521 Type *RetTy = FTy->getReturnType();
5523 TargetLowering::ArgListTy Args;
5524 TargetLowering::ArgListEntry Entry;
5525 Args.reserve(CS.arg_size());
5527 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5529 const Value *V = *i;
5532 if (V->getType()->isEmptyTy())
5535 SDValue ArgNode = getValue(V);
5536 Entry.Node = ArgNode; Entry.Ty = V->getType();
5538 // Skip the first return-type Attribute to get to params.
5539 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5540 Args.push_back(Entry);
5543 // Check if target-independent constraints permit a tail call here.
5544 // Target-dependent constraints are checked within TLI->LowerCallTo.
5545 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5548 TargetLowering::CallLoweringInfo CLI(DAG);
5549 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5550 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5551 .setTailCall(isTailCall);
5552 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5554 if (Result.first.getNode())
5555 setValue(CS.getInstruction(), Result.first);
5558 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5559 /// value is equal or not-equal to zero.
5560 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5561 for (const User *U : V->users()) {
5562 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5563 if (IC->isEquality())
5564 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5565 if (C->isNullValue())
5567 // Unknown instruction.
5573 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5575 SelectionDAGBuilder &Builder) {
5577 // Check to see if this load can be trivially constant folded, e.g. if the
5578 // input is from a string literal.
5579 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5580 // Cast pointer to the type we really want to load.
5581 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5582 PointerType::getUnqual(LoadTy));
5584 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5585 const_cast<Constant *>(LoadInput), *Builder.DL))
5586 return Builder.getValue(LoadCst);
5589 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5590 // still constant memory, the input chain can be the entry node.
5592 bool ConstantMemory = false;
5594 // Do not serialize (non-volatile) loads of constant memory with anything.
5595 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5596 Root = Builder.DAG.getEntryNode();
5597 ConstantMemory = true;
5599 // Do not serialize non-volatile loads against each other.
5600 Root = Builder.DAG.getRoot();
5603 SDValue Ptr = Builder.getValue(PtrVal);
5604 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5605 Ptr, MachinePointerInfo(PtrVal),
5607 false /*nontemporal*/,
5608 false /*isinvariant*/, 1 /* align=1 */);
5610 if (!ConstantMemory)
5611 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5615 /// processIntegerCallValue - Record the value for an instruction that
5616 /// produces an integer result, converting the type where necessary.
5617 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5620 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5622 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5624 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5625 setValue(&I, Value);
5628 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5629 /// If so, return true and lower it, otherwise return false and it will be
5630 /// lowered like a normal call.
5631 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5632 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5633 if (I.getNumArgOperands() != 3)
5636 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5637 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5638 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5639 !I.getType()->isIntegerTy())
5642 const Value *Size = I.getArgOperand(2);
5643 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5644 if (CSize && CSize->getZExtValue() == 0) {
5645 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5646 setValue(&I, DAG.getConstant(0, CallVT));
5650 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5651 std::pair<SDValue, SDValue> Res =
5652 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5653 getValue(LHS), getValue(RHS), getValue(Size),
5654 MachinePointerInfo(LHS),
5655 MachinePointerInfo(RHS));
5656 if (Res.first.getNode()) {
5657 processIntegerCallValue(I, Res.first, true);
5658 PendingLoads.push_back(Res.second);
5662 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5663 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5664 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5665 bool ActuallyDoIt = true;
5668 switch (CSize->getZExtValue()) {
5670 LoadVT = MVT::Other;
5672 ActuallyDoIt = false;
5676 LoadTy = Type::getInt16Ty(CSize->getContext());
5680 LoadTy = Type::getInt32Ty(CSize->getContext());
5684 LoadTy = Type::getInt64Ty(CSize->getContext());
5688 LoadVT = MVT::v4i32;
5689 LoadTy = Type::getInt32Ty(CSize->getContext());
5690 LoadTy = VectorType::get(LoadTy, 4);
5695 // This turns into unaligned loads. We only do this if the target natively
5696 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5697 // we'll only produce a small number of byte loads.
5699 // Require that we can find a legal MVT, and only do this if the target
5700 // supports unaligned loads of that type. Expanding into byte loads would
5702 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5703 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5704 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5705 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5706 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5707 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5708 // TODO: Check alignment of src and dest ptrs.
5709 if (!TLI.isTypeLegal(LoadVT) ||
5710 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5711 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5712 ActuallyDoIt = false;
5716 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5717 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5719 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5721 processIntegerCallValue(I, Res, false);
5730 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5731 /// form. If so, return true and lower it, otherwise return false and it
5732 /// will be lowered like a normal call.
5733 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5734 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5735 if (I.getNumArgOperands() != 3)
5738 const Value *Src = I.getArgOperand(0);
5739 const Value *Char = I.getArgOperand(1);
5740 const Value *Length = I.getArgOperand(2);
5741 if (!Src->getType()->isPointerTy() ||
5742 !Char->getType()->isIntegerTy() ||
5743 !Length->getType()->isIntegerTy() ||
5744 !I.getType()->isPointerTy())
5747 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5748 std::pair<SDValue, SDValue> Res =
5749 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5750 getValue(Src), getValue(Char), getValue(Length),
5751 MachinePointerInfo(Src));
5752 if (Res.first.getNode()) {
5753 setValue(&I, Res.first);
5754 PendingLoads.push_back(Res.second);
5761 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5762 /// optimized form. If so, return true and lower it, otherwise return false
5763 /// and it will be lowered like a normal call.
5764 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5765 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5766 if (I.getNumArgOperands() != 2)
5769 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5770 if (!Arg0->getType()->isPointerTy() ||
5771 !Arg1->getType()->isPointerTy() ||
5772 !I.getType()->isPointerTy())
5775 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5776 std::pair<SDValue, SDValue> Res =
5777 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5778 getValue(Arg0), getValue(Arg1),
5779 MachinePointerInfo(Arg0),
5780 MachinePointerInfo(Arg1), isStpcpy);
5781 if (Res.first.getNode()) {
5782 setValue(&I, Res.first);
5783 DAG.setRoot(Res.second);
5790 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5791 /// If so, return true and lower it, otherwise return false and it will be
5792 /// lowered like a normal call.
5793 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5794 // Verify that the prototype makes sense. int strcmp(void*,void*)
5795 if (I.getNumArgOperands() != 2)
5798 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5799 if (!Arg0->getType()->isPointerTy() ||
5800 !Arg1->getType()->isPointerTy() ||
5801 !I.getType()->isIntegerTy())
5804 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5805 std::pair<SDValue, SDValue> Res =
5806 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5807 getValue(Arg0), getValue(Arg1),
5808 MachinePointerInfo(Arg0),
5809 MachinePointerInfo(Arg1));
5810 if (Res.first.getNode()) {
5811 processIntegerCallValue(I, Res.first, true);
5812 PendingLoads.push_back(Res.second);
5819 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5820 /// form. If so, return true and lower it, otherwise return false and it
5821 /// will be lowered like a normal call.
5822 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5823 // Verify that the prototype makes sense. size_t strlen(char *)
5824 if (I.getNumArgOperands() != 1)
5827 const Value *Arg0 = I.getArgOperand(0);
5828 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5831 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5832 std::pair<SDValue, SDValue> Res =
5833 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5834 getValue(Arg0), MachinePointerInfo(Arg0));
5835 if (Res.first.getNode()) {
5836 processIntegerCallValue(I, Res.first, false);
5837 PendingLoads.push_back(Res.second);
5844 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5845 /// form. If so, return true and lower it, otherwise return false and it
5846 /// will be lowered like a normal call.
5847 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5848 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5849 if (I.getNumArgOperands() != 2)
5852 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5853 if (!Arg0->getType()->isPointerTy() ||
5854 !Arg1->getType()->isIntegerTy() ||
5855 !I.getType()->isIntegerTy())
5858 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5859 std::pair<SDValue, SDValue> Res =
5860 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5861 getValue(Arg0), getValue(Arg1),
5862 MachinePointerInfo(Arg0));
5863 if (Res.first.getNode()) {
5864 processIntegerCallValue(I, Res.first, false);
5865 PendingLoads.push_back(Res.second);
5872 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5873 /// operation (as expected), translate it to an SDNode with the specified opcode
5874 /// and return true.
5875 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5877 // Sanity check that it really is a unary floating-point call.
5878 if (I.getNumArgOperands() != 1 ||
5879 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5880 I.getType() != I.getArgOperand(0)->getType() ||
5881 !I.onlyReadsMemory())
5884 SDValue Tmp = getValue(I.getArgOperand(0));
5885 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5889 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5890 /// operation (as expected), translate it to an SDNode with the specified opcode
5891 /// and return true.
5892 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5894 // Sanity check that it really is a binary floating-point call.
5895 if (I.getNumArgOperands() != 2 ||
5896 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5897 I.getType() != I.getArgOperand(0)->getType() ||
5898 I.getType() != I.getArgOperand(1)->getType() ||
5899 !I.onlyReadsMemory())
5902 SDValue Tmp0 = getValue(I.getArgOperand(0));
5903 SDValue Tmp1 = getValue(I.getArgOperand(1));
5904 EVT VT = Tmp0.getValueType();
5905 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5909 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5910 // Handle inline assembly differently.
5911 if (isa<InlineAsm>(I.getCalledValue())) {
5916 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5917 ComputeUsesVAFloatArgument(I, &MMI);
5919 const char *RenameFn = nullptr;
5920 if (Function *F = I.getCalledFunction()) {
5921 if (F->isDeclaration()) {
5922 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5923 if (unsigned IID = II->getIntrinsicID(F)) {
5924 RenameFn = visitIntrinsicCall(I, IID);
5929 if (unsigned IID = F->getIntrinsicID()) {
5930 RenameFn = visitIntrinsicCall(I, IID);
5936 // Check for well-known libc/libm calls. If the function is internal, it
5937 // can't be a library call.
5939 if (!F->hasLocalLinkage() && F->hasName() &&
5940 LibInfo->getLibFunc(F->getName(), Func) &&
5941 LibInfo->hasOptimizedCodeGen(Func)) {
5944 case LibFunc::copysign:
5945 case LibFunc::copysignf:
5946 case LibFunc::copysignl:
5947 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5948 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5949 I.getType() == I.getArgOperand(0)->getType() &&
5950 I.getType() == I.getArgOperand(1)->getType() &&
5951 I.onlyReadsMemory()) {
5952 SDValue LHS = getValue(I.getArgOperand(0));
5953 SDValue RHS = getValue(I.getArgOperand(1));
5954 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5955 LHS.getValueType(), LHS, RHS));
5960 case LibFunc::fabsf:
5961 case LibFunc::fabsl:
5962 if (visitUnaryFloatCall(I, ISD::FABS))
5966 case LibFunc::fminf:
5967 case LibFunc::fminl:
5968 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5972 case LibFunc::fmaxf:
5973 case LibFunc::fmaxl:
5974 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5980 if (visitUnaryFloatCall(I, ISD::FSIN))
5986 if (visitUnaryFloatCall(I, ISD::FCOS))
5990 case LibFunc::sqrtf:
5991 case LibFunc::sqrtl:
5992 case LibFunc::sqrt_finite:
5993 case LibFunc::sqrtf_finite:
5994 case LibFunc::sqrtl_finite:
5995 if (visitUnaryFloatCall(I, ISD::FSQRT))
5998 case LibFunc::floor:
5999 case LibFunc::floorf:
6000 case LibFunc::floorl:
6001 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6004 case LibFunc::nearbyint:
6005 case LibFunc::nearbyintf:
6006 case LibFunc::nearbyintl:
6007 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6011 case LibFunc::ceilf:
6012 case LibFunc::ceill:
6013 if (visitUnaryFloatCall(I, ISD::FCEIL))
6017 case LibFunc::rintf:
6018 case LibFunc::rintl:
6019 if (visitUnaryFloatCall(I, ISD::FRINT))
6022 case LibFunc::round:
6023 case LibFunc::roundf:
6024 case LibFunc::roundl:
6025 if (visitUnaryFloatCall(I, ISD::FROUND))
6028 case LibFunc::trunc:
6029 case LibFunc::truncf:
6030 case LibFunc::truncl:
6031 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6035 case LibFunc::log2f:
6036 case LibFunc::log2l:
6037 if (visitUnaryFloatCall(I, ISD::FLOG2))
6041 case LibFunc::exp2f:
6042 case LibFunc::exp2l:
6043 if (visitUnaryFloatCall(I, ISD::FEXP2))
6046 case LibFunc::memcmp:
6047 if (visitMemCmpCall(I))
6050 case LibFunc::memchr:
6051 if (visitMemChrCall(I))
6054 case LibFunc::strcpy:
6055 if (visitStrCpyCall(I, false))
6058 case LibFunc::stpcpy:
6059 if (visitStrCpyCall(I, true))
6062 case LibFunc::strcmp:
6063 if (visitStrCmpCall(I))
6066 case LibFunc::strlen:
6067 if (visitStrLenCall(I))
6070 case LibFunc::strnlen:
6071 if (visitStrNLenCall(I))
6080 Callee = getValue(I.getCalledValue());
6082 Callee = DAG.getExternalSymbol(RenameFn,
6083 DAG.getTargetLoweringInfo().getPointerTy());
6085 // Check if we can potentially perform a tail call. More detailed checking is
6086 // be done within LowerCallTo, after more information about the call is known.
6087 LowerCallTo(&I, Callee, I.isTailCall());
6092 /// AsmOperandInfo - This contains information for each constraint that we are
6094 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6096 /// CallOperand - If this is the result output operand or a clobber
6097 /// this is null, otherwise it is the incoming operand to the CallInst.
6098 /// This gets modified as the asm is processed.
6099 SDValue CallOperand;
6101 /// AssignedRegs - If this is a register or register class operand, this
6102 /// contains the set of register corresponding to the operand.
6103 RegsForValue AssignedRegs;
6105 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6106 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6109 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6110 /// corresponds to. If there is no Value* for this operand, it returns
6112 EVT getCallOperandValEVT(LLVMContext &Context,
6113 const TargetLowering &TLI,
6114 const DataLayout *DL) const {
6115 if (!CallOperandVal) return MVT::Other;
6117 if (isa<BasicBlock>(CallOperandVal))
6118 return TLI.getPointerTy();
6120 llvm::Type *OpTy = CallOperandVal->getType();
6122 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6123 // If this is an indirect operand, the operand is a pointer to the
6126 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6128 report_fatal_error("Indirect operand for inline asm not a pointer!");
6129 OpTy = PtrTy->getElementType();
6132 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6133 if (StructType *STy = dyn_cast<StructType>(OpTy))
6134 if (STy->getNumElements() == 1)
6135 OpTy = STy->getElementType(0);
6137 // If OpTy is not a single value, it may be a struct/union that we
6138 // can tile with integers.
6139 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6140 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6149 OpTy = IntegerType::get(Context, BitSize);
6154 return TLI.getValueType(OpTy, true);
6158 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6160 } // end anonymous namespace
6162 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6163 /// specified operand. We prefer to assign virtual registers, to allow the
6164 /// register allocator to handle the assignment process. However, if the asm
6165 /// uses features that we can't model on machineinstrs, we have SDISel do the
6166 /// allocation. This produces generally horrible, but correct, code.
6168 /// OpInfo describes the operand.
6170 static void GetRegistersForValue(SelectionDAG &DAG,
6171 const TargetLowering &TLI,
6173 SDISelAsmOperandInfo &OpInfo) {
6174 LLVMContext &Context = *DAG.getContext();
6176 MachineFunction &MF = DAG.getMachineFunction();
6177 SmallVector<unsigned, 4> Regs;
6179 // If this is a constraint for a single physreg, or a constraint for a
6180 // register class, find it.
6181 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6182 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6183 OpInfo.ConstraintCode,
6184 OpInfo.ConstraintVT);
6186 unsigned NumRegs = 1;
6187 if (OpInfo.ConstraintVT != MVT::Other) {
6188 // If this is a FP input in an integer register (or visa versa) insert a bit
6189 // cast of the input value. More generally, handle any case where the input
6190 // value disagrees with the register class we plan to stick this in.
6191 if (OpInfo.Type == InlineAsm::isInput &&
6192 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6193 // Try to convert to the first EVT that the reg class contains. If the
6194 // types are identical size, use a bitcast to convert (e.g. two differing
6196 MVT RegVT = *PhysReg.second->vt_begin();
6197 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6198 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6199 RegVT, OpInfo.CallOperand);
6200 OpInfo.ConstraintVT = RegVT;
6201 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6202 // If the input is a FP value and we want it in FP registers, do a
6203 // bitcast to the corresponding integer type. This turns an f64 value
6204 // into i64, which can be passed with two i32 values on a 32-bit
6206 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6207 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6208 RegVT, OpInfo.CallOperand);
6209 OpInfo.ConstraintVT = RegVT;
6213 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6217 EVT ValueVT = OpInfo.ConstraintVT;
6219 // If this is a constraint for a specific physical register, like {r17},
6221 if (unsigned AssignedReg = PhysReg.first) {
6222 const TargetRegisterClass *RC = PhysReg.second;
6223 if (OpInfo.ConstraintVT == MVT::Other)
6224 ValueVT = *RC->vt_begin();
6226 // Get the actual register value type. This is important, because the user
6227 // may have asked for (e.g.) the AX register in i32 type. We need to
6228 // remember that AX is actually i16 to get the right extension.
6229 RegVT = *RC->vt_begin();
6231 // This is a explicit reference to a physical register.
6232 Regs.push_back(AssignedReg);
6234 // If this is an expanded reference, add the rest of the regs to Regs.
6236 TargetRegisterClass::iterator I = RC->begin();
6237 for (; *I != AssignedReg; ++I)
6238 assert(I != RC->end() && "Didn't find reg!");
6240 // Already added the first reg.
6242 for (; NumRegs; --NumRegs, ++I) {
6243 assert(I != RC->end() && "Ran out of registers to allocate!");
6248 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6252 // Otherwise, if this was a reference to an LLVM register class, create vregs
6253 // for this reference.
6254 if (const TargetRegisterClass *RC = PhysReg.second) {
6255 RegVT = *RC->vt_begin();
6256 if (OpInfo.ConstraintVT == MVT::Other)
6259 // Create the appropriate number of virtual registers.
6260 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6261 for (; NumRegs; --NumRegs)
6262 Regs.push_back(RegInfo.createVirtualRegister(RC));
6264 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6268 // Otherwise, we couldn't allocate enough registers for this.
6271 /// visitInlineAsm - Handle a call to an InlineAsm object.
6273 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6274 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6276 /// ConstraintOperands - Information about all of the constraints.
6277 SDISelAsmOperandInfoVector ConstraintOperands;
6279 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6280 TargetLowering::AsmOperandInfoVector TargetConstraints =
6281 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
6283 bool hasMemory = false;
6285 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6286 unsigned ResNo = 0; // ResNo - The result number of the next output.
6287 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6288 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6289 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6291 MVT OpVT = MVT::Other;
6293 // Compute the value type for each operand.
6294 switch (OpInfo.Type) {
6295 case InlineAsm::isOutput:
6296 // Indirect outputs just consume an argument.
6297 if (OpInfo.isIndirect) {
6298 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6302 // The return value of the call is this value. As such, there is no
6303 // corresponding argument.
6304 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6305 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6306 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6308 assert(ResNo == 0 && "Asm only has one result!");
6309 OpVT = TLI.getSimpleValueType(CS.getType());
6313 case InlineAsm::isInput:
6314 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6316 case InlineAsm::isClobber:
6321 // If this is an input or an indirect output, process the call argument.
6322 // BasicBlocks are labels, currently appearing only in asm's.
6323 if (OpInfo.CallOperandVal) {
6324 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6325 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6327 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6331 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6334 OpInfo.ConstraintVT = OpVT;
6336 // Indirect operand accesses access memory.
6337 if (OpInfo.isIndirect)
6340 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6341 TargetLowering::ConstraintType
6342 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6343 if (CType == TargetLowering::C_Memory) {
6351 SDValue Chain, Flag;
6353 // We won't need to flush pending loads if this asm doesn't touch
6354 // memory and is nonvolatile.
6355 if (hasMemory || IA->hasSideEffects())
6358 Chain = DAG.getRoot();
6360 // Second pass over the constraints: compute which constraint option to use
6361 // and assign registers to constraints that want a specific physreg.
6362 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6363 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6365 // If this is an output operand with a matching input operand, look up the
6366 // matching input. If their types mismatch, e.g. one is an integer, the
6367 // other is floating point, or their sizes are different, flag it as an
6369 if (OpInfo.hasMatchingInput()) {
6370 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6372 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6373 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6374 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6375 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6376 OpInfo.ConstraintVT);
6377 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6378 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6379 Input.ConstraintVT);
6380 if ((OpInfo.ConstraintVT.isInteger() !=
6381 Input.ConstraintVT.isInteger()) ||
6382 (MatchRC.second != InputRC.second)) {
6383 report_fatal_error("Unsupported asm: input constraint"
6384 " with a matching output constraint of"
6385 " incompatible type!");
6387 Input.ConstraintVT = OpInfo.ConstraintVT;
6391 // Compute the constraint code and ConstraintType to use.
6392 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6394 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6395 OpInfo.Type == InlineAsm::isClobber)
6398 // If this is a memory input, and if the operand is not indirect, do what we
6399 // need to to provide an address for the memory input.
6400 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6401 !OpInfo.isIndirect) {
6402 assert((OpInfo.isMultipleAlternative ||
6403 (OpInfo.Type == InlineAsm::isInput)) &&
6404 "Can only indirectify direct input operands!");
6406 // Memory operands really want the address of the value. If we don't have
6407 // an indirect input, put it in the constpool if we can, otherwise spill
6408 // it to a stack slot.
6409 // TODO: This isn't quite right. We need to handle these according to
6410 // the addressing mode that the constraint wants. Also, this may take
6411 // an additional register for the computation and we don't want that
6414 // If the operand is a float, integer, or vector constant, spill to a
6415 // constant pool entry to get its address.
6416 const Value *OpVal = OpInfo.CallOperandVal;
6417 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6418 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6419 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6420 TLI.getPointerTy());
6422 // Otherwise, create a stack slot and emit a store to it before the
6424 Type *Ty = OpVal->getType();
6425 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6426 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6427 MachineFunction &MF = DAG.getMachineFunction();
6428 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6429 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6430 Chain = DAG.getStore(Chain, getCurSDLoc(),
6431 OpInfo.CallOperand, StackSlot,
6432 MachinePointerInfo::getFixedStack(SSFI),
6434 OpInfo.CallOperand = StackSlot;
6437 // There is no longer a Value* corresponding to this operand.
6438 OpInfo.CallOperandVal = nullptr;
6440 // It is now an indirect operand.
6441 OpInfo.isIndirect = true;
6444 // If this constraint is for a specific register, allocate it before
6446 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6447 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6450 // Second pass - Loop over all of the operands, assigning virtual or physregs
6451 // to register class operands.
6452 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6453 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6455 // C_Register operands have already been allocated, Other/Memory don't need
6457 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6458 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6461 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6462 std::vector<SDValue> AsmNodeOperands;
6463 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6464 AsmNodeOperands.push_back(
6465 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6466 TLI.getPointerTy()));
6468 // If we have a !srcloc metadata node associated with it, we want to attach
6469 // this to the ultimately generated inline asm machineinstr. To do this, we
6470 // pass in the third operand as this (potentially null) inline asm MDNode.
6471 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6472 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6474 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6475 // bits as operand 3.
6476 unsigned ExtraInfo = 0;
6477 if (IA->hasSideEffects())
6478 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6479 if (IA->isAlignStack())
6480 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6481 // Set the asm dialect.
6482 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6484 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6485 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6486 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6488 // Compute the constraint code and ConstraintType to use.
6489 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6491 // Ideally, we would only check against memory constraints. However, the
6492 // meaning of an other constraint can be target-specific and we can't easily
6493 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6494 // for other constriants as well.
6495 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6496 OpInfo.ConstraintType == TargetLowering::C_Other) {
6497 if (OpInfo.Type == InlineAsm::isInput)
6498 ExtraInfo |= InlineAsm::Extra_MayLoad;
6499 else if (OpInfo.Type == InlineAsm::isOutput)
6500 ExtraInfo |= InlineAsm::Extra_MayStore;
6501 else if (OpInfo.Type == InlineAsm::isClobber)
6502 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6506 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6507 TLI.getPointerTy()));
6509 // Loop over all of the inputs, copying the operand values into the
6510 // appropriate registers and processing the output regs.
6511 RegsForValue RetValRegs;
6513 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6514 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6516 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6517 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6519 switch (OpInfo.Type) {
6520 case InlineAsm::isOutput: {
6521 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6522 OpInfo.ConstraintType != TargetLowering::C_Register) {
6523 // Memory output, or 'other' output (e.g. 'X' constraint).
6524 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6526 unsigned ConstraintID =
6527 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6528 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6529 "Failed to convert memory constraint code to constraint id.");
6531 // Add information to the INLINEASM node to know about this output.
6532 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6533 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6534 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
6535 AsmNodeOperands.push_back(OpInfo.CallOperand);
6539 // Otherwise, this is a register or register class output.
6541 // Copy the output from the appropriate register. Find a register that
6543 if (OpInfo.AssignedRegs.Regs.empty()) {
6544 LLVMContext &Ctx = *DAG.getContext();
6545 Ctx.emitError(CS.getInstruction(),
6546 "couldn't allocate output register for constraint '" +
6547 Twine(OpInfo.ConstraintCode) + "'");
6551 // If this is an indirect operand, store through the pointer after the
6553 if (OpInfo.isIndirect) {
6554 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6555 OpInfo.CallOperandVal));
6557 // This is the result value of the call.
6558 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6559 // Concatenate this output onto the outputs list.
6560 RetValRegs.append(OpInfo.AssignedRegs);
6563 // Add information to the INLINEASM node to know that this register is
6566 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6567 ? InlineAsm::Kind_RegDefEarlyClobber
6568 : InlineAsm::Kind_RegDef,
6569 false, 0, DAG, AsmNodeOperands);
6572 case InlineAsm::isInput: {
6573 SDValue InOperandVal = OpInfo.CallOperand;
6575 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6576 // If this is required to match an output register we have already set,
6577 // just use its register.
6578 unsigned OperandNo = OpInfo.getMatchedOperand();
6580 // Scan until we find the definition we already emitted of this operand.
6581 // When we find it, create a RegsForValue operand.
6582 unsigned CurOp = InlineAsm::Op_FirstOperand;
6583 for (; OperandNo; --OperandNo) {
6584 // Advance to the next operand.
6586 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6587 assert((InlineAsm::isRegDefKind(OpFlag) ||
6588 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6589 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6590 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6594 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6595 if (InlineAsm::isRegDefKind(OpFlag) ||
6596 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6597 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6598 if (OpInfo.isIndirect) {
6599 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6600 LLVMContext &Ctx = *DAG.getContext();
6601 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6602 " don't know how to handle tied "
6603 "indirect register inputs");
6607 RegsForValue MatchedRegs;
6608 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6609 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6610 MatchedRegs.RegVTs.push_back(RegVT);
6611 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6612 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6614 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6615 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6617 LLVMContext &Ctx = *DAG.getContext();
6618 Ctx.emitError(CS.getInstruction(),
6619 "inline asm error: This value"
6620 " type register class is not natively supported!");
6624 // Use the produced MatchedRegs object to
6625 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6626 Chain, &Flag, CS.getInstruction());
6627 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6628 true, OpInfo.getMatchedOperand(),
6629 DAG, AsmNodeOperands);
6633 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6634 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6635 "Unexpected number of operands");
6636 // Add information to the INLINEASM node to know about this input.
6637 // See InlineAsm.h isUseOperandTiedToDef.
6638 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6639 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6640 OpInfo.getMatchedOperand());
6641 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6642 TLI.getPointerTy()));
6643 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6647 // Treat indirect 'X' constraint as memory.
6648 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6650 OpInfo.ConstraintType = TargetLowering::C_Memory;
6652 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6653 std::vector<SDValue> Ops;
6654 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6657 LLVMContext &Ctx = *DAG.getContext();
6658 Ctx.emitError(CS.getInstruction(),
6659 "invalid operand for inline asm constraint '" +
6660 Twine(OpInfo.ConstraintCode) + "'");
6664 // Add information to the INLINEASM node to know about this input.
6665 unsigned ResOpType =
6666 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6667 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6668 TLI.getPointerTy()));
6669 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6673 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6674 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6675 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6676 "Memory operands expect pointer values");
6678 unsigned ConstraintID =
6679 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6680 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6681 "Failed to convert memory constraint code to constraint id.");
6683 // Add information to the INLINEASM node to know about this input.
6684 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6685 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6686 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
6687 AsmNodeOperands.push_back(InOperandVal);
6691 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6692 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6693 "Unknown constraint type!");
6695 // TODO: Support this.
6696 if (OpInfo.isIndirect) {
6697 LLVMContext &Ctx = *DAG.getContext();
6698 Ctx.emitError(CS.getInstruction(),
6699 "Don't know how to handle indirect register inputs yet "
6700 "for constraint '" +
6701 Twine(OpInfo.ConstraintCode) + "'");
6705 // Copy the input into the appropriate registers.
6706 if (OpInfo.AssignedRegs.Regs.empty()) {
6707 LLVMContext &Ctx = *DAG.getContext();
6708 Ctx.emitError(CS.getInstruction(),
6709 "couldn't allocate input reg for constraint '" +
6710 Twine(OpInfo.ConstraintCode) + "'");
6714 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6715 Chain, &Flag, CS.getInstruction());
6717 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6718 DAG, AsmNodeOperands);
6721 case InlineAsm::isClobber: {
6722 // Add the clobbered value to the operand list, so that the register
6723 // allocator is aware that the physreg got clobbered.
6724 if (!OpInfo.AssignedRegs.Regs.empty())
6725 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6733 // Finish up input operands. Set the input chain and add the flag last.
6734 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6735 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6737 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6738 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6739 Flag = Chain.getValue(1);
6741 // If this asm returns a register value, copy the result from that register
6742 // and set it as the value of the call.
6743 if (!RetValRegs.Regs.empty()) {
6744 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6745 Chain, &Flag, CS.getInstruction());
6747 // FIXME: Why don't we do this for inline asms with MRVs?
6748 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6749 EVT ResultType = TLI.getValueType(CS.getType());
6751 // If any of the results of the inline asm is a vector, it may have the
6752 // wrong width/num elts. This can happen for register classes that can
6753 // contain multiple different value types. The preg or vreg allocated may
6754 // not have the same VT as was expected. Convert it to the right type
6755 // with bit_convert.
6756 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6757 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6760 } else if (ResultType != Val.getValueType() &&
6761 ResultType.isInteger() && Val.getValueType().isInteger()) {
6762 // If a result value was tied to an input value, the computed result may
6763 // have a wider width than the expected result. Extract the relevant
6765 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6768 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6771 setValue(CS.getInstruction(), Val);
6772 // Don't need to use this as a chain in this case.
6773 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6777 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6779 // Process indirect outputs, first output all of the flagged copies out of
6781 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6782 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6783 const Value *Ptr = IndirectStoresToEmit[i].second;
6784 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6786 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6789 // Emit the non-flagged stores from the physregs.
6790 SmallVector<SDValue, 8> OutChains;
6791 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6792 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6793 StoresToEmit[i].first,
6794 getValue(StoresToEmit[i].second),
6795 MachinePointerInfo(StoresToEmit[i].second),
6797 OutChains.push_back(Val);
6800 if (!OutChains.empty())
6801 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6806 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6807 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6808 MVT::Other, getRoot(),
6809 getValue(I.getArgOperand(0)),
6810 DAG.getSrcValue(I.getArgOperand(0))));
6813 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6815 const DataLayout &DL = *TLI.getDataLayout();
6816 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6817 getRoot(), getValue(I.getOperand(0)),
6818 DAG.getSrcValue(I.getOperand(0)),
6819 DL.getABITypeAlignment(I.getType()));
6821 DAG.setRoot(V.getValue(1));
6824 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6825 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6826 MVT::Other, getRoot(),
6827 getValue(I.getArgOperand(0)),
6828 DAG.getSrcValue(I.getArgOperand(0))));
6831 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6832 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6833 MVT::Other, getRoot(),
6834 getValue(I.getArgOperand(0)),
6835 getValue(I.getArgOperand(1)),
6836 DAG.getSrcValue(I.getArgOperand(0)),
6837 DAG.getSrcValue(I.getArgOperand(1))));
6840 /// \brief Lower an argument list according to the target calling convention.
6842 /// \return A tuple of <return-value, token-chain>
6844 /// This is a helper for lowering intrinsics that follow a target calling
6845 /// convention or require stack pointer adjustment. Only a subset of the
6846 /// intrinsic's operands need to participate in the calling convention.
6847 std::pair<SDValue, SDValue>
6848 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6849 unsigned NumArgs, SDValue Callee,
6851 MachineBasicBlock *LandingPad,
6852 bool IsPatchPoint) {
6853 TargetLowering::ArgListTy Args;
6854 Args.reserve(NumArgs);
6856 // Populate the argument list.
6857 // Attributes for args start at offset 1, after the return attribute.
6858 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6859 ArgI != ArgE; ++ArgI) {
6860 const Value *V = CS->getOperand(ArgI);
6862 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6864 TargetLowering::ArgListEntry Entry;
6865 Entry.Node = getValue(V);
6866 Entry.Ty = V->getType();
6867 Entry.setAttributes(&CS, AttrI);
6868 Args.push_back(Entry);
6871 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6872 TargetLowering::CallLoweringInfo CLI(DAG);
6873 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6874 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6875 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6877 return lowerInvokable(CLI, LandingPad);
6880 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6881 /// or patchpoint target node's operand list.
6883 /// Constants are converted to TargetConstants purely as an optimization to
6884 /// avoid constant materialization and register allocation.
6886 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6887 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6888 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6889 /// address materialization and register allocation, but may also be required
6890 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6891 /// alloca in the entry block, then the runtime may assume that the alloca's
6892 /// StackMap location can be read immediately after compilation and that the
6893 /// location is valid at any point during execution (this is similar to the
6894 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6895 /// only available in a register, then the runtime would need to trap when
6896 /// execution reaches the StackMap in order to read the alloca's location.
6897 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6898 SmallVectorImpl<SDValue> &Ops,
6899 SelectionDAGBuilder &Builder) {
6900 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6901 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6904 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6906 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6907 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6908 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6910 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6912 Ops.push_back(OpVal);
6916 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6917 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6918 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6919 // [live variables...])
6921 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6923 SDValue Chain, InFlag, Callee, NullPtr;
6924 SmallVector<SDValue, 32> Ops;
6926 SDLoc DL = getCurSDLoc();
6927 Callee = getValue(CI.getCalledValue());
6928 NullPtr = DAG.getIntPtrConstant(0, true);
6930 // The stackmap intrinsic only records the live variables (the arguemnts
6931 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6932 // intrinsic, this won't be lowered to a function call. This means we don't
6933 // have to worry about calling conventions and target specific lowering code.
6934 // Instead we perform the call lowering right here.
6936 // chain, flag = CALLSEQ_START(chain, 0)
6937 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6938 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6940 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6941 InFlag = Chain.getValue(1);
6943 // Add the <id> and <numBytes> constants.
6944 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6945 Ops.push_back(DAG.getTargetConstant(
6946 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6947 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6948 Ops.push_back(DAG.getTargetConstant(
6949 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6951 // Push live variables for the stack map.
6952 addStackMapLiveVars(&CI, 2, Ops, *this);
6954 // We are not pushing any register mask info here on the operands list,
6955 // because the stackmap doesn't clobber anything.
6957 // Push the chain and the glue flag.
6958 Ops.push_back(Chain);
6959 Ops.push_back(InFlag);
6961 // Create the STACKMAP node.
6962 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6963 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6964 Chain = SDValue(SM, 0);
6965 InFlag = Chain.getValue(1);
6967 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6969 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6971 // Set the root to the target-lowered call chain.
6974 // Inform the Frame Information that we have a stackmap in this function.
6975 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6978 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6979 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6980 MachineBasicBlock *LandingPad) {
6981 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6986 // [live variables...])
6988 CallingConv::ID CC = CS.getCallingConv();
6989 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6990 bool HasDef = !CS->getType()->isVoidTy();
6991 SDValue Callee = getValue(CS->getOperand(2)); // <target>
6993 // Get the real number of arguments participating in the call <numArgs>
6994 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6995 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6997 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6998 // Intrinsics include all meta-operands up to but not including CC.
6999 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7000 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7001 "Not enough arguments provided to the patchpoint intrinsic");
7003 // For AnyRegCC the arguments are lowered later on manually.
7004 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7005 std::pair<SDValue, SDValue> Result =
7006 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7009 SDNode *CallEnd = Result.second.getNode();
7010 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7011 CallEnd = CallEnd->getOperand(0).getNode();
7013 /// Get a call instruction from the call sequence chain.
7014 /// Tail calls are not allowed.
7015 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7016 "Expected a callseq node.");
7017 SDNode *Call = CallEnd->getOperand(0).getNode();
7018 bool HasGlue = Call->getGluedNode();
7020 // Replace the target specific call node with the patchable intrinsic.
7021 SmallVector<SDValue, 8> Ops;
7023 // Add the <id> and <numBytes> constants.
7024 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7025 Ops.push_back(DAG.getTargetConstant(
7026 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7027 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7028 Ops.push_back(DAG.getTargetConstant(
7029 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7031 // Assume that the Callee is a constant address.
7032 // FIXME: handle function symbols in the future.
7034 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7035 /*isTarget=*/true));
7037 // Adjust <numArgs> to account for any arguments that have been passed on the
7039 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7040 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7041 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7042 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7044 // Add the calling convention
7045 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7047 // Add the arguments we omitted previously. The register allocator should
7048 // place these in any free register.
7050 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7051 Ops.push_back(getValue(CS.getArgument(i)));
7053 // Push the arguments from the call instruction up to the register mask.
7054 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7055 Ops.append(Call->op_begin() + 2, e);
7057 // Push live variables for the stack map.
7058 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7060 // Push the register mask info.
7062 Ops.push_back(*(Call->op_end()-2));
7064 Ops.push_back(*(Call->op_end()-1));
7066 // Push the chain (this is originally the first operand of the call, but
7067 // becomes now the last or second to last operand).
7068 Ops.push_back(*(Call->op_begin()));
7070 // Push the glue flag (last operand).
7072 Ops.push_back(*(Call->op_end()-1));
7075 if (IsAnyRegCC && HasDef) {
7076 // Create the return types based on the intrinsic definition
7077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7078 SmallVector<EVT, 3> ValueVTs;
7079 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7080 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7082 // There is always a chain and a glue type at the end
7083 ValueVTs.push_back(MVT::Other);
7084 ValueVTs.push_back(MVT::Glue);
7085 NodeTys = DAG.getVTList(ValueVTs);
7087 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7089 // Replace the target specific call node with a PATCHPOINT node.
7090 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7091 getCurSDLoc(), NodeTys, Ops);
7093 // Update the NodeMap.
7096 setValue(CS.getInstruction(), SDValue(MN, 0));
7098 setValue(CS.getInstruction(), Result.first);
7101 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7102 // call sequence. Furthermore the location of the chain and glue can change
7103 // when the AnyReg calling convention is used and the intrinsic returns a
7105 if (IsAnyRegCC && HasDef) {
7106 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7107 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7108 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7110 DAG.ReplaceAllUsesWith(Call, MN);
7111 DAG.DeleteNode(Call);
7113 // Inform the Frame Information that we have a patchpoint in this function.
7114 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7117 /// Returns an AttributeSet representing the attributes applied to the return
7118 /// value of the given call.
7119 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7120 SmallVector<Attribute::AttrKind, 2> Attrs;
7122 Attrs.push_back(Attribute::SExt);
7124 Attrs.push_back(Attribute::ZExt);
7126 Attrs.push_back(Attribute::InReg);
7128 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7132 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7133 /// implementation, which just calls LowerCall.
7134 /// FIXME: When all targets are
7135 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7136 std::pair<SDValue, SDValue>
7137 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7138 // Handle the incoming return values from the call.
7140 Type *OrigRetTy = CLI.RetTy;
7141 SmallVector<EVT, 4> RetTys;
7142 SmallVector<uint64_t, 4> Offsets;
7143 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7145 SmallVector<ISD::OutputArg, 4> Outs;
7146 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7148 bool CanLowerReturn =
7149 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7150 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7152 SDValue DemoteStackSlot;
7153 int DemoteStackIdx = -100;
7154 if (!CanLowerReturn) {
7155 // FIXME: equivalent assert?
7156 // assert(!CS.hasInAllocaArgument() &&
7157 // "sret demotion is incompatible with inalloca");
7158 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7159 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7160 MachineFunction &MF = CLI.DAG.getMachineFunction();
7161 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7162 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7164 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7166 Entry.Node = DemoteStackSlot;
7167 Entry.Ty = StackSlotPtrType;
7168 Entry.isSExt = false;
7169 Entry.isZExt = false;
7170 Entry.isInReg = false;
7171 Entry.isSRet = true;
7172 Entry.isNest = false;
7173 Entry.isByVal = false;
7174 Entry.isReturned = false;
7175 Entry.Alignment = Align;
7176 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7177 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7179 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7181 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7182 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7183 for (unsigned i = 0; i != NumRegs; ++i) {
7184 ISD::InputArg MyFlags;
7185 MyFlags.VT = RegisterVT;
7187 MyFlags.Used = CLI.IsReturnValueUsed;
7189 MyFlags.Flags.setSExt();
7191 MyFlags.Flags.setZExt();
7193 MyFlags.Flags.setInReg();
7194 CLI.Ins.push_back(MyFlags);
7199 // Handle all of the outgoing arguments.
7201 CLI.OutVals.clear();
7202 ArgListTy &Args = CLI.getArgs();
7203 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7204 SmallVector<EVT, 4> ValueVTs;
7205 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7206 Type *FinalType = Args[i].Ty;
7207 if (Args[i].isByVal)
7208 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7209 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7210 FinalType, CLI.CallConv, CLI.IsVarArg);
7211 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7213 EVT VT = ValueVTs[Value];
7214 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7215 SDValue Op = SDValue(Args[i].Node.getNode(),
7216 Args[i].Node.getResNo() + Value);
7217 ISD::ArgFlagsTy Flags;
7218 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7224 if (Args[i].isInReg)
7228 if (Args[i].isByVal)
7230 if (Args[i].isInAlloca) {
7231 Flags.setInAlloca();
7232 // Set the byval flag for CCAssignFn callbacks that don't know about
7233 // inalloca. This way we can know how many bytes we should've allocated
7234 // and how many bytes a callee cleanup function will pop. If we port
7235 // inalloca to more targets, we'll have to add custom inalloca handling
7236 // in the various CC lowering callbacks.
7239 if (Args[i].isByVal || Args[i].isInAlloca) {
7240 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7241 Type *ElementTy = Ty->getElementType();
7242 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7243 // For ByVal, alignment should come from FE. BE will guess if this
7244 // info is not there but there are cases it cannot get right.
7245 unsigned FrameAlign;
7246 if (Args[i].Alignment)
7247 FrameAlign = Args[i].Alignment;
7249 FrameAlign = getByValTypeAlignment(ElementTy);
7250 Flags.setByValAlign(FrameAlign);
7255 Flags.setInConsecutiveRegs();
7256 Flags.setOrigAlign(OriginalAlignment);
7258 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7259 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7260 SmallVector<SDValue, 4> Parts(NumParts);
7261 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7264 ExtendKind = ISD::SIGN_EXTEND;
7265 else if (Args[i].isZExt)
7266 ExtendKind = ISD::ZERO_EXTEND;
7268 // Conservatively only handle 'returned' on non-vectors for now
7269 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7270 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7271 "unexpected use of 'returned'");
7272 // Before passing 'returned' to the target lowering code, ensure that
7273 // either the register MVT and the actual EVT are the same size or that
7274 // the return value and argument are extended in the same way; in these
7275 // cases it's safe to pass the argument register value unchanged as the
7276 // return register value (although it's at the target's option whether
7278 // TODO: allow code generation to take advantage of partially preserved
7279 // registers rather than clobbering the entire register when the
7280 // parameter extension method is not compatible with the return
7282 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7283 (ExtendKind != ISD::ANY_EXTEND &&
7284 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7285 Flags.setReturned();
7288 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7289 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7291 for (unsigned j = 0; j != NumParts; ++j) {
7292 // if it isn't first piece, alignment must be 1
7293 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7294 i < CLI.NumFixedArgs,
7295 i, j*Parts[j].getValueType().getStoreSize());
7296 if (NumParts > 1 && j == 0)
7297 MyFlags.Flags.setSplit();
7299 MyFlags.Flags.setOrigAlign(1);
7301 CLI.Outs.push_back(MyFlags);
7302 CLI.OutVals.push_back(Parts[j]);
7305 if (NeedsRegBlock && Value == NumValues - 1)
7306 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7310 SmallVector<SDValue, 4> InVals;
7311 CLI.Chain = LowerCall(CLI, InVals);
7313 // Verify that the target's LowerCall behaved as expected.
7314 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7315 "LowerCall didn't return a valid chain!");
7316 assert((!CLI.IsTailCall || InVals.empty()) &&
7317 "LowerCall emitted a return value for a tail call!");
7318 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7319 "LowerCall didn't emit the correct number of values!");
7321 // For a tail call, the return value is merely live-out and there aren't
7322 // any nodes in the DAG representing it. Return a special value to
7323 // indicate that a tail call has been emitted and no more Instructions
7324 // should be processed in the current block.
7325 if (CLI.IsTailCall) {
7326 CLI.DAG.setRoot(CLI.Chain);
7327 return std::make_pair(SDValue(), SDValue());
7330 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7331 assert(InVals[i].getNode() &&
7332 "LowerCall emitted a null value!");
7333 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7334 "LowerCall emitted a value with the wrong type!");
7337 SmallVector<SDValue, 4> ReturnValues;
7338 if (!CanLowerReturn) {
7339 // The instruction result is the result of loading from the
7340 // hidden sret parameter.
7341 SmallVector<EVT, 1> PVTs;
7342 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7344 ComputeValueVTs(*this, PtrRetTy, PVTs);
7345 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7346 EVT PtrVT = PVTs[0];
7348 unsigned NumValues = RetTys.size();
7349 ReturnValues.resize(NumValues);
7350 SmallVector<SDValue, 4> Chains(NumValues);
7352 for (unsigned i = 0; i < NumValues; ++i) {
7353 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7354 CLI.DAG.getConstant(Offsets[i], PtrVT));
7355 SDValue L = CLI.DAG.getLoad(
7356 RetTys[i], CLI.DL, CLI.Chain, Add,
7357 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7359 ReturnValues[i] = L;
7360 Chains[i] = L.getValue(1);
7363 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7365 // Collect the legal value parts into potentially illegal values
7366 // that correspond to the original function's return values.
7367 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7369 AssertOp = ISD::AssertSext;
7370 else if (CLI.RetZExt)
7371 AssertOp = ISD::AssertZext;
7372 unsigned CurReg = 0;
7373 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7375 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7376 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7378 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7379 NumRegs, RegisterVT, VT, nullptr,
7384 // For a function returning void, there is no return value. We can't create
7385 // such a node, so we just return a null return value in that case. In
7386 // that case, nothing will actually look at the value.
7387 if (ReturnValues.empty())
7388 return std::make_pair(SDValue(), CLI.Chain);
7391 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7392 CLI.DAG.getVTList(RetTys), ReturnValues);
7393 return std::make_pair(Res, CLI.Chain);
7396 void TargetLowering::LowerOperationWrapper(SDNode *N,
7397 SmallVectorImpl<SDValue> &Results,
7398 SelectionDAG &DAG) const {
7399 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7401 Results.push_back(Res);
7404 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7405 llvm_unreachable("LowerOperation not implemented for this target!");
7409 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7410 SDValue Op = getNonRegisterValue(V);
7411 assert((Op.getOpcode() != ISD::CopyFromReg ||
7412 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7413 "Copy from a reg to the same reg!");
7414 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7417 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7418 SDValue Chain = DAG.getEntryNode();
7420 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7421 FuncInfo.PreferredExtendType.end())
7423 : FuncInfo.PreferredExtendType[V];
7424 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7425 PendingExports.push_back(Chain);
7428 #include "llvm/CodeGen/SelectionDAGISel.h"
7430 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7431 /// entry block, return true. This includes arguments used by switches, since
7432 /// the switch may expand into multiple basic blocks.
7433 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7434 // With FastISel active, we may be splitting blocks, so force creation
7435 // of virtual registers for all non-dead arguments.
7437 return A->use_empty();
7439 const BasicBlock *Entry = A->getParent()->begin();
7440 for (const User *U : A->users())
7441 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7442 return false; // Use not in entry block.
7447 void SelectionDAGISel::LowerArguments(const Function &F) {
7448 SelectionDAG &DAG = SDB->DAG;
7449 SDLoc dl = SDB->getCurSDLoc();
7450 const DataLayout *DL = TLI->getDataLayout();
7451 SmallVector<ISD::InputArg, 16> Ins;
7453 if (!FuncInfo->CanLowerReturn) {
7454 // Put in an sret pointer parameter before all the other parameters.
7455 SmallVector<EVT, 1> ValueVTs;
7456 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7458 // NOTE: Assuming that a pointer will never break down to more than one VT
7460 ISD::ArgFlagsTy Flags;
7462 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7463 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7464 ISD::InputArg::NoArgIndex, 0);
7465 Ins.push_back(RetArg);
7468 // Set up the incoming argument description vector.
7470 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7471 I != E; ++I, ++Idx) {
7472 SmallVector<EVT, 4> ValueVTs;
7473 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7474 bool isArgValueUsed = !I->use_empty();
7475 unsigned PartBase = 0;
7476 Type *FinalType = I->getType();
7477 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7478 FinalType = cast<PointerType>(FinalType)->getElementType();
7479 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7480 FinalType, F.getCallingConv(), F.isVarArg());
7481 for (unsigned Value = 0, NumValues = ValueVTs.size();
7482 Value != NumValues; ++Value) {
7483 EVT VT = ValueVTs[Value];
7484 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7485 ISD::ArgFlagsTy Flags;
7486 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7488 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7490 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7492 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7494 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7496 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7498 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7499 Flags.setInAlloca();
7500 // Set the byval flag for CCAssignFn callbacks that don't know about
7501 // inalloca. This way we can know how many bytes we should've allocated
7502 // and how many bytes a callee cleanup function will pop. If we port
7503 // inalloca to more targets, we'll have to add custom inalloca handling
7504 // in the various CC lowering callbacks.
7507 if (Flags.isByVal() || Flags.isInAlloca()) {
7508 PointerType *Ty = cast<PointerType>(I->getType());
7509 Type *ElementTy = Ty->getElementType();
7510 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7511 // For ByVal, alignment should be passed from FE. BE will guess if
7512 // this info is not there but there are cases it cannot get right.
7513 unsigned FrameAlign;
7514 if (F.getParamAlignment(Idx))
7515 FrameAlign = F.getParamAlignment(Idx);
7517 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7518 Flags.setByValAlign(FrameAlign);
7520 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7523 Flags.setInConsecutiveRegs();
7524 Flags.setOrigAlign(OriginalAlignment);
7526 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7527 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7528 for (unsigned i = 0; i != NumRegs; ++i) {
7529 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7530 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7531 if (NumRegs > 1 && i == 0)
7532 MyFlags.Flags.setSplit();
7533 // if it isn't first piece, alignment must be 1
7535 MyFlags.Flags.setOrigAlign(1);
7536 Ins.push_back(MyFlags);
7538 if (NeedsRegBlock && Value == NumValues - 1)
7539 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7540 PartBase += VT.getStoreSize();
7544 // Call the target to set up the argument values.
7545 SmallVector<SDValue, 8> InVals;
7546 SDValue NewRoot = TLI->LowerFormalArguments(
7547 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7549 // Verify that the target's LowerFormalArguments behaved as expected.
7550 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7551 "LowerFormalArguments didn't return a valid chain!");
7552 assert(InVals.size() == Ins.size() &&
7553 "LowerFormalArguments didn't emit the correct number of values!");
7555 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7556 assert(InVals[i].getNode() &&
7557 "LowerFormalArguments emitted a null value!");
7558 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7559 "LowerFormalArguments emitted a value with the wrong type!");
7563 // Update the DAG with the new chain value resulting from argument lowering.
7564 DAG.setRoot(NewRoot);
7566 // Set up the argument values.
7569 if (!FuncInfo->CanLowerReturn) {
7570 // Create a virtual register for the sret pointer, and put in a copy
7571 // from the sret argument into it.
7572 SmallVector<EVT, 1> ValueVTs;
7573 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7574 MVT VT = ValueVTs[0].getSimpleVT();
7575 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7576 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7577 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7578 RegVT, VT, nullptr, AssertOp);
7580 MachineFunction& MF = SDB->DAG.getMachineFunction();
7581 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7582 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7583 FuncInfo->DemoteRegister = SRetReg;
7585 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7586 DAG.setRoot(NewRoot);
7588 // i indexes lowered arguments. Bump it past the hidden sret argument.
7589 // Idx indexes LLVM arguments. Don't touch it.
7593 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7595 SmallVector<SDValue, 4> ArgValues;
7596 SmallVector<EVT, 4> ValueVTs;
7597 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7598 unsigned NumValues = ValueVTs.size();
7600 // If this argument is unused then remember its value. It is used to generate
7601 // debugging information.
7602 if (I->use_empty() && NumValues) {
7603 SDB->setUnusedArgValue(I, InVals[i]);
7605 // Also remember any frame index for use in FastISel.
7606 if (FrameIndexSDNode *FI =
7607 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7608 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7611 for (unsigned Val = 0; Val != NumValues; ++Val) {
7612 EVT VT = ValueVTs[Val];
7613 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7614 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7616 if (!I->use_empty()) {
7617 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7618 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7619 AssertOp = ISD::AssertSext;
7620 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7621 AssertOp = ISD::AssertZext;
7623 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7624 NumParts, PartVT, VT,
7625 nullptr, AssertOp));
7631 // We don't need to do anything else for unused arguments.
7632 if (ArgValues.empty())
7635 // Note down frame index.
7636 if (FrameIndexSDNode *FI =
7637 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7638 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7640 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7641 SDB->getCurSDLoc());
7643 SDB->setValue(I, Res);
7644 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7645 if (LoadSDNode *LNode =
7646 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7647 if (FrameIndexSDNode *FI =
7648 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7649 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7652 // If this argument is live outside of the entry block, insert a copy from
7653 // wherever we got it to the vreg that other BB's will reference it as.
7654 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7655 // If we can, though, try to skip creating an unnecessary vreg.
7656 // FIXME: This isn't very clean... it would be nice to make this more
7657 // general. It's also subtly incompatible with the hacks FastISel
7659 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7660 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7661 FuncInfo->ValueMap[I] = Reg;
7665 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7666 FuncInfo->InitializeRegForValue(I);
7667 SDB->CopyToExportRegsIfNeeded(I);
7671 assert(i == InVals.size() && "Argument register count mismatch!");
7673 // Finally, if the target has anything special to do, allow it to do so.
7674 EmitFunctionEntryCode();
7677 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7678 /// ensure constants are generated when needed. Remember the virtual registers
7679 /// that need to be added to the Machine PHI nodes as input. We cannot just
7680 /// directly add them, because expansion might result in multiple MBB's for one
7681 /// BB. As such, the start of the BB might correspond to a different MBB than
7685 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7686 const TerminatorInst *TI = LLVMBB->getTerminator();
7688 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7690 // Check PHI nodes in successors that expect a value to be available from this
7692 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7693 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7694 if (!isa<PHINode>(SuccBB->begin())) continue;
7695 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7697 // If this terminator has multiple identical successors (common for
7698 // switches), only handle each succ once.
7699 if (!SuccsHandled.insert(SuccMBB).second)
7702 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7704 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7705 // nodes and Machine PHI nodes, but the incoming operands have not been
7707 for (BasicBlock::const_iterator I = SuccBB->begin();
7708 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7709 // Ignore dead phi's.
7710 if (PN->use_empty()) continue;
7713 if (PN->getType()->isEmptyTy())
7717 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7719 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7720 unsigned &RegOut = ConstantsOut[C];
7722 RegOut = FuncInfo.CreateRegs(C->getType());
7723 CopyValueToVirtualRegister(C, RegOut);
7727 DenseMap<const Value *, unsigned>::iterator I =
7728 FuncInfo.ValueMap.find(PHIOp);
7729 if (I != FuncInfo.ValueMap.end())
7732 assert(isa<AllocaInst>(PHIOp) &&
7733 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7734 "Didn't codegen value into a register!??");
7735 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7736 CopyValueToVirtualRegister(PHIOp, Reg);
7740 // Remember that this register needs to added to the machine PHI node as
7741 // the input for this MBB.
7742 SmallVector<EVT, 4> ValueVTs;
7743 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7744 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7745 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7746 EVT VT = ValueVTs[vti];
7747 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7748 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7749 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7750 Reg += NumRegisters;
7755 ConstantsOut.clear();
7758 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7761 SelectionDAGBuilder::StackProtectorDescriptor::
7762 AddSuccessorMBB(const BasicBlock *BB,
7763 MachineBasicBlock *ParentMBB,
7765 MachineBasicBlock *SuccMBB) {
7766 // If SuccBB has not been created yet, create it.
7768 MachineFunction *MF = ParentMBB->getParent();
7769 MachineFunction::iterator BBI = ParentMBB;
7770 SuccMBB = MF->CreateMachineBasicBlock(BB);
7771 MF->insert(++BBI, SuccMBB);
7773 // Add it as a successor of ParentMBB.
7774 ParentMBB->addSuccessor(
7775 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7779 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7780 MachineFunction::iterator I = MBB;
7781 if (++I == FuncInfo.MF->end())