1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1164 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1165 bool IsSEH = isAsynchronousEHPersonality(Pers);
1166 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1167 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1168 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1169 if (IsMSVCCXX || IsCoreCLR)
1170 CatchPadMBB->setIsEHFuncletEntry();
1172 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1174 // Update machine-CFG edge.
1175 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1177 // CatchPads in SEH are not funclets, they are merely markers which indicate
1178 // where to insert register restoration code.
1180 DAG.setRoot(DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1181 getControlRoot(), DAG.getBasicBlock(NormalDestMBB),
1182 DAG.getBasicBlock(FuncInfo.MF->begin())));
1186 // If this is not a fall-through branch or optimizations are switched off,
1188 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1189 TM.getOptLevel() == CodeGenOpt::None)
1190 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1192 DAG.getBasicBlock(NormalDestMBB)));
1195 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1196 // Update machine-CFG edge.
1197 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1198 FuncInfo.MBB->addSuccessor(TargetMBB);
1200 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1201 bool IsSEH = isAsynchronousEHPersonality(Pers);
1203 // If this is not a fall-through branch or optimizations are switched off,
1205 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1206 TM.getOptLevel() == CodeGenOpt::None)
1207 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1208 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1212 // Figure out the funclet membership for the catchret's successor.
1213 // This will be used by the FuncletLayout pass to determine how to order the
1215 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1216 WinEHFuncInfo &EHInfo =
1217 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1218 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1219 assert(SuccessorColor && "No parent funclet for catchret!");
1220 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1221 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1223 // Create the terminator node.
1224 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1225 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1226 DAG.getBasicBlock(SuccessorColorMBB));
1230 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1231 llvm_unreachable("should never codegen catchendpads");
1234 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1235 // Don't emit any special code for the cleanuppad instruction. It just marks
1236 // the start of a funclet.
1237 FuncInfo.MBB->setIsEHFuncletEntry();
1238 FuncInfo.MBB->setIsCleanupFuncletEntry();
1241 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1242 /// many places it could ultimately go. In the IR, we have a single unwind
1243 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1244 /// This function skips over imaginary basic blocks that hold catchpad,
1245 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1246 /// basic block destinations.
1248 findUnwindDestinations(FunctionLoweringInfo &FuncInfo,
1249 const BasicBlock *EHPadBB,
1250 SmallVectorImpl<MachineBasicBlock *> &UnwindDests) {
1251 EHPersonality Personality =
1252 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1253 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1254 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1256 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1257 if (isa<LandingPadInst>(Pad)) {
1258 // Stop on landingpads. They are not funclets.
1259 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1261 } else if (isa<CleanupPadInst>(Pad)) {
1262 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1264 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1265 UnwindDests.back()->setIsEHFuncletEntry();
1267 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1268 // Add the catchpad handler to the possible destinations.
1269 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1270 // In MSVC C++, catchblocks are funclets and need prologues.
1271 if (IsMSVCCXX || IsCoreCLR)
1272 UnwindDests.back()->setIsEHFuncletEntry();
1273 EHPadBB = CPI->getUnwindDest();
1274 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
1275 EHPadBB = CEPI->getUnwindDest();
1276 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
1277 EHPadBB = CEPI->getUnwindDest();
1282 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1283 // Update successor info.
1284 // FIXME: The weights for catchpads will be wrong.
1285 SmallVector<MachineBasicBlock *, 1> UnwindDests;
1286 findUnwindDestinations(FuncInfo, I.getUnwindDest(), UnwindDests);
1287 for (MachineBasicBlock *UnwindDest : UnwindDests) {
1288 UnwindDest->setIsEHPad();
1289 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest);
1292 // Create the terminator node.
1294 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1298 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1299 report_fatal_error("visitCleanupEndPad not yet implemented!");
1302 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1303 report_fatal_error("visitTerminatePad not yet implemented!");
1306 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1307 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1308 auto &DL = DAG.getDataLayout();
1309 SDValue Chain = getControlRoot();
1310 SmallVector<ISD::OutputArg, 8> Outs;
1311 SmallVector<SDValue, 8> OutVals;
1313 if (!FuncInfo.CanLowerReturn) {
1314 unsigned DemoteReg = FuncInfo.DemoteRegister;
1315 const Function *F = I.getParent()->getParent();
1317 // Emit a store of the return value through the virtual register.
1318 // Leave Outs empty so that LowerReturn won't try to load return
1319 // registers the usual way.
1320 SmallVector<EVT, 1> PtrValueVTs;
1321 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1324 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1325 SDValue RetOp = getValue(I.getOperand(0));
1327 SmallVector<EVT, 4> ValueVTs;
1328 SmallVector<uint64_t, 4> Offsets;
1329 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1330 unsigned NumValues = ValueVTs.size();
1332 SmallVector<SDValue, 4> Chains(NumValues);
1333 for (unsigned i = 0; i != NumValues; ++i) {
1334 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1335 RetPtr.getValueType(), RetPtr,
1336 DAG.getIntPtrConstant(Offsets[i],
1339 DAG.getStore(Chain, getCurSDLoc(),
1340 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1341 // FIXME: better loc info would be nice.
1342 Add, MachinePointerInfo(), false, false, 0);
1345 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1346 MVT::Other, Chains);
1347 } else if (I.getNumOperands() != 0) {
1348 SmallVector<EVT, 4> ValueVTs;
1349 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1350 unsigned NumValues = ValueVTs.size();
1352 SDValue RetOp = getValue(I.getOperand(0));
1354 const Function *F = I.getParent()->getParent();
1356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1357 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1359 ExtendKind = ISD::SIGN_EXTEND;
1360 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1362 ExtendKind = ISD::ZERO_EXTEND;
1364 LLVMContext &Context = F->getContext();
1365 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1368 for (unsigned j = 0; j != NumValues; ++j) {
1369 EVT VT = ValueVTs[j];
1371 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1372 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1374 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1375 MVT PartVT = TLI.getRegisterType(Context, VT);
1376 SmallVector<SDValue, 4> Parts(NumParts);
1377 getCopyToParts(DAG, getCurSDLoc(),
1378 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1379 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1381 // 'inreg' on function refers to return value
1382 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1386 // Propagate extension type if any
1387 if (ExtendKind == ISD::SIGN_EXTEND)
1389 else if (ExtendKind == ISD::ZERO_EXTEND)
1392 for (unsigned i = 0; i < NumParts; ++i) {
1393 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1394 VT, /*isfixed=*/true, 0, 0));
1395 OutVals.push_back(Parts[i]);
1401 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1402 CallingConv::ID CallConv =
1403 DAG.getMachineFunction().getFunction()->getCallingConv();
1404 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1405 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1407 // Verify that the target's LowerReturn behaved as expected.
1408 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1409 "LowerReturn didn't return a valid chain!");
1411 // Update the DAG with the new chain value resulting from return lowering.
1415 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1416 /// created for it, emit nodes to copy the value into the virtual
1418 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1420 if (V->getType()->isEmptyTy())
1423 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1424 if (VMI != FuncInfo.ValueMap.end()) {
1425 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1426 CopyValueToVirtualRegister(V, VMI->second);
1430 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1431 /// the current basic block, add it to ValueMap now so that we'll get a
1433 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1434 // No need to export constants.
1435 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1437 // Already exported?
1438 if (FuncInfo.isExportedInst(V)) return;
1440 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1441 CopyValueToVirtualRegister(V, Reg);
1444 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1445 const BasicBlock *FromBB) {
1446 // The operands of the setcc have to be in this block. We don't know
1447 // how to export them from some other block.
1448 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1449 // Can export from current BB.
1450 if (VI->getParent() == FromBB)
1453 // Is already exported, noop.
1454 return FuncInfo.isExportedInst(V);
1457 // If this is an argument, we can export it if the BB is the entry block or
1458 // if it is already exported.
1459 if (isa<Argument>(V)) {
1460 if (FromBB == &FromBB->getParent()->getEntryBlock())
1463 // Otherwise, can only export this if it is already exported.
1464 return FuncInfo.isExportedInst(V);
1467 // Otherwise, constants can always be exported.
1471 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1472 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1473 const MachineBasicBlock *Dst) const {
1474 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1477 const BasicBlock *SrcBB = Src->getBasicBlock();
1478 const BasicBlock *DstBB = Dst->getBasicBlock();
1479 return BPI->getEdgeWeight(SrcBB, DstBB);
1482 void SelectionDAGBuilder::
1483 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1484 uint32_t Weight /* = 0 */) {
1486 Weight = getEdgeWeight(Src, Dst);
1487 Src->addSuccessor(Dst, Weight);
1491 static bool InBlock(const Value *V, const BasicBlock *BB) {
1492 if (const Instruction *I = dyn_cast<Instruction>(V))
1493 return I->getParent() == BB;
1497 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1498 /// This function emits a branch and is used at the leaves of an OR or an
1499 /// AND operator tree.
1502 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1503 MachineBasicBlock *TBB,
1504 MachineBasicBlock *FBB,
1505 MachineBasicBlock *CurBB,
1506 MachineBasicBlock *SwitchBB,
1509 const BasicBlock *BB = CurBB->getBasicBlock();
1511 // If the leaf of the tree is a comparison, merge the condition into
1513 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1514 // The operands of the cmp have to be in this block. We don't know
1515 // how to export them from some other block. If this is the first block
1516 // of the sequence, no exporting is needed.
1517 if (CurBB == SwitchBB ||
1518 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1519 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1520 ISD::CondCode Condition;
1521 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1522 Condition = getICmpCondCode(IC->getPredicate());
1524 const FCmpInst *FC = cast<FCmpInst>(Cond);
1525 Condition = getFCmpCondCode(FC->getPredicate());
1526 if (TM.Options.NoNaNsFPMath)
1527 Condition = getFCmpCodeWithoutNaN(Condition);
1530 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1531 TBB, FBB, CurBB, TWeight, FWeight);
1532 SwitchCases.push_back(CB);
1537 // Create a CaseBlock record representing this branch.
1538 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1539 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1540 SwitchCases.push_back(CB);
1543 /// Scale down both weights to fit into uint32_t.
1544 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1545 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1546 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1547 NewTrue = NewTrue / Scale;
1548 NewFalse = NewFalse / Scale;
1551 /// FindMergedConditions - If Cond is an expression like
1552 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1553 MachineBasicBlock *TBB,
1554 MachineBasicBlock *FBB,
1555 MachineBasicBlock *CurBB,
1556 MachineBasicBlock *SwitchBB,
1557 Instruction::BinaryOps Opc,
1560 // If this node is not part of the or/and tree, emit it as a branch.
1561 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1562 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1563 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1564 BOp->getParent() != CurBB->getBasicBlock() ||
1565 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1566 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1567 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1572 // Create TmpBB after CurBB.
1573 MachineFunction::iterator BBI = CurBB;
1574 MachineFunction &MF = DAG.getMachineFunction();
1575 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1576 CurBB->getParent()->insert(++BBI, TmpBB);
1578 if (Opc == Instruction::Or) {
1579 // Codegen X | Y as:
1588 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1589 // The requirement is that
1590 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1591 // = TrueProb for original BB.
1592 // Assuming the original weights are A and B, one choice is to set BB1's
1593 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1595 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1596 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1597 // TmpBB, but the math is more complicated.
1599 uint64_t NewTrueWeight = TWeight;
1600 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1601 ScaleWeights(NewTrueWeight, NewFalseWeight);
1602 // Emit the LHS condition.
1603 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1604 NewTrueWeight, NewFalseWeight);
1606 NewTrueWeight = TWeight;
1607 NewFalseWeight = 2 * (uint64_t)FWeight;
1608 ScaleWeights(NewTrueWeight, NewFalseWeight);
1609 // Emit the RHS condition into TmpBB.
1610 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1611 NewTrueWeight, NewFalseWeight);
1613 assert(Opc == Instruction::And && "Unknown merge op!");
1614 // Codegen X & Y as:
1622 // This requires creation of TmpBB after CurBB.
1624 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1625 // The requirement is that
1626 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1627 // = FalseProb for original BB.
1628 // Assuming the original weights are A and B, one choice is to set BB1's
1629 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1631 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1633 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1634 uint64_t NewFalseWeight = FWeight;
1635 ScaleWeights(NewTrueWeight, NewFalseWeight);
1636 // Emit the LHS condition.
1637 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1638 NewTrueWeight, NewFalseWeight);
1640 NewTrueWeight = 2 * (uint64_t)TWeight;
1641 NewFalseWeight = FWeight;
1642 ScaleWeights(NewTrueWeight, NewFalseWeight);
1643 // Emit the RHS condition into TmpBB.
1644 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1645 NewTrueWeight, NewFalseWeight);
1649 /// If the set of cases should be emitted as a series of branches, return true.
1650 /// If we should emit this as a bunch of and/or'd together conditions, return
1653 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1654 if (Cases.size() != 2) return true;
1656 // If this is two comparisons of the same values or'd or and'd together, they
1657 // will get folded into a single comparison, so don't emit two blocks.
1658 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1659 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1660 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1661 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1665 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1666 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1667 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1668 Cases[0].CC == Cases[1].CC &&
1669 isa<Constant>(Cases[0].CmpRHS) &&
1670 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1671 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1673 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1680 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1681 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1683 // Update machine-CFG edges.
1684 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1686 if (I.isUnconditional()) {
1687 // Update machine-CFG edges.
1688 BrMBB->addSuccessor(Succ0MBB);
1690 // If this is not a fall-through branch or optimizations are switched off,
1692 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1693 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1694 MVT::Other, getControlRoot(),
1695 DAG.getBasicBlock(Succ0MBB)));
1700 // If this condition is one of the special cases we handle, do special stuff
1702 const Value *CondVal = I.getCondition();
1703 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1705 // If this is a series of conditions that are or'd or and'd together, emit
1706 // this as a sequence of branches instead of setcc's with and/or operations.
1707 // As long as jumps are not expensive, this should improve performance.
1708 // For example, instead of something like:
1721 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1722 Instruction::BinaryOps Opcode = BOp->getOpcode();
1723 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1724 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1725 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1726 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1727 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1728 getEdgeWeight(BrMBB, Succ1MBB));
1729 // If the compares in later blocks need to use values not currently
1730 // exported from this block, export them now. This block should always
1731 // be the first entry.
1732 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1734 // Allow some cases to be rejected.
1735 if (ShouldEmitAsBranches(SwitchCases)) {
1736 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1737 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1738 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1741 // Emit the branch for this block.
1742 visitSwitchCase(SwitchCases[0], BrMBB);
1743 SwitchCases.erase(SwitchCases.begin());
1747 // Okay, we decided not to do this, remove any inserted MBB's and clear
1749 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1750 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1752 SwitchCases.clear();
1756 // Create a CaseBlock record representing this branch.
1757 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1758 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1760 // Use visitSwitchCase to actually insert the fast branch sequence for this
1762 visitSwitchCase(CB, BrMBB);
1765 /// visitSwitchCase - Emits the necessary code to represent a single node in
1766 /// the binary search tree resulting from lowering a switch instruction.
1767 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1768 MachineBasicBlock *SwitchBB) {
1770 SDValue CondLHS = getValue(CB.CmpLHS);
1771 SDLoc dl = getCurSDLoc();
1773 // Build the setcc now.
1775 // Fold "(X == true)" to X and "(X == false)" to !X to
1776 // handle common cases produced by branch lowering.
1777 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1778 CB.CC == ISD::SETEQ)
1780 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1781 CB.CC == ISD::SETEQ) {
1782 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1783 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1785 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1787 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1789 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1790 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1792 SDValue CmpOp = getValue(CB.CmpMHS);
1793 EVT VT = CmpOp.getValueType();
1795 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1796 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1799 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1800 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1801 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1802 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1806 // Update successor info
1807 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1808 // TrueBB and FalseBB are always different unless the incoming IR is
1809 // degenerate. This only happens when running llc on weird IR.
1810 if (CB.TrueBB != CB.FalseBB)
1811 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1813 // If the lhs block is the next block, invert the condition so that we can
1814 // fall through to the lhs instead of the rhs block.
1815 if (CB.TrueBB == NextBlock(SwitchBB)) {
1816 std::swap(CB.TrueBB, CB.FalseBB);
1817 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1818 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1821 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1822 MVT::Other, getControlRoot(), Cond,
1823 DAG.getBasicBlock(CB.TrueBB));
1825 // Insert the false branch. Do this even if it's a fall through branch,
1826 // this makes it easier to do DAG optimizations which require inverting
1827 // the branch condition.
1828 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1829 DAG.getBasicBlock(CB.FalseBB));
1831 DAG.setRoot(BrCond);
1834 /// visitJumpTable - Emit JumpTable node in the current MBB
1835 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1836 // Emit the code for the jump table
1837 assert(JT.Reg != -1U && "Should lower JT Header first!");
1838 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1839 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1841 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1842 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1843 MVT::Other, Index.getValue(1),
1845 DAG.setRoot(BrJumpTable);
1848 /// visitJumpTableHeader - This function emits necessary code to produce index
1849 /// in the JumpTable from switch case.
1850 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1851 JumpTableHeader &JTH,
1852 MachineBasicBlock *SwitchBB) {
1853 SDLoc dl = getCurSDLoc();
1855 // Subtract the lowest switch case value from the value being switched on and
1856 // conditional branch to default mbb if the result is greater than the
1857 // difference between smallest and largest cases.
1858 SDValue SwitchOp = getValue(JTH.SValue);
1859 EVT VT = SwitchOp.getValueType();
1860 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1861 DAG.getConstant(JTH.First, dl, VT));
1863 // The SDNode we just created, which holds the value being switched on minus
1864 // the smallest case value, needs to be copied to a virtual register so it
1865 // can be used as an index into the jump table in a subsequent basic block.
1866 // This value may be smaller or larger than the target's pointer type, and
1867 // therefore require extension or truncating.
1868 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1869 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1871 unsigned JumpTableReg =
1872 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1873 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1874 JumpTableReg, SwitchOp);
1875 JT.Reg = JumpTableReg;
1877 // Emit the range check for the jump table, and branch to the default block
1878 // for the switch statement if the value being switched on exceeds the largest
1879 // case in the switch.
1880 SDValue CMP = DAG.getSetCC(
1881 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1882 Sub.getValueType()),
1883 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1885 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1886 MVT::Other, CopyTo, CMP,
1887 DAG.getBasicBlock(JT.Default));
1889 // Avoid emitting unnecessary branches to the next block.
1890 if (JT.MBB != NextBlock(SwitchBB))
1891 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1892 DAG.getBasicBlock(JT.MBB));
1894 DAG.setRoot(BrCond);
1897 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1898 /// tail spliced into a stack protector check success bb.
1900 /// For a high level explanation of how this fits into the stack protector
1901 /// generation see the comment on the declaration of class
1902 /// StackProtectorDescriptor.
1903 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1904 MachineBasicBlock *ParentBB) {
1906 // First create the loads to the guard/stack slot for the comparison.
1907 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1908 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1910 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1911 int FI = MFI->getStackProtectorIndex();
1913 const Value *IRGuard = SPD.getGuard();
1914 SDValue GuardPtr = getValue(IRGuard);
1915 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1917 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1920 SDLoc dl = getCurSDLoc();
1922 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1923 // guard value from the virtual register holding the value. Otherwise, emit a
1924 // volatile load to retrieve the stack guard value.
1925 unsigned GuardReg = SPD.getGuardReg();
1927 if (GuardReg && TLI.useLoadStackGuardNode())
1928 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1931 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1932 GuardPtr, MachinePointerInfo(IRGuard, 0),
1933 true, false, false, Align);
1935 SDValue StackSlot = DAG.getLoad(
1936 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1937 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1938 false, false, Align);
1940 // Perform the comparison via a subtract/getsetcc.
1941 EVT VT = Guard.getValueType();
1942 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1944 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1946 Sub.getValueType()),
1947 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1949 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1950 // branch to failure MBB.
1951 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1952 MVT::Other, StackSlot.getOperand(0),
1953 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1954 // Otherwise branch to success MBB.
1955 SDValue Br = DAG.getNode(ISD::BR, dl,
1957 DAG.getBasicBlock(SPD.getSuccessMBB()));
1962 /// Codegen the failure basic block for a stack protector check.
1964 /// A failure stack protector machine basic block consists simply of a call to
1965 /// __stack_chk_fail().
1967 /// For a high level explanation of how this fits into the stack protector
1968 /// generation see the comment on the declaration of class
1969 /// StackProtectorDescriptor.
1971 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1974 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1975 nullptr, 0, false, getCurSDLoc(), false, false).second;
1979 /// visitBitTestHeader - This function emits necessary code to produce value
1980 /// suitable for "bit tests"
1981 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1982 MachineBasicBlock *SwitchBB) {
1983 SDLoc dl = getCurSDLoc();
1985 // Subtract the minimum value
1986 SDValue SwitchOp = getValue(B.SValue);
1987 EVT VT = SwitchOp.getValueType();
1988 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1989 DAG.getConstant(B.First, dl, VT));
1992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1993 SDValue RangeCmp = DAG.getSetCC(
1994 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1995 Sub.getValueType()),
1996 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1998 // Determine the type of the test operands.
1999 bool UsePtrType = false;
2000 if (!TLI.isTypeLegal(VT))
2003 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2004 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2005 // Switch table case range are encoded into series of masks.
2006 // Just use pointer type, it's guaranteed to fit.
2012 VT = TLI.getPointerTy(DAG.getDataLayout());
2013 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2016 B.RegVT = VT.getSimpleVT();
2017 B.Reg = FuncInfo.CreateReg(B.RegVT);
2018 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2020 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2022 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2023 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2025 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2026 MVT::Other, CopyTo, RangeCmp,
2027 DAG.getBasicBlock(B.Default));
2029 // Avoid emitting unnecessary branches to the next block.
2030 if (MBB != NextBlock(SwitchBB))
2031 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2032 DAG.getBasicBlock(MBB));
2034 DAG.setRoot(BrRange);
2037 /// visitBitTestCase - this function produces one "bit test"
2038 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2039 MachineBasicBlock* NextMBB,
2040 uint32_t BranchWeightToNext,
2043 MachineBasicBlock *SwitchBB) {
2044 SDLoc dl = getCurSDLoc();
2046 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2048 unsigned PopCount = countPopulation(B.Mask);
2049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2050 if (PopCount == 1) {
2051 // Testing for a single bit; just compare the shift count with what it
2052 // would need to be to shift a 1 bit in that position.
2054 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2055 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2057 } else if (PopCount == BB.Range) {
2058 // There is only one zero bit in the range, test for it directly.
2060 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2061 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2064 // Make desired shift
2065 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2066 DAG.getConstant(1, dl, VT), ShiftOp);
2068 // Emit bit tests and jumps
2069 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2070 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2072 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2073 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2076 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2077 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2078 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2079 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2081 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2082 MVT::Other, getControlRoot(),
2083 Cmp, DAG.getBasicBlock(B.TargetBB));
2085 // Avoid emitting unnecessary branches to the next block.
2086 if (NextMBB != NextBlock(SwitchBB))
2087 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2088 DAG.getBasicBlock(NextMBB));
2093 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2094 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2096 // Retrieve successors. Look through artificial IR level blocks like catchpads
2097 // and catchendpads for successors.
2098 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2099 const BasicBlock *EHPadBB = I.getSuccessor(1);
2101 const Value *Callee(I.getCalledValue());
2102 const Function *Fn = dyn_cast<Function>(Callee);
2103 if (isa<InlineAsm>(Callee))
2105 else if (Fn && Fn->isIntrinsic()) {
2106 switch (Fn->getIntrinsicID()) {
2108 llvm_unreachable("Cannot invoke this intrinsic");
2109 case Intrinsic::donothing:
2110 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2112 case Intrinsic::experimental_patchpoint_void:
2113 case Intrinsic::experimental_patchpoint_i64:
2114 visitPatchpoint(&I, EHPadBB);
2116 case Intrinsic::experimental_gc_statepoint:
2117 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2121 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2123 // If the value of the invoke is used outside of its defining block, make it
2124 // available as a virtual register.
2125 // We already took care of the exported value for the statepoint instruction
2126 // during call to the LowerStatepoint.
2127 if (!isStatepoint(I)) {
2128 CopyToExportRegsIfNeeded(&I);
2131 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2132 findUnwindDestinations(FuncInfo, EHPadBB, UnwindDests);
2134 // Update successor info.
2135 // FIXME: The weights for catchpads will be wrong.
2136 addSuccessorWithWeight(InvokeMBB, Return);
2137 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2138 UnwindDest->setIsEHPad();
2139 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2142 // Drop into normal successor.
2143 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2144 MVT::Other, getControlRoot(),
2145 DAG.getBasicBlock(Return)));
2148 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2149 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2152 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2153 assert(FuncInfo.MBB->isEHPad() &&
2154 "Call to landingpad not in landing pad!");
2156 MachineBasicBlock *MBB = FuncInfo.MBB;
2157 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2158 AddLandingPadInfo(LP, MMI, MBB);
2160 // If there aren't registers to copy the values into (e.g., during SjLj
2161 // exceptions), then don't bother to create these DAG nodes.
2162 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2163 if (TLI.getExceptionPointerRegister() == 0 &&
2164 TLI.getExceptionSelectorRegister() == 0)
2167 SmallVector<EVT, 2> ValueVTs;
2168 SDLoc dl = getCurSDLoc();
2169 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2170 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2172 // Get the two live-in registers as SDValues. The physregs have already been
2173 // copied into virtual registers.
2175 if (FuncInfo.ExceptionPointerVirtReg) {
2176 Ops[0] = DAG.getZExtOrTrunc(
2177 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2178 FuncInfo.ExceptionPointerVirtReg,
2179 TLI.getPointerTy(DAG.getDataLayout())),
2182 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2184 Ops[1] = DAG.getZExtOrTrunc(
2185 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2186 FuncInfo.ExceptionSelectorVirtReg,
2187 TLI.getPointerTy(DAG.getDataLayout())),
2191 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2192 DAG.getVTList(ValueVTs), Ops);
2196 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2198 for (const CaseCluster &CC : Clusters)
2199 assert(CC.Low == CC.High && "Input clusters must be single-case");
2202 std::sort(Clusters.begin(), Clusters.end(),
2203 [](const CaseCluster &a, const CaseCluster &b) {
2204 return a.Low->getValue().slt(b.Low->getValue());
2207 // Merge adjacent clusters with the same destination.
2208 const unsigned N = Clusters.size();
2209 unsigned DstIndex = 0;
2210 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2211 CaseCluster &CC = Clusters[SrcIndex];
2212 const ConstantInt *CaseVal = CC.Low;
2213 MachineBasicBlock *Succ = CC.MBB;
2215 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2216 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2217 // If this case has the same successor and is a neighbour, merge it into
2218 // the previous cluster.
2219 Clusters[DstIndex - 1].High = CaseVal;
2220 Clusters[DstIndex - 1].Weight += CC.Weight;
2221 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2223 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2224 sizeof(Clusters[SrcIndex]));
2227 Clusters.resize(DstIndex);
2230 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2231 MachineBasicBlock *Last) {
2233 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2234 if (JTCases[i].first.HeaderBB == First)
2235 JTCases[i].first.HeaderBB = Last;
2237 // Update BitTestCases.
2238 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2239 if (BitTestCases[i].Parent == First)
2240 BitTestCases[i].Parent = Last;
2243 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2244 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2246 // Update machine-CFG edges with unique successors.
2247 SmallSet<BasicBlock*, 32> Done;
2248 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2249 BasicBlock *BB = I.getSuccessor(i);
2250 bool Inserted = Done.insert(BB).second;
2254 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2255 addSuccessorWithWeight(IndirectBrMBB, Succ);
2258 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2259 MVT::Other, getControlRoot(),
2260 getValue(I.getAddress())));
2263 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {}
2265 void SelectionDAGBuilder::visitFSub(const User &I) {
2266 // -0.0 - X --> fneg
2267 Type *Ty = I.getType();
2268 if (isa<Constant>(I.getOperand(0)) &&
2269 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2270 SDValue Op2 = getValue(I.getOperand(1));
2271 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2272 Op2.getValueType(), Op2));
2276 visitBinary(I, ISD::FSUB);
2279 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2280 SDValue Op1 = getValue(I.getOperand(0));
2281 SDValue Op2 = getValue(I.getOperand(1));
2288 if (const OverflowingBinaryOperator *OFBinOp =
2289 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2290 nuw = OFBinOp->hasNoUnsignedWrap();
2291 nsw = OFBinOp->hasNoSignedWrap();
2293 if (const PossiblyExactOperator *ExactOp =
2294 dyn_cast<const PossiblyExactOperator>(&I))
2295 exact = ExactOp->isExact();
2296 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2297 FMF = FPOp->getFastMathFlags();
2300 Flags.setExact(exact);
2301 Flags.setNoSignedWrap(nsw);
2302 Flags.setNoUnsignedWrap(nuw);
2303 if (EnableFMFInDAG) {
2304 Flags.setAllowReciprocal(FMF.allowReciprocal());
2305 Flags.setNoInfs(FMF.noInfs());
2306 Flags.setNoNaNs(FMF.noNaNs());
2307 Flags.setNoSignedZeros(FMF.noSignedZeros());
2308 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2310 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2312 setValue(&I, BinNodeValue);
2315 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2316 SDValue Op1 = getValue(I.getOperand(0));
2317 SDValue Op2 = getValue(I.getOperand(1));
2319 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2320 Op2.getValueType(), DAG.getDataLayout());
2322 // Coerce the shift amount to the right type if we can.
2323 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2324 unsigned ShiftSize = ShiftTy.getSizeInBits();
2325 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2326 SDLoc DL = getCurSDLoc();
2328 // If the operand is smaller than the shift count type, promote it.
2329 if (ShiftSize > Op2Size)
2330 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2332 // If the operand is larger than the shift count type but the shift
2333 // count type has enough bits to represent any shift value, truncate
2334 // it now. This is a common case and it exposes the truncate to
2335 // optimization early.
2336 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2337 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2338 // Otherwise we'll need to temporarily settle for some other convenient
2339 // type. Type legalization will make adjustments once the shiftee is split.
2341 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2348 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2350 if (const OverflowingBinaryOperator *OFBinOp =
2351 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2352 nuw = OFBinOp->hasNoUnsignedWrap();
2353 nsw = OFBinOp->hasNoSignedWrap();
2355 if (const PossiblyExactOperator *ExactOp =
2356 dyn_cast<const PossiblyExactOperator>(&I))
2357 exact = ExactOp->isExact();
2360 Flags.setExact(exact);
2361 Flags.setNoSignedWrap(nsw);
2362 Flags.setNoUnsignedWrap(nuw);
2363 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2368 void SelectionDAGBuilder::visitSDiv(const User &I) {
2369 SDValue Op1 = getValue(I.getOperand(0));
2370 SDValue Op2 = getValue(I.getOperand(1));
2373 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2374 cast<PossiblyExactOperator>(&I)->isExact());
2375 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2379 void SelectionDAGBuilder::visitICmp(const User &I) {
2380 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2381 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2382 predicate = IC->getPredicate();
2383 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2384 predicate = ICmpInst::Predicate(IC->getPredicate());
2385 SDValue Op1 = getValue(I.getOperand(0));
2386 SDValue Op2 = getValue(I.getOperand(1));
2387 ISD::CondCode Opcode = getICmpCondCode(predicate);
2389 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2391 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2394 void SelectionDAGBuilder::visitFCmp(const User &I) {
2395 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2396 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2397 predicate = FC->getPredicate();
2398 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2399 predicate = FCmpInst::Predicate(FC->getPredicate());
2400 SDValue Op1 = getValue(I.getOperand(0));
2401 SDValue Op2 = getValue(I.getOperand(1));
2402 ISD::CondCode Condition = getFCmpCondCode(predicate);
2404 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2405 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2406 // further optimization, but currently FMF is only applicable to binary nodes.
2407 if (TM.Options.NoNaNsFPMath)
2408 Condition = getFCmpCodeWithoutNaN(Condition);
2409 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2411 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2414 void SelectionDAGBuilder::visitSelect(const User &I) {
2415 SmallVector<EVT, 4> ValueVTs;
2416 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2418 unsigned NumValues = ValueVTs.size();
2419 if (NumValues == 0) return;
2421 SmallVector<SDValue, 4> Values(NumValues);
2422 SDValue Cond = getValue(I.getOperand(0));
2423 SDValue LHSVal = getValue(I.getOperand(1));
2424 SDValue RHSVal = getValue(I.getOperand(2));
2425 auto BaseOps = {Cond};
2426 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2427 ISD::VSELECT : ISD::SELECT;
2429 // Min/max matching is only viable if all output VTs are the same.
2430 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2431 EVT VT = ValueVTs[0];
2432 LLVMContext &Ctx = *DAG.getContext();
2433 auto &TLI = DAG.getTargetLoweringInfo();
2434 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2435 VT = TLI.getTypeToTransformTo(Ctx, VT);
2438 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2439 ISD::NodeType Opc = ISD::DELETED_NODE;
2440 switch (SPR.Flavor) {
2441 case SPF_UMAX: Opc = ISD::UMAX; break;
2442 case SPF_UMIN: Opc = ISD::UMIN; break;
2443 case SPF_SMAX: Opc = ISD::SMAX; break;
2444 case SPF_SMIN: Opc = ISD::SMIN; break;
2446 switch (SPR.NaNBehavior) {
2447 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2448 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2449 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2450 case SPNB_RETURNS_ANY:
2451 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2457 switch (SPR.NaNBehavior) {
2458 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2459 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2460 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2461 case SPNB_RETURNS_ANY:
2462 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2470 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2471 // If the underlying comparison instruction is used by any other instruction,
2472 // the consumed instructions won't be destroyed, so it is not profitable
2473 // to convert to a min/max.
2474 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2476 LHSVal = getValue(LHS);
2477 RHSVal = getValue(RHS);
2482 for (unsigned i = 0; i != NumValues; ++i) {
2483 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2484 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2485 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2486 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2487 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2491 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2492 DAG.getVTList(ValueVTs), Values));
2495 void SelectionDAGBuilder::visitTrunc(const User &I) {
2496 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2497 SDValue N = getValue(I.getOperand(0));
2498 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2500 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2503 void SelectionDAGBuilder::visitZExt(const User &I) {
2504 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2505 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2506 SDValue N = getValue(I.getOperand(0));
2507 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2509 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2512 void SelectionDAGBuilder::visitSExt(const User &I) {
2513 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2514 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2515 SDValue N = getValue(I.getOperand(0));
2516 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2518 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2521 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2522 // FPTrunc is never a no-op cast, no need to check
2523 SDValue N = getValue(I.getOperand(0));
2524 SDLoc dl = getCurSDLoc();
2525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2526 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2527 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2528 DAG.getTargetConstant(
2529 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2532 void SelectionDAGBuilder::visitFPExt(const User &I) {
2533 // FPExt is never a no-op cast, no need to check
2534 SDValue N = getValue(I.getOperand(0));
2535 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2537 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2540 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2541 // FPToUI is never a no-op cast, no need to check
2542 SDValue N = getValue(I.getOperand(0));
2543 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2545 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2548 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2549 // FPToSI is never a no-op cast, no need to check
2550 SDValue N = getValue(I.getOperand(0));
2551 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2553 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2556 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2557 // UIToFP is never a no-op cast, no need to check
2558 SDValue N = getValue(I.getOperand(0));
2559 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2561 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2564 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2565 // SIToFP is never a no-op cast, no need to check
2566 SDValue N = getValue(I.getOperand(0));
2567 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2569 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2572 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2573 // What to do depends on the size of the integer and the size of the pointer.
2574 // We can either truncate, zero extend, or no-op, accordingly.
2575 SDValue N = getValue(I.getOperand(0));
2576 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2578 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2581 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2582 // What to do depends on the size of the integer and the size of the pointer.
2583 // We can either truncate, zero extend, or no-op, accordingly.
2584 SDValue N = getValue(I.getOperand(0));
2585 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2587 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2590 void SelectionDAGBuilder::visitBitCast(const User &I) {
2591 SDValue N = getValue(I.getOperand(0));
2592 SDLoc dl = getCurSDLoc();
2593 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2596 // BitCast assures us that source and destination are the same size so this is
2597 // either a BITCAST or a no-op.
2598 if (DestVT != N.getValueType())
2599 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2600 DestVT, N)); // convert types.
2601 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2602 // might fold any kind of constant expression to an integer constant and that
2603 // is not what we are looking for. Only regcognize a bitcast of a genuine
2604 // constant integer as an opaque constant.
2605 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2606 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2609 setValue(&I, N); // noop cast.
2612 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2614 const Value *SV = I.getOperand(0);
2615 SDValue N = getValue(SV);
2616 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2618 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2619 unsigned DestAS = I.getType()->getPointerAddressSpace();
2621 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2622 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2627 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2629 SDValue InVec = getValue(I.getOperand(0));
2630 SDValue InVal = getValue(I.getOperand(1));
2631 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2632 TLI.getVectorIdxTy(DAG.getDataLayout()));
2633 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2634 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2635 InVec, InVal, InIdx));
2638 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2639 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2640 SDValue InVec = getValue(I.getOperand(0));
2641 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2642 TLI.getVectorIdxTy(DAG.getDataLayout()));
2643 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2644 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2648 // Utility for visitShuffleVector - Return true if every element in Mask,
2649 // beginning from position Pos and ending in Pos+Size, falls within the
2650 // specified sequential range [L, L+Pos). or is undef.
2651 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2652 unsigned Pos, unsigned Size, int Low) {
2653 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2654 if (Mask[i] >= 0 && Mask[i] != Low)
2659 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2660 SDValue Src1 = getValue(I.getOperand(0));
2661 SDValue Src2 = getValue(I.getOperand(1));
2663 SmallVector<int, 8> Mask;
2664 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2665 unsigned MaskNumElts = Mask.size();
2667 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2668 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2669 EVT SrcVT = Src1.getValueType();
2670 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2672 if (SrcNumElts == MaskNumElts) {
2673 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2678 // Normalize the shuffle vector since mask and vector length don't match.
2679 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2680 // Mask is longer than the source vectors and is a multiple of the source
2681 // vectors. We can use concatenate vector to make the mask and vectors
2683 if (SrcNumElts*2 == MaskNumElts) {
2684 // First check for Src1 in low and Src2 in high
2685 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2686 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2687 // The shuffle is concatenating two vectors together.
2688 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2692 // Then check for Src2 in low and Src1 in high
2693 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2694 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2695 // The shuffle is concatenating two vectors together.
2696 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2702 // Pad both vectors with undefs to make them the same length as the mask.
2703 unsigned NumConcat = MaskNumElts / SrcNumElts;
2704 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2705 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2706 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2708 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2709 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2713 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2714 getCurSDLoc(), VT, MOps1);
2715 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2716 getCurSDLoc(), VT, MOps2);
2718 // Readjust mask for new input vector length.
2719 SmallVector<int, 8> MappedOps;
2720 for (unsigned i = 0; i != MaskNumElts; ++i) {
2722 if (Idx >= (int)SrcNumElts)
2723 Idx -= SrcNumElts - MaskNumElts;
2724 MappedOps.push_back(Idx);
2727 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2732 if (SrcNumElts > MaskNumElts) {
2733 // Analyze the access pattern of the vector to see if we can extract
2734 // two subvectors and do the shuffle. The analysis is done by calculating
2735 // the range of elements the mask access on both vectors.
2736 int MinRange[2] = { static_cast<int>(SrcNumElts),
2737 static_cast<int>(SrcNumElts)};
2738 int MaxRange[2] = {-1, -1};
2740 for (unsigned i = 0; i != MaskNumElts; ++i) {
2746 if (Idx >= (int)SrcNumElts) {
2750 if (Idx > MaxRange[Input])
2751 MaxRange[Input] = Idx;
2752 if (Idx < MinRange[Input])
2753 MinRange[Input] = Idx;
2756 // Check if the access is smaller than the vector size and can we find
2757 // a reasonable extract index.
2758 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2760 int StartIdx[2]; // StartIdx to extract from
2761 for (unsigned Input = 0; Input < 2; ++Input) {
2762 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2763 RangeUse[Input] = 0; // Unused
2764 StartIdx[Input] = 0;
2768 // Find a good start index that is a multiple of the mask length. Then
2769 // see if the rest of the elements are in range.
2770 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2771 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2772 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2773 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2776 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2777 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2780 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2781 // Extract appropriate subvector and generate a vector shuffle
2782 for (unsigned Input = 0; Input < 2; ++Input) {
2783 SDValue &Src = Input == 0 ? Src1 : Src2;
2784 if (RangeUse[Input] == 0)
2785 Src = DAG.getUNDEF(VT);
2787 SDLoc dl = getCurSDLoc();
2789 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2790 DAG.getConstant(StartIdx[Input], dl,
2791 TLI.getVectorIdxTy(DAG.getDataLayout())));
2795 // Calculate new mask.
2796 SmallVector<int, 8> MappedOps;
2797 for (unsigned i = 0; i != MaskNumElts; ++i) {
2800 if (Idx < (int)SrcNumElts)
2803 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2805 MappedOps.push_back(Idx);
2808 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2814 // We can't use either concat vectors or extract subvectors so fall back to
2815 // replacing the shuffle with extract and build vector.
2816 // to insert and build vector.
2817 EVT EltVT = VT.getVectorElementType();
2818 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2819 SDLoc dl = getCurSDLoc();
2820 SmallVector<SDValue,8> Ops;
2821 for (unsigned i = 0; i != MaskNumElts; ++i) {
2826 Res = DAG.getUNDEF(EltVT);
2828 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2829 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2831 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2832 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2838 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2841 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2842 const Value *Op0 = I.getOperand(0);
2843 const Value *Op1 = I.getOperand(1);
2844 Type *AggTy = I.getType();
2845 Type *ValTy = Op1->getType();
2846 bool IntoUndef = isa<UndefValue>(Op0);
2847 bool FromUndef = isa<UndefValue>(Op1);
2849 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2851 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2852 SmallVector<EVT, 4> AggValueVTs;
2853 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2854 SmallVector<EVT, 4> ValValueVTs;
2855 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2857 unsigned NumAggValues = AggValueVTs.size();
2858 unsigned NumValValues = ValValueVTs.size();
2859 SmallVector<SDValue, 4> Values(NumAggValues);
2861 // Ignore an insertvalue that produces an empty object
2862 if (!NumAggValues) {
2863 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2867 SDValue Agg = getValue(Op0);
2869 // Copy the beginning value(s) from the original aggregate.
2870 for (; i != LinearIndex; ++i)
2871 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2872 SDValue(Agg.getNode(), Agg.getResNo() + i);
2873 // Copy values from the inserted value(s).
2875 SDValue Val = getValue(Op1);
2876 for (; i != LinearIndex + NumValValues; ++i)
2877 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2878 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2880 // Copy remaining value(s) from the original aggregate.
2881 for (; i != NumAggValues; ++i)
2882 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2883 SDValue(Agg.getNode(), Agg.getResNo() + i);
2885 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2886 DAG.getVTList(AggValueVTs), Values));
2889 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2890 const Value *Op0 = I.getOperand(0);
2891 Type *AggTy = Op0->getType();
2892 Type *ValTy = I.getType();
2893 bool OutOfUndef = isa<UndefValue>(Op0);
2895 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2897 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2898 SmallVector<EVT, 4> ValValueVTs;
2899 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2901 unsigned NumValValues = ValValueVTs.size();
2903 // Ignore a extractvalue that produces an empty object
2904 if (!NumValValues) {
2905 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2909 SmallVector<SDValue, 4> Values(NumValValues);
2911 SDValue Agg = getValue(Op0);
2912 // Copy out the selected value(s).
2913 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2914 Values[i - LinearIndex] =
2916 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2917 SDValue(Agg.getNode(), Agg.getResNo() + i);
2919 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2920 DAG.getVTList(ValValueVTs), Values));
2923 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2924 Value *Op0 = I.getOperand(0);
2925 // Note that the pointer operand may be a vector of pointers. Take the scalar
2926 // element which holds a pointer.
2927 Type *Ty = Op0->getType()->getScalarType();
2928 unsigned AS = Ty->getPointerAddressSpace();
2929 SDValue N = getValue(Op0);
2930 SDLoc dl = getCurSDLoc();
2932 // Normalize Vector GEP - all scalar operands should be converted to the
2934 unsigned VectorWidth = I.getType()->isVectorTy() ?
2935 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2937 if (VectorWidth && !N.getValueType().isVector()) {
2938 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2939 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2940 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2942 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2944 const Value *Idx = *OI;
2945 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2946 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2949 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2950 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2951 DAG.getConstant(Offset, dl, N.getValueType()));
2954 Ty = StTy->getElementType(Field);
2956 Ty = cast<SequentialType>(Ty)->getElementType();
2958 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2959 unsigned PtrSize = PtrTy.getSizeInBits();
2960 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2962 // If this is a scalar constant or a splat vector of constants,
2963 // handle it quickly.
2964 const auto *CI = dyn_cast<ConstantInt>(Idx);
2965 if (!CI && isa<ConstantDataVector>(Idx) &&
2966 cast<ConstantDataVector>(Idx)->getSplatValue())
2967 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2972 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2973 SDValue OffsVal = VectorWidth ?
2974 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2975 DAG.getConstant(Offs, dl, PtrTy);
2976 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2980 // N = N + Idx * ElementSize;
2981 SDValue IdxN = getValue(Idx);
2983 if (!IdxN.getValueType().isVector() && VectorWidth) {
2984 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2985 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2986 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2988 // If the index is smaller or larger than intptr_t, truncate or extend
2990 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2992 // If this is a multiply by a power of two, turn it into a shl
2993 // immediately. This is a very common case.
2994 if (ElementSize != 1) {
2995 if (ElementSize.isPowerOf2()) {
2996 unsigned Amt = ElementSize.logBase2();
2997 IdxN = DAG.getNode(ISD::SHL, dl,
2998 N.getValueType(), IdxN,
2999 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3001 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3002 IdxN = DAG.getNode(ISD::MUL, dl,
3003 N.getValueType(), IdxN, Scale);
3007 N = DAG.getNode(ISD::ADD, dl,
3008 N.getValueType(), N, IdxN);
3015 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3016 // If this is a fixed sized alloca in the entry block of the function,
3017 // allocate it statically on the stack.
3018 if (FuncInfo.StaticAllocaMap.count(&I))
3019 return; // getValue will auto-populate this.
3021 SDLoc dl = getCurSDLoc();
3022 Type *Ty = I.getAllocatedType();
3023 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3024 auto &DL = DAG.getDataLayout();
3025 uint64_t TySize = DL.getTypeAllocSize(Ty);
3027 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3029 SDValue AllocSize = getValue(I.getArraySize());
3031 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3032 if (AllocSize.getValueType() != IntPtr)
3033 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3035 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3037 DAG.getConstant(TySize, dl, IntPtr));
3039 // Handle alignment. If the requested alignment is less than or equal to
3040 // the stack alignment, ignore it. If the size is greater than or equal to
3041 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3042 unsigned StackAlign =
3043 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3044 if (Align <= StackAlign)
3047 // Round the size of the allocation up to the stack alignment size
3048 // by add SA-1 to the size.
3049 AllocSize = DAG.getNode(ISD::ADD, dl,
3050 AllocSize.getValueType(), AllocSize,
3051 DAG.getIntPtrConstant(StackAlign - 1, dl));
3053 // Mask out the low bits for alignment purposes.
3054 AllocSize = DAG.getNode(ISD::AND, dl,
3055 AllocSize.getValueType(), AllocSize,
3056 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3059 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3060 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3061 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3063 DAG.setRoot(DSA.getValue(1));
3065 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3068 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3070 return visitAtomicLoad(I);
3072 const Value *SV = I.getOperand(0);
3073 SDValue Ptr = getValue(SV);
3075 Type *Ty = I.getType();
3077 bool isVolatile = I.isVolatile();
3078 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3080 // The IR notion of invariant_load only guarantees that all *non-faulting*
3081 // invariant loads result in the same value. The MI notion of invariant load
3082 // guarantees that the load can be legally moved to any location within its
3083 // containing function. The MI notion of invariant_load is stronger than the
3084 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3085 // with a guarantee that the location being loaded from is dereferenceable
3086 // throughout the function's lifetime.
3088 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3089 isDereferenceablePointer(SV, DAG.getDataLayout());
3090 unsigned Alignment = I.getAlignment();
3093 I.getAAMetadata(AAInfo);
3094 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3096 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3097 SmallVector<EVT, 4> ValueVTs;
3098 SmallVector<uint64_t, 4> Offsets;
3099 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3100 unsigned NumValues = ValueVTs.size();
3105 bool ConstantMemory = false;
3106 if (isVolatile || NumValues > MaxParallelChains)
3107 // Serialize volatile loads with other side effects.
3109 else if (AA->pointsToConstantMemory(MemoryLocation(
3110 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3111 // Do not serialize (non-volatile) loads of constant memory with anything.
3112 Root = DAG.getEntryNode();
3113 ConstantMemory = true;
3115 // Do not serialize non-volatile loads against each other.
3116 Root = DAG.getRoot();
3119 SDLoc dl = getCurSDLoc();
3122 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3124 SmallVector<SDValue, 4> Values(NumValues);
3125 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3126 EVT PtrVT = Ptr.getValueType();
3127 unsigned ChainI = 0;
3128 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3129 // Serializing loads here may result in excessive register pressure, and
3130 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3131 // could recover a bit by hoisting nodes upward in the chain by recognizing
3132 // they are side-effect free or do not alias. The optimizer should really
3133 // avoid this case by converting large object/array copies to llvm.memcpy
3134 // (MaxParallelChains should always remain as failsafe).
3135 if (ChainI == MaxParallelChains) {
3136 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3137 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3138 makeArrayRef(Chains.data(), ChainI));
3142 SDValue A = DAG.getNode(ISD::ADD, dl,
3144 DAG.getConstant(Offsets[i], dl, PtrVT));
3145 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3146 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3147 isNonTemporal, isInvariant, Alignment, AAInfo,
3151 Chains[ChainI] = L.getValue(1);
3154 if (!ConstantMemory) {
3155 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3156 makeArrayRef(Chains.data(), ChainI));
3160 PendingLoads.push_back(Chain);
3163 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3164 DAG.getVTList(ValueVTs), Values));
3167 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3169 return visitAtomicStore(I);
3171 const Value *SrcV = I.getOperand(0);
3172 const Value *PtrV = I.getOperand(1);
3174 SmallVector<EVT, 4> ValueVTs;
3175 SmallVector<uint64_t, 4> Offsets;
3176 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3177 SrcV->getType(), ValueVTs, &Offsets);
3178 unsigned NumValues = ValueVTs.size();
3182 // Get the lowered operands. Note that we do this after
3183 // checking if NumResults is zero, because with zero results
3184 // the operands won't have values in the map.
3185 SDValue Src = getValue(SrcV);
3186 SDValue Ptr = getValue(PtrV);
3188 SDValue Root = getRoot();
3189 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3190 EVT PtrVT = Ptr.getValueType();
3191 bool isVolatile = I.isVolatile();
3192 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3193 unsigned Alignment = I.getAlignment();
3194 SDLoc dl = getCurSDLoc();
3197 I.getAAMetadata(AAInfo);
3199 unsigned ChainI = 0;
3200 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3201 // See visitLoad comments.
3202 if (ChainI == MaxParallelChains) {
3203 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3204 makeArrayRef(Chains.data(), ChainI));
3208 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3209 DAG.getConstant(Offsets[i], dl, PtrVT));
3210 SDValue St = DAG.getStore(Root, dl,
3211 SDValue(Src.getNode(), Src.getResNo() + i),
3212 Add, MachinePointerInfo(PtrV, Offsets[i]),
3213 isVolatile, isNonTemporal, Alignment, AAInfo);
3214 Chains[ChainI] = St;
3217 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3218 makeArrayRef(Chains.data(), ChainI));
3219 DAG.setRoot(StoreNode);
3222 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3223 SDLoc sdl = getCurSDLoc();
3225 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3226 Value *PtrOperand = I.getArgOperand(1);
3227 SDValue Ptr = getValue(PtrOperand);
3228 SDValue Src0 = getValue(I.getArgOperand(0));
3229 SDValue Mask = getValue(I.getArgOperand(3));
3230 EVT VT = Src0.getValueType();
3231 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3233 Alignment = DAG.getEVTAlignment(VT);
3236 I.getAAMetadata(AAInfo);
3238 MachineMemOperand *MMO =
3239 DAG.getMachineFunction().
3240 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3241 MachineMemOperand::MOStore, VT.getStoreSize(),
3243 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3245 DAG.setRoot(StoreNode);
3246 setValue(&I, StoreNode);
3249 // Get a uniform base for the Gather/Scatter intrinsic.
3250 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3251 // We try to represent it as a base pointer + vector of indices.
3252 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3253 // The first operand of the GEP may be a single pointer or a vector of pointers
3255 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3257 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3258 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3260 // When the first GEP operand is a single pointer - it is the uniform base we
3261 // are looking for. If first operand of the GEP is a splat vector - we
3262 // extract the spalt value and use it as a uniform base.
3263 // In all other cases the function returns 'false'.
3265 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3266 SelectionDAGBuilder* SDB) {
3268 SelectionDAG& DAG = SDB->DAG;
3269 LLVMContext &Context = *DAG.getContext();
3271 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3272 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3273 if (!GEP || GEP->getNumOperands() > 2)
3276 Value *GEPPtr = GEP->getPointerOperand();
3277 if (!GEPPtr->getType()->isVectorTy())
3279 else if (!(Ptr = getSplatValue(GEPPtr)))
3282 Value *IndexVal = GEP->getOperand(1);
3284 // The operands of the GEP may be defined in another basic block.
3285 // In this case we'll not find nodes for the operands.
3286 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3289 Base = SDB->getValue(Ptr);
3290 Index = SDB->getValue(IndexVal);
3292 // Suppress sign extension.
3293 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3294 if (SDB->findValue(Sext->getOperand(0))) {
3295 IndexVal = Sext->getOperand(0);
3296 Index = SDB->getValue(IndexVal);
3299 if (!Index.getValueType().isVector()) {
3300 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3301 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3302 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3303 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3308 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3309 SDLoc sdl = getCurSDLoc();
3311 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3312 Value *Ptr = I.getArgOperand(1);
3313 SDValue Src0 = getValue(I.getArgOperand(0));
3314 SDValue Mask = getValue(I.getArgOperand(3));
3315 EVT VT = Src0.getValueType();
3316 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3318 Alignment = DAG.getEVTAlignment(VT);
3319 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3322 I.getAAMetadata(AAInfo);
3326 Value *BasePtr = Ptr;
3327 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3329 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3330 MachineMemOperand *MMO = DAG.getMachineFunction().
3331 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3332 MachineMemOperand::MOStore, VT.getStoreSize(),
3335 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3336 Index = getValue(Ptr);
3338 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3339 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3341 DAG.setRoot(Scatter);
3342 setValue(&I, Scatter);
3345 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3346 SDLoc sdl = getCurSDLoc();
3348 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3349 Value *PtrOperand = I.getArgOperand(0);
3350 SDValue Ptr = getValue(PtrOperand);
3351 SDValue Src0 = getValue(I.getArgOperand(3));
3352 SDValue Mask = getValue(I.getArgOperand(2));
3354 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3355 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3356 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3358 Alignment = DAG.getEVTAlignment(VT);
3361 I.getAAMetadata(AAInfo);
3362 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3364 SDValue InChain = DAG.getRoot();
3365 if (AA->pointsToConstantMemory(MemoryLocation(
3366 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3368 // Do not serialize (non-volatile) loads of constant memory with anything.
3369 InChain = DAG.getEntryNode();
3372 MachineMemOperand *MMO =
3373 DAG.getMachineFunction().
3374 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3375 MachineMemOperand::MOLoad, VT.getStoreSize(),
3376 Alignment, AAInfo, Ranges);
3378 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3380 SDValue OutChain = Load.getValue(1);
3381 DAG.setRoot(OutChain);
3385 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3386 SDLoc sdl = getCurSDLoc();
3388 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3389 Value *Ptr = I.getArgOperand(0);
3390 SDValue Src0 = getValue(I.getArgOperand(3));
3391 SDValue Mask = getValue(I.getArgOperand(2));
3393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3394 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3395 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3397 Alignment = DAG.getEVTAlignment(VT);
3400 I.getAAMetadata(AAInfo);
3401 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3403 SDValue Root = DAG.getRoot();
3406 Value *BasePtr = Ptr;
3407 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3408 bool ConstantMemory = false;
3410 AA->pointsToConstantMemory(MemoryLocation(
3411 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3413 // Do not serialize (non-volatile) loads of constant memory with anything.
3414 Root = DAG.getEntryNode();
3415 ConstantMemory = true;
3418 MachineMemOperand *MMO =
3419 DAG.getMachineFunction().
3420 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3421 MachineMemOperand::MOLoad, VT.getStoreSize(),
3422 Alignment, AAInfo, Ranges);
3425 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3426 Index = getValue(Ptr);
3428 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3429 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3432 SDValue OutChain = Gather.getValue(1);
3433 if (!ConstantMemory)
3434 PendingLoads.push_back(OutChain);
3435 setValue(&I, Gather);
3438 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3439 SDLoc dl = getCurSDLoc();
3440 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3441 AtomicOrdering FailureOrder = I.getFailureOrdering();
3442 SynchronizationScope Scope = I.getSynchScope();
3444 SDValue InChain = getRoot();
3446 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3447 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3448 SDValue L = DAG.getAtomicCmpSwap(
3449 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3450 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3451 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3452 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3454 SDValue OutChain = L.getValue(2);
3457 DAG.setRoot(OutChain);
3460 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3461 SDLoc dl = getCurSDLoc();
3463 switch (I.getOperation()) {
3464 default: llvm_unreachable("Unknown atomicrmw operation");
3465 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3466 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3467 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3468 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3469 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3470 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3471 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3472 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3473 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3474 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3475 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3477 AtomicOrdering Order = I.getOrdering();
3478 SynchronizationScope Scope = I.getSynchScope();
3480 SDValue InChain = getRoot();
3483 DAG.getAtomic(NT, dl,
3484 getValue(I.getValOperand()).getSimpleValueType(),
3486 getValue(I.getPointerOperand()),
3487 getValue(I.getValOperand()),
3488 I.getPointerOperand(),
3489 /* Alignment=*/ 0, Order, Scope);
3491 SDValue OutChain = L.getValue(1);
3494 DAG.setRoot(OutChain);
3497 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3498 SDLoc dl = getCurSDLoc();
3499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3502 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3503 TLI.getPointerTy(DAG.getDataLayout()));
3504 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3505 TLI.getPointerTy(DAG.getDataLayout()));
3506 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3509 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3510 SDLoc dl = getCurSDLoc();
3511 AtomicOrdering Order = I.getOrdering();
3512 SynchronizationScope Scope = I.getSynchScope();
3514 SDValue InChain = getRoot();
3516 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3517 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3519 if (I.getAlignment() < VT.getSizeInBits() / 8)
3520 report_fatal_error("Cannot generate unaligned atomic load");
3522 MachineMemOperand *MMO =
3523 DAG.getMachineFunction().
3524 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3525 MachineMemOperand::MOVolatile |
3526 MachineMemOperand::MOLoad,
3528 I.getAlignment() ? I.getAlignment() :
3529 DAG.getEVTAlignment(VT));
3531 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3533 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3534 getValue(I.getPointerOperand()), MMO,
3537 SDValue OutChain = L.getValue(1);
3540 DAG.setRoot(OutChain);
3543 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3544 SDLoc dl = getCurSDLoc();
3546 AtomicOrdering Order = I.getOrdering();
3547 SynchronizationScope Scope = I.getSynchScope();
3549 SDValue InChain = getRoot();
3551 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3553 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3555 if (I.getAlignment() < VT.getSizeInBits() / 8)
3556 report_fatal_error("Cannot generate unaligned atomic store");
3559 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3561 getValue(I.getPointerOperand()),
3562 getValue(I.getValueOperand()),
3563 I.getPointerOperand(), I.getAlignment(),
3566 DAG.setRoot(OutChain);
3569 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3571 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3572 unsigned Intrinsic) {
3573 bool HasChain = !I.doesNotAccessMemory();
3574 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3576 // Build the operand list.
3577 SmallVector<SDValue, 8> Ops;
3578 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3580 // We don't need to serialize loads against other loads.
3581 Ops.push_back(DAG.getRoot());
3583 Ops.push_back(getRoot());
3587 // Info is set by getTgtMemInstrinsic
3588 TargetLowering::IntrinsicInfo Info;
3589 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3590 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3592 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3593 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3594 Info.opc == ISD::INTRINSIC_W_CHAIN)
3595 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3596 TLI.getPointerTy(DAG.getDataLayout())));
3598 // Add all operands of the call to the operand list.
3599 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3600 SDValue Op = getValue(I.getArgOperand(i));
3604 SmallVector<EVT, 4> ValueVTs;
3605 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3608 ValueVTs.push_back(MVT::Other);
3610 SDVTList VTs = DAG.getVTList(ValueVTs);
3614 if (IsTgtIntrinsic) {
3615 // This is target intrinsic that touches memory
3616 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3617 VTs, Ops, Info.memVT,
3618 MachinePointerInfo(Info.ptrVal, Info.offset),
3619 Info.align, Info.vol,
3620 Info.readMem, Info.writeMem, Info.size);
3621 } else if (!HasChain) {
3622 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3623 } else if (!I.getType()->isVoidTy()) {
3624 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3626 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3630 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3632 PendingLoads.push_back(Chain);
3637 if (!I.getType()->isVoidTy()) {
3638 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3639 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3640 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3643 setValue(&I, Result);
3647 /// GetSignificand - Get the significand and build it into a floating-point
3648 /// number with exponent of 1:
3650 /// Op = (Op & 0x007fffff) | 0x3f800000;
3652 /// where Op is the hexadecimal representation of floating point value.
3654 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3655 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3656 DAG.getConstant(0x007fffff, dl, MVT::i32));
3657 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3658 DAG.getConstant(0x3f800000, dl, MVT::i32));
3659 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3662 /// GetExponent - Get the exponent:
3664 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3666 /// where Op is the hexadecimal representation of floating point value.
3668 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3670 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3671 DAG.getConstant(0x7f800000, dl, MVT::i32));
3672 SDValue t1 = DAG.getNode(
3673 ISD::SRL, dl, MVT::i32, t0,
3674 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3675 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3676 DAG.getConstant(127, dl, MVT::i32));
3677 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3680 /// getF32Constant - Get 32-bit floating point constant.
3682 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3683 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3687 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3688 SelectionDAG &DAG) {
3689 // TODO: What fast-math-flags should be set on the floating-point nodes?
3691 // IntegerPartOfX = ((int32_t)(t0);
3692 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3694 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3695 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3696 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3698 // IntegerPartOfX <<= 23;
3699 IntegerPartOfX = DAG.getNode(
3700 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3701 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3702 DAG.getDataLayout())));
3704 SDValue TwoToFractionalPartOfX;
3705 if (LimitFloatPrecision <= 6) {
3706 // For floating-point precision of 6:
3708 // TwoToFractionalPartOfX =
3710 // (0.735607626f + 0.252464424f * x) * x;
3712 // error 0.0144103317, which is 6 bits
3713 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3714 getF32Constant(DAG, 0x3e814304, dl));
3715 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3716 getF32Constant(DAG, 0x3f3c50c8, dl));
3717 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3718 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3719 getF32Constant(DAG, 0x3f7f5e7e, dl));
3720 } else if (LimitFloatPrecision <= 12) {
3721 // For floating-point precision of 12:
3723 // TwoToFractionalPartOfX =
3726 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3728 // error 0.000107046256, which is 13 to 14 bits
3729 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3730 getF32Constant(DAG, 0x3da235e3, dl));
3731 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3732 getF32Constant(DAG, 0x3e65b8f3, dl));
3733 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3734 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3735 getF32Constant(DAG, 0x3f324b07, dl));
3736 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3737 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3738 getF32Constant(DAG, 0x3f7ff8fd, dl));
3739 } else { // LimitFloatPrecision <= 18
3740 // For floating-point precision of 18:
3742 // TwoToFractionalPartOfX =
3746 // (0.554906021e-1f +
3747 // (0.961591928e-2f +
3748 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3749 // error 2.47208000*10^(-7), which is better than 18 bits
3750 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3751 getF32Constant(DAG, 0x3924b03e, dl));
3752 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3753 getF32Constant(DAG, 0x3ab24b87, dl));
3754 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3755 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3756 getF32Constant(DAG, 0x3c1d8c17, dl));
3757 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3758 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3759 getF32Constant(DAG, 0x3d634a1d, dl));
3760 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3761 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3762 getF32Constant(DAG, 0x3e75fe14, dl));
3763 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3764 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3765 getF32Constant(DAG, 0x3f317234, dl));
3766 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3767 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3768 getF32Constant(DAG, 0x3f800000, dl));
3771 // Add the exponent into the result in integer domain.
3772 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3773 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3774 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3777 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3778 /// limited-precision mode.
3779 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3780 const TargetLowering &TLI) {
3781 if (Op.getValueType() == MVT::f32 &&
3782 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3784 // Put the exponent in the right bit position for later addition to the
3787 // #define LOG2OFe 1.4426950f
3788 // t0 = Op * LOG2OFe
3790 // TODO: What fast-math-flags should be set here?
3791 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3792 getF32Constant(DAG, 0x3fb8aa3b, dl));
3793 return getLimitedPrecisionExp2(t0, dl, DAG);
3796 // No special expansion.
3797 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3800 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3801 /// limited-precision mode.
3802 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3803 const TargetLowering &TLI) {
3805 // TODO: What fast-math-flags should be set on the floating-point nodes?
3807 if (Op.getValueType() == MVT::f32 &&
3808 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3809 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3811 // Scale the exponent by log(2) [0.69314718f].
3812 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3813 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3814 getF32Constant(DAG, 0x3f317218, dl));
3816 // Get the significand and build it into a floating-point number with
3818 SDValue X = GetSignificand(DAG, Op1, dl);
3820 SDValue LogOfMantissa;
3821 if (LimitFloatPrecision <= 6) {
3822 // For floating-point precision of 6:
3826 // (1.4034025f - 0.23903021f * x) * x;
3828 // error 0.0034276066, which is better than 8 bits
3829 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3830 getF32Constant(DAG, 0xbe74c456, dl));
3831 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3832 getF32Constant(DAG, 0x3fb3a2b1, dl));
3833 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3834 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3835 getF32Constant(DAG, 0x3f949a29, dl));
3836 } else if (LimitFloatPrecision <= 12) {
3837 // For floating-point precision of 12:
3843 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3845 // error 0.000061011436, which is 14 bits
3846 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3847 getF32Constant(DAG, 0xbd67b6d6, dl));
3848 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3849 getF32Constant(DAG, 0x3ee4f4b8, dl));
3850 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3851 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3852 getF32Constant(DAG, 0x3fbc278b, dl));
3853 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3854 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3855 getF32Constant(DAG, 0x40348e95, dl));
3856 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3857 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3858 getF32Constant(DAG, 0x3fdef31a, dl));
3859 } else { // LimitFloatPrecision <= 18
3860 // For floating-point precision of 18:
3868 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3870 // error 0.0000023660568, which is better than 18 bits
3871 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3872 getF32Constant(DAG, 0xbc91e5ac, dl));
3873 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3874 getF32Constant(DAG, 0x3e4350aa, dl));
3875 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3876 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3877 getF32Constant(DAG, 0x3f60d3e3, dl));
3878 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3879 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3880 getF32Constant(DAG, 0x4011cdf0, dl));
3881 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3882 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3883 getF32Constant(DAG, 0x406cfd1c, dl));
3884 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3885 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3886 getF32Constant(DAG, 0x408797cb, dl));
3887 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3888 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3889 getF32Constant(DAG, 0x4006dcab, dl));
3892 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3895 // No special expansion.
3896 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3899 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3900 /// limited-precision mode.
3901 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3902 const TargetLowering &TLI) {
3904 // TODO: What fast-math-flags should be set on the floating-point nodes?
3906 if (Op.getValueType() == MVT::f32 &&
3907 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3908 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3910 // Get the exponent.
3911 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3913 // Get the significand and build it into a floating-point number with
3915 SDValue X = GetSignificand(DAG, Op1, dl);
3917 // Different possible minimax approximations of significand in
3918 // floating-point for various degrees of accuracy over [1,2].
3919 SDValue Log2ofMantissa;
3920 if (LimitFloatPrecision <= 6) {
3921 // For floating-point precision of 6:
3923 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3925 // error 0.0049451742, which is more than 7 bits
3926 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3927 getF32Constant(DAG, 0xbeb08fe0, dl));
3928 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3929 getF32Constant(DAG, 0x40019463, dl));
3930 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3931 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3932 getF32Constant(DAG, 0x3fd6633d, dl));
3933 } else if (LimitFloatPrecision <= 12) {
3934 // For floating-point precision of 12:
3940 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3942 // error 0.0000876136000, which is better than 13 bits
3943 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3944 getF32Constant(DAG, 0xbda7262e, dl));
3945 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3946 getF32Constant(DAG, 0x3f25280b, dl));
3947 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3948 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3949 getF32Constant(DAG, 0x4007b923, dl));
3950 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3951 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3952 getF32Constant(DAG, 0x40823e2f, dl));
3953 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3954 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3955 getF32Constant(DAG, 0x4020d29c, dl));
3956 } else { // LimitFloatPrecision <= 18
3957 // For floating-point precision of 18:
3966 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3968 // error 0.0000018516, which is better than 18 bits
3969 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3970 getF32Constant(DAG, 0xbcd2769e, dl));
3971 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3972 getF32Constant(DAG, 0x3e8ce0b9, dl));
3973 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3974 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3975 getF32Constant(DAG, 0x3fa22ae7, dl));
3976 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3977 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3978 getF32Constant(DAG, 0x40525723, dl));
3979 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3980 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3981 getF32Constant(DAG, 0x40aaf200, dl));
3982 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3983 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3984 getF32Constant(DAG, 0x40c39dad, dl));
3985 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3986 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3987 getF32Constant(DAG, 0x4042902c, dl));
3990 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3993 // No special expansion.
3994 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3997 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3998 /// limited-precision mode.
3999 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4000 const TargetLowering &TLI) {
4002 // TODO: What fast-math-flags should be set on the floating-point nodes?
4004 if (Op.getValueType() == MVT::f32 &&
4005 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4006 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4008 // Scale the exponent by log10(2) [0.30102999f].
4009 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4010 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4011 getF32Constant(DAG, 0x3e9a209a, dl));
4013 // Get the significand and build it into a floating-point number with
4015 SDValue X = GetSignificand(DAG, Op1, dl);
4017 SDValue Log10ofMantissa;
4018 if (LimitFloatPrecision <= 6) {
4019 // For floating-point precision of 6:
4021 // Log10ofMantissa =
4023 // (0.60948995f - 0.10380950f * x) * x;
4025 // error 0.0014886165, which is 6 bits
4026 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4027 getF32Constant(DAG, 0xbdd49a13, dl));
4028 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4029 getF32Constant(DAG, 0x3f1c0789, dl));
4030 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4031 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4032 getF32Constant(DAG, 0x3f011300, dl));
4033 } else if (LimitFloatPrecision <= 12) {
4034 // For floating-point precision of 12:
4036 // Log10ofMantissa =
4039 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4041 // error 0.00019228036, which is better than 12 bits
4042 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4043 getF32Constant(DAG, 0x3d431f31, dl));
4044 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4045 getF32Constant(DAG, 0x3ea21fb2, dl));
4046 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4047 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4048 getF32Constant(DAG, 0x3f6ae232, dl));
4049 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4050 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4051 getF32Constant(DAG, 0x3f25f7c3, dl));
4052 } else { // LimitFloatPrecision <= 18
4053 // For floating-point precision of 18:
4055 // Log10ofMantissa =
4060 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4062 // error 0.0000037995730, which is better than 18 bits
4063 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4064 getF32Constant(DAG, 0x3c5d51ce, dl));
4065 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4066 getF32Constant(DAG, 0x3e00685a, dl));
4067 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4068 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4069 getF32Constant(DAG, 0x3efb6798, dl));
4070 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4071 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4072 getF32Constant(DAG, 0x3f88d192, dl));
4073 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4074 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4075 getF32Constant(DAG, 0x3fc4316c, dl));
4076 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4077 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4078 getF32Constant(DAG, 0x3f57ce70, dl));
4081 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4084 // No special expansion.
4085 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4088 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4089 /// limited-precision mode.
4090 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4091 const TargetLowering &TLI) {
4092 if (Op.getValueType() == MVT::f32 &&
4093 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4094 return getLimitedPrecisionExp2(Op, dl, DAG);
4096 // No special expansion.
4097 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4100 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4101 /// limited-precision mode with x == 10.0f.
4102 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4103 SelectionDAG &DAG, const TargetLowering &TLI) {
4104 bool IsExp10 = false;
4105 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4106 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4107 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4109 IsExp10 = LHSC->isExactlyValue(Ten);
4113 // TODO: What fast-math-flags should be set on the FMUL node?
4115 // Put the exponent in the right bit position for later addition to the
4118 // #define LOG2OF10 3.3219281f
4119 // t0 = Op * LOG2OF10;
4120 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4121 getF32Constant(DAG, 0x40549a78, dl));
4122 return getLimitedPrecisionExp2(t0, dl, DAG);
4125 // No special expansion.
4126 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4130 /// ExpandPowI - Expand a llvm.powi intrinsic.
4131 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4132 SelectionDAG &DAG) {
4133 // If RHS is a constant, we can expand this out to a multiplication tree,
4134 // otherwise we end up lowering to a call to __powidf2 (for example). When
4135 // optimizing for size, we only want to do this if the expansion would produce
4136 // a small number of multiplies, otherwise we do the full expansion.
4137 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4138 // Get the exponent as a positive value.
4139 unsigned Val = RHSC->getSExtValue();
4140 if ((int)Val < 0) Val = -Val;
4142 // powi(x, 0) -> 1.0
4144 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4146 const Function *F = DAG.getMachineFunction().getFunction();
4147 if (!F->optForSize() ||
4148 // If optimizing for size, don't insert too many multiplies.
4149 // This inserts up to 5 multiplies.
4150 countPopulation(Val) + Log2_32(Val) < 7) {
4151 // We use the simple binary decomposition method to generate the multiply
4152 // sequence. There are more optimal ways to do this (for example,
4153 // powi(x,15) generates one more multiply than it should), but this has
4154 // the benefit of being both really simple and much better than a libcall.
4155 SDValue Res; // Logically starts equal to 1.0
4156 SDValue CurSquare = LHS;
4157 // TODO: Intrinsics should have fast-math-flags that propagate to these
4162 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4164 Res = CurSquare; // 1.0*CurSquare.
4167 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4168 CurSquare, CurSquare);
4172 // If the original was negative, invert the result, producing 1/(x*x*x).
4173 if (RHSC->getSExtValue() < 0)
4174 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4175 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4180 // Otherwise, expand to a libcall.
4181 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4184 // getTruncatedArgReg - Find underlying register used for an truncated
4186 static unsigned getTruncatedArgReg(const SDValue &N) {
4187 if (N.getOpcode() != ISD::TRUNCATE)
4190 const SDValue &Ext = N.getOperand(0);
4191 if (Ext.getOpcode() == ISD::AssertZext ||
4192 Ext.getOpcode() == ISD::AssertSext) {
4193 const SDValue &CFR = Ext.getOperand(0);
4194 if (CFR.getOpcode() == ISD::CopyFromReg)
4195 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4196 if (CFR.getOpcode() == ISD::TRUNCATE)
4197 return getTruncatedArgReg(CFR);
4202 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4203 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4204 /// At the end of instruction selection, they will be inserted to the entry BB.
4205 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4206 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4207 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4208 const Argument *Arg = dyn_cast<Argument>(V);
4212 MachineFunction &MF = DAG.getMachineFunction();
4213 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4215 // Ignore inlined function arguments here.
4217 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4218 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4221 Optional<MachineOperand> Op;
4222 // Some arguments' frame index is recorded during argument lowering.
4223 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4224 Op = MachineOperand::CreateFI(FI);
4226 if (!Op && N.getNode()) {
4228 if (N.getOpcode() == ISD::CopyFromReg)
4229 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4231 Reg = getTruncatedArgReg(N);
4232 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4233 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4234 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4239 Op = MachineOperand::CreateReg(Reg, false);
4243 // Check if ValueMap has reg number.
4244 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4245 if (VMI != FuncInfo.ValueMap.end())
4246 Op = MachineOperand::CreateReg(VMI->second, false);
4249 if (!Op && N.getNode())
4250 // Check if frame index is available.
4251 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4252 if (FrameIndexSDNode *FINode =
4253 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4254 Op = MachineOperand::CreateFI(FINode->getIndex());
4259 assert(Variable->isValidLocationForIntrinsic(DL) &&
4260 "Expected inlined-at fields to agree");
4262 FuncInfo.ArgDbgValues.push_back(
4263 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4264 Op->getReg(), Offset, Variable, Expr));
4266 FuncInfo.ArgDbgValues.push_back(
4267 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4270 .addMetadata(Variable)
4271 .addMetadata(Expr));
4276 // VisualStudio defines setjmp as _setjmp
4277 #if defined(_MSC_VER) && defined(setjmp) && \
4278 !defined(setjmp_undefined_for_msvc)
4279 # pragma push_macro("setjmp")
4281 # define setjmp_undefined_for_msvc
4284 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4285 /// we want to emit this as a call to a named external function, return the name
4286 /// otherwise lower it and return null.
4288 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4289 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4290 SDLoc sdl = getCurSDLoc();
4291 DebugLoc dl = getCurDebugLoc();
4294 switch (Intrinsic) {
4296 // By default, turn this into a target intrinsic node.
4297 visitTargetIntrinsic(I, Intrinsic);
4299 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4300 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4301 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4302 case Intrinsic::returnaddress:
4303 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4304 TLI.getPointerTy(DAG.getDataLayout()),
4305 getValue(I.getArgOperand(0))));
4307 case Intrinsic::frameaddress:
4308 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4309 TLI.getPointerTy(DAG.getDataLayout()),
4310 getValue(I.getArgOperand(0))));
4312 case Intrinsic::read_register: {
4313 Value *Reg = I.getArgOperand(0);
4314 SDValue Chain = getRoot();
4316 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4317 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4318 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4319 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4321 DAG.setRoot(Res.getValue(1));
4324 case Intrinsic::write_register: {
4325 Value *Reg = I.getArgOperand(0);
4326 Value *RegValue = I.getArgOperand(1);
4327 SDValue Chain = getRoot();
4329 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4330 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4331 RegName, getValue(RegValue)));
4334 case Intrinsic::setjmp:
4335 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4336 case Intrinsic::longjmp:
4337 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4338 case Intrinsic::memcpy: {
4339 // FIXME: this definition of "user defined address space" is x86-specific
4340 // Assert for address < 256 since we support only user defined address
4342 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4344 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4346 "Unknown address space");
4347 SDValue Op1 = getValue(I.getArgOperand(0));
4348 SDValue Op2 = getValue(I.getArgOperand(1));
4349 SDValue Op3 = getValue(I.getArgOperand(2));
4350 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4352 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4353 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4354 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4355 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4357 MachinePointerInfo(I.getArgOperand(0)),
4358 MachinePointerInfo(I.getArgOperand(1)));
4359 updateDAGForMaybeTailCall(MC);
4362 case Intrinsic::memset: {
4363 // FIXME: this definition of "user defined address space" is x86-specific
4364 // Assert for address < 256 since we support only user defined address
4366 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4368 "Unknown address space");
4369 SDValue Op1 = getValue(I.getArgOperand(0));
4370 SDValue Op2 = getValue(I.getArgOperand(1));
4371 SDValue Op3 = getValue(I.getArgOperand(2));
4372 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4374 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4375 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4376 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4377 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4378 isTC, MachinePointerInfo(I.getArgOperand(0)));
4379 updateDAGForMaybeTailCall(MS);
4382 case Intrinsic::memmove: {
4383 // FIXME: this definition of "user defined address space" is x86-specific
4384 // Assert for address < 256 since we support only user defined address
4386 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4388 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4390 "Unknown address space");
4391 SDValue Op1 = getValue(I.getArgOperand(0));
4392 SDValue Op2 = getValue(I.getArgOperand(1));
4393 SDValue Op3 = getValue(I.getArgOperand(2));
4394 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4396 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4397 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4398 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4399 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4400 isTC, MachinePointerInfo(I.getArgOperand(0)),
4401 MachinePointerInfo(I.getArgOperand(1)));
4402 updateDAGForMaybeTailCall(MM);
4405 case Intrinsic::dbg_declare: {
4406 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4407 DILocalVariable *Variable = DI.getVariable();
4408 DIExpression *Expression = DI.getExpression();
4409 const Value *Address = DI.getAddress();
4410 assert(Variable && "Missing variable");
4412 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4416 // Check if address has undef value.
4417 if (isa<UndefValue>(Address) ||
4418 (Address->use_empty() && !isa<Argument>(Address))) {
4419 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4423 SDValue &N = NodeMap[Address];
4424 if (!N.getNode() && isa<Argument>(Address))
4425 // Check unused arguments map.
4426 N = UnusedArgNodeMap[Address];
4429 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4430 Address = BCI->getOperand(0);
4431 // Parameters are handled specially.
4432 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4434 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4436 if (isParameter && !AI) {
4437 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4439 // Byval parameter. We have a frame index at this point.
4440 SDV = DAG.getFrameIndexDbgValue(
4441 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4443 // Address is an argument, so try to emit its dbg value using
4444 // virtual register info from the FuncInfo.ValueMap.
4445 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4450 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4451 true, 0, dl, SDNodeOrder);
4453 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4455 // If Address is an argument then try to emit its dbg value using
4456 // virtual register info from the FuncInfo.ValueMap.
4457 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4459 // If variable is pinned by a alloca in dominating bb then
4460 // use StaticAllocaMap.
4461 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4462 if (AI->getParent() != DI.getParent()) {
4463 DenseMap<const AllocaInst*, int>::iterator SI =
4464 FuncInfo.StaticAllocaMap.find(AI);
4465 if (SI != FuncInfo.StaticAllocaMap.end()) {
4466 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4467 0, dl, SDNodeOrder);
4468 DAG.AddDbgValue(SDV, nullptr, false);
4473 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4478 case Intrinsic::dbg_value: {
4479 const DbgValueInst &DI = cast<DbgValueInst>(I);
4480 assert(DI.getVariable() && "Missing variable");
4482 DILocalVariable *Variable = DI.getVariable();
4483 DIExpression *Expression = DI.getExpression();
4484 uint64_t Offset = DI.getOffset();
4485 const Value *V = DI.getValue();
4490 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4491 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4493 DAG.AddDbgValue(SDV, nullptr, false);
4495 // Do not use getValue() in here; we don't want to generate code at
4496 // this point if it hasn't been done yet.
4497 SDValue N = NodeMap[V];
4498 if (!N.getNode() && isa<Argument>(V))
4499 // Check unused arguments map.
4500 N = UnusedArgNodeMap[V];
4502 // A dbg.value for an alloca is always indirect.
4503 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4504 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4506 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4507 IsIndirect, Offset, dl, SDNodeOrder);
4508 DAG.AddDbgValue(SDV, N.getNode(), false);
4510 } else if (!V->use_empty() ) {
4511 // Do not call getValue(V) yet, as we don't want to generate code.
4512 // Remember it for later.
4513 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4514 DanglingDebugInfoMap[V] = DDI;
4516 // We may expand this to cover more cases. One case where we have no
4517 // data available is an unreferenced parameter.
4518 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4522 // Build a debug info table entry.
4523 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4524 V = BCI->getOperand(0);
4525 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4526 // Don't handle byval struct arguments or VLAs, for example.
4528 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4529 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4532 DenseMap<const AllocaInst*, int>::iterator SI =
4533 FuncInfo.StaticAllocaMap.find(AI);
4534 if (SI == FuncInfo.StaticAllocaMap.end())
4535 return nullptr; // VLAs.
4539 case Intrinsic::eh_typeid_for: {
4540 // Find the type id for the given typeinfo.
4541 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4542 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4543 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4548 case Intrinsic::eh_return_i32:
4549 case Intrinsic::eh_return_i64:
4550 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4551 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4554 getValue(I.getArgOperand(0)),
4555 getValue(I.getArgOperand(1))));
4557 case Intrinsic::eh_unwind_init:
4558 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4560 case Intrinsic::eh_dwarf_cfa: {
4561 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4562 TLI.getPointerTy(DAG.getDataLayout()));
4563 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4564 CfaArg.getValueType(),
4565 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4566 CfaArg.getValueType()),
4568 SDValue FA = DAG.getNode(
4569 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4570 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4571 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4575 case Intrinsic::eh_sjlj_callsite: {
4576 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4577 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4578 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4579 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4581 MMI.setCurrentCallSite(CI->getZExtValue());
4584 case Intrinsic::eh_sjlj_functioncontext: {
4585 // Get and store the index of the function context.
4586 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4588 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4589 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4590 MFI->setFunctionContextIndex(FI);
4593 case Intrinsic::eh_sjlj_setjmp: {
4596 Ops[1] = getValue(I.getArgOperand(0));
4597 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4598 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4599 setValue(&I, Op.getValue(0));
4600 DAG.setRoot(Op.getValue(1));
4603 case Intrinsic::eh_sjlj_longjmp: {
4604 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4605 getRoot(), getValue(I.getArgOperand(0))));
4608 case Intrinsic::eh_sjlj_setup_dispatch: {
4609 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4614 case Intrinsic::masked_gather:
4615 visitMaskedGather(I);
4617 case Intrinsic::masked_load:
4620 case Intrinsic::masked_scatter:
4621 visitMaskedScatter(I);
4623 case Intrinsic::masked_store:
4624 visitMaskedStore(I);
4626 case Intrinsic::x86_mmx_pslli_w:
4627 case Intrinsic::x86_mmx_pslli_d:
4628 case Intrinsic::x86_mmx_pslli_q:
4629 case Intrinsic::x86_mmx_psrli_w:
4630 case Intrinsic::x86_mmx_psrli_d:
4631 case Intrinsic::x86_mmx_psrli_q:
4632 case Intrinsic::x86_mmx_psrai_w:
4633 case Intrinsic::x86_mmx_psrai_d: {
4634 SDValue ShAmt = getValue(I.getArgOperand(1));
4635 if (isa<ConstantSDNode>(ShAmt)) {
4636 visitTargetIntrinsic(I, Intrinsic);
4639 unsigned NewIntrinsic = 0;
4640 EVT ShAmtVT = MVT::v2i32;
4641 switch (Intrinsic) {
4642 case Intrinsic::x86_mmx_pslli_w:
4643 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4645 case Intrinsic::x86_mmx_pslli_d:
4646 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4648 case Intrinsic::x86_mmx_pslli_q:
4649 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4651 case Intrinsic::x86_mmx_psrli_w:
4652 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4654 case Intrinsic::x86_mmx_psrli_d:
4655 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4657 case Intrinsic::x86_mmx_psrli_q:
4658 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4660 case Intrinsic::x86_mmx_psrai_w:
4661 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4663 case Intrinsic::x86_mmx_psrai_d:
4664 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4666 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4669 // The vector shift intrinsics with scalars uses 32b shift amounts but
4670 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4672 // We must do this early because v2i32 is not a legal type.
4675 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4676 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4677 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4678 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4679 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4680 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4681 getValue(I.getArgOperand(0)), ShAmt);
4685 case Intrinsic::convertff:
4686 case Intrinsic::convertfsi:
4687 case Intrinsic::convertfui:
4688 case Intrinsic::convertsif:
4689 case Intrinsic::convertuif:
4690 case Intrinsic::convertss:
4691 case Intrinsic::convertsu:
4692 case Intrinsic::convertus:
4693 case Intrinsic::convertuu: {
4694 ISD::CvtCode Code = ISD::CVT_INVALID;
4695 switch (Intrinsic) {
4696 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4697 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4698 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4699 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4700 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4701 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4702 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4703 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4704 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4705 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4707 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4708 const Value *Op1 = I.getArgOperand(0);
4709 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4710 DAG.getValueType(DestVT),
4711 DAG.getValueType(getValue(Op1).getValueType()),
4712 getValue(I.getArgOperand(1)),
4713 getValue(I.getArgOperand(2)),
4718 case Intrinsic::powi:
4719 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4720 getValue(I.getArgOperand(1)), DAG));
4722 case Intrinsic::log:
4723 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4725 case Intrinsic::log2:
4726 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4728 case Intrinsic::log10:
4729 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4731 case Intrinsic::exp:
4732 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4734 case Intrinsic::exp2:
4735 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4737 case Intrinsic::pow:
4738 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4739 getValue(I.getArgOperand(1)), DAG, TLI));
4741 case Intrinsic::sqrt:
4742 case Intrinsic::fabs:
4743 case Intrinsic::sin:
4744 case Intrinsic::cos:
4745 case Intrinsic::floor:
4746 case Intrinsic::ceil:
4747 case Intrinsic::trunc:
4748 case Intrinsic::rint:
4749 case Intrinsic::nearbyint:
4750 case Intrinsic::round: {
4752 switch (Intrinsic) {
4753 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4754 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4755 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4756 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4757 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4758 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4759 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4760 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4761 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4762 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4763 case Intrinsic::round: Opcode = ISD::FROUND; break;
4766 setValue(&I, DAG.getNode(Opcode, sdl,
4767 getValue(I.getArgOperand(0)).getValueType(),
4768 getValue(I.getArgOperand(0))));
4771 case Intrinsic::minnum:
4772 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4773 getValue(I.getArgOperand(0)).getValueType(),
4774 getValue(I.getArgOperand(0)),
4775 getValue(I.getArgOperand(1))));
4777 case Intrinsic::maxnum:
4778 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4779 getValue(I.getArgOperand(0)).getValueType(),
4780 getValue(I.getArgOperand(0)),
4781 getValue(I.getArgOperand(1))));
4783 case Intrinsic::copysign:
4784 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4785 getValue(I.getArgOperand(0)).getValueType(),
4786 getValue(I.getArgOperand(0)),
4787 getValue(I.getArgOperand(1))));
4789 case Intrinsic::fma:
4790 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4791 getValue(I.getArgOperand(0)).getValueType(),
4792 getValue(I.getArgOperand(0)),
4793 getValue(I.getArgOperand(1)),
4794 getValue(I.getArgOperand(2))));
4796 case Intrinsic::fmuladd: {
4797 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4798 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4799 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4800 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4801 getValue(I.getArgOperand(0)).getValueType(),
4802 getValue(I.getArgOperand(0)),
4803 getValue(I.getArgOperand(1)),
4804 getValue(I.getArgOperand(2))));
4806 // TODO: Intrinsic calls should have fast-math-flags.
4807 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4808 getValue(I.getArgOperand(0)).getValueType(),
4809 getValue(I.getArgOperand(0)),
4810 getValue(I.getArgOperand(1)));
4811 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4812 getValue(I.getArgOperand(0)).getValueType(),
4814 getValue(I.getArgOperand(2)));
4819 case Intrinsic::convert_to_fp16:
4820 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4821 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4822 getValue(I.getArgOperand(0)),
4823 DAG.getTargetConstant(0, sdl,
4826 case Intrinsic::convert_from_fp16:
4827 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4828 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4829 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4830 getValue(I.getArgOperand(0)))));
4832 case Intrinsic::pcmarker: {
4833 SDValue Tmp = getValue(I.getArgOperand(0));
4834 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4837 case Intrinsic::readcyclecounter: {
4838 SDValue Op = getRoot();
4839 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4840 DAG.getVTList(MVT::i64, MVT::Other), Op);
4842 DAG.setRoot(Res.getValue(1));
4845 case Intrinsic::bswap:
4846 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4847 getValue(I.getArgOperand(0)).getValueType(),
4848 getValue(I.getArgOperand(0))));
4850 case Intrinsic::uabsdiff:
4851 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4852 getValue(I.getArgOperand(0)).getValueType(),
4853 getValue(I.getArgOperand(0)),
4854 getValue(I.getArgOperand(1))));
4856 case Intrinsic::sabsdiff:
4857 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4858 getValue(I.getArgOperand(0)).getValueType(),
4859 getValue(I.getArgOperand(0)),
4860 getValue(I.getArgOperand(1))));
4862 case Intrinsic::cttz: {
4863 SDValue Arg = getValue(I.getArgOperand(0));
4864 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4865 EVT Ty = Arg.getValueType();
4866 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4870 case Intrinsic::ctlz: {
4871 SDValue Arg = getValue(I.getArgOperand(0));
4872 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4873 EVT Ty = Arg.getValueType();
4874 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4878 case Intrinsic::ctpop: {
4879 SDValue Arg = getValue(I.getArgOperand(0));
4880 EVT Ty = Arg.getValueType();
4881 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4884 case Intrinsic::stacksave: {
4885 SDValue Op = getRoot();
4887 ISD::STACKSAVE, sdl,
4888 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4890 DAG.setRoot(Res.getValue(1));
4893 case Intrinsic::stackrestore: {
4894 Res = getValue(I.getArgOperand(0));
4895 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4898 case Intrinsic::stackprotector: {
4899 // Emit code into the DAG to store the stack guard onto the stack.
4900 MachineFunction &MF = DAG.getMachineFunction();
4901 MachineFrameInfo *MFI = MF.getFrameInfo();
4902 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4903 SDValue Src, Chain = getRoot();
4904 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4905 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4907 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4908 // global variable __stack_chk_guard.
4910 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4911 if (BC->getOpcode() == Instruction::BitCast)
4912 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4914 if (GV && TLI.useLoadStackGuardNode()) {
4915 // Emit a LOAD_STACK_GUARD node.
4916 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4918 MachinePointerInfo MPInfo(GV);
4919 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4920 unsigned Flags = MachineMemOperand::MOLoad |
4921 MachineMemOperand::MOInvariant;
4922 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4923 PtrTy.getSizeInBits() / 8,
4924 DAG.getEVTAlignment(PtrTy));
4925 Node->setMemRefs(MemRefs, MemRefs + 1);
4927 // Copy the guard value to a virtual register so that it can be
4928 // retrieved in the epilogue.
4929 Src = SDValue(Node, 0);
4930 const TargetRegisterClass *RC =
4931 TLI.getRegClassFor(Src.getSimpleValueType());
4932 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4934 SPDescriptor.setGuardReg(Reg);
4935 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4937 Src = getValue(I.getArgOperand(0)); // The guard's value.
4940 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4942 int FI = FuncInfo.StaticAllocaMap[Slot];
4943 MFI->setStackProtectorIndex(FI);
4945 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4947 // Store the stack protector onto the stack.
4948 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4949 DAG.getMachineFunction(), FI),
4955 case Intrinsic::objectsize: {
4956 // If we don't know by now, we're never going to know.
4957 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4959 assert(CI && "Non-constant type in __builtin_object_size?");
4961 SDValue Arg = getValue(I.getCalledValue());
4962 EVT Ty = Arg.getValueType();
4965 Res = DAG.getConstant(-1ULL, sdl, Ty);
4967 Res = DAG.getConstant(0, sdl, Ty);
4972 case Intrinsic::annotation:
4973 case Intrinsic::ptr_annotation:
4974 // Drop the intrinsic, but forward the value
4975 setValue(&I, getValue(I.getOperand(0)));
4977 case Intrinsic::assume:
4978 case Intrinsic::var_annotation:
4979 // Discard annotate attributes and assumptions
4982 case Intrinsic::init_trampoline: {
4983 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4987 Ops[1] = getValue(I.getArgOperand(0));
4988 Ops[2] = getValue(I.getArgOperand(1));
4989 Ops[3] = getValue(I.getArgOperand(2));
4990 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4991 Ops[5] = DAG.getSrcValue(F);
4993 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4998 case Intrinsic::adjust_trampoline: {
4999 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5000 TLI.getPointerTy(DAG.getDataLayout()),
5001 getValue(I.getArgOperand(0))));
5004 case Intrinsic::gcroot:
5006 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5007 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5009 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5010 GFI->addStackRoot(FI->getIndex(), TypeMap);
5013 case Intrinsic::gcread:
5014 case Intrinsic::gcwrite:
5015 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5016 case Intrinsic::flt_rounds:
5017 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5020 case Intrinsic::expect: {
5021 // Just replace __builtin_expect(exp, c) with EXP.
5022 setValue(&I, getValue(I.getArgOperand(0)));
5026 case Intrinsic::debugtrap:
5027 case Intrinsic::trap: {
5028 StringRef TrapFuncName =
5030 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5031 .getValueAsString();
5032 if (TrapFuncName.empty()) {
5033 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5034 ISD::TRAP : ISD::DEBUGTRAP;
5035 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5038 TargetLowering::ArgListTy Args;
5040 TargetLowering::CallLoweringInfo CLI(DAG);
5041 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5042 CallingConv::C, I.getType(),
5043 DAG.getExternalSymbol(TrapFuncName.data(),
5044 TLI.getPointerTy(DAG.getDataLayout())),
5045 std::move(Args), 0);
5047 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5048 DAG.setRoot(Result.second);
5052 case Intrinsic::uadd_with_overflow:
5053 case Intrinsic::sadd_with_overflow:
5054 case Intrinsic::usub_with_overflow:
5055 case Intrinsic::ssub_with_overflow:
5056 case Intrinsic::umul_with_overflow:
5057 case Intrinsic::smul_with_overflow: {
5059 switch (Intrinsic) {
5060 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5061 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5062 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5063 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5064 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5065 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5066 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5068 SDValue Op1 = getValue(I.getArgOperand(0));
5069 SDValue Op2 = getValue(I.getArgOperand(1));
5071 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5072 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5075 case Intrinsic::prefetch: {
5077 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5079 Ops[1] = getValue(I.getArgOperand(0));
5080 Ops[2] = getValue(I.getArgOperand(1));
5081 Ops[3] = getValue(I.getArgOperand(2));
5082 Ops[4] = getValue(I.getArgOperand(3));
5083 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5084 DAG.getVTList(MVT::Other), Ops,
5085 EVT::getIntegerVT(*Context, 8),
5086 MachinePointerInfo(I.getArgOperand(0)),
5088 false, /* volatile */
5090 rw==1)); /* write */
5093 case Intrinsic::lifetime_start:
5094 case Intrinsic::lifetime_end: {
5095 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5096 // Stack coloring is not enabled in O0, discard region information.
5097 if (TM.getOptLevel() == CodeGenOpt::None)
5100 SmallVector<Value *, 4> Allocas;
5101 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5103 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5104 E = Allocas.end(); Object != E; ++Object) {
5105 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5107 // Could not find an Alloca.
5108 if (!LifetimeObject)
5111 // First check that the Alloca is static, otherwise it won't have a
5112 // valid frame index.
5113 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5114 if (SI == FuncInfo.StaticAllocaMap.end())
5117 int FI = SI->second;
5122 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5123 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5125 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5130 case Intrinsic::invariant_start:
5131 // Discard region information.
5132 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5134 case Intrinsic::invariant_end:
5135 // Discard region information.
5137 case Intrinsic::stackprotectorcheck: {
5138 // Do not actually emit anything for this basic block. Instead we initialize
5139 // the stack protector descriptor and export the guard variable so we can
5140 // access it in FinishBasicBlock.
5141 const BasicBlock *BB = I.getParent();
5142 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5143 ExportFromCurrentBlock(SPDescriptor.getGuard());
5145 // Flush our exports since we are going to process a terminator.
5146 (void)getControlRoot();
5149 case Intrinsic::clear_cache:
5150 return TLI.getClearCacheBuiltinName();
5151 case Intrinsic::eh_actions:
5152 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5154 case Intrinsic::donothing:
5157 case Intrinsic::experimental_stackmap: {
5161 case Intrinsic::experimental_patchpoint_void:
5162 case Intrinsic::experimental_patchpoint_i64: {
5163 visitPatchpoint(&I);
5166 case Intrinsic::experimental_gc_statepoint: {
5170 case Intrinsic::experimental_gc_result_int:
5171 case Intrinsic::experimental_gc_result_float:
5172 case Intrinsic::experimental_gc_result_ptr:
5173 case Intrinsic::experimental_gc_result: {
5177 case Intrinsic::experimental_gc_relocate: {
5181 case Intrinsic::instrprof_increment:
5182 llvm_unreachable("instrprof failed to lower an increment");
5184 case Intrinsic::localescape: {
5185 MachineFunction &MF = DAG.getMachineFunction();
5186 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5188 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5189 // is the same on all targets.
5190 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5191 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5192 if (isa<ConstantPointerNull>(Arg))
5193 continue; // Skip null pointers. They represent a hole in index space.
5194 AllocaInst *Slot = cast<AllocaInst>(Arg);
5195 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5196 "can only escape static allocas");
5197 int FI = FuncInfo.StaticAllocaMap[Slot];
5198 MCSymbol *FrameAllocSym =
5199 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5200 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5201 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5202 TII->get(TargetOpcode::LOCAL_ESCAPE))
5203 .addSym(FrameAllocSym)
5210 case Intrinsic::localrecover: {
5211 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5212 MachineFunction &MF = DAG.getMachineFunction();
5213 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5215 // Get the symbol that defines the frame offset.
5216 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5217 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5218 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5219 MCSymbol *FrameAllocSym =
5220 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5221 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5223 // Create a MCSymbol for the label to avoid any target lowering
5224 // that would make this PC relative.
5225 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5227 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5229 // Add the offset to the FP.
5230 Value *FP = I.getArgOperand(1);
5231 SDValue FPVal = getValue(FP);
5232 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5237 case Intrinsic::eh_begincatch:
5238 case Intrinsic::eh_endcatch:
5239 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5240 case Intrinsic::eh_exceptioncode_old: {
5241 unsigned Reg = TLI.getExceptionPointerRegister();
5242 assert(Reg && "cannot get exception code on this platform");
5243 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5244 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5245 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5246 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5248 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5249 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5254 case Intrinsic::eh_exceptionpointer:
5255 case Intrinsic::eh_exceptioncode: {
5256 // Get the exception pointer vreg, copy from it, and resize it to fit.
5257 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5258 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5259 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5260 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5262 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5263 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5270 std::pair<SDValue, SDValue>
5271 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5272 const BasicBlock *EHPadBB) {
5273 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5274 MCSymbol *BeginLabel = nullptr;
5277 // Insert a label before the invoke call to mark the try range. This can be
5278 // used to detect deletion of the invoke via the MachineModuleInfo.
5279 BeginLabel = MMI.getContext().createTempSymbol();
5281 // For SjLj, keep track of which landing pads go with which invokes
5282 // so as to maintain the ordering of pads in the LSDA.
5283 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5284 if (CallSiteIndex) {
5285 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5286 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5288 // Now that the call site is handled, stop tracking it.
5289 MMI.setCurrentCallSite(0);
5292 // Both PendingLoads and PendingExports must be flushed here;
5293 // this call might not return.
5295 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5297 CLI.setChain(getRoot());
5299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5300 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5302 assert((CLI.IsTailCall || Result.second.getNode()) &&
5303 "Non-null chain expected with non-tail call!");
5304 assert((Result.second.getNode() || !Result.first.getNode()) &&
5305 "Null value expected with tail call!");
5307 if (!Result.second.getNode()) {
5308 // As a special case, a null chain means that a tail call has been emitted
5309 // and the DAG root is already updated.
5312 // Since there's no actual continuation from this block, nothing can be
5313 // relying on us setting vregs for them.
5314 PendingExports.clear();
5316 DAG.setRoot(Result.second);
5320 // Insert a label at the end of the invoke call to mark the try range. This
5321 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5322 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5323 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5325 // Inform MachineModuleInfo of range.
5326 if (MMI.hasEHFunclets()) {
5327 WinEHFuncInfo &EHInfo =
5328 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5329 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5331 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5338 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5340 const BasicBlock *EHPadBB) {
5341 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5342 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5343 Type *RetTy = FTy->getReturnType();
5345 TargetLowering::ArgListTy Args;
5346 TargetLowering::ArgListEntry Entry;
5347 Args.reserve(CS.arg_size());
5349 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5351 const Value *V = *i;
5354 if (V->getType()->isEmptyTy())
5357 SDValue ArgNode = getValue(V);
5358 Entry.Node = ArgNode; Entry.Ty = V->getType();
5360 // Skip the first return-type Attribute to get to params.
5361 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5362 Args.push_back(Entry);
5364 // If we have an explicit sret argument that is an Instruction, (i.e., it
5365 // might point to function-local memory), we can't meaningfully tail-call.
5366 if (Entry.isSRet && isa<Instruction>(V))
5370 // Check if target-independent constraints permit a tail call here.
5371 // Target-dependent constraints are checked within TLI->LowerCallTo.
5372 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5375 TargetLowering::CallLoweringInfo CLI(DAG);
5376 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5377 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5378 .setTailCall(isTailCall);
5379 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5381 if (Result.first.getNode())
5382 setValue(CS.getInstruction(), Result.first);
5385 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5386 /// value is equal or not-equal to zero.
5387 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5388 for (const User *U : V->users()) {
5389 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5390 if (IC->isEquality())
5391 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5392 if (C->isNullValue())
5394 // Unknown instruction.
5400 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5402 SelectionDAGBuilder &Builder) {
5404 // Check to see if this load can be trivially constant folded, e.g. if the
5405 // input is from a string literal.
5406 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5407 // Cast pointer to the type we really want to load.
5408 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5409 PointerType::getUnqual(LoadTy));
5411 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5412 const_cast<Constant *>(LoadInput), *Builder.DL))
5413 return Builder.getValue(LoadCst);
5416 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5417 // still constant memory, the input chain can be the entry node.
5419 bool ConstantMemory = false;
5421 // Do not serialize (non-volatile) loads of constant memory with anything.
5422 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5423 Root = Builder.DAG.getEntryNode();
5424 ConstantMemory = true;
5426 // Do not serialize non-volatile loads against each other.
5427 Root = Builder.DAG.getRoot();
5430 SDValue Ptr = Builder.getValue(PtrVal);
5431 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5432 Ptr, MachinePointerInfo(PtrVal),
5434 false /*nontemporal*/,
5435 false /*isinvariant*/, 1 /* align=1 */);
5437 if (!ConstantMemory)
5438 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5442 /// processIntegerCallValue - Record the value for an instruction that
5443 /// produces an integer result, converting the type where necessary.
5444 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5447 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5450 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5452 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5453 setValue(&I, Value);
5456 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5457 /// If so, return true and lower it, otherwise return false and it will be
5458 /// lowered like a normal call.
5459 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5460 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5461 if (I.getNumArgOperands() != 3)
5464 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5465 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5466 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5467 !I.getType()->isIntegerTy())
5470 const Value *Size = I.getArgOperand(2);
5471 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5472 if (CSize && CSize->getZExtValue() == 0) {
5473 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5475 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5479 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5480 std::pair<SDValue, SDValue> Res =
5481 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5482 getValue(LHS), getValue(RHS), getValue(Size),
5483 MachinePointerInfo(LHS),
5484 MachinePointerInfo(RHS));
5485 if (Res.first.getNode()) {
5486 processIntegerCallValue(I, Res.first, true);
5487 PendingLoads.push_back(Res.second);
5491 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5492 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5493 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5494 bool ActuallyDoIt = true;
5497 switch (CSize->getZExtValue()) {
5499 LoadVT = MVT::Other;
5501 ActuallyDoIt = false;
5505 LoadTy = Type::getInt16Ty(CSize->getContext());
5509 LoadTy = Type::getInt32Ty(CSize->getContext());
5513 LoadTy = Type::getInt64Ty(CSize->getContext());
5517 LoadVT = MVT::v4i32;
5518 LoadTy = Type::getInt32Ty(CSize->getContext());
5519 LoadTy = VectorType::get(LoadTy, 4);
5524 // This turns into unaligned loads. We only do this if the target natively
5525 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5526 // we'll only produce a small number of byte loads.
5528 // Require that we can find a legal MVT, and only do this if the target
5529 // supports unaligned loads of that type. Expanding into byte loads would
5531 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5532 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5533 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5534 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5535 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5536 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5537 // TODO: Check alignment of src and dest ptrs.
5538 if (!TLI.isTypeLegal(LoadVT) ||
5539 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5540 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5541 ActuallyDoIt = false;
5545 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5546 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5548 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5550 processIntegerCallValue(I, Res, false);
5559 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5560 /// form. If so, return true and lower it, otherwise return false and it
5561 /// will be lowered like a normal call.
5562 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5563 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5564 if (I.getNumArgOperands() != 3)
5567 const Value *Src = I.getArgOperand(0);
5568 const Value *Char = I.getArgOperand(1);
5569 const Value *Length = I.getArgOperand(2);
5570 if (!Src->getType()->isPointerTy() ||
5571 !Char->getType()->isIntegerTy() ||
5572 !Length->getType()->isIntegerTy() ||
5573 !I.getType()->isPointerTy())
5576 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5577 std::pair<SDValue, SDValue> Res =
5578 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5579 getValue(Src), getValue(Char), getValue(Length),
5580 MachinePointerInfo(Src));
5581 if (Res.first.getNode()) {
5582 setValue(&I, Res.first);
5583 PendingLoads.push_back(Res.second);
5590 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5591 /// optimized form. If so, return true and lower it, otherwise return false
5592 /// and it will be lowered like a normal call.
5593 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5594 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5595 if (I.getNumArgOperands() != 2)
5598 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5599 if (!Arg0->getType()->isPointerTy() ||
5600 !Arg1->getType()->isPointerTy() ||
5601 !I.getType()->isPointerTy())
5604 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5605 std::pair<SDValue, SDValue> Res =
5606 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5607 getValue(Arg0), getValue(Arg1),
5608 MachinePointerInfo(Arg0),
5609 MachinePointerInfo(Arg1), isStpcpy);
5610 if (Res.first.getNode()) {
5611 setValue(&I, Res.first);
5612 DAG.setRoot(Res.second);
5619 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5620 /// If so, return true and lower it, otherwise return false and it will be
5621 /// lowered like a normal call.
5622 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5623 // Verify that the prototype makes sense. int strcmp(void*,void*)
5624 if (I.getNumArgOperands() != 2)
5627 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5628 if (!Arg0->getType()->isPointerTy() ||
5629 !Arg1->getType()->isPointerTy() ||
5630 !I.getType()->isIntegerTy())
5633 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5634 std::pair<SDValue, SDValue> Res =
5635 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5636 getValue(Arg0), getValue(Arg1),
5637 MachinePointerInfo(Arg0),
5638 MachinePointerInfo(Arg1));
5639 if (Res.first.getNode()) {
5640 processIntegerCallValue(I, Res.first, true);
5641 PendingLoads.push_back(Res.second);
5648 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5649 /// form. If so, return true and lower it, otherwise return false and it
5650 /// will be lowered like a normal call.
5651 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5652 // Verify that the prototype makes sense. size_t strlen(char *)
5653 if (I.getNumArgOperands() != 1)
5656 const Value *Arg0 = I.getArgOperand(0);
5657 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5660 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5661 std::pair<SDValue, SDValue> Res =
5662 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5663 getValue(Arg0), MachinePointerInfo(Arg0));
5664 if (Res.first.getNode()) {
5665 processIntegerCallValue(I, Res.first, false);
5666 PendingLoads.push_back(Res.second);
5673 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5674 /// form. If so, return true and lower it, otherwise return false and it
5675 /// will be lowered like a normal call.
5676 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5677 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5678 if (I.getNumArgOperands() != 2)
5681 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5682 if (!Arg0->getType()->isPointerTy() ||
5683 !Arg1->getType()->isIntegerTy() ||
5684 !I.getType()->isIntegerTy())
5687 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5688 std::pair<SDValue, SDValue> Res =
5689 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5690 getValue(Arg0), getValue(Arg1),
5691 MachinePointerInfo(Arg0));
5692 if (Res.first.getNode()) {
5693 processIntegerCallValue(I, Res.first, false);
5694 PendingLoads.push_back(Res.second);
5701 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5702 /// operation (as expected), translate it to an SDNode with the specified opcode
5703 /// and return true.
5704 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5706 // Sanity check that it really is a unary floating-point call.
5707 if (I.getNumArgOperands() != 1 ||
5708 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5709 I.getType() != I.getArgOperand(0)->getType() ||
5710 !I.onlyReadsMemory())
5713 SDValue Tmp = getValue(I.getArgOperand(0));
5714 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5718 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5719 /// operation (as expected), translate it to an SDNode with the specified opcode
5720 /// and return true.
5721 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5723 // Sanity check that it really is a binary floating-point call.
5724 if (I.getNumArgOperands() != 2 ||
5725 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5726 I.getType() != I.getArgOperand(0)->getType() ||
5727 I.getType() != I.getArgOperand(1)->getType() ||
5728 !I.onlyReadsMemory())
5731 SDValue Tmp0 = getValue(I.getArgOperand(0));
5732 SDValue Tmp1 = getValue(I.getArgOperand(1));
5733 EVT VT = Tmp0.getValueType();
5734 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5738 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5739 // Handle inline assembly differently.
5740 if (isa<InlineAsm>(I.getCalledValue())) {
5745 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5746 ComputeUsesVAFloatArgument(I, &MMI);
5748 const char *RenameFn = nullptr;
5749 if (Function *F = I.getCalledFunction()) {
5750 if (F->isDeclaration()) {
5751 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5752 if (unsigned IID = II->getIntrinsicID(F)) {
5753 RenameFn = visitIntrinsicCall(I, IID);
5758 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5759 RenameFn = visitIntrinsicCall(I, IID);
5765 // Check for well-known libc/libm calls. If the function is internal, it
5766 // can't be a library call.
5768 if (!F->hasLocalLinkage() && F->hasName() &&
5769 LibInfo->getLibFunc(F->getName(), Func) &&
5770 LibInfo->hasOptimizedCodeGen(Func)) {
5773 case LibFunc::copysign:
5774 case LibFunc::copysignf:
5775 case LibFunc::copysignl:
5776 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5777 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5778 I.getType() == I.getArgOperand(0)->getType() &&
5779 I.getType() == I.getArgOperand(1)->getType() &&
5780 I.onlyReadsMemory()) {
5781 SDValue LHS = getValue(I.getArgOperand(0));
5782 SDValue RHS = getValue(I.getArgOperand(1));
5783 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5784 LHS.getValueType(), LHS, RHS));
5789 case LibFunc::fabsf:
5790 case LibFunc::fabsl:
5791 if (visitUnaryFloatCall(I, ISD::FABS))
5795 case LibFunc::fminf:
5796 case LibFunc::fminl:
5797 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5801 case LibFunc::fmaxf:
5802 case LibFunc::fmaxl:
5803 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5809 if (visitUnaryFloatCall(I, ISD::FSIN))
5815 if (visitUnaryFloatCall(I, ISD::FCOS))
5819 case LibFunc::sqrtf:
5820 case LibFunc::sqrtl:
5821 case LibFunc::sqrt_finite:
5822 case LibFunc::sqrtf_finite:
5823 case LibFunc::sqrtl_finite:
5824 if (visitUnaryFloatCall(I, ISD::FSQRT))
5827 case LibFunc::floor:
5828 case LibFunc::floorf:
5829 case LibFunc::floorl:
5830 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5833 case LibFunc::nearbyint:
5834 case LibFunc::nearbyintf:
5835 case LibFunc::nearbyintl:
5836 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5840 case LibFunc::ceilf:
5841 case LibFunc::ceill:
5842 if (visitUnaryFloatCall(I, ISD::FCEIL))
5846 case LibFunc::rintf:
5847 case LibFunc::rintl:
5848 if (visitUnaryFloatCall(I, ISD::FRINT))
5851 case LibFunc::round:
5852 case LibFunc::roundf:
5853 case LibFunc::roundl:
5854 if (visitUnaryFloatCall(I, ISD::FROUND))
5857 case LibFunc::trunc:
5858 case LibFunc::truncf:
5859 case LibFunc::truncl:
5860 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5864 case LibFunc::log2f:
5865 case LibFunc::log2l:
5866 if (visitUnaryFloatCall(I, ISD::FLOG2))
5870 case LibFunc::exp2f:
5871 case LibFunc::exp2l:
5872 if (visitUnaryFloatCall(I, ISD::FEXP2))
5875 case LibFunc::memcmp:
5876 if (visitMemCmpCall(I))
5879 case LibFunc::memchr:
5880 if (visitMemChrCall(I))
5883 case LibFunc::strcpy:
5884 if (visitStrCpyCall(I, false))
5887 case LibFunc::stpcpy:
5888 if (visitStrCpyCall(I, true))
5891 case LibFunc::strcmp:
5892 if (visitStrCmpCall(I))
5895 case LibFunc::strlen:
5896 if (visitStrLenCall(I))
5899 case LibFunc::strnlen:
5900 if (visitStrNLenCall(I))
5909 Callee = getValue(I.getCalledValue());
5911 Callee = DAG.getExternalSymbol(
5913 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5915 // Check if we can potentially perform a tail call. More detailed checking is
5916 // be done within LowerCallTo, after more information about the call is known.
5917 LowerCallTo(&I, Callee, I.isTailCall());
5922 /// AsmOperandInfo - This contains information for each constraint that we are
5924 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5926 /// CallOperand - If this is the result output operand or a clobber
5927 /// this is null, otherwise it is the incoming operand to the CallInst.
5928 /// This gets modified as the asm is processed.
5929 SDValue CallOperand;
5931 /// AssignedRegs - If this is a register or register class operand, this
5932 /// contains the set of register corresponding to the operand.
5933 RegsForValue AssignedRegs;
5935 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5936 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5939 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5940 /// corresponds to. If there is no Value* for this operand, it returns
5942 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5943 const DataLayout &DL) const {
5944 if (!CallOperandVal) return MVT::Other;
5946 if (isa<BasicBlock>(CallOperandVal))
5947 return TLI.getPointerTy(DL);
5949 llvm::Type *OpTy = CallOperandVal->getType();
5951 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5952 // If this is an indirect operand, the operand is a pointer to the
5955 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5957 report_fatal_error("Indirect operand for inline asm not a pointer!");
5958 OpTy = PtrTy->getElementType();
5961 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5962 if (StructType *STy = dyn_cast<StructType>(OpTy))
5963 if (STy->getNumElements() == 1)
5964 OpTy = STy->getElementType(0);
5966 // If OpTy is not a single value, it may be a struct/union that we
5967 // can tile with integers.
5968 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5969 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5978 OpTy = IntegerType::get(Context, BitSize);
5983 return TLI.getValueType(DL, OpTy, true);
5987 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5989 } // end anonymous namespace
5991 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5992 /// specified operand. We prefer to assign virtual registers, to allow the
5993 /// register allocator to handle the assignment process. However, if the asm
5994 /// uses features that we can't model on machineinstrs, we have SDISel do the
5995 /// allocation. This produces generally horrible, but correct, code.
5997 /// OpInfo describes the operand.
5999 static void GetRegistersForValue(SelectionDAG &DAG,
6000 const TargetLowering &TLI,
6002 SDISelAsmOperandInfo &OpInfo) {
6003 LLVMContext &Context = *DAG.getContext();
6005 MachineFunction &MF = DAG.getMachineFunction();
6006 SmallVector<unsigned, 4> Regs;
6008 // If this is a constraint for a single physreg, or a constraint for a
6009 // register class, find it.
6010 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6011 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6012 OpInfo.ConstraintCode,
6013 OpInfo.ConstraintVT);
6015 unsigned NumRegs = 1;
6016 if (OpInfo.ConstraintVT != MVT::Other) {
6017 // If this is a FP input in an integer register (or visa versa) insert a bit
6018 // cast of the input value. More generally, handle any case where the input
6019 // value disagrees with the register class we plan to stick this in.
6020 if (OpInfo.Type == InlineAsm::isInput &&
6021 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6022 // Try to convert to the first EVT that the reg class contains. If the
6023 // types are identical size, use a bitcast to convert (e.g. two differing
6025 MVT RegVT = *PhysReg.second->vt_begin();
6026 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6027 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6028 RegVT, OpInfo.CallOperand);
6029 OpInfo.ConstraintVT = RegVT;
6030 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6031 // If the input is a FP value and we want it in FP registers, do a
6032 // bitcast to the corresponding integer type. This turns an f64 value
6033 // into i64, which can be passed with two i32 values on a 32-bit
6035 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6036 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6037 RegVT, OpInfo.CallOperand);
6038 OpInfo.ConstraintVT = RegVT;
6042 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6046 EVT ValueVT = OpInfo.ConstraintVT;
6048 // If this is a constraint for a specific physical register, like {r17},
6050 if (unsigned AssignedReg = PhysReg.first) {
6051 const TargetRegisterClass *RC = PhysReg.second;
6052 if (OpInfo.ConstraintVT == MVT::Other)
6053 ValueVT = *RC->vt_begin();
6055 // Get the actual register value type. This is important, because the user
6056 // may have asked for (e.g.) the AX register in i32 type. We need to
6057 // remember that AX is actually i16 to get the right extension.
6058 RegVT = *RC->vt_begin();
6060 // This is a explicit reference to a physical register.
6061 Regs.push_back(AssignedReg);
6063 // If this is an expanded reference, add the rest of the regs to Regs.
6065 TargetRegisterClass::iterator I = RC->begin();
6066 for (; *I != AssignedReg; ++I)
6067 assert(I != RC->end() && "Didn't find reg!");
6069 // Already added the first reg.
6071 for (; NumRegs; --NumRegs, ++I) {
6072 assert(I != RC->end() && "Ran out of registers to allocate!");
6077 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6081 // Otherwise, if this was a reference to an LLVM register class, create vregs
6082 // for this reference.
6083 if (const TargetRegisterClass *RC = PhysReg.second) {
6084 RegVT = *RC->vt_begin();
6085 if (OpInfo.ConstraintVT == MVT::Other)
6088 // Create the appropriate number of virtual registers.
6089 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6090 for (; NumRegs; --NumRegs)
6091 Regs.push_back(RegInfo.createVirtualRegister(RC));
6093 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6097 // Otherwise, we couldn't allocate enough registers for this.
6100 /// visitInlineAsm - Handle a call to an InlineAsm object.
6102 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6103 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6105 /// ConstraintOperands - Information about all of the constraints.
6106 SDISelAsmOperandInfoVector ConstraintOperands;
6108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6109 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6110 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6112 bool hasMemory = false;
6114 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6115 unsigned ResNo = 0; // ResNo - The result number of the next output.
6116 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6117 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6118 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6120 MVT OpVT = MVT::Other;
6122 // Compute the value type for each operand.
6123 switch (OpInfo.Type) {
6124 case InlineAsm::isOutput:
6125 // Indirect outputs just consume an argument.
6126 if (OpInfo.isIndirect) {
6127 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6131 // The return value of the call is this value. As such, there is no
6132 // corresponding argument.
6133 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6134 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6135 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6136 STy->getElementType(ResNo));
6138 assert(ResNo == 0 && "Asm only has one result!");
6139 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6143 case InlineAsm::isInput:
6144 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6146 case InlineAsm::isClobber:
6151 // If this is an input or an indirect output, process the call argument.
6152 // BasicBlocks are labels, currently appearing only in asm's.
6153 if (OpInfo.CallOperandVal) {
6154 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6155 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6157 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6160 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6161 DAG.getDataLayout()).getSimpleVT();
6164 OpInfo.ConstraintVT = OpVT;
6166 // Indirect operand accesses access memory.
6167 if (OpInfo.isIndirect)
6170 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6171 TargetLowering::ConstraintType
6172 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6173 if (CType == TargetLowering::C_Memory) {
6181 SDValue Chain, Flag;
6183 // We won't need to flush pending loads if this asm doesn't touch
6184 // memory and is nonvolatile.
6185 if (hasMemory || IA->hasSideEffects())
6188 Chain = DAG.getRoot();
6190 // Second pass over the constraints: compute which constraint option to use
6191 // and assign registers to constraints that want a specific physreg.
6192 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6193 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6195 // If this is an output operand with a matching input operand, look up the
6196 // matching input. If their types mismatch, e.g. one is an integer, the
6197 // other is floating point, or their sizes are different, flag it as an
6199 if (OpInfo.hasMatchingInput()) {
6200 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6202 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6203 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6204 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6205 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6206 OpInfo.ConstraintVT);
6207 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6208 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6209 Input.ConstraintVT);
6210 if ((OpInfo.ConstraintVT.isInteger() !=
6211 Input.ConstraintVT.isInteger()) ||
6212 (MatchRC.second != InputRC.second)) {
6213 report_fatal_error("Unsupported asm: input constraint"
6214 " with a matching output constraint of"
6215 " incompatible type!");
6217 Input.ConstraintVT = OpInfo.ConstraintVT;
6221 // Compute the constraint code and ConstraintType to use.
6222 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6224 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6225 OpInfo.Type == InlineAsm::isClobber)
6228 // If this is a memory input, and if the operand is not indirect, do what we
6229 // need to to provide an address for the memory input.
6230 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6231 !OpInfo.isIndirect) {
6232 assert((OpInfo.isMultipleAlternative ||
6233 (OpInfo.Type == InlineAsm::isInput)) &&
6234 "Can only indirectify direct input operands!");
6236 // Memory operands really want the address of the value. If we don't have
6237 // an indirect input, put it in the constpool if we can, otherwise spill
6238 // it to a stack slot.
6239 // TODO: This isn't quite right. We need to handle these according to
6240 // the addressing mode that the constraint wants. Also, this may take
6241 // an additional register for the computation and we don't want that
6244 // If the operand is a float, integer, or vector constant, spill to a
6245 // constant pool entry to get its address.
6246 const Value *OpVal = OpInfo.CallOperandVal;
6247 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6248 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6249 OpInfo.CallOperand = DAG.getConstantPool(
6250 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6252 // Otherwise, create a stack slot and emit a store to it before the
6254 Type *Ty = OpVal->getType();
6255 auto &DL = DAG.getDataLayout();
6256 uint64_t TySize = DL.getTypeAllocSize(Ty);
6257 unsigned Align = DL.getPrefTypeAlignment(Ty);
6258 MachineFunction &MF = DAG.getMachineFunction();
6259 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6261 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6262 Chain = DAG.getStore(
6263 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6264 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6266 OpInfo.CallOperand = StackSlot;
6269 // There is no longer a Value* corresponding to this operand.
6270 OpInfo.CallOperandVal = nullptr;
6272 // It is now an indirect operand.
6273 OpInfo.isIndirect = true;
6276 // If this constraint is for a specific register, allocate it before
6278 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6279 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6282 // Second pass - Loop over all of the operands, assigning virtual or physregs
6283 // to register class operands.
6284 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6285 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6287 // C_Register operands have already been allocated, Other/Memory don't need
6289 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6290 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6293 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6294 std::vector<SDValue> AsmNodeOperands;
6295 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6296 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6297 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6299 // If we have a !srcloc metadata node associated with it, we want to attach
6300 // this to the ultimately generated inline asm machineinstr. To do this, we
6301 // pass in the third operand as this (potentially null) inline asm MDNode.
6302 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6303 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6305 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6306 // bits as operand 3.
6307 unsigned ExtraInfo = 0;
6308 if (IA->hasSideEffects())
6309 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6310 if (IA->isAlignStack())
6311 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6312 // Set the asm dialect.
6313 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6315 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6316 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6317 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6319 // Compute the constraint code and ConstraintType to use.
6320 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6322 // Ideally, we would only check against memory constraints. However, the
6323 // meaning of an other constraint can be target-specific and we can't easily
6324 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6325 // for other constriants as well.
6326 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6327 OpInfo.ConstraintType == TargetLowering::C_Other) {
6328 if (OpInfo.Type == InlineAsm::isInput)
6329 ExtraInfo |= InlineAsm::Extra_MayLoad;
6330 else if (OpInfo.Type == InlineAsm::isOutput)
6331 ExtraInfo |= InlineAsm::Extra_MayStore;
6332 else if (OpInfo.Type == InlineAsm::isClobber)
6333 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6337 AsmNodeOperands.push_back(DAG.getTargetConstant(
6338 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6340 // Loop over all of the inputs, copying the operand values into the
6341 // appropriate registers and processing the output regs.
6342 RegsForValue RetValRegs;
6344 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6345 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6347 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6348 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6350 switch (OpInfo.Type) {
6351 case InlineAsm::isOutput: {
6352 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6353 OpInfo.ConstraintType != TargetLowering::C_Register) {
6354 // Memory output, or 'other' output (e.g. 'X' constraint).
6355 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6357 unsigned ConstraintID =
6358 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6359 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6360 "Failed to convert memory constraint code to constraint id.");
6362 // Add information to the INLINEASM node to know about this output.
6363 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6364 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6365 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6367 AsmNodeOperands.push_back(OpInfo.CallOperand);
6371 // Otherwise, this is a register or register class output.
6373 // Copy the output from the appropriate register. Find a register that
6375 if (OpInfo.AssignedRegs.Regs.empty()) {
6376 LLVMContext &Ctx = *DAG.getContext();
6377 Ctx.emitError(CS.getInstruction(),
6378 "couldn't allocate output register for constraint '" +
6379 Twine(OpInfo.ConstraintCode) + "'");
6383 // If this is an indirect operand, store through the pointer after the
6385 if (OpInfo.isIndirect) {
6386 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6387 OpInfo.CallOperandVal));
6389 // This is the result value of the call.
6390 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6391 // Concatenate this output onto the outputs list.
6392 RetValRegs.append(OpInfo.AssignedRegs);
6395 // Add information to the INLINEASM node to know that this register is
6398 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6399 ? InlineAsm::Kind_RegDefEarlyClobber
6400 : InlineAsm::Kind_RegDef,
6401 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6404 case InlineAsm::isInput: {
6405 SDValue InOperandVal = OpInfo.CallOperand;
6407 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6408 // If this is required to match an output register we have already set,
6409 // just use its register.
6410 unsigned OperandNo = OpInfo.getMatchedOperand();
6412 // Scan until we find the definition we already emitted of this operand.
6413 // When we find it, create a RegsForValue operand.
6414 unsigned CurOp = InlineAsm::Op_FirstOperand;
6415 for (; OperandNo; --OperandNo) {
6416 // Advance to the next operand.
6418 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6419 assert((InlineAsm::isRegDefKind(OpFlag) ||
6420 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6421 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6422 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6426 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6427 if (InlineAsm::isRegDefKind(OpFlag) ||
6428 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6429 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6430 if (OpInfo.isIndirect) {
6431 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6432 LLVMContext &Ctx = *DAG.getContext();
6433 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6434 " don't know how to handle tied "
6435 "indirect register inputs");
6439 RegsForValue MatchedRegs;
6440 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6441 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6442 MatchedRegs.RegVTs.push_back(RegVT);
6443 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6444 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6446 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6447 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6449 LLVMContext &Ctx = *DAG.getContext();
6450 Ctx.emitError(CS.getInstruction(),
6451 "inline asm error: This value"
6452 " type register class is not natively supported!");
6456 SDLoc dl = getCurSDLoc();
6457 // Use the produced MatchedRegs object to
6458 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6459 Chain, &Flag, CS.getInstruction());
6460 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6461 true, OpInfo.getMatchedOperand(), dl,
6462 DAG, AsmNodeOperands);
6466 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6467 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6468 "Unexpected number of operands");
6469 // Add information to the INLINEASM node to know about this input.
6470 // See InlineAsm.h isUseOperandTiedToDef.
6471 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6472 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6473 OpInfo.getMatchedOperand());
6474 AsmNodeOperands.push_back(DAG.getTargetConstant(
6475 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6476 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6480 // Treat indirect 'X' constraint as memory.
6481 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6483 OpInfo.ConstraintType = TargetLowering::C_Memory;
6485 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6486 std::vector<SDValue> Ops;
6487 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6490 LLVMContext &Ctx = *DAG.getContext();
6491 Ctx.emitError(CS.getInstruction(),
6492 "invalid operand for inline asm constraint '" +
6493 Twine(OpInfo.ConstraintCode) + "'");
6497 // Add information to the INLINEASM node to know about this input.
6498 unsigned ResOpType =
6499 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6500 AsmNodeOperands.push_back(DAG.getTargetConstant(
6501 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6502 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6506 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6507 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6508 assert(InOperandVal.getValueType() ==
6509 TLI.getPointerTy(DAG.getDataLayout()) &&
6510 "Memory operands expect pointer values");
6512 unsigned ConstraintID =
6513 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6514 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6515 "Failed to convert memory constraint code to constraint id.");
6517 // Add information to the INLINEASM node to know about this input.
6518 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6519 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6520 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6523 AsmNodeOperands.push_back(InOperandVal);
6527 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6528 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6529 "Unknown constraint type!");
6531 // TODO: Support this.
6532 if (OpInfo.isIndirect) {
6533 LLVMContext &Ctx = *DAG.getContext();
6534 Ctx.emitError(CS.getInstruction(),
6535 "Don't know how to handle indirect register inputs yet "
6536 "for constraint '" +
6537 Twine(OpInfo.ConstraintCode) + "'");
6541 // Copy the input into the appropriate registers.
6542 if (OpInfo.AssignedRegs.Regs.empty()) {
6543 LLVMContext &Ctx = *DAG.getContext();
6544 Ctx.emitError(CS.getInstruction(),
6545 "couldn't allocate input reg for constraint '" +
6546 Twine(OpInfo.ConstraintCode) + "'");
6550 SDLoc dl = getCurSDLoc();
6552 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6553 Chain, &Flag, CS.getInstruction());
6555 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6556 dl, DAG, AsmNodeOperands);
6559 case InlineAsm::isClobber: {
6560 // Add the clobbered value to the operand list, so that the register
6561 // allocator is aware that the physreg got clobbered.
6562 if (!OpInfo.AssignedRegs.Regs.empty())
6563 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6564 false, 0, getCurSDLoc(), DAG,
6571 // Finish up input operands. Set the input chain and add the flag last.
6572 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6573 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6575 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6576 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6577 Flag = Chain.getValue(1);
6579 // If this asm returns a register value, copy the result from that register
6580 // and set it as the value of the call.
6581 if (!RetValRegs.Regs.empty()) {
6582 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6583 Chain, &Flag, CS.getInstruction());
6585 // FIXME: Why don't we do this for inline asms with MRVs?
6586 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6587 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6589 // If any of the results of the inline asm is a vector, it may have the
6590 // wrong width/num elts. This can happen for register classes that can
6591 // contain multiple different value types. The preg or vreg allocated may
6592 // not have the same VT as was expected. Convert it to the right type
6593 // with bit_convert.
6594 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6595 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6598 } else if (ResultType != Val.getValueType() &&
6599 ResultType.isInteger() && Val.getValueType().isInteger()) {
6600 // If a result value was tied to an input value, the computed result may
6601 // have a wider width than the expected result. Extract the relevant
6603 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6606 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6609 setValue(CS.getInstruction(), Val);
6610 // Don't need to use this as a chain in this case.
6611 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6615 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6617 // Process indirect outputs, first output all of the flagged copies out of
6619 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6620 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6621 const Value *Ptr = IndirectStoresToEmit[i].second;
6622 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6624 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6627 // Emit the non-flagged stores from the physregs.
6628 SmallVector<SDValue, 8> OutChains;
6629 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6630 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6631 StoresToEmit[i].first,
6632 getValue(StoresToEmit[i].second),
6633 MachinePointerInfo(StoresToEmit[i].second),
6635 OutChains.push_back(Val);
6638 if (!OutChains.empty())
6639 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6644 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6645 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6646 MVT::Other, getRoot(),
6647 getValue(I.getArgOperand(0)),
6648 DAG.getSrcValue(I.getArgOperand(0))));
6651 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6652 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6653 const DataLayout &DL = DAG.getDataLayout();
6654 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6655 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6656 DAG.getSrcValue(I.getOperand(0)),
6657 DL.getABITypeAlignment(I.getType()));
6659 DAG.setRoot(V.getValue(1));
6662 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6663 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6664 MVT::Other, getRoot(),
6665 getValue(I.getArgOperand(0)),
6666 DAG.getSrcValue(I.getArgOperand(0))));
6669 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6670 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6671 MVT::Other, getRoot(),
6672 getValue(I.getArgOperand(0)),
6673 getValue(I.getArgOperand(1)),
6674 DAG.getSrcValue(I.getArgOperand(0)),
6675 DAG.getSrcValue(I.getArgOperand(1))));
6678 /// \brief Lower an argument list according to the target calling convention.
6680 /// \return A tuple of <return-value, token-chain>
6682 /// This is a helper for lowering intrinsics that follow a target calling
6683 /// convention or require stack pointer adjustment. Only a subset of the
6684 /// intrinsic's operands need to participate in the calling convention.
6685 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6686 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6687 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6688 TargetLowering::ArgListTy Args;
6689 Args.reserve(NumArgs);
6691 // Populate the argument list.
6692 // Attributes for args start at offset 1, after the return attribute.
6693 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6694 ArgI != ArgE; ++ArgI) {
6695 const Value *V = CS->getOperand(ArgI);
6697 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6699 TargetLowering::ArgListEntry Entry;
6700 Entry.Node = getValue(V);
6701 Entry.Ty = V->getType();
6702 Entry.setAttributes(&CS, AttrI);
6703 Args.push_back(Entry);
6706 TargetLowering::CallLoweringInfo CLI(DAG);
6707 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6708 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6709 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6711 return lowerInvokable(CLI, EHPadBB);
6714 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6715 /// or patchpoint target node's operand list.
6717 /// Constants are converted to TargetConstants purely as an optimization to
6718 /// avoid constant materialization and register allocation.
6720 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6721 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6722 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6723 /// address materialization and register allocation, but may also be required
6724 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6725 /// alloca in the entry block, then the runtime may assume that the alloca's
6726 /// StackMap location can be read immediately after compilation and that the
6727 /// location is valid at any point during execution (this is similar to the
6728 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6729 /// only available in a register, then the runtime would need to trap when
6730 /// execution reaches the StackMap in order to read the alloca's location.
6731 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6732 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6733 SelectionDAGBuilder &Builder) {
6734 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6735 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6738 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6740 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6741 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6742 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6743 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6744 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6746 Ops.push_back(OpVal);
6750 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6751 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6752 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6753 // [live variables...])
6755 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6757 SDValue Chain, InFlag, Callee, NullPtr;
6758 SmallVector<SDValue, 32> Ops;
6760 SDLoc DL = getCurSDLoc();
6761 Callee = getValue(CI.getCalledValue());
6762 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6764 // The stackmap intrinsic only records the live variables (the arguemnts
6765 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6766 // intrinsic, this won't be lowered to a function call. This means we don't
6767 // have to worry about calling conventions and target specific lowering code.
6768 // Instead we perform the call lowering right here.
6770 // chain, flag = CALLSEQ_START(chain, 0)
6771 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6772 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6774 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6775 InFlag = Chain.getValue(1);
6777 // Add the <id> and <numBytes> constants.
6778 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6779 Ops.push_back(DAG.getTargetConstant(
6780 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6781 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6782 Ops.push_back(DAG.getTargetConstant(
6783 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6786 // Push live variables for the stack map.
6787 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6789 // We are not pushing any register mask info here on the operands list,
6790 // because the stackmap doesn't clobber anything.
6792 // Push the chain and the glue flag.
6793 Ops.push_back(Chain);
6794 Ops.push_back(InFlag);
6796 // Create the STACKMAP node.
6797 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6798 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6799 Chain = SDValue(SM, 0);
6800 InFlag = Chain.getValue(1);
6802 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6804 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6806 // Set the root to the target-lowered call chain.
6809 // Inform the Frame Information that we have a stackmap in this function.
6810 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6813 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6814 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6815 const BasicBlock *EHPadBB) {
6816 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6821 // [live variables...])
6823 CallingConv::ID CC = CS.getCallingConv();
6824 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6825 bool HasDef = !CS->getType()->isVoidTy();
6826 SDLoc dl = getCurSDLoc();
6827 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6829 // Handle immediate and symbolic callees.
6830 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6831 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6833 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6834 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6835 SDLoc(SymbolicCallee),
6836 SymbolicCallee->getValueType(0));
6838 // Get the real number of arguments participating in the call <numArgs>
6839 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6840 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6842 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6843 // Intrinsics include all meta-operands up to but not including CC.
6844 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6845 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6846 "Not enough arguments provided to the patchpoint intrinsic");
6848 // For AnyRegCC the arguments are lowered later on manually.
6849 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6851 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6852 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6853 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6855 SDNode *CallEnd = Result.second.getNode();
6856 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6857 CallEnd = CallEnd->getOperand(0).getNode();
6859 /// Get a call instruction from the call sequence chain.
6860 /// Tail calls are not allowed.
6861 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6862 "Expected a callseq node.");
6863 SDNode *Call = CallEnd->getOperand(0).getNode();
6864 bool HasGlue = Call->getGluedNode();
6866 // Replace the target specific call node with the patchable intrinsic.
6867 SmallVector<SDValue, 8> Ops;
6869 // Add the <id> and <numBytes> constants.
6870 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6871 Ops.push_back(DAG.getTargetConstant(
6872 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6873 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6874 Ops.push_back(DAG.getTargetConstant(
6875 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6879 Ops.push_back(Callee);
6881 // Adjust <numArgs> to account for any arguments that have been passed on the
6883 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6884 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6885 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6886 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6888 // Add the calling convention
6889 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6891 // Add the arguments we omitted previously. The register allocator should
6892 // place these in any free register.
6894 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6895 Ops.push_back(getValue(CS.getArgument(i)));
6897 // Push the arguments from the call instruction up to the register mask.
6898 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6899 Ops.append(Call->op_begin() + 2, e);
6901 // Push live variables for the stack map.
6902 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6904 // Push the register mask info.
6906 Ops.push_back(*(Call->op_end()-2));
6908 Ops.push_back(*(Call->op_end()-1));
6910 // Push the chain (this is originally the first operand of the call, but
6911 // becomes now the last or second to last operand).
6912 Ops.push_back(*(Call->op_begin()));
6914 // Push the glue flag (last operand).
6916 Ops.push_back(*(Call->op_end()-1));
6919 if (IsAnyRegCC && HasDef) {
6920 // Create the return types based on the intrinsic definition
6921 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6922 SmallVector<EVT, 3> ValueVTs;
6923 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6924 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6926 // There is always a chain and a glue type at the end
6927 ValueVTs.push_back(MVT::Other);
6928 ValueVTs.push_back(MVT::Glue);
6929 NodeTys = DAG.getVTList(ValueVTs);
6931 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6933 // Replace the target specific call node with a PATCHPOINT node.
6934 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6937 // Update the NodeMap.
6940 setValue(CS.getInstruction(), SDValue(MN, 0));
6942 setValue(CS.getInstruction(), Result.first);
6945 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6946 // call sequence. Furthermore the location of the chain and glue can change
6947 // when the AnyReg calling convention is used and the intrinsic returns a
6949 if (IsAnyRegCC && HasDef) {
6950 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6951 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6952 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6954 DAG.ReplaceAllUsesWith(Call, MN);
6955 DAG.DeleteNode(Call);
6957 // Inform the Frame Information that we have a patchpoint in this function.
6958 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6961 /// Returns an AttributeSet representing the attributes applied to the return
6962 /// value of the given call.
6963 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6964 SmallVector<Attribute::AttrKind, 2> Attrs;
6966 Attrs.push_back(Attribute::SExt);
6968 Attrs.push_back(Attribute::ZExt);
6970 Attrs.push_back(Attribute::InReg);
6972 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6976 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6977 /// implementation, which just calls LowerCall.
6978 /// FIXME: When all targets are
6979 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6980 std::pair<SDValue, SDValue>
6981 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6982 // Handle the incoming return values from the call.
6984 Type *OrigRetTy = CLI.RetTy;
6985 SmallVector<EVT, 4> RetTys;
6986 SmallVector<uint64_t, 4> Offsets;
6987 auto &DL = CLI.DAG.getDataLayout();
6988 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6990 SmallVector<ISD::OutputArg, 4> Outs;
6991 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6993 bool CanLowerReturn =
6994 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6995 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6997 SDValue DemoteStackSlot;
6998 int DemoteStackIdx = -100;
6999 if (!CanLowerReturn) {
7000 // FIXME: equivalent assert?
7001 // assert(!CS.hasInAllocaArgument() &&
7002 // "sret demotion is incompatible with inalloca");
7003 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7004 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7005 MachineFunction &MF = CLI.DAG.getMachineFunction();
7006 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7007 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7009 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7011 Entry.Node = DemoteStackSlot;
7012 Entry.Ty = StackSlotPtrType;
7013 Entry.isSExt = false;
7014 Entry.isZExt = false;
7015 Entry.isInReg = false;
7016 Entry.isSRet = true;
7017 Entry.isNest = false;
7018 Entry.isByVal = false;
7019 Entry.isReturned = false;
7020 Entry.Alignment = Align;
7021 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7022 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7024 // sret demotion isn't compatible with tail-calls, since the sret argument
7025 // points into the callers stack frame.
7026 CLI.IsTailCall = false;
7028 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7030 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7031 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7032 for (unsigned i = 0; i != NumRegs; ++i) {
7033 ISD::InputArg MyFlags;
7034 MyFlags.VT = RegisterVT;
7036 MyFlags.Used = CLI.IsReturnValueUsed;
7038 MyFlags.Flags.setSExt();
7040 MyFlags.Flags.setZExt();
7042 MyFlags.Flags.setInReg();
7043 CLI.Ins.push_back(MyFlags);
7048 // Handle all of the outgoing arguments.
7050 CLI.OutVals.clear();
7051 ArgListTy &Args = CLI.getArgs();
7052 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7053 SmallVector<EVT, 4> ValueVTs;
7054 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7055 Type *FinalType = Args[i].Ty;
7056 if (Args[i].isByVal)
7057 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7058 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7059 FinalType, CLI.CallConv, CLI.IsVarArg);
7060 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7062 EVT VT = ValueVTs[Value];
7063 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7064 SDValue Op = SDValue(Args[i].Node.getNode(),
7065 Args[i].Node.getResNo() + Value);
7066 ISD::ArgFlagsTy Flags;
7067 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7073 if (Args[i].isInReg)
7077 if (Args[i].isByVal)
7079 if (Args[i].isInAlloca) {
7080 Flags.setInAlloca();
7081 // Set the byval flag for CCAssignFn callbacks that don't know about
7082 // inalloca. This way we can know how many bytes we should've allocated
7083 // and how many bytes a callee cleanup function will pop. If we port
7084 // inalloca to more targets, we'll have to add custom inalloca handling
7085 // in the various CC lowering callbacks.
7088 if (Args[i].isByVal || Args[i].isInAlloca) {
7089 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7090 Type *ElementTy = Ty->getElementType();
7091 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7092 // For ByVal, alignment should come from FE. BE will guess if this
7093 // info is not there but there are cases it cannot get right.
7094 unsigned FrameAlign;
7095 if (Args[i].Alignment)
7096 FrameAlign = Args[i].Alignment;
7098 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7099 Flags.setByValAlign(FrameAlign);
7104 Flags.setInConsecutiveRegs();
7105 Flags.setOrigAlign(OriginalAlignment);
7107 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7108 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7109 SmallVector<SDValue, 4> Parts(NumParts);
7110 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7113 ExtendKind = ISD::SIGN_EXTEND;
7114 else if (Args[i].isZExt)
7115 ExtendKind = ISD::ZERO_EXTEND;
7117 // Conservatively only handle 'returned' on non-vectors for now
7118 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7119 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7120 "unexpected use of 'returned'");
7121 // Before passing 'returned' to the target lowering code, ensure that
7122 // either the register MVT and the actual EVT are the same size or that
7123 // the return value and argument are extended in the same way; in these
7124 // cases it's safe to pass the argument register value unchanged as the
7125 // return register value (although it's at the target's option whether
7127 // TODO: allow code generation to take advantage of partially preserved
7128 // registers rather than clobbering the entire register when the
7129 // parameter extension method is not compatible with the return
7131 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7132 (ExtendKind != ISD::ANY_EXTEND &&
7133 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7134 Flags.setReturned();
7137 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7138 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7140 for (unsigned j = 0; j != NumParts; ++j) {
7141 // if it isn't first piece, alignment must be 1
7142 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7143 i < CLI.NumFixedArgs,
7144 i, j*Parts[j].getValueType().getStoreSize());
7145 if (NumParts > 1 && j == 0)
7146 MyFlags.Flags.setSplit();
7148 MyFlags.Flags.setOrigAlign(1);
7150 CLI.Outs.push_back(MyFlags);
7151 CLI.OutVals.push_back(Parts[j]);
7154 if (NeedsRegBlock && Value == NumValues - 1)
7155 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7159 SmallVector<SDValue, 4> InVals;
7160 CLI.Chain = LowerCall(CLI, InVals);
7162 // Verify that the target's LowerCall behaved as expected.
7163 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7164 "LowerCall didn't return a valid chain!");
7165 assert((!CLI.IsTailCall || InVals.empty()) &&
7166 "LowerCall emitted a return value for a tail call!");
7167 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7168 "LowerCall didn't emit the correct number of values!");
7170 // For a tail call, the return value is merely live-out and there aren't
7171 // any nodes in the DAG representing it. Return a special value to
7172 // indicate that a tail call has been emitted and no more Instructions
7173 // should be processed in the current block.
7174 if (CLI.IsTailCall) {
7175 CLI.DAG.setRoot(CLI.Chain);
7176 return std::make_pair(SDValue(), SDValue());
7179 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7180 assert(InVals[i].getNode() &&
7181 "LowerCall emitted a null value!");
7182 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7183 "LowerCall emitted a value with the wrong type!");
7186 SmallVector<SDValue, 4> ReturnValues;
7187 if (!CanLowerReturn) {
7188 // The instruction result is the result of loading from the
7189 // hidden sret parameter.
7190 SmallVector<EVT, 1> PVTs;
7191 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7193 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7194 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7195 EVT PtrVT = PVTs[0];
7197 unsigned NumValues = RetTys.size();
7198 ReturnValues.resize(NumValues);
7199 SmallVector<SDValue, 4> Chains(NumValues);
7201 for (unsigned i = 0; i < NumValues; ++i) {
7202 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7203 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7205 SDValue L = CLI.DAG.getLoad(
7206 RetTys[i], CLI.DL, CLI.Chain, Add,
7207 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7208 DemoteStackIdx, Offsets[i]),
7209 false, false, false, 1);
7210 ReturnValues[i] = L;
7211 Chains[i] = L.getValue(1);
7214 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7216 // Collect the legal value parts into potentially illegal values
7217 // that correspond to the original function's return values.
7218 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7220 AssertOp = ISD::AssertSext;
7221 else if (CLI.RetZExt)
7222 AssertOp = ISD::AssertZext;
7223 unsigned CurReg = 0;
7224 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7226 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7227 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7229 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7230 NumRegs, RegisterVT, VT, nullptr,
7235 // For a function returning void, there is no return value. We can't create
7236 // such a node, so we just return a null return value in that case. In
7237 // that case, nothing will actually look at the value.
7238 if (ReturnValues.empty())
7239 return std::make_pair(SDValue(), CLI.Chain);
7242 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7243 CLI.DAG.getVTList(RetTys), ReturnValues);
7244 return std::make_pair(Res, CLI.Chain);
7247 void TargetLowering::LowerOperationWrapper(SDNode *N,
7248 SmallVectorImpl<SDValue> &Results,
7249 SelectionDAG &DAG) const {
7250 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7252 Results.push_back(Res);
7255 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7256 llvm_unreachable("LowerOperation not implemented for this target!");
7260 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7261 SDValue Op = getNonRegisterValue(V);
7262 assert((Op.getOpcode() != ISD::CopyFromReg ||
7263 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7264 "Copy from a reg to the same reg!");
7265 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7268 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7270 SDValue Chain = DAG.getEntryNode();
7272 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7273 FuncInfo.PreferredExtendType.end())
7275 : FuncInfo.PreferredExtendType[V];
7276 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7277 PendingExports.push_back(Chain);
7280 #include "llvm/CodeGen/SelectionDAGISel.h"
7282 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7283 /// entry block, return true. This includes arguments used by switches, since
7284 /// the switch may expand into multiple basic blocks.
7285 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7286 // With FastISel active, we may be splitting blocks, so force creation
7287 // of virtual registers for all non-dead arguments.
7289 return A->use_empty();
7291 const BasicBlock *Entry = A->getParent()->begin();
7292 for (const User *U : A->users())
7293 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7294 return false; // Use not in entry block.
7299 void SelectionDAGISel::LowerArguments(const Function &F) {
7300 SelectionDAG &DAG = SDB->DAG;
7301 SDLoc dl = SDB->getCurSDLoc();
7302 const DataLayout &DL = DAG.getDataLayout();
7303 SmallVector<ISD::InputArg, 16> Ins;
7305 if (!FuncInfo->CanLowerReturn) {
7306 // Put in an sret pointer parameter before all the other parameters.
7307 SmallVector<EVT, 1> ValueVTs;
7308 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7309 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7311 // NOTE: Assuming that a pointer will never break down to more than one VT
7313 ISD::ArgFlagsTy Flags;
7315 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7316 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7317 ISD::InputArg::NoArgIndex, 0);
7318 Ins.push_back(RetArg);
7321 // Set up the incoming argument description vector.
7323 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7324 I != E; ++I, ++Idx) {
7325 SmallVector<EVT, 4> ValueVTs;
7326 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7327 bool isArgValueUsed = !I->use_empty();
7328 unsigned PartBase = 0;
7329 Type *FinalType = I->getType();
7330 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7331 FinalType = cast<PointerType>(FinalType)->getElementType();
7332 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7333 FinalType, F.getCallingConv(), F.isVarArg());
7334 for (unsigned Value = 0, NumValues = ValueVTs.size();
7335 Value != NumValues; ++Value) {
7336 EVT VT = ValueVTs[Value];
7337 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7338 ISD::ArgFlagsTy Flags;
7339 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7341 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7343 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7345 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7347 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7349 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7351 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7352 Flags.setInAlloca();
7353 // Set the byval flag for CCAssignFn callbacks that don't know about
7354 // inalloca. This way we can know how many bytes we should've allocated
7355 // and how many bytes a callee cleanup function will pop. If we port
7356 // inalloca to more targets, we'll have to add custom inalloca handling
7357 // in the various CC lowering callbacks.
7360 if (Flags.isByVal() || Flags.isInAlloca()) {
7361 PointerType *Ty = cast<PointerType>(I->getType());
7362 Type *ElementTy = Ty->getElementType();
7363 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7364 // For ByVal, alignment should be passed from FE. BE will guess if
7365 // this info is not there but there are cases it cannot get right.
7366 unsigned FrameAlign;
7367 if (F.getParamAlignment(Idx))
7368 FrameAlign = F.getParamAlignment(Idx);
7370 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7371 Flags.setByValAlign(FrameAlign);
7373 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7376 Flags.setInConsecutiveRegs();
7377 Flags.setOrigAlign(OriginalAlignment);
7379 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7380 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7381 for (unsigned i = 0; i != NumRegs; ++i) {
7382 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7383 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7384 if (NumRegs > 1 && i == 0)
7385 MyFlags.Flags.setSplit();
7386 // if it isn't first piece, alignment must be 1
7388 MyFlags.Flags.setOrigAlign(1);
7389 Ins.push_back(MyFlags);
7391 if (NeedsRegBlock && Value == NumValues - 1)
7392 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7393 PartBase += VT.getStoreSize();
7397 // Call the target to set up the argument values.
7398 SmallVector<SDValue, 8> InVals;
7399 SDValue NewRoot = TLI->LowerFormalArguments(
7400 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7402 // Verify that the target's LowerFormalArguments behaved as expected.
7403 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7404 "LowerFormalArguments didn't return a valid chain!");
7405 assert(InVals.size() == Ins.size() &&
7406 "LowerFormalArguments didn't emit the correct number of values!");
7408 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7409 assert(InVals[i].getNode() &&
7410 "LowerFormalArguments emitted a null value!");
7411 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7412 "LowerFormalArguments emitted a value with the wrong type!");
7416 // Update the DAG with the new chain value resulting from argument lowering.
7417 DAG.setRoot(NewRoot);
7419 // Set up the argument values.
7422 if (!FuncInfo->CanLowerReturn) {
7423 // Create a virtual register for the sret pointer, and put in a copy
7424 // from the sret argument into it.
7425 SmallVector<EVT, 1> ValueVTs;
7426 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7427 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7428 MVT VT = ValueVTs[0].getSimpleVT();
7429 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7430 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7431 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7432 RegVT, VT, nullptr, AssertOp);
7434 MachineFunction& MF = SDB->DAG.getMachineFunction();
7435 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7436 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7437 FuncInfo->DemoteRegister = SRetReg;
7439 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7440 DAG.setRoot(NewRoot);
7442 // i indexes lowered arguments. Bump it past the hidden sret argument.
7443 // Idx indexes LLVM arguments. Don't touch it.
7447 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7449 SmallVector<SDValue, 4> ArgValues;
7450 SmallVector<EVT, 4> ValueVTs;
7451 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7452 unsigned NumValues = ValueVTs.size();
7454 // If this argument is unused then remember its value. It is used to generate
7455 // debugging information.
7456 if (I->use_empty() && NumValues) {
7457 SDB->setUnusedArgValue(I, InVals[i]);
7459 // Also remember any frame index for use in FastISel.
7460 if (FrameIndexSDNode *FI =
7461 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7462 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7465 for (unsigned Val = 0; Val != NumValues; ++Val) {
7466 EVT VT = ValueVTs[Val];
7467 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7468 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7470 if (!I->use_empty()) {
7471 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7472 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7473 AssertOp = ISD::AssertSext;
7474 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7475 AssertOp = ISD::AssertZext;
7477 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7478 NumParts, PartVT, VT,
7479 nullptr, AssertOp));
7485 // We don't need to do anything else for unused arguments.
7486 if (ArgValues.empty())
7489 // Note down frame index.
7490 if (FrameIndexSDNode *FI =
7491 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7492 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7494 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7495 SDB->getCurSDLoc());
7497 SDB->setValue(I, Res);
7498 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7499 if (LoadSDNode *LNode =
7500 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7501 if (FrameIndexSDNode *FI =
7502 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7503 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7506 // If this argument is live outside of the entry block, insert a copy from
7507 // wherever we got it to the vreg that other BB's will reference it as.
7508 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7509 // If we can, though, try to skip creating an unnecessary vreg.
7510 // FIXME: This isn't very clean... it would be nice to make this more
7511 // general. It's also subtly incompatible with the hacks FastISel
7513 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7514 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7515 FuncInfo->ValueMap[I] = Reg;
7519 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7520 FuncInfo->InitializeRegForValue(I);
7521 SDB->CopyToExportRegsIfNeeded(I);
7525 assert(i == InVals.size() && "Argument register count mismatch!");
7527 // Finally, if the target has anything special to do, allow it to do so.
7528 EmitFunctionEntryCode();
7531 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7532 /// ensure constants are generated when needed. Remember the virtual registers
7533 /// that need to be added to the Machine PHI nodes as input. We cannot just
7534 /// directly add them, because expansion might result in multiple MBB's for one
7535 /// BB. As such, the start of the BB might correspond to a different MBB than
7539 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7540 const TerminatorInst *TI = LLVMBB->getTerminator();
7542 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7544 // Check PHI nodes in successors that expect a value to be available from this
7546 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7547 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7548 if (!isa<PHINode>(SuccBB->begin())) continue;
7549 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7551 // If this terminator has multiple identical successors (common for
7552 // switches), only handle each succ once.
7553 if (!SuccsHandled.insert(SuccMBB).second)
7556 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7558 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7559 // nodes and Machine PHI nodes, but the incoming operands have not been
7561 for (BasicBlock::const_iterator I = SuccBB->begin();
7562 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7563 // Ignore dead phi's.
7564 if (PN->use_empty()) continue;
7567 if (PN->getType()->isEmptyTy())
7571 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7573 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7574 unsigned &RegOut = ConstantsOut[C];
7576 RegOut = FuncInfo.CreateRegs(C->getType());
7577 CopyValueToVirtualRegister(C, RegOut);
7581 DenseMap<const Value *, unsigned>::iterator I =
7582 FuncInfo.ValueMap.find(PHIOp);
7583 if (I != FuncInfo.ValueMap.end())
7586 assert(isa<AllocaInst>(PHIOp) &&
7587 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7588 "Didn't codegen value into a register!??");
7589 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7590 CopyValueToVirtualRegister(PHIOp, Reg);
7594 // Remember that this register needs to added to the machine PHI node as
7595 // the input for this MBB.
7596 SmallVector<EVT, 4> ValueVTs;
7597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7598 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7599 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7600 EVT VT = ValueVTs[vti];
7601 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7602 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7603 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7604 Reg += NumRegisters;
7609 ConstantsOut.clear();
7612 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7615 SelectionDAGBuilder::StackProtectorDescriptor::
7616 AddSuccessorMBB(const BasicBlock *BB,
7617 MachineBasicBlock *ParentMBB,
7619 MachineBasicBlock *SuccMBB) {
7620 // If SuccBB has not been created yet, create it.
7622 MachineFunction *MF = ParentMBB->getParent();
7623 MachineFunction::iterator BBI = ParentMBB;
7624 SuccMBB = MF->CreateMachineBasicBlock(BB);
7625 MF->insert(++BBI, SuccMBB);
7627 // Add it as a successor of ParentMBB.
7628 ParentMBB->addSuccessor(
7629 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7633 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7634 MachineFunction::iterator I = MBB;
7635 if (++I == FuncInfo.MF->end())
7640 /// During lowering new call nodes can be created (such as memset, etc.).
7641 /// Those will become new roots of the current DAG, but complications arise
7642 /// when they are tail calls. In such cases, the call lowering will update
7643 /// the root, but the builder still needs to know that a tail call has been
7644 /// lowered in order to avoid generating an additional return.
7645 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7646 // If the node is null, we do have a tail call.
7647 if (MaybeTC.getNode() != nullptr)
7648 DAG.setRoot(MaybeTC);
7653 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7654 unsigned *TotalCases, unsigned First,
7656 assert(Last >= First);
7657 assert(TotalCases[Last] >= TotalCases[First]);
7659 APInt LowCase = Clusters[First].Low->getValue();
7660 APInt HighCase = Clusters[Last].High->getValue();
7661 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7663 // FIXME: A range of consecutive cases has 100% density, but only requires one
7664 // comparison to lower. We should discriminate against such consecutive ranges
7667 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7668 uint64_t Range = Diff + 1;
7671 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7673 assert(NumCases < UINT64_MAX / 100);
7674 assert(Range >= NumCases);
7676 return NumCases * 100 >= Range * MinJumpTableDensity;
7679 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7680 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7681 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7684 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7685 unsigned First, unsigned Last,
7686 const SwitchInst *SI,
7687 MachineBasicBlock *DefaultMBB,
7688 CaseCluster &JTCluster) {
7689 assert(First <= Last);
7691 uint32_t Weight = 0;
7692 unsigned NumCmps = 0;
7693 std::vector<MachineBasicBlock*> Table;
7694 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7695 for (unsigned I = First; I <= Last; ++I) {
7696 assert(Clusters[I].Kind == CC_Range);
7697 Weight += Clusters[I].Weight;
7698 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7699 APInt Low = Clusters[I].Low->getValue();
7700 APInt High = Clusters[I].High->getValue();
7701 NumCmps += (Low == High) ? 1 : 2;
7703 // Fill the gap between this and the previous cluster.
7704 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7705 assert(PreviousHigh.slt(Low));
7706 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7707 for (uint64_t J = 0; J < Gap; J++)
7708 Table.push_back(DefaultMBB);
7710 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7711 for (uint64_t J = 0; J < ClusterSize; ++J)
7712 Table.push_back(Clusters[I].MBB);
7713 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7716 unsigned NumDests = JTWeights.size();
7717 if (isSuitableForBitTests(NumDests, NumCmps,
7718 Clusters[First].Low->getValue(),
7719 Clusters[Last].High->getValue())) {
7720 // Clusters[First..Last] should be lowered as bit tests instead.
7724 // Create the MBB that will load from and jump through the table.
7725 // Note: We create it here, but it's not inserted into the function yet.
7726 MachineFunction *CurMF = FuncInfo.MF;
7727 MachineBasicBlock *JumpTableMBB =
7728 CurMF->CreateMachineBasicBlock(SI->getParent());
7730 // Add successors. Note: use table order for determinism.
7731 SmallPtrSet<MachineBasicBlock *, 8> Done;
7732 for (MachineBasicBlock *Succ : Table) {
7733 if (Done.count(Succ))
7735 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7739 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7740 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7741 ->createJumpTableIndex(Table);
7743 // Set up the jump table info.
7744 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7745 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7746 Clusters[Last].High->getValue(), SI->getCondition(),
7748 JTCases.emplace_back(std::move(JTH), std::move(JT));
7750 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7751 JTCases.size() - 1, Weight);
7755 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7756 const SwitchInst *SI,
7757 MachineBasicBlock *DefaultMBB) {
7759 // Clusters must be non-empty, sorted, and only contain Range clusters.
7760 assert(!Clusters.empty());
7761 for (CaseCluster &C : Clusters)
7762 assert(C.Kind == CC_Range);
7763 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7764 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7768 if (!areJTsAllowed(TLI))
7771 const int64_t N = Clusters.size();
7772 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7774 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7775 SmallVector<unsigned, 8> TotalCases(N);
7777 for (unsigned i = 0; i < N; ++i) {
7778 APInt Hi = Clusters[i].High->getValue();
7779 APInt Lo = Clusters[i].Low->getValue();
7780 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7782 TotalCases[i] += TotalCases[i - 1];
7785 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7786 // Cheap case: the whole range might be suitable for jump table.
7787 CaseCluster JTCluster;
7788 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7789 Clusters[0] = JTCluster;
7795 // The algorithm below is not suitable for -O0.
7796 if (TM.getOptLevel() == CodeGenOpt::None)
7799 // Split Clusters into minimum number of dense partitions. The algorithm uses
7800 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7801 // for the Case Statement'" (1994), but builds the MinPartitions array in
7802 // reverse order to make it easier to reconstruct the partitions in ascending
7803 // order. In the choice between two optimal partitionings, it picks the one
7804 // which yields more jump tables.
7806 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7807 SmallVector<unsigned, 8> MinPartitions(N);
7808 // LastElement[i] is the last element of the partition starting at i.
7809 SmallVector<unsigned, 8> LastElement(N);
7810 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7811 SmallVector<unsigned, 8> NumTables(N);
7813 // Base case: There is only one way to partition Clusters[N-1].
7814 MinPartitions[N - 1] = 1;
7815 LastElement[N - 1] = N - 1;
7816 assert(MinJumpTableSize > 1);
7817 NumTables[N - 1] = 0;
7819 // Note: loop indexes are signed to avoid underflow.
7820 for (int64_t i = N - 2; i >= 0; i--) {
7821 // Find optimal partitioning of Clusters[i..N-1].
7822 // Baseline: Put Clusters[i] into a partition on its own.
7823 MinPartitions[i] = MinPartitions[i + 1] + 1;
7825 NumTables[i] = NumTables[i + 1];
7827 // Search for a solution that results in fewer partitions.
7828 for (int64_t j = N - 1; j > i; j--) {
7829 // Try building a partition from Clusters[i..j].
7830 if (isDense(Clusters, &TotalCases[0], i, j)) {
7831 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7832 bool IsTable = j - i + 1 >= MinJumpTableSize;
7833 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7835 // If this j leads to fewer partitions, or same number of partitions
7836 // with more lookup tables, it is a better partitioning.
7837 if (NumPartitions < MinPartitions[i] ||
7838 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7839 MinPartitions[i] = NumPartitions;
7841 NumTables[i] = Tables;
7847 // Iterate over the partitions, replacing some with jump tables in-place.
7848 unsigned DstIndex = 0;
7849 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7850 Last = LastElement[First];
7851 assert(Last >= First);
7852 assert(DstIndex <= First);
7853 unsigned NumClusters = Last - First + 1;
7855 CaseCluster JTCluster;
7856 if (NumClusters >= MinJumpTableSize &&
7857 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7858 Clusters[DstIndex++] = JTCluster;
7860 for (unsigned I = First; I <= Last; ++I)
7861 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7864 Clusters.resize(DstIndex);
7867 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7868 // FIXME: Using the pointer type doesn't seem ideal.
7869 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7870 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7874 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7877 const APInt &High) {
7878 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7879 // range of cases both require only one branch to lower. Just looking at the
7880 // number of clusters and destinations should be enough to decide whether to
7883 // To lower a range with bit tests, the range must fit the bitwidth of a
7885 if (!rangeFitsInWord(Low, High))
7888 // Decide whether it's profitable to lower this range with bit tests. Each
7889 // destination requires a bit test and branch, and there is an overall range
7890 // check branch. For a small number of clusters, separate comparisons might be
7891 // cheaper, and for many destinations, splitting the range might be better.
7892 return (NumDests == 1 && NumCmps >= 3) ||
7893 (NumDests == 2 && NumCmps >= 5) ||
7894 (NumDests == 3 && NumCmps >= 6);
7897 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7898 unsigned First, unsigned Last,
7899 const SwitchInst *SI,
7900 CaseCluster &BTCluster) {
7901 assert(First <= Last);
7905 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7906 unsigned NumCmps = 0;
7907 for (int64_t I = First; I <= Last; ++I) {
7908 assert(Clusters[I].Kind == CC_Range);
7909 Dests.set(Clusters[I].MBB->getNumber());
7910 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7912 unsigned NumDests = Dests.count();
7914 APInt Low = Clusters[First].Low->getValue();
7915 APInt High = Clusters[Last].High->getValue();
7916 assert(Low.slt(High));
7918 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7924 const int BitWidth = DAG.getTargetLoweringInfo()
7925 .getPointerTy(DAG.getDataLayout())
7927 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7929 // Check if the clusters cover a contiguous range such that no value in the
7930 // range will jump to the default statement.
7931 bool ContiguousRange = true;
7932 for (int64_t I = First + 1; I <= Last; ++I) {
7933 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7934 ContiguousRange = false;
7939 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7940 // Optimize the case where all the case values fit in a word without having
7941 // to subtract minValue. In this case, we can optimize away the subtraction.
7942 LowBound = APInt::getNullValue(Low.getBitWidth());
7944 ContiguousRange = false;
7947 CmpRange = High - Low;
7951 uint32_t TotalWeight = 0;
7952 for (unsigned i = First; i <= Last; ++i) {
7953 // Find the CaseBits for this destination.
7955 for (j = 0; j < CBV.size(); ++j)
7956 if (CBV[j].BB == Clusters[i].MBB)
7958 if (j == CBV.size())
7959 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7960 CaseBits *CB = &CBV[j];
7962 // Update Mask, Bits and ExtraWeight.
7963 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7964 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7965 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7966 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7967 CB->Bits += Hi - Lo + 1;
7968 CB->ExtraWeight += Clusters[i].Weight;
7969 TotalWeight += Clusters[i].Weight;
7970 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7974 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7975 // Sort by weight first, number of bits second.
7976 if (a.ExtraWeight != b.ExtraWeight)
7977 return a.ExtraWeight > b.ExtraWeight;
7978 return a.Bits > b.Bits;
7981 for (auto &CB : CBV) {
7982 MachineBasicBlock *BitTestBB =
7983 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7984 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7986 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7987 SI->getCondition(), -1U, MVT::Other, false,
7988 ContiguousRange, nullptr, nullptr, std::move(BTI),
7991 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7992 BitTestCases.size() - 1, TotalWeight);
7996 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7997 const SwitchInst *SI) {
7998 // Partition Clusters into as few subsets as possible, where each subset has a
7999 // range that fits in a machine word and has <= 3 unique destinations.
8002 // Clusters must be sorted and contain Range or JumpTable clusters.
8003 assert(!Clusters.empty());
8004 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8005 for (const CaseCluster &C : Clusters)
8006 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8007 for (unsigned i = 1; i < Clusters.size(); ++i)
8008 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8011 // The algorithm below is not suitable for -O0.
8012 if (TM.getOptLevel() == CodeGenOpt::None)
8015 // If target does not have legal shift left, do not emit bit tests at all.
8016 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8017 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8018 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8021 int BitWidth = PTy.getSizeInBits();
8022 const int64_t N = Clusters.size();
8024 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8025 SmallVector<unsigned, 8> MinPartitions(N);
8026 // LastElement[i] is the last element of the partition starting at i.
8027 SmallVector<unsigned, 8> LastElement(N);
8029 // FIXME: This might not be the best algorithm for finding bit test clusters.
8031 // Base case: There is only one way to partition Clusters[N-1].
8032 MinPartitions[N - 1] = 1;
8033 LastElement[N - 1] = N - 1;
8035 // Note: loop indexes are signed to avoid underflow.
8036 for (int64_t i = N - 2; i >= 0; --i) {
8037 // Find optimal partitioning of Clusters[i..N-1].
8038 // Baseline: Put Clusters[i] into a partition on its own.
8039 MinPartitions[i] = MinPartitions[i + 1] + 1;
8042 // Search for a solution that results in fewer partitions.
8043 // Note: the search is limited by BitWidth, reducing time complexity.
8044 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8045 // Try building a partition from Clusters[i..j].
8048 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8049 Clusters[j].High->getValue()))
8052 // Check nbr of destinations and cluster types.
8053 // FIXME: This works, but doesn't seem very efficient.
8054 bool RangesOnly = true;
8055 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8056 for (int64_t k = i; k <= j; k++) {
8057 if (Clusters[k].Kind != CC_Range) {
8061 Dests.set(Clusters[k].MBB->getNumber());
8063 if (!RangesOnly || Dests.count() > 3)
8066 // Check if it's a better partition.
8067 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8068 if (NumPartitions < MinPartitions[i]) {
8069 // Found a better partition.
8070 MinPartitions[i] = NumPartitions;
8076 // Iterate over the partitions, replacing with bit-test clusters in-place.
8077 unsigned DstIndex = 0;
8078 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8079 Last = LastElement[First];
8080 assert(First <= Last);
8081 assert(DstIndex <= First);
8083 CaseCluster BitTestCluster;
8084 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8085 Clusters[DstIndex++] = BitTestCluster;
8087 size_t NumClusters = Last - First + 1;
8088 std::memmove(&Clusters[DstIndex], &Clusters[First],
8089 sizeof(Clusters[0]) * NumClusters);
8090 DstIndex += NumClusters;
8093 Clusters.resize(DstIndex);
8096 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8097 MachineBasicBlock *SwitchMBB,
8098 MachineBasicBlock *DefaultMBB) {
8099 MachineFunction *CurMF = FuncInfo.MF;
8100 MachineBasicBlock *NextMBB = nullptr;
8101 MachineFunction::iterator BBI = W.MBB;
8102 if (++BBI != FuncInfo.MF->end())
8105 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8107 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8109 if (Size == 2 && W.MBB == SwitchMBB) {
8110 // If any two of the cases has the same destination, and if one value
8111 // is the same as the other, but has one bit unset that the other has set,
8112 // use bit manipulation to do two compares at once. For example:
8113 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8114 // TODO: This could be extended to merge any 2 cases in switches with 3
8116 // TODO: Handle cases where W.CaseBB != SwitchBB.
8117 CaseCluster &Small = *W.FirstCluster;
8118 CaseCluster &Big = *W.LastCluster;
8120 if (Small.Low == Small.High && Big.Low == Big.High &&
8121 Small.MBB == Big.MBB) {
8122 const APInt &SmallValue = Small.Low->getValue();
8123 const APInt &BigValue = Big.Low->getValue();
8125 // Check that there is only one bit different.
8126 APInt CommonBit = BigValue ^ SmallValue;
8127 if (CommonBit.isPowerOf2()) {
8128 SDValue CondLHS = getValue(Cond);
8129 EVT VT = CondLHS.getValueType();
8130 SDLoc DL = getCurSDLoc();
8132 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8133 DAG.getConstant(CommonBit, DL, VT));
8134 SDValue Cond = DAG.getSetCC(
8135 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8138 // Update successor info.
8139 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8140 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8141 addSuccessorWithWeight(
8142 SwitchMBB, DefaultMBB,
8143 // The default destination is the first successor in IR.
8144 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8147 // Insert the true branch.
8149 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8150 DAG.getBasicBlock(Small.MBB));
8151 // Insert the false branch.
8152 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8153 DAG.getBasicBlock(DefaultMBB));
8155 DAG.setRoot(BrCond);
8161 if (TM.getOptLevel() != CodeGenOpt::None) {
8162 // Order cases by weight so the most likely case will be checked first.
8163 std::sort(W.FirstCluster, W.LastCluster + 1,
8164 [](const CaseCluster &a, const CaseCluster &b) {
8165 return a.Weight > b.Weight;
8168 // Rearrange the case blocks so that the last one falls through if possible
8169 // without without changing the order of weights.
8170 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8172 if (I->Weight > W.LastCluster->Weight)
8174 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8175 std::swap(*I, *W.LastCluster);
8181 // Compute total weight.
8182 uint32_t DefaultWeight = W.DefaultWeight;
8183 uint32_t UnhandledWeights = DefaultWeight;
8184 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8185 UnhandledWeights += I->Weight;
8186 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8189 MachineBasicBlock *CurMBB = W.MBB;
8190 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8191 MachineBasicBlock *Fallthrough;
8192 if (I == W.LastCluster) {
8193 // For the last cluster, fall through to the default destination.
8194 Fallthrough = DefaultMBB;
8196 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8197 CurMF->insert(BBI, Fallthrough);
8198 // Put Cond in a virtual register to make it available from the new blocks.
8199 ExportFromCurrentBlock(Cond);
8201 UnhandledWeights -= I->Weight;
8204 case CC_JumpTable: {
8205 // FIXME: Optimize away range check based on pivot comparisons.
8206 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8207 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8209 // The jump block hasn't been inserted yet; insert it here.
8210 MachineBasicBlock *JumpMBB = JT->MBB;
8211 CurMF->insert(BBI, JumpMBB);
8213 uint32_t JumpWeight = I->Weight;
8214 uint32_t FallthroughWeight = UnhandledWeights;
8216 // If the default statement is a target of the jump table, we evenly
8217 // distribute the default weight to successors of CurMBB. Also update
8218 // the weight on the edge from JumpMBB to Fallthrough.
8219 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8220 SE = JumpMBB->succ_end();
8222 if (*SI == DefaultMBB) {
8223 JumpWeight += DefaultWeight / 2;
8224 FallthroughWeight -= DefaultWeight / 2;
8225 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8230 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8231 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8233 // The jump table header will be inserted in our current block, do the
8234 // range check, and fall through to our fallthrough block.
8235 JTH->HeaderBB = CurMBB;
8236 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8238 // If we're in the right place, emit the jump table header right now.
8239 if (CurMBB == SwitchMBB) {
8240 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8241 JTH->Emitted = true;
8246 // FIXME: Optimize away range check based on pivot comparisons.
8247 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8249 // The bit test blocks haven't been inserted yet; insert them here.
8250 for (BitTestCase &BTC : BTB->Cases)
8251 CurMF->insert(BBI, BTC.ThisBB);
8253 // Fill in fields of the BitTestBlock.
8254 BTB->Parent = CurMBB;
8255 BTB->Default = Fallthrough;
8257 BTB->DefaultWeight = UnhandledWeights;
8258 // If the cases in bit test don't form a contiguous range, we evenly
8259 // distribute the weight on the edge to Fallthrough to two successors
8261 if (!BTB->ContiguousRange) {
8262 BTB->Weight += DefaultWeight / 2;
8263 BTB->DefaultWeight -= DefaultWeight / 2;
8266 // If we're in the right place, emit the bit test header right now.
8267 if (CurMBB == SwitchMBB) {
8268 visitBitTestHeader(*BTB, SwitchMBB);
8269 BTB->Emitted = true;
8274 const Value *RHS, *LHS, *MHS;
8276 if (I->Low == I->High) {
8277 // Check Cond == I->Low.
8283 // Check I->Low <= Cond <= I->High.
8290 // The false weight is the sum of all unhandled cases.
8291 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8294 if (CurMBB == SwitchMBB)
8295 visitSwitchCase(CB, SwitchMBB);
8297 SwitchCases.push_back(CB);
8302 CurMBB = Fallthrough;
8306 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8307 CaseClusterIt First,
8308 CaseClusterIt Last) {
8309 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8310 if (X.Weight != CC.Weight)
8311 return X.Weight > CC.Weight;
8313 // Ties are broken by comparing the case value.
8314 return X.Low->getValue().slt(CC.Low->getValue());
8318 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8319 const SwitchWorkListItem &W,
8321 MachineBasicBlock *SwitchMBB) {
8322 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8323 "Clusters not sorted?");
8325 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8327 // Balance the tree based on branch weights to create a near-optimal (in terms
8328 // of search time given key frequency) binary search tree. See e.g. Kurt
8329 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8330 CaseClusterIt LastLeft = W.FirstCluster;
8331 CaseClusterIt FirstRight = W.LastCluster;
8332 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8333 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8335 // Move LastLeft and FirstRight towards each other from opposite directions to
8336 // find a partitioning of the clusters which balances the weight on both
8337 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8338 // taken to ensure 0-weight nodes are distributed evenly.
8340 while (LastLeft + 1 < FirstRight) {
8341 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8342 LeftWeight += (++LastLeft)->Weight;
8344 RightWeight += (--FirstRight)->Weight;
8349 // Our binary search tree differs from a typical BST in that ours can have up
8350 // to three values in each leaf. The pivot selection above doesn't take that
8351 // into account, which means the tree might require more nodes and be less
8352 // efficient. We compensate for this here.
8354 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8355 unsigned NumRight = W.LastCluster - FirstRight + 1;
8357 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8358 // If one side has less than 3 clusters, and the other has more than 3,
8359 // consider taking a cluster from the other side.
8361 if (NumLeft < NumRight) {
8362 // Consider moving the first cluster on the right to the left side.
8363 CaseCluster &CC = *FirstRight;
8364 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8365 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8366 if (LeftSideRank <= RightSideRank) {
8367 // Moving the cluster to the left does not demote it.
8373 assert(NumRight < NumLeft);
8374 // Consider moving the last element on the left to the right side.
8375 CaseCluster &CC = *LastLeft;
8376 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8377 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8378 if (RightSideRank <= LeftSideRank) {
8379 // Moving the cluster to the right does not demot it.
8389 assert(LastLeft + 1 == FirstRight);
8390 assert(LastLeft >= W.FirstCluster);
8391 assert(FirstRight <= W.LastCluster);
8393 // Use the first element on the right as pivot since we will make less-than
8394 // comparisons against it.
8395 CaseClusterIt PivotCluster = FirstRight;
8396 assert(PivotCluster > W.FirstCluster);
8397 assert(PivotCluster <= W.LastCluster);
8399 CaseClusterIt FirstLeft = W.FirstCluster;
8400 CaseClusterIt LastRight = W.LastCluster;
8402 const ConstantInt *Pivot = PivotCluster->Low;
8404 // New blocks will be inserted immediately after the current one.
8405 MachineFunction::iterator BBI = W.MBB;
8408 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8409 // we can branch to its destination directly if it's squeezed exactly in
8410 // between the known lower bound and Pivot - 1.
8411 MachineBasicBlock *LeftMBB;
8412 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8413 FirstLeft->Low == W.GE &&
8414 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8415 LeftMBB = FirstLeft->MBB;
8417 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8418 FuncInfo.MF->insert(BBI, LeftMBB);
8420 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8421 // Put Cond in a virtual register to make it available from the new blocks.
8422 ExportFromCurrentBlock(Cond);
8425 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8426 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8427 // directly if RHS.High equals the current upper bound.
8428 MachineBasicBlock *RightMBB;
8429 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8430 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8431 RightMBB = FirstRight->MBB;
8433 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8434 FuncInfo.MF->insert(BBI, RightMBB);
8436 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8437 // Put Cond in a virtual register to make it available from the new blocks.
8438 ExportFromCurrentBlock(Cond);
8441 // Create the CaseBlock record that will be used to lower the branch.
8442 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8443 LeftWeight, RightWeight);
8445 if (W.MBB == SwitchMBB)
8446 visitSwitchCase(CB, SwitchMBB);
8448 SwitchCases.push_back(CB);
8451 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8452 // Extract cases from the switch.
8453 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8454 CaseClusterVector Clusters;
8455 Clusters.reserve(SI.getNumCases());
8456 for (auto I : SI.cases()) {
8457 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8458 const ConstantInt *CaseVal = I.getCaseValue();
8460 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8461 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8464 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8466 // Cluster adjacent cases with the same destination. We do this at all
8467 // optimization levels because it's cheap to do and will make codegen faster
8468 // if there are many clusters.
8469 sortAndRangeify(Clusters);
8471 if (TM.getOptLevel() != CodeGenOpt::None) {
8472 // Replace an unreachable default with the most popular destination.
8473 // FIXME: Exploit unreachable default more aggressively.
8474 bool UnreachableDefault =
8475 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8476 if (UnreachableDefault && !Clusters.empty()) {
8477 DenseMap<const BasicBlock *, unsigned> Popularity;
8478 unsigned MaxPop = 0;
8479 const BasicBlock *MaxBB = nullptr;
8480 for (auto I : SI.cases()) {
8481 const BasicBlock *BB = I.getCaseSuccessor();
8482 if (++Popularity[BB] > MaxPop) {
8483 MaxPop = Popularity[BB];
8488 assert(MaxPop > 0 && MaxBB);
8489 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8491 // Remove cases that were pointing to the destination that is now the
8493 CaseClusterVector New;
8494 New.reserve(Clusters.size());
8495 for (CaseCluster &CC : Clusters) {
8496 if (CC.MBB != DefaultMBB)
8499 Clusters = std::move(New);
8503 // If there is only the default destination, jump there directly.
8504 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8505 if (Clusters.empty()) {
8506 SwitchMBB->addSuccessor(DefaultMBB);
8507 if (DefaultMBB != NextBlock(SwitchMBB)) {
8508 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8509 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8514 findJumpTables(Clusters, &SI, DefaultMBB);
8515 findBitTestClusters(Clusters, &SI);
8518 dbgs() << "Case clusters: ";
8519 for (const CaseCluster &C : Clusters) {
8520 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8521 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8523 C.Low->getValue().print(dbgs(), true);
8524 if (C.Low != C.High) {
8526 C.High->getValue().print(dbgs(), true);
8533 assert(!Clusters.empty());
8534 SwitchWorkList WorkList;
8535 CaseClusterIt First = Clusters.begin();
8536 CaseClusterIt Last = Clusters.end() - 1;
8537 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8538 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8540 while (!WorkList.empty()) {
8541 SwitchWorkListItem W = WorkList.back();
8542 WorkList.pop_back();
8543 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8545 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8546 // For optimized builds, lower large range as a balanced binary tree.
8547 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8551 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);