1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
61 #include "llvm/Target/TargetSubtargetInfo.h"
65 #define DEBUG_TYPE "isel"
67 /// LimitFloatPrecision - Generate low-precision inline sequences for
68 /// some float libcalls (6, 8 or 12 bits).
69 static unsigned LimitFloatPrecision;
71 static cl::opt<unsigned, true>
72 LimitFPPrecision("limit-float-precision",
73 cl::desc("Generate low-precision inline sequences "
74 "for some float libcalls"),
75 cl::location(LimitFloatPrecision),
78 // Limit the width of DAG chains. This is important in general to prevent
79 // prevent DAG-based analysis from blowing up. For example, alias analysis and
80 // load clustering may not complete in reasonable time. It is difficult to
81 // recognize and avoid this situation within each individual analysis, and
82 // future analyses are likely to have the same behavior. Limiting DAG width is
83 // the safe approach, and will be especially important with global DAGs.
85 // MaxParallelChains default is arbitrarily high to avoid affecting
86 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
87 // sequence over this should have been converted to llvm.memcpy by the
88 // frontend. It easy to induce this behavior with .ll code such as:
89 // %buffer = alloca [4096 x i8]
90 // %data = load [4096 x i8]* %argPtr
91 // store [4096 x i8] %data, [4096 x i8]* %buffer
92 static const unsigned MaxParallelChains = 64;
94 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
95 const SDValue *Parts, unsigned NumParts,
96 MVT PartVT, EVT ValueVT, const Value *V);
98 /// getCopyFromParts - Create a value that contains the specified legal parts
99 /// combined into the value they represent. If the parts combine to a type
100 /// larger then ValueVT then AssertOp can be used to specify whether the extra
101 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
102 /// (ISD::AssertSext).
103 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts,
105 unsigned NumParts, MVT PartVT, EVT ValueVT,
107 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
108 if (ValueVT.isVector())
109 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
112 assert(NumParts > 0 && "No parts to assemble!");
113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
114 SDValue Val = Parts[0];
117 // Assemble the value from multiple parts.
118 if (ValueVT.isInteger()) {
119 unsigned PartBits = PartVT.getSizeInBits();
120 unsigned ValueBits = ValueVT.getSizeInBits();
122 // Assemble the power of 2 part.
123 unsigned RoundParts = NumParts & (NumParts - 1) ?
124 1 << Log2_32(NumParts) : NumParts;
125 unsigned RoundBits = PartBits * RoundParts;
126 EVT RoundVT = RoundBits == ValueBits ?
127 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
130 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
132 if (RoundParts > 2) {
133 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
135 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
136 RoundParts / 2, PartVT, HalfVT, V);
138 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
139 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
142 if (TLI.isBigEndian())
145 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
147 if (RoundParts < NumParts) {
148 // Assemble the trailing non-power-of-2 part.
149 unsigned OddParts = NumParts - RoundParts;
150 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
151 Hi = getCopyFromParts(DAG, DL,
152 Parts + RoundParts, OddParts, PartVT, OddVT, V);
154 // Combine the round and odd parts.
156 if (TLI.isBigEndian())
158 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
159 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
160 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
161 DAG.getConstant(Lo.getValueType().getSizeInBits(),
162 TLI.getPointerTy()));
163 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
164 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
166 } else if (PartVT.isFloatingPoint()) {
167 // FP split into multiple FP parts (for ppcf128)
168 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
171 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
172 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
173 if (TLI.hasBigEndianPartOrdering(ValueVT))
175 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
177 // FP split into integer parts (soft fp)
178 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
179 !PartVT.isVector() && "Unexpected split");
180 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
181 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 // There is now one part, held in Val. Correct it to match ValueVT.
186 EVT PartEVT = Val.getValueType();
188 if (PartEVT == ValueVT)
191 if (PartEVT.isInteger() && ValueVT.isInteger()) {
192 if (ValueVT.bitsLT(PartEVT)) {
193 // For a truncate, see if we have any information to
194 // indicate whether the truncated bits will always be
195 // zero or sign-extension.
196 if (AssertOp != ISD::DELETED_NODE)
197 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
198 DAG.getValueType(ValueVT));
199 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
201 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
204 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
205 // FP_ROUND's are always exact here.
206 if (ValueVT.bitsLT(Val.getValueType()))
207 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
208 DAG.getTargetConstant(1, TLI.getPointerTy()));
210 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
214 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
216 llvm_unreachable("Unknown mismatch!");
219 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
220 const Twine &ErrMsg) {
221 const Instruction *I = dyn_cast_or_null<Instruction>(V);
223 return Ctx.emitError(ErrMsg);
225 const char *AsmError = ", possible invalid constraint for vector type";
226 if (const CallInst *CI = dyn_cast<CallInst>(I))
227 if (isa<InlineAsm>(CI->getCalledValue()))
228 return Ctx.emitError(I, ErrMsg + AsmError);
230 return Ctx.emitError(I, ErrMsg);
233 /// getCopyFromPartsVector - Create a value that contains the specified legal
234 /// parts combined into the value they represent. If the parts combine to a
235 /// type larger then ValueVT then AssertOp can be used to specify whether the
236 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
237 /// ValueVT (ISD::AssertSext).
238 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
239 const SDValue *Parts, unsigned NumParts,
240 MVT PartVT, EVT ValueVT, const Value *V) {
241 assert(ValueVT.isVector() && "Not a vector value");
242 assert(NumParts > 0 && "No parts to assemble!");
243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
244 SDValue Val = Parts[0];
246 // Handle a multi-element vector.
250 unsigned NumIntermediates;
252 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
253 NumIntermediates, RegisterVT);
254 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
255 NumParts = NumRegs; // Silence a compiler warning.
256 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
257 assert(RegisterVT == Parts[0].getSimpleValueType() &&
258 "Part type doesn't match part!");
260 // Assemble the parts into intermediate operands.
261 SmallVector<SDValue, 8> Ops(NumIntermediates);
262 if (NumIntermediates == NumParts) {
263 // If the register was not expanded, truncate or copy the value,
265 for (unsigned i = 0; i != NumParts; ++i)
266 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
267 PartVT, IntermediateVT, V);
268 } else if (NumParts > 0) {
269 // If the intermediate type was expanded, build the intermediate
270 // operands from the parts.
271 assert(NumParts % NumIntermediates == 0 &&
272 "Must expand into a divisible number of parts!");
273 unsigned Factor = NumParts / NumIntermediates;
274 for (unsigned i = 0; i != NumIntermediates; ++i)
275 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
276 PartVT, IntermediateVT, V);
279 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
280 // intermediate operands.
281 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
286 // There is now one part, held in Val. Correct it to match ValueVT.
287 EVT PartEVT = Val.getValueType();
289 if (PartEVT == ValueVT)
292 if (PartEVT.isVector()) {
293 // If the element type of the source/dest vectors are the same, but the
294 // parts vector has more elements than the value vector, then we have a
295 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
297 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
298 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
299 "Cannot narrow, it would be a lossy transformation");
300 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
301 DAG.getConstant(0, TLI.getVectorIdxTy()));
304 // Vector/Vector bitcast.
305 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
306 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
308 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
309 "Cannot handle this kind of promotion");
310 // Promoted vector extract
311 bool Smaller = ValueVT.bitsLE(PartEVT);
312 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
317 // Trivial bitcast if the types are the same size and the destination
318 // vector type is legal.
319 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
320 TLI.isTypeLegal(ValueVT))
321 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
323 // Handle cases such as i8 -> <1 x i1>
324 if (ValueVT.getVectorNumElements() != 1) {
325 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
326 "non-trivial scalar-to-vector conversion");
327 return DAG.getUNDEF(ValueVT);
330 if (ValueVT.getVectorNumElements() == 1 &&
331 ValueVT.getVectorElementType() != PartEVT) {
332 bool Smaller = ValueVT.bitsLE(PartEVT);
333 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
334 DL, ValueVT.getScalarType(), Val);
337 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
340 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
341 SDValue Val, SDValue *Parts, unsigned NumParts,
342 MVT PartVT, const Value *V);
344 /// getCopyToParts - Create a series of nodes that contain the specified value
345 /// split into legal parts. If the parts contain more bits than Val, then, for
346 /// integers, ExtendKind can be used to specify how to generate the extra bits.
347 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V,
350 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
351 EVT ValueVT = Val.getValueType();
353 // Handle the vector case separately.
354 if (ValueVT.isVector())
355 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 unsigned PartBits = PartVT.getSizeInBits();
359 unsigned OrigNumParts = NumParts;
360 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
365 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
366 EVT PartEVT = PartVT;
367 if (PartEVT == ValueVT) {
368 assert(NumParts == 1 && "No-op copy with multiple parts!");
373 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
374 // If the parts cover more bits than the value has, promote the value.
375 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
376 assert(NumParts == 1 && "Do not know what to promote to!");
377 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
379 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
380 ValueVT.isInteger() &&
381 "Unknown mismatch!");
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
384 if (PartVT == MVT::x86mmx)
385 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
387 } else if (PartBits == ValueVT.getSizeInBits()) {
388 // Different types of the same size.
389 assert(NumParts == 1 && PartEVT != ValueVT);
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
392 // If the parts cover less bits than value has, truncate the value.
393 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
394 ValueVT.isInteger() &&
395 "Unknown mismatch!");
396 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
397 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
398 if (PartVT == MVT::x86mmx)
399 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
402 // The value may have changed - recompute ValueVT.
403 ValueVT = Val.getValueType();
404 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
405 "Failed to tile the value with PartVT!");
408 if (PartEVT != ValueVT)
409 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
410 "scalar-to-vector conversion failed");
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getConstant(i,
494 TLI.getVectorIdxTy())));
496 for (unsigned i = ValueVT.getVectorNumElements(),
497 e = PartVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getUNDEF(ElementVT));
500 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
502 // FIXME: Use CONCAT for 2x -> 4x.
504 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
505 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType().bitsGE(
508 ValueVT.getVectorElementType()) &&
509 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
511 // Promoted vector extract
512 bool Smaller = PartEVT.bitsLE(ValueVT);
513 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
516 // Vector -> scalar conversion.
517 assert(ValueVT.getVectorNumElements() == 1 &&
518 "Only trivial vector-to-scalar conversions should get here!");
519 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
520 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
522 bool Smaller = ValueVT.bitsLE(PartVT);
523 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
531 // Handle a multi-element vector.
534 unsigned NumIntermediates;
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
537 NumIntermediates, RegisterVT);
538 unsigned NumElements = ValueVT.getVectorNumElements();
540 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
541 NumParts = NumRegs; // Silence a compiler warning.
542 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
544 // Split the vector into intermediate operands.
545 SmallVector<SDValue, 8> Ops(NumIntermediates);
546 for (unsigned i = 0; i != NumIntermediates; ++i) {
547 if (IntermediateVT.isVector())
548 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
550 DAG.getConstant(i * (NumElements / NumIntermediates),
551 TLI.getVectorIdxTy()));
553 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
555 DAG.getConstant(i, TLI.getVectorIdxTy()));
558 // Split the intermediate operands into legal parts.
559 if (NumParts == NumIntermediates) {
560 // If the register was not expanded, promote or copy the value,
562 for (unsigned i = 0; i != NumParts; ++i)
563 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
564 } else if (NumParts > 0) {
565 // If the intermediate type was expanded, split each the value into
567 assert(NumParts % NumIntermediates == 0 &&
568 "Must expand into a divisible number of parts!");
569 unsigned Factor = NumParts / NumIntermediates;
570 for (unsigned i = 0; i != NumIntermediates; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 /// RegsForValue - This struct represents the registers (physical or virtual)
577 /// that a particular set of values is assigned, and the type information
578 /// about the value. The most common situation is to represent one value at a
579 /// time, but struct or array values are handled element-wise as multiple
580 /// values. The splitting of aggregates is performed recursively, so that we
581 /// never have aggregate-typed registers. The values at this point do not
582 /// necessarily have legal types, so each value may require one or more
583 /// registers of some legal type.
585 struct RegsForValue {
586 /// ValueVTs - The value types of the values, which may not be legal, and
587 /// may need be promoted or synthesized from one or more registers.
589 SmallVector<EVT, 4> ValueVTs;
591 /// RegVTs - The value types of the registers. This is the same size as
592 /// ValueVTs and it records, for each value, what the type of the assigned
593 /// register or registers are. (Individual values are never synthesized
594 /// from more than one type of register.)
596 /// With virtual registers, the contents of RegVTs is redundant with TLI's
597 /// getRegisterType member function, however when with physical registers
598 /// it is necessary to have a separate record of the types.
600 SmallVector<MVT, 4> RegVTs;
602 /// Regs - This list holds the registers assigned to the values.
603 /// Each legal or promoted value requires one register, and each
604 /// expanded value requires multiple registers.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
611 MVT regvt, EVT valuevt)
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
614 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
615 unsigned Reg, Type *Ty) {
616 ComputeValueVTs(tli, Ty, ValueVTs);
618 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
621 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
622 for (unsigned i = 0; i != NumRegs; ++i)
623 Regs.push_back(Reg + i);
624 RegVTs.push_back(RegisterVT);
629 /// append - Add the specified values to this one.
630 void append(const RegsForValue &RHS) {
631 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
632 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
633 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
636 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
637 /// this value and returns the result as a ValueVTs value. This uses
638 /// Chain/Flag as the input and updates them for the output Chain/Flag.
639 /// If the Flag pointer is NULL, no flag is used.
640 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
642 SDValue &Chain, SDValue *Flag,
643 const Value *V = nullptr) const;
645 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
646 /// specified value into the registers specified by this object. This uses
647 /// Chain/Flag as the input and updates them for the output Chain/Flag.
648 /// If the Flag pointer is NULL, no flag is used.
650 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
651 SDValue *Flag, const Value *V,
652 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
654 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
655 /// operand list. This adds the code marker, matching input operand index
656 /// (if applicable), and includes the number of values added into it.
657 void AddInlineAsmOperands(unsigned Kind,
658 bool HasMatching, unsigned MatchingIdx,
660 std::vector<SDValue> &Ops) const;
664 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
665 /// this value and returns the result as a ValueVT value. This uses
666 /// Chain/Flag as the input and updates them for the output Chain/Flag.
667 /// If the Flag pointer is NULL, no flag is used.
668 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
669 FunctionLoweringInfo &FuncInfo,
671 SDValue &Chain, SDValue *Flag,
672 const Value *V) const {
673 // A Value with type {} or [0 x %t] needs no registers.
674 if (ValueVTs.empty())
677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
679 // Assemble the legal parts into the final values.
680 SmallVector<SDValue, 4> Values(ValueVTs.size());
681 SmallVector<SDValue, 8> Parts;
682 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
683 // Copy the legal parts from the registers.
684 EVT ValueVT = ValueVTs[Value];
685 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
686 MVT RegisterVT = RegVTs[Value];
688 Parts.resize(NumRegs);
689 for (unsigned i = 0; i != NumRegs; ++i) {
692 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
694 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
695 *Flag = P.getValue(2);
698 Chain = P.getValue(1);
701 // If the source register was virtual and if we know something about it,
702 // add an assert node.
703 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
704 !RegisterVT.isInteger() || RegisterVT.isVector())
707 const FunctionLoweringInfo::LiveOutInfo *LOI =
708 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
712 unsigned RegSize = RegisterVT.getSizeInBits();
713 unsigned NumSignBits = LOI->NumSignBits;
714 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
716 if (NumZeroBits == RegSize) {
717 // The current value is a zero.
718 // Explicitly express that as it would be easier for
719 // optimizations to kick in.
720 Parts[i] = DAG.getConstant(0, RegisterVT);
724 // FIXME: We capture more information than the dag can represent. For
725 // now, just use the tightest assertzext/assertsext possible.
727 EVT FromVT(MVT::Other);
728 if (NumSignBits == RegSize)
729 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
730 else if (NumZeroBits >= RegSize-1)
731 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
732 else if (NumSignBits > RegSize-8)
733 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
734 else if (NumZeroBits >= RegSize-8)
735 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
736 else if (NumSignBits > RegSize-16)
737 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
738 else if (NumZeroBits >= RegSize-16)
739 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
740 else if (NumSignBits > RegSize-32)
741 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
742 else if (NumZeroBits >= RegSize-32)
743 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
747 // Add an assertion node.
748 assert(FromVT != MVT::Other);
749 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
750 RegisterVT, P, DAG.getValueType(FromVT));
753 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
754 NumRegs, RegisterVT, ValueVT, V);
759 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
762 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
763 /// specified value into the registers specified by this object. This uses
764 /// Chain/Flag as the input and updates them for the output Chain/Flag.
765 /// If the Flag pointer is NULL, no flag is used.
766 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
767 SDValue &Chain, SDValue *Flag, const Value *V,
768 ISD::NodeType PreferredExtendType) const {
769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
770 ISD::NodeType ExtendKind = PreferredExtendType;
772 // Get the list of the values's legal parts.
773 unsigned NumRegs = Regs.size();
774 SmallVector<SDValue, 8> Parts(NumRegs);
775 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
776 EVT ValueVT = ValueVTs[Value];
777 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
778 MVT RegisterVT = RegVTs[Value];
780 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
781 ExtendKind = ISD::ZERO_EXTEND;
783 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
784 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
788 // Copy the parts into the registers.
789 SmallVector<SDValue, 8> Chains(NumRegs);
790 for (unsigned i = 0; i != NumRegs; ++i) {
793 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
795 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
796 *Flag = Part.getValue(1);
799 Chains[i] = Part.getValue(0);
802 if (NumRegs == 1 || Flag)
803 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
804 // flagged to it. That is the CopyToReg nodes and the user are considered
805 // a single scheduling unit. If we create a TokenFactor and return it as
806 // chain, then the TokenFactor is both a predecessor (operand) of the
807 // user as well as a successor (the TF operands are flagged to the user).
808 // c1, f1 = CopyToReg
809 // c2, f2 = CopyToReg
810 // c3 = TokenFactor c1, c2
813 Chain = Chains[NumRegs-1];
815 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
818 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
819 /// operand list. This adds the code marker and includes the number of
820 /// values added into it.
821 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
822 unsigned MatchingIdx,
824 std::vector<SDValue> &Ops) const {
825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
827 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
829 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
830 else if (!Regs.empty() &&
831 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
832 // Put the register class of the virtual registers in the flag word. That
833 // way, later passes can recompute register class constraints for inline
834 // assembly as well as normal instructions.
835 // Don't do this for tied operands that can use the regclass information
837 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
838 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
839 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
842 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
845 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
846 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
847 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
848 MVT RegisterVT = RegVTs[Value];
849 for (unsigned i = 0; i != NumRegs; ++i) {
850 assert(Reg < Regs.size() && "Mismatch in # registers expected");
851 unsigned TheReg = Regs[Reg++];
852 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
854 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
855 // If we clobbered the stack pointer, MFI should know about it.
856 assert(DAG.getMachineFunction().getFrameInfo()->
857 hasInlineAsmWithSPAdjust());
863 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
864 const TargetLibraryInfo *li) {
868 DL = DAG.getSubtarget().getDataLayout();
869 Context = DAG.getContext();
870 LPadToCallSiteMap.clear();
873 /// clear - Clear out the current SelectionDAG and the associated
874 /// state and prepare this SelectionDAGBuilder object to be used
875 /// for a new block. This doesn't clear out information about
876 /// additional blocks that are needed to complete switch lowering
877 /// or PHI node updating; that information is cleared out as it is
879 void SelectionDAGBuilder::clear() {
881 UnusedArgNodeMap.clear();
882 PendingLoads.clear();
883 PendingExports.clear();
886 SDNodeOrder = LowestSDNodeOrder;
889 /// clearDanglingDebugInfo - Clear the dangling debug information
890 /// map. This function is separated from the clear so that debug
891 /// information that is dangling in a basic block can be properly
892 /// resolved in a different basic block. This allows the
893 /// SelectionDAG to resolve dangling debug information attached
895 void SelectionDAGBuilder::clearDanglingDebugInfo() {
896 DanglingDebugInfoMap.clear();
899 /// getRoot - Return the current virtual root of the Selection DAG,
900 /// flushing any PendingLoad items. This must be done before emitting
901 /// a store or any other node that may need to be ordered after any
902 /// prior load instructions.
904 SDValue SelectionDAGBuilder::getRoot() {
905 if (PendingLoads.empty())
906 return DAG.getRoot();
908 if (PendingLoads.size() == 1) {
909 SDValue Root = PendingLoads[0];
911 PendingLoads.clear();
915 // Otherwise, we have to make a token factor node.
916 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
918 PendingLoads.clear();
923 /// getControlRoot - Similar to getRoot, but instead of flushing all the
924 /// PendingLoad items, flush all the PendingExports items. It is necessary
925 /// to do this before emitting a terminator instruction.
927 SDValue SelectionDAGBuilder::getControlRoot() {
928 SDValue Root = DAG.getRoot();
930 if (PendingExports.empty())
933 // Turn all of the CopyToReg chains into one factored node.
934 if (Root.getOpcode() != ISD::EntryToken) {
935 unsigned i = 0, e = PendingExports.size();
936 for (; i != e; ++i) {
937 assert(PendingExports[i].getNode()->getNumOperands() > 1);
938 if (PendingExports[i].getNode()->getOperand(0) == Root)
939 break; // Don't add the root if we already indirectly depend on it.
943 PendingExports.push_back(Root);
946 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
948 PendingExports.clear();
953 void SelectionDAGBuilder::visit(const Instruction &I) {
954 // Set up outgoing PHI node register values before emitting the terminator.
955 if (isa<TerminatorInst>(&I))
956 HandlePHINodesInSuccessorBlocks(I.getParent());
962 visit(I.getOpcode(), I);
964 if (!isa<TerminatorInst>(&I) && !HasTailCall)
965 CopyToExportRegsIfNeeded(&I);
970 void SelectionDAGBuilder::visitPHI(const PHINode &) {
971 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
974 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
975 // Note: this doesn't use InstVisitor, because it has to work with
976 // ConstantExpr's in addition to instructions.
978 default: llvm_unreachable("Unknown instruction type encountered!");
979 // Build the switch statement using the Instruction.def file.
980 #define HANDLE_INST(NUM, OPCODE, CLASS) \
981 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
982 #include "llvm/IR/Instruction.def"
986 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
987 // generate the debug data structures now that we've seen its definition.
988 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
992 const DbgValueInst *DI = DDI.getDI();
993 DebugLoc dl = DDI.getdl();
994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
995 MDNode *Variable = DI->getVariable();
996 MDNode *Expr = DI->getExpression();
997 uint64_t Offset = DI->getOffset();
998 // A dbg.value for an alloca is always indirect.
999 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1001 if (Val.getNode()) {
1002 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1004 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1005 IsIndirect, Offset, dl, DbgSDNodeOrder);
1006 DAG.AddDbgValue(SDV, Val.getNode(), false);
1009 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1010 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1014 /// getValue - Return an SDValue for the given Value.
1015 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1016 // If we already have an SDValue for this value, use it. It's important
1017 // to do this first, so that we don't create a CopyFromReg if we already
1018 // have a regular SDValue.
1019 SDValue &N = NodeMap[V];
1020 if (N.getNode()) return N;
1022 // If there's a virtual register allocated and initialized for this
1024 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1029 SDValue Chain = DAG.getEntryNode();
1030 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1031 resolveDanglingDebugInfo(V, N);
1035 // Otherwise create a new SDValue and remember it.
1036 SDValue Val = getValueImpl(V);
1038 resolveDanglingDebugInfo(V, Val);
1042 /// getNonRegisterValue - Return an SDValue for the given Value, but
1043 /// don't look in FuncInfo.ValueMap for a virtual register.
1044 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1045 // If we already have an SDValue for this value, use it.
1046 SDValue &N = NodeMap[V];
1047 if (N.getNode()) return N;
1049 // Otherwise create a new SDValue and remember it.
1050 SDValue Val = getValueImpl(V);
1052 resolveDanglingDebugInfo(V, Val);
1056 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1057 /// Create an SDValue for the given value.
1058 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1061 if (const Constant *C = dyn_cast<Constant>(V)) {
1062 EVT VT = TLI.getValueType(V->getType(), true);
1064 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1065 return DAG.getConstant(*CI, VT);
1067 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1068 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1070 if (isa<ConstantPointerNull>(C)) {
1071 unsigned AS = V->getType()->getPointerAddressSpace();
1072 return DAG.getConstant(0, TLI.getPointerTy(AS));
1075 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1076 return DAG.getConstantFP(*CFP, VT);
1078 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1079 return DAG.getUNDEF(VT);
1081 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1082 visit(CE->getOpcode(), *CE);
1083 SDValue N1 = NodeMap[V];
1084 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1088 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1089 SmallVector<SDValue, 4> Constants;
1090 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1092 SDNode *Val = getValue(*OI).getNode();
1093 // If the operand is an empty aggregate, there are no values.
1095 // Add each leaf value from the operand to the Constants list
1096 // to form a flattened list of all the values.
1097 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1098 Constants.push_back(SDValue(Val, i));
1101 return DAG.getMergeValues(Constants, getCurSDLoc());
1104 if (const ConstantDataSequential *CDS =
1105 dyn_cast<ConstantDataSequential>(C)) {
1106 SmallVector<SDValue, 4> Ops;
1107 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1108 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1109 // Add each leaf value from the operand to the Constants list
1110 // to form a flattened list of all the values.
1111 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1112 Ops.push_back(SDValue(Val, i));
1115 if (isa<ArrayType>(CDS->getType()))
1116 return DAG.getMergeValues(Ops, getCurSDLoc());
1117 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1121 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1122 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1123 "Unknown struct or array constant!");
1125 SmallVector<EVT, 4> ValueVTs;
1126 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1127 unsigned NumElts = ValueVTs.size();
1129 return SDValue(); // empty struct
1130 SmallVector<SDValue, 4> Constants(NumElts);
1131 for (unsigned i = 0; i != NumElts; ++i) {
1132 EVT EltVT = ValueVTs[i];
1133 if (isa<UndefValue>(C))
1134 Constants[i] = DAG.getUNDEF(EltVT);
1135 else if (EltVT.isFloatingPoint())
1136 Constants[i] = DAG.getConstantFP(0, EltVT);
1138 Constants[i] = DAG.getConstant(0, EltVT);
1141 return DAG.getMergeValues(Constants, getCurSDLoc());
1144 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1145 return DAG.getBlockAddress(BA, VT);
1147 VectorType *VecTy = cast<VectorType>(V->getType());
1148 unsigned NumElements = VecTy->getNumElements();
1150 // Now that we know the number and type of the elements, get that number of
1151 // elements into the Ops array based on what kind of constant it is.
1152 SmallVector<SDValue, 16> Ops;
1153 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1154 for (unsigned i = 0; i != NumElements; ++i)
1155 Ops.push_back(getValue(CV->getOperand(i)));
1157 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1158 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1161 if (EltVT.isFloatingPoint())
1162 Op = DAG.getConstantFP(0, EltVT);
1164 Op = DAG.getConstant(0, EltVT);
1165 Ops.assign(NumElements, Op);
1168 // Create a BUILD_VECTOR node.
1169 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1172 // If this is a static alloca, generate it as the frameindex instead of
1174 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1175 DenseMap<const AllocaInst*, int>::iterator SI =
1176 FuncInfo.StaticAllocaMap.find(AI);
1177 if (SI != FuncInfo.StaticAllocaMap.end())
1178 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1181 // If this is an instruction which fast-isel has deferred, select it now.
1182 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1183 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1184 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1185 SDValue Chain = DAG.getEntryNode();
1186 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1189 llvm_unreachable("Can't get register for value!");
1192 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1194 SDValue Chain = getControlRoot();
1195 SmallVector<ISD::OutputArg, 8> Outs;
1196 SmallVector<SDValue, 8> OutVals;
1198 if (!FuncInfo.CanLowerReturn) {
1199 unsigned DemoteReg = FuncInfo.DemoteRegister;
1200 const Function *F = I.getParent()->getParent();
1202 // Emit a store of the return value through the virtual register.
1203 // Leave Outs empty so that LowerReturn won't try to load return
1204 // registers the usual way.
1205 SmallVector<EVT, 1> PtrValueVTs;
1206 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1209 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1210 SDValue RetOp = getValue(I.getOperand(0));
1212 SmallVector<EVT, 4> ValueVTs;
1213 SmallVector<uint64_t, 4> Offsets;
1214 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1215 unsigned NumValues = ValueVTs.size();
1217 SmallVector<SDValue, 4> Chains(NumValues);
1218 for (unsigned i = 0; i != NumValues; ++i) {
1219 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1220 RetPtr.getValueType(), RetPtr,
1221 DAG.getIntPtrConstant(Offsets[i]));
1223 DAG.getStore(Chain, getCurSDLoc(),
1224 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1225 // FIXME: better loc info would be nice.
1226 Add, MachinePointerInfo(), false, false, 0);
1229 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1230 MVT::Other, Chains);
1231 } else if (I.getNumOperands() != 0) {
1232 SmallVector<EVT, 4> ValueVTs;
1233 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1234 unsigned NumValues = ValueVTs.size();
1236 SDValue RetOp = getValue(I.getOperand(0));
1237 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1238 EVT VT = ValueVTs[j];
1240 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1242 const Function *F = I.getParent()->getParent();
1243 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1245 ExtendKind = ISD::SIGN_EXTEND;
1246 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1248 ExtendKind = ISD::ZERO_EXTEND;
1250 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1251 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1253 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1254 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1255 SmallVector<SDValue, 4> Parts(NumParts);
1256 getCopyToParts(DAG, getCurSDLoc(),
1257 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1258 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1260 // 'inreg' on function refers to return value
1261 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1262 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1266 // Propagate extension type if any
1267 if (ExtendKind == ISD::SIGN_EXTEND)
1269 else if (ExtendKind == ISD::ZERO_EXTEND)
1272 for (unsigned i = 0; i < NumParts; ++i) {
1273 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1274 VT, /*isfixed=*/true, 0, 0));
1275 OutVals.push_back(Parts[i]);
1281 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1282 CallingConv::ID CallConv =
1283 DAG.getMachineFunction().getFunction()->getCallingConv();
1284 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1285 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1287 // Verify that the target's LowerReturn behaved as expected.
1288 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1289 "LowerReturn didn't return a valid chain!");
1291 // Update the DAG with the new chain value resulting from return lowering.
1295 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1296 /// created for it, emit nodes to copy the value into the virtual
1298 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1300 if (V->getType()->isEmptyTy())
1303 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1304 if (VMI != FuncInfo.ValueMap.end()) {
1305 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1306 CopyValueToVirtualRegister(V, VMI->second);
1310 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1311 /// the current basic block, add it to ValueMap now so that we'll get a
1313 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1314 // No need to export constants.
1315 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1317 // Already exported?
1318 if (FuncInfo.isExportedInst(V)) return;
1320 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1321 CopyValueToVirtualRegister(V, Reg);
1324 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1325 const BasicBlock *FromBB) {
1326 // The operands of the setcc have to be in this block. We don't know
1327 // how to export them from some other block.
1328 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1329 // Can export from current BB.
1330 if (VI->getParent() == FromBB)
1333 // Is already exported, noop.
1334 return FuncInfo.isExportedInst(V);
1337 // If this is an argument, we can export it if the BB is the entry block or
1338 // if it is already exported.
1339 if (isa<Argument>(V)) {
1340 if (FromBB == &FromBB->getParent()->getEntryBlock())
1343 // Otherwise, can only export this if it is already exported.
1344 return FuncInfo.isExportedInst(V);
1347 // Otherwise, constants can always be exported.
1351 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1352 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1353 const MachineBasicBlock *Dst) const {
1354 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1357 const BasicBlock *SrcBB = Src->getBasicBlock();
1358 const BasicBlock *DstBB = Dst->getBasicBlock();
1359 return BPI->getEdgeWeight(SrcBB, DstBB);
1362 void SelectionDAGBuilder::
1363 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1364 uint32_t Weight /* = 0 */) {
1366 Weight = getEdgeWeight(Src, Dst);
1367 Src->addSuccessor(Dst, Weight);
1371 static bool InBlock(const Value *V, const BasicBlock *BB) {
1372 if (const Instruction *I = dyn_cast<Instruction>(V))
1373 return I->getParent() == BB;
1377 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1378 /// This function emits a branch and is used at the leaves of an OR or an
1379 /// AND operator tree.
1382 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1383 MachineBasicBlock *TBB,
1384 MachineBasicBlock *FBB,
1385 MachineBasicBlock *CurBB,
1386 MachineBasicBlock *SwitchBB,
1389 const BasicBlock *BB = CurBB->getBasicBlock();
1391 // If the leaf of the tree is a comparison, merge the condition into
1393 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1394 // The operands of the cmp have to be in this block. We don't know
1395 // how to export them from some other block. If this is the first block
1396 // of the sequence, no exporting is needed.
1397 if (CurBB == SwitchBB ||
1398 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1399 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1400 ISD::CondCode Condition;
1401 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1402 Condition = getICmpCondCode(IC->getPredicate());
1403 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1404 Condition = getFCmpCondCode(FC->getPredicate());
1405 if (TM.Options.NoNaNsFPMath)
1406 Condition = getFCmpCodeWithoutNaN(Condition);
1408 Condition = ISD::SETEQ; // silence warning.
1409 llvm_unreachable("Unknown compare instruction");
1412 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1413 TBB, FBB, CurBB, TWeight, FWeight);
1414 SwitchCases.push_back(CB);
1419 // Create a CaseBlock record representing this branch.
1420 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1421 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1422 SwitchCases.push_back(CB);
1425 /// Scale down both weights to fit into uint32_t.
1426 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1427 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1428 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1429 NewTrue = NewTrue / Scale;
1430 NewFalse = NewFalse / Scale;
1433 /// FindMergedConditions - If Cond is an expression like
1434 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1435 MachineBasicBlock *TBB,
1436 MachineBasicBlock *FBB,
1437 MachineBasicBlock *CurBB,
1438 MachineBasicBlock *SwitchBB,
1439 unsigned Opc, uint32_t TWeight,
1441 // If this node is not part of the or/and tree, emit it as a branch.
1442 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1443 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1444 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1445 BOp->getParent() != CurBB->getBasicBlock() ||
1446 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1447 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1448 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1453 // Create TmpBB after CurBB.
1454 MachineFunction::iterator BBI = CurBB;
1455 MachineFunction &MF = DAG.getMachineFunction();
1456 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1457 CurBB->getParent()->insert(++BBI, TmpBB);
1459 if (Opc == Instruction::Or) {
1460 // Codegen X | Y as:
1469 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1470 // The requirement is that
1471 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1472 // = TrueProb for orignal BB.
1473 // Assuming the orignal weights are A and B, one choice is to set BB1's
1474 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1476 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1477 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1478 // TmpBB, but the math is more complicated.
1480 uint64_t NewTrueWeight = TWeight;
1481 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1482 ScaleWeights(NewTrueWeight, NewFalseWeight);
1483 // Emit the LHS condition.
1484 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1485 NewTrueWeight, NewFalseWeight);
1487 NewTrueWeight = TWeight;
1488 NewFalseWeight = 2 * (uint64_t)FWeight;
1489 ScaleWeights(NewTrueWeight, NewFalseWeight);
1490 // Emit the RHS condition into TmpBB.
1491 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1492 NewTrueWeight, NewFalseWeight);
1494 assert(Opc == Instruction::And && "Unknown merge op!");
1495 // Codegen X & Y as:
1503 // This requires creation of TmpBB after CurBB.
1505 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1506 // The requirement is that
1507 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1508 // = FalseProb for orignal BB.
1509 // Assuming the orignal weights are A and B, one choice is to set BB1's
1510 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1512 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1514 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1515 uint64_t NewFalseWeight = FWeight;
1516 ScaleWeights(NewTrueWeight, NewFalseWeight);
1517 // Emit the LHS condition.
1518 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1519 NewTrueWeight, NewFalseWeight);
1521 NewTrueWeight = 2 * (uint64_t)TWeight;
1522 NewFalseWeight = FWeight;
1523 ScaleWeights(NewTrueWeight, NewFalseWeight);
1524 // Emit the RHS condition into TmpBB.
1525 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1526 NewTrueWeight, NewFalseWeight);
1530 /// If the set of cases should be emitted as a series of branches, return true.
1531 /// If we should emit this as a bunch of and/or'd together conditions, return
1534 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1535 if (Cases.size() != 2) return true;
1537 // If this is two comparisons of the same values or'd or and'd together, they
1538 // will get folded into a single comparison, so don't emit two blocks.
1539 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1540 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1541 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1542 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1546 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1547 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1548 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1549 Cases[0].CC == Cases[1].CC &&
1550 isa<Constant>(Cases[0].CmpRHS) &&
1551 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1552 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1554 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1561 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1562 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1564 // Update machine-CFG edges.
1565 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1567 // Figure out which block is immediately after the current one.
1568 MachineBasicBlock *NextBlock = nullptr;
1569 MachineFunction::iterator BBI = BrMBB;
1570 if (++BBI != FuncInfo.MF->end())
1573 if (I.isUnconditional()) {
1574 // Update machine-CFG edges.
1575 BrMBB->addSuccessor(Succ0MBB);
1577 // If this is not a fall-through branch or optimizations are switched off,
1579 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1580 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1581 MVT::Other, getControlRoot(),
1582 DAG.getBasicBlock(Succ0MBB)));
1587 // If this condition is one of the special cases we handle, do special stuff
1589 const Value *CondVal = I.getCondition();
1590 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1592 // If this is a series of conditions that are or'd or and'd together, emit
1593 // this as a sequence of branches instead of setcc's with and/or operations.
1594 // As long as jumps are not expensive, this should improve performance.
1595 // For example, instead of something like:
1608 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1609 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1610 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1611 BOp->getOpcode() == Instruction::Or)) {
1612 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1613 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1614 getEdgeWeight(BrMBB, Succ1MBB));
1615 // If the compares in later blocks need to use values not currently
1616 // exported from this block, export them now. This block should always
1617 // be the first entry.
1618 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1620 // Allow some cases to be rejected.
1621 if (ShouldEmitAsBranches(SwitchCases)) {
1622 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1623 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1624 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1627 // Emit the branch for this block.
1628 visitSwitchCase(SwitchCases[0], BrMBB);
1629 SwitchCases.erase(SwitchCases.begin());
1633 // Okay, we decided not to do this, remove any inserted MBB's and clear
1635 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1636 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1638 SwitchCases.clear();
1642 // Create a CaseBlock record representing this branch.
1643 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1644 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1646 // Use visitSwitchCase to actually insert the fast branch sequence for this
1648 visitSwitchCase(CB, BrMBB);
1651 /// visitSwitchCase - Emits the necessary code to represent a single node in
1652 /// the binary search tree resulting from lowering a switch instruction.
1653 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1654 MachineBasicBlock *SwitchBB) {
1656 SDValue CondLHS = getValue(CB.CmpLHS);
1657 SDLoc dl = getCurSDLoc();
1659 // Build the setcc now.
1661 // Fold "(X == true)" to X and "(X == false)" to !X to
1662 // handle common cases produced by branch lowering.
1663 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1664 CB.CC == ISD::SETEQ)
1666 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1667 CB.CC == ISD::SETEQ) {
1668 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1669 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1671 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1673 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1675 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1676 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1678 SDValue CmpOp = getValue(CB.CmpMHS);
1679 EVT VT = CmpOp.getValueType();
1681 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1682 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1685 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1686 VT, CmpOp, DAG.getConstant(Low, VT));
1687 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1688 DAG.getConstant(High-Low, VT), ISD::SETULE);
1692 // Update successor info
1693 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1694 // TrueBB and FalseBB are always different unless the incoming IR is
1695 // degenerate. This only happens when running llc on weird IR.
1696 if (CB.TrueBB != CB.FalseBB)
1697 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1699 // Set NextBlock to be the MBB immediately after the current one, if any.
1700 // This is used to avoid emitting unnecessary branches to the next block.
1701 MachineBasicBlock *NextBlock = nullptr;
1702 MachineFunction::iterator BBI = SwitchBB;
1703 if (++BBI != FuncInfo.MF->end())
1706 // If the lhs block is the next block, invert the condition so that we can
1707 // fall through to the lhs instead of the rhs block.
1708 if (CB.TrueBB == NextBlock) {
1709 std::swap(CB.TrueBB, CB.FalseBB);
1710 SDValue True = DAG.getConstant(1, Cond.getValueType());
1711 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1714 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1715 MVT::Other, getControlRoot(), Cond,
1716 DAG.getBasicBlock(CB.TrueBB));
1718 // Insert the false branch. Do this even if it's a fall through branch,
1719 // this makes it easier to do DAG optimizations which require inverting
1720 // the branch condition.
1721 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1722 DAG.getBasicBlock(CB.FalseBB));
1724 DAG.setRoot(BrCond);
1727 /// visitJumpTable - Emit JumpTable node in the current MBB
1728 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1729 // Emit the code for the jump table
1730 assert(JT.Reg != -1U && "Should lower JT Header first!");
1731 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1732 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1734 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1735 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1736 MVT::Other, Index.getValue(1),
1738 DAG.setRoot(BrJumpTable);
1741 /// visitJumpTableHeader - This function emits necessary code to produce index
1742 /// in the JumpTable from switch case.
1743 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1744 JumpTableHeader &JTH,
1745 MachineBasicBlock *SwitchBB) {
1746 // Subtract the lowest switch case value from the value being switched on and
1747 // conditional branch to default mbb if the result is greater than the
1748 // difference between smallest and largest cases.
1749 SDValue SwitchOp = getValue(JTH.SValue);
1750 EVT VT = SwitchOp.getValueType();
1751 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1752 DAG.getConstant(JTH.First, VT));
1754 // The SDNode we just created, which holds the value being switched on minus
1755 // the smallest case value, needs to be copied to a virtual register so it
1756 // can be used as an index into the jump table in a subsequent basic block.
1757 // This value may be smaller or larger than the target's pointer type, and
1758 // therefore require extension or truncating.
1759 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1760 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1762 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1763 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1764 JumpTableReg, SwitchOp);
1765 JT.Reg = JumpTableReg;
1767 // Emit the range check for the jump table, and branch to the default block
1768 // for the switch statement if the value being switched on exceeds the largest
1769 // case in the switch.
1771 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1772 Sub.getValueType()),
1773 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1775 // Set NextBlock to be the MBB immediately after the current one, if any.
1776 // This is used to avoid emitting unnecessary branches to the next block.
1777 MachineBasicBlock *NextBlock = nullptr;
1778 MachineFunction::iterator BBI = SwitchBB;
1780 if (++BBI != FuncInfo.MF->end())
1783 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1784 MVT::Other, CopyTo, CMP,
1785 DAG.getBasicBlock(JT.Default));
1787 if (JT.MBB != NextBlock)
1788 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1789 DAG.getBasicBlock(JT.MBB));
1791 DAG.setRoot(BrCond);
1794 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1795 /// tail spliced into a stack protector check success bb.
1797 /// For a high level explanation of how this fits into the stack protector
1798 /// generation see the comment on the declaration of class
1799 /// StackProtectorDescriptor.
1800 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1801 MachineBasicBlock *ParentBB) {
1803 // First create the loads to the guard/stack slot for the comparison.
1804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1805 EVT PtrTy = TLI.getPointerTy();
1807 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1808 int FI = MFI->getStackProtectorIndex();
1810 const Value *IRGuard = SPD.getGuard();
1811 SDValue GuardPtr = getValue(IRGuard);
1812 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1815 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1819 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1820 // guard value from the virtual register holding the value. Otherwise, emit a
1821 // volatile load to retrieve the stack guard value.
1822 unsigned GuardReg = SPD.getGuardReg();
1824 if (GuardReg && TLI.useLoadStackGuardNode())
1825 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1828 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1829 GuardPtr, MachinePointerInfo(IRGuard, 0),
1830 true, false, false, Align);
1832 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1834 MachinePointerInfo::getFixedStack(FI),
1835 true, false, false, Align);
1837 // Perform the comparison via a subtract/getsetcc.
1838 EVT VT = Guard.getValueType();
1839 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1842 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1843 Sub.getValueType()),
1844 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1846 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1847 // branch to failure MBB.
1848 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1849 MVT::Other, StackSlot.getOperand(0),
1850 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1851 // Otherwise branch to success MBB.
1852 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1854 DAG.getBasicBlock(SPD.getSuccessMBB()));
1859 /// Codegen the failure basic block for a stack protector check.
1861 /// A failure stack protector machine basic block consists simply of a call to
1862 /// __stack_chk_fail().
1864 /// For a high level explanation of how this fits into the stack protector
1865 /// generation see the comment on the declaration of class
1866 /// StackProtectorDescriptor.
1868 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1869 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1871 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1872 nullptr, 0, false, getCurSDLoc(), false, false).second;
1876 /// visitBitTestHeader - This function emits necessary code to produce value
1877 /// suitable for "bit tests"
1878 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1879 MachineBasicBlock *SwitchBB) {
1880 // Subtract the minimum value
1881 SDValue SwitchOp = getValue(B.SValue);
1882 EVT VT = SwitchOp.getValueType();
1883 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1884 DAG.getConstant(B.First, VT));
1887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1889 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1890 Sub.getValueType()),
1891 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1893 // Determine the type of the test operands.
1894 bool UsePtrType = false;
1895 if (!TLI.isTypeLegal(VT))
1898 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1899 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1900 // Switch table case range are encoded into series of masks.
1901 // Just use pointer type, it's guaranteed to fit.
1907 VT = TLI.getPointerTy();
1908 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1911 B.RegVT = VT.getSimpleVT();
1912 B.Reg = FuncInfo.CreateReg(B.RegVT);
1913 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1916 // Set NextBlock to be the MBB immediately after the current one, if any.
1917 // This is used to avoid emitting unnecessary branches to the next block.
1918 MachineBasicBlock *NextBlock = nullptr;
1919 MachineFunction::iterator BBI = SwitchBB;
1920 if (++BBI != FuncInfo.MF->end())
1923 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1925 addSuccessorWithWeight(SwitchBB, B.Default);
1926 addSuccessorWithWeight(SwitchBB, MBB);
1928 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1929 MVT::Other, CopyTo, RangeCmp,
1930 DAG.getBasicBlock(B.Default));
1932 if (MBB != NextBlock)
1933 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1934 DAG.getBasicBlock(MBB));
1936 DAG.setRoot(BrRange);
1939 /// visitBitTestCase - this function produces one "bit test"
1940 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1941 MachineBasicBlock* NextMBB,
1942 uint32_t BranchWeightToNext,
1945 MachineBasicBlock *SwitchBB) {
1947 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1950 unsigned PopCount = CountPopulation_64(B.Mask);
1951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1952 if (PopCount == 1) {
1953 // Testing for a single bit; just compare the shift count with what it
1954 // would need to be to shift a 1 bit in that position.
1956 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1957 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1958 } else if (PopCount == BB.Range) {
1959 // There is only one zero bit in the range, test for it directly.
1961 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1962 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), ISD::SETNE);
1964 // Make desired shift
1965 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1966 DAG.getConstant(1, VT), ShiftOp);
1968 // Emit bit tests and jumps
1969 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1970 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1971 Cmp = DAG.getSetCC(getCurSDLoc(),
1972 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1973 DAG.getConstant(0, VT), ISD::SETNE);
1976 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1977 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1978 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1979 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1981 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1982 MVT::Other, getControlRoot(),
1983 Cmp, DAG.getBasicBlock(B.TargetBB));
1985 // Set NextBlock to be the MBB immediately after the current one, if any.
1986 // This is used to avoid emitting unnecessary branches to the next block.
1987 MachineBasicBlock *NextBlock = nullptr;
1988 MachineFunction::iterator BBI = SwitchBB;
1989 if (++BBI != FuncInfo.MF->end())
1992 if (NextMBB != NextBlock)
1993 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1994 DAG.getBasicBlock(NextMBB));
1999 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2000 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2002 // Retrieve successors.
2003 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2004 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2006 const Value *Callee(I.getCalledValue());
2007 const Function *Fn = dyn_cast<Function>(Callee);
2008 if (isa<InlineAsm>(Callee))
2010 else if (Fn && Fn->isIntrinsic()) {
2011 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2012 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2014 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2016 // If the value of the invoke is used outside of its defining block, make it
2017 // available as a virtual register.
2018 CopyToExportRegsIfNeeded(&I);
2020 // Update successor info
2021 addSuccessorWithWeight(InvokeMBB, Return);
2022 addSuccessorWithWeight(InvokeMBB, LandingPad);
2024 // Drop into normal successor.
2025 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2026 MVT::Other, getControlRoot(),
2027 DAG.getBasicBlock(Return)));
2030 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2031 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2034 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2035 assert(FuncInfo.MBB->isLandingPad() &&
2036 "Call to landingpad not in landing pad!");
2038 MachineBasicBlock *MBB = FuncInfo.MBB;
2039 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2040 AddLandingPadInfo(LP, MMI, MBB);
2042 // If there aren't registers to copy the values into (e.g., during SjLj
2043 // exceptions), then don't bother to create these DAG nodes.
2044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2045 if (TLI.getExceptionPointerRegister() == 0 &&
2046 TLI.getExceptionSelectorRegister() == 0)
2049 SmallVector<EVT, 2> ValueVTs;
2050 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2051 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2053 // Get the two live-in registers as SDValues. The physregs have already been
2054 // copied into virtual registers.
2056 Ops[0] = DAG.getZExtOrTrunc(
2057 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2058 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2059 getCurSDLoc(), ValueVTs[0]);
2060 Ops[1] = DAG.getZExtOrTrunc(
2061 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2062 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2063 getCurSDLoc(), ValueVTs[1]);
2066 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2067 DAG.getVTList(ValueVTs), Ops);
2071 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2072 /// small case ranges).
2073 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2074 CaseRecVector& WorkList,
2076 MachineBasicBlock *Default,
2077 MachineBasicBlock *SwitchBB) {
2078 // Size is the number of Cases represented by this range.
2079 size_t Size = CR.Range.second - CR.Range.first;
2083 // Get the MachineFunction which holds the current MBB. This is used when
2084 // inserting any additional MBBs necessary to represent the switch.
2085 MachineFunction *CurMF = FuncInfo.MF;
2087 // Figure out which block is immediately after the current one.
2088 MachineBasicBlock *NextBlock = nullptr;
2089 MachineFunction::iterator BBI = CR.CaseBB;
2091 if (++BBI != FuncInfo.MF->end())
2094 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2095 // If any two of the cases has the same destination, and if one value
2096 // is the same as the other, but has one bit unset that the other has set,
2097 // use bit manipulation to do two compares at once. For example:
2098 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2099 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2100 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2101 if (Size == 2 && CR.CaseBB == SwitchBB) {
2102 Case &Small = *CR.Range.first;
2103 Case &Big = *(CR.Range.second-1);
2105 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2106 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2107 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2109 // Check that there is only one bit different.
2110 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2111 (SmallValue | BigValue) == BigValue) {
2112 // Isolate the common bit.
2113 APInt CommonBit = BigValue & ~SmallValue;
2114 assert((SmallValue | CommonBit) == BigValue &&
2115 CommonBit.countPopulation() == 1 && "Not a common bit?");
2117 SDValue CondLHS = getValue(SV);
2118 EVT VT = CondLHS.getValueType();
2119 SDLoc DL = getCurSDLoc();
2121 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2122 DAG.getConstant(CommonBit, VT));
2123 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2124 Or, DAG.getConstant(BigValue, VT),
2127 // Update successor info.
2128 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2129 addSuccessorWithWeight(SwitchBB, Small.BB,
2130 Small.ExtraWeight + Big.ExtraWeight);
2131 addSuccessorWithWeight(SwitchBB, Default,
2132 // The default destination is the first successor in IR.
2133 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2135 // Insert the true branch.
2136 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2137 getControlRoot(), Cond,
2138 DAG.getBasicBlock(Small.BB));
2140 // Insert the false branch.
2141 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2142 DAG.getBasicBlock(Default));
2144 DAG.setRoot(BrCond);
2150 // Order cases by weight so the most likely case will be checked first.
2151 uint32_t UnhandledWeights = 0;
2153 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2154 uint32_t IWeight = I->ExtraWeight;
2155 UnhandledWeights += IWeight;
2156 for (CaseItr J = CR.Range.first; J < I; ++J) {
2157 uint32_t JWeight = J->ExtraWeight;
2158 if (IWeight > JWeight)
2163 // Rearrange the case blocks so that the last one falls through if possible.
2164 Case &BackCase = *(CR.Range.second-1);
2166 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2167 // The last case block won't fall through into 'NextBlock' if we emit the
2168 // branches in this order. See if rearranging a case value would help.
2169 // We start at the bottom as it's the case with the least weight.
2170 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2171 if (I->BB == NextBlock) {
2172 std::swap(*I, BackCase);
2177 // Create a CaseBlock record representing a conditional branch to
2178 // the Case's target mbb if the value being switched on SV is equal
2180 MachineBasicBlock *CurBlock = CR.CaseBB;
2181 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2182 MachineBasicBlock *FallThrough;
2184 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2185 CurMF->insert(BBI, FallThrough);
2187 // Put SV in a virtual register to make it available from the new blocks.
2188 ExportFromCurrentBlock(SV);
2190 // If the last case doesn't match, go to the default block.
2191 FallThrough = Default;
2194 const Value *RHS, *LHS, *MHS;
2196 if (I->High == I->Low) {
2197 // This is just small small case range :) containing exactly 1 case
2199 LHS = SV; RHS = I->High; MHS = nullptr;
2202 LHS = I->Low; MHS = SV; RHS = I->High;
2205 // The false weight should be sum of all un-handled cases.
2206 UnhandledWeights -= I->ExtraWeight;
2207 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2209 /* trueweight */ I->ExtraWeight,
2210 /* falseweight */ UnhandledWeights);
2212 // If emitting the first comparison, just call visitSwitchCase to emit the
2213 // code into the current block. Otherwise, push the CaseBlock onto the
2214 // vector to be later processed by SDISel, and insert the node's MBB
2215 // before the next MBB.
2216 if (CurBlock == SwitchBB)
2217 visitSwitchCase(CB, SwitchBB);
2219 SwitchCases.push_back(CB);
2221 CurBlock = FallThrough;
2227 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2228 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2229 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2232 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2233 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2234 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2235 return (LastExt - FirstExt + 1ULL);
2238 /// handleJTSwitchCase - Emit jumptable for current switch case range
2239 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2240 CaseRecVector &WorkList,
2242 MachineBasicBlock *Default,
2243 MachineBasicBlock *SwitchBB) {
2244 Case& FrontCase = *CR.Range.first;
2245 Case& BackCase = *(CR.Range.second-1);
2247 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2248 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2250 APInt TSize(First.getBitWidth(), 0);
2251 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2255 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2258 APInt Range = ComputeRange(First, Last);
2259 // The density is TSize / Range. Require at least 40%.
2260 // It should not be possible for IntTSize to saturate for sane code, but make
2261 // sure we handle Range saturation correctly.
2262 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2263 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2264 if (IntTSize * 10 < IntRange * 4)
2267 DEBUG(dbgs() << "Lowering jump table\n"
2268 << "First entry: " << First << ". Last entry: " << Last << '\n'
2269 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2271 // Get the MachineFunction which holds the current MBB. This is used when
2272 // inserting any additional MBBs necessary to represent the switch.
2273 MachineFunction *CurMF = FuncInfo.MF;
2275 // Figure out which block is immediately after the current one.
2276 MachineFunction::iterator BBI = CR.CaseBB;
2279 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2281 // Create a new basic block to hold the code for loading the address
2282 // of the jump table, and jumping to it. Update successor information;
2283 // we will either branch to the default case for the switch, or the jump
2285 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2286 CurMF->insert(BBI, JumpTableBB);
2288 addSuccessorWithWeight(CR.CaseBB, Default);
2289 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2291 // Build a vector of destination BBs, corresponding to each target
2292 // of the jump table. If the value of the jump table slot corresponds to
2293 // a case statement, push the case's BB onto the vector, otherwise, push
2295 std::vector<MachineBasicBlock*> DestBBs;
2297 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2298 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2299 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2301 if (Low.sle(TEI) && TEI.sle(High)) {
2302 DestBBs.push_back(I->BB);
2306 DestBBs.push_back(Default);
2310 // Calculate weight for each unique destination in CR.
2311 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2313 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2314 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2315 DestWeights.find(I->BB);
2316 if (Itr != DestWeights.end())
2317 Itr->second += I->ExtraWeight;
2319 DestWeights[I->BB] = I->ExtraWeight;
2322 // Update successor info. Add one edge to each unique successor.
2323 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2324 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2325 E = DestBBs.end(); I != E; ++I) {
2326 if (!SuccsHandled[(*I)->getNumber()]) {
2327 SuccsHandled[(*I)->getNumber()] = true;
2328 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2329 DestWeights.find(*I);
2330 addSuccessorWithWeight(JumpTableBB, *I,
2331 Itr != DestWeights.end() ? Itr->second : 0);
2335 // Create a jump table index for this jump table.
2336 unsigned JTEncoding = TLI.getJumpTableEncoding();
2337 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2338 ->createJumpTableIndex(DestBBs);
2340 // Set the jump table information so that we can codegen it as a second
2341 // MachineBasicBlock
2342 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2343 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2344 if (CR.CaseBB == SwitchBB)
2345 visitJumpTableHeader(JT, JTH, SwitchBB);
2347 JTCases.push_back(JumpTableBlock(JTH, JT));
2351 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2353 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2354 CaseRecVector& WorkList,
2356 MachineBasicBlock* Default,
2357 MachineBasicBlock* SwitchBB) {
2358 // Get the MachineFunction which holds the current MBB. This is used when
2359 // inserting any additional MBBs necessary to represent the switch.
2360 MachineFunction *CurMF = FuncInfo.MF;
2362 // Figure out which block is immediately after the current one.
2363 MachineFunction::iterator BBI = CR.CaseBB;
2366 Case& FrontCase = *CR.Range.first;
2367 Case& BackCase = *(CR.Range.second-1);
2368 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2370 // Size is the number of Cases represented by this range.
2371 unsigned Size = CR.Range.second - CR.Range.first;
2373 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2374 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2376 CaseItr Pivot = CR.Range.first + Size/2;
2378 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2379 // (heuristically) allow us to emit JumpTable's later.
2380 APInt TSize(First.getBitWidth(), 0);
2381 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2385 APInt LSize = FrontCase.size();
2386 APInt RSize = TSize-LSize;
2387 DEBUG(dbgs() << "Selecting best pivot: \n"
2388 << "First: " << First << ", Last: " << Last <<'\n'
2389 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2390 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2392 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2393 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2394 APInt Range = ComputeRange(LEnd, RBegin);
2395 assert((Range - 2ULL).isNonNegative() &&
2396 "Invalid case distance");
2397 // Use volatile double here to avoid excess precision issues on some hosts,
2398 // e.g. that use 80-bit X87 registers.
2399 volatile double LDensity =
2400 (double)LSize.roundToDouble() /
2401 (LEnd - First + 1ULL).roundToDouble();
2402 volatile double RDensity =
2403 (double)RSize.roundToDouble() /
2404 (Last - RBegin + 1ULL).roundToDouble();
2405 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2406 // Should always split in some non-trivial place
2407 DEBUG(dbgs() <<"=>Step\n"
2408 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2409 << "LDensity: " << LDensity
2410 << ", RDensity: " << RDensity << '\n'
2411 << "Metric: " << Metric << '\n');
2412 if (FMetric < Metric) {
2415 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2422 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2423 if (areJTsAllowed(TLI)) {
2424 // If our case is dense we *really* should handle it earlier!
2425 assert((FMetric > 0) && "Should handle dense range earlier!");
2427 Pivot = CR.Range.first + Size/2;
2430 CaseRange LHSR(CR.Range.first, Pivot);
2431 CaseRange RHSR(Pivot, CR.Range.second);
2432 const Constant *C = Pivot->Low;
2433 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2435 // We know that we branch to the LHS if the Value being switched on is
2436 // less than the Pivot value, C. We use this to optimize our binary
2437 // tree a bit, by recognizing that if SV is greater than or equal to the
2438 // LHS's Case Value, and that Case Value is exactly one less than the
2439 // Pivot's Value, then we can branch directly to the LHS's Target,
2440 // rather than creating a leaf node for it.
2441 if ((LHSR.second - LHSR.first) == 1 &&
2442 LHSR.first->High == CR.GE &&
2443 cast<ConstantInt>(C)->getValue() ==
2444 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2445 TrueBB = LHSR.first->BB;
2447 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2448 CurMF->insert(BBI, TrueBB);
2449 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2451 // Put SV in a virtual register to make it available from the new blocks.
2452 ExportFromCurrentBlock(SV);
2455 // Similar to the optimization above, if the Value being switched on is
2456 // known to be less than the Constant CR.LT, and the current Case Value
2457 // is CR.LT - 1, then we can branch directly to the target block for
2458 // the current Case Value, rather than emitting a RHS leaf node for it.
2459 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2460 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2461 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2462 FalseBB = RHSR.first->BB;
2464 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2465 CurMF->insert(BBI, FalseBB);
2466 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2468 // Put SV in a virtual register to make it available from the new blocks.
2469 ExportFromCurrentBlock(SV);
2472 // Create a CaseBlock record representing a conditional branch to
2473 // the LHS node if the value being switched on SV is less than C.
2474 // Otherwise, branch to LHS.
2475 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2477 if (CR.CaseBB == SwitchBB)
2478 visitSwitchCase(CB, SwitchBB);
2480 SwitchCases.push_back(CB);
2485 /// handleBitTestsSwitchCase - if current case range has few destination and
2486 /// range span less, than machine word bitwidth, encode case range into series
2487 /// of masks and emit bit tests with these masks.
2488 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2489 CaseRecVector& WorkList,
2491 MachineBasicBlock* Default,
2492 MachineBasicBlock* SwitchBB) {
2493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2494 EVT PTy = TLI.getPointerTy();
2495 unsigned IntPtrBits = PTy.getSizeInBits();
2497 Case& FrontCase = *CR.Range.first;
2498 Case& BackCase = *(CR.Range.second-1);
2500 // Get the MachineFunction which holds the current MBB. This is used when
2501 // inserting any additional MBBs necessary to represent the switch.
2502 MachineFunction *CurMF = FuncInfo.MF;
2504 // If target does not have legal shift left, do not emit bit tests at all.
2505 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2509 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2511 // Single case counts one, case range - two.
2512 numCmps += (I->Low == I->High ? 1 : 2);
2515 // Count unique destinations
2516 SmallSet<MachineBasicBlock*, 4> Dests;
2517 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2518 Dests.insert(I->BB);
2519 if (Dests.size() > 3)
2520 // Don't bother the code below, if there are too much unique destinations
2523 DEBUG(dbgs() << "Total number of unique destinations: "
2524 << Dests.size() << '\n'
2525 << "Total number of comparisons: " << numCmps << '\n');
2527 // Compute span of values.
2528 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2529 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2530 APInt cmpRange = maxValue - minValue;
2532 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2533 << "Low bound: " << minValue << '\n'
2534 << "High bound: " << maxValue << '\n');
2536 if (cmpRange.uge(IntPtrBits) ||
2537 (!(Dests.size() == 1 && numCmps >= 3) &&
2538 !(Dests.size() == 2 && numCmps >= 5) &&
2539 !(Dests.size() >= 3 && numCmps >= 6)))
2542 DEBUG(dbgs() << "Emitting bit tests\n");
2543 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2545 // Optimize the case where all the case values fit in a
2546 // word without having to subtract minValue. In this case,
2547 // we can optimize away the subtraction.
2548 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2549 cmpRange = maxValue;
2551 lowBound = minValue;
2554 CaseBitsVector CasesBits;
2555 unsigned i, count = 0;
2557 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2558 MachineBasicBlock* Dest = I->BB;
2559 for (i = 0; i < count; ++i)
2560 if (Dest == CasesBits[i].BB)
2564 assert((count < 3) && "Too much destinations to test!");
2565 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2569 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2570 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2572 uint64_t lo = (lowValue - lowBound).getZExtValue();
2573 uint64_t hi = (highValue - lowBound).getZExtValue();
2574 CasesBits[i].ExtraWeight += I->ExtraWeight;
2576 for (uint64_t j = lo; j <= hi; j++) {
2577 CasesBits[i].Mask |= 1ULL << j;
2578 CasesBits[i].Bits++;
2582 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2586 // Figure out which block is immediately after the current one.
2587 MachineFunction::iterator BBI = CR.CaseBB;
2590 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2592 DEBUG(dbgs() << "Cases:\n");
2593 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2594 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2595 << ", Bits: " << CasesBits[i].Bits
2596 << ", BB: " << CasesBits[i].BB << '\n');
2598 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2599 CurMF->insert(BBI, CaseBB);
2600 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2602 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2604 // Put SV in a virtual register to make it available from the new blocks.
2605 ExportFromCurrentBlock(SV);
2608 BitTestBlock BTB(lowBound, cmpRange, SV,
2609 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2610 CR.CaseBB, Default, std::move(BTC));
2612 if (CR.CaseBB == SwitchBB)
2613 visitBitTestHeader(BTB, SwitchBB);
2615 BitTestCases.push_back(std::move(BTB));
2620 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2621 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2622 const SwitchInst& SI) {
2625 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2626 // Start with "simple" cases
2627 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2629 const BasicBlock *SuccBB = i.getCaseSuccessor();
2630 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2632 uint32_t ExtraWeight =
2633 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2635 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2636 SMBB, ExtraWeight));
2638 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2640 // Merge case into clusters
2641 if (Cases.size() >= 2)
2642 // Must recompute end() each iteration because it may be
2643 // invalidated by erase if we hold on to it
2644 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2645 J != Cases.end(); ) {
2646 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2647 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2648 MachineBasicBlock* nextBB = J->BB;
2649 MachineBasicBlock* currentBB = I->BB;
2651 // If the two neighboring cases go to the same destination, merge them
2652 // into a single case.
2653 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2655 I->ExtraWeight += J->ExtraWeight;
2662 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2663 if (I->Low != I->High)
2664 // A range counts double, since it requires two compares.
2671 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2672 MachineBasicBlock *Last) {
2674 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2675 if (JTCases[i].first.HeaderBB == First)
2676 JTCases[i].first.HeaderBB = Last;
2678 // Update BitTestCases.
2679 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2680 if (BitTestCases[i].Parent == First)
2681 BitTestCases[i].Parent = Last;
2684 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2685 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2687 // Figure out which block is immediately after the current one.
2688 MachineBasicBlock *NextBlock = nullptr;
2689 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2691 // If there is only the default destination, branch to it if it is not the
2692 // next basic block. Otherwise, just fall through.
2693 if (!SI.getNumCases()) {
2694 // Update machine-CFG edges.
2696 // If this is not a fall-through branch, emit the branch.
2697 SwitchMBB->addSuccessor(Default);
2698 if (Default != NextBlock)
2699 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2700 MVT::Other, getControlRoot(),
2701 DAG.getBasicBlock(Default)));
2706 // If there are any non-default case statements, create a vector of Cases
2707 // representing each one, and sort the vector so that we can efficiently
2708 // create a binary search tree from them.
2710 size_t numCmps = Clusterify(Cases, SI);
2711 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2712 << ". Total compares: " << numCmps << '\n');
2715 // Get the Value to be switched on and default basic blocks, which will be
2716 // inserted into CaseBlock records, representing basic blocks in the binary
2718 const Value *SV = SI.getCondition();
2720 // Push the initial CaseRec onto the worklist
2721 CaseRecVector WorkList;
2722 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2723 CaseRange(Cases.begin(),Cases.end())));
2725 while (!WorkList.empty()) {
2726 // Grab a record representing a case range to process off the worklist
2727 CaseRec CR = WorkList.back();
2728 WorkList.pop_back();
2730 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2733 // If the range has few cases (two or less) emit a series of specific
2735 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2738 // If the switch has more than N blocks, and is at least 40% dense, and the
2739 // target supports indirect branches, then emit a jump table rather than
2740 // lowering the switch to a binary tree of conditional branches.
2741 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2742 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2745 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2746 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2747 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2751 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2752 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2754 // Update machine-CFG edges with unique successors.
2755 SmallSet<BasicBlock*, 32> Done;
2756 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2757 BasicBlock *BB = I.getSuccessor(i);
2758 bool Inserted = Done.insert(BB);
2762 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2763 addSuccessorWithWeight(IndirectBrMBB, Succ);
2766 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2767 MVT::Other, getControlRoot(),
2768 getValue(I.getAddress())));
2771 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2772 if (DAG.getTarget().Options.TrapUnreachable)
2773 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2776 void SelectionDAGBuilder::visitFSub(const User &I) {
2777 // -0.0 - X --> fneg
2778 Type *Ty = I.getType();
2779 if (isa<Constant>(I.getOperand(0)) &&
2780 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2781 SDValue Op2 = getValue(I.getOperand(1));
2782 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2783 Op2.getValueType(), Op2));
2787 visitBinary(I, ISD::FSUB);
2790 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2791 SDValue Op1 = getValue(I.getOperand(0));
2792 SDValue Op2 = getValue(I.getOperand(1));
2797 if (const OverflowingBinaryOperator *OFBinOp =
2798 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2799 nuw = OFBinOp->hasNoUnsignedWrap();
2800 nsw = OFBinOp->hasNoSignedWrap();
2802 if (const PossiblyExactOperator *ExactOp =
2803 dyn_cast<const PossiblyExactOperator>(&I))
2804 exact = ExactOp->isExact();
2806 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2807 Op1, Op2, nuw, nsw, exact);
2808 setValue(&I, BinNodeValue);
2811 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2812 SDValue Op1 = getValue(I.getOperand(0));
2813 SDValue Op2 = getValue(I.getOperand(1));
2816 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2818 // Coerce the shift amount to the right type if we can.
2819 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2820 unsigned ShiftSize = ShiftTy.getSizeInBits();
2821 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2822 SDLoc DL = getCurSDLoc();
2824 // If the operand is smaller than the shift count type, promote it.
2825 if (ShiftSize > Op2Size)
2826 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2828 // If the operand is larger than the shift count type but the shift
2829 // count type has enough bits to represent any shift value, truncate
2830 // it now. This is a common case and it exposes the truncate to
2831 // optimization early.
2832 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2833 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2834 // Otherwise we'll need to temporarily settle for some other convenient
2835 // type. Type legalization will make adjustments once the shiftee is split.
2837 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2844 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2846 if (const OverflowingBinaryOperator *OFBinOp =
2847 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2848 nuw = OFBinOp->hasNoUnsignedWrap();
2849 nsw = OFBinOp->hasNoSignedWrap();
2851 if (const PossiblyExactOperator *ExactOp =
2852 dyn_cast<const PossiblyExactOperator>(&I))
2853 exact = ExactOp->isExact();
2856 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2861 void SelectionDAGBuilder::visitSDiv(const User &I) {
2862 SDValue Op1 = getValue(I.getOperand(0));
2863 SDValue Op2 = getValue(I.getOperand(1));
2865 // Turn exact SDivs into multiplications.
2866 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2868 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2869 !isa<ConstantSDNode>(Op1) &&
2870 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2871 setValue(&I, DAG.getTargetLoweringInfo()
2872 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2874 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2878 void SelectionDAGBuilder::visitICmp(const User &I) {
2879 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2880 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2881 predicate = IC->getPredicate();
2882 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2883 predicate = ICmpInst::Predicate(IC->getPredicate());
2884 SDValue Op1 = getValue(I.getOperand(0));
2885 SDValue Op2 = getValue(I.getOperand(1));
2886 ISD::CondCode Opcode = getICmpCondCode(predicate);
2888 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2889 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2892 void SelectionDAGBuilder::visitFCmp(const User &I) {
2893 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2894 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2895 predicate = FC->getPredicate();
2896 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2897 predicate = FCmpInst::Predicate(FC->getPredicate());
2898 SDValue Op1 = getValue(I.getOperand(0));
2899 SDValue Op2 = getValue(I.getOperand(1));
2900 ISD::CondCode Condition = getFCmpCondCode(predicate);
2901 if (TM.Options.NoNaNsFPMath)
2902 Condition = getFCmpCodeWithoutNaN(Condition);
2903 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2904 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2907 void SelectionDAGBuilder::visitSelect(const User &I) {
2908 SmallVector<EVT, 4> ValueVTs;
2909 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2910 unsigned NumValues = ValueVTs.size();
2911 if (NumValues == 0) return;
2913 SmallVector<SDValue, 4> Values(NumValues);
2914 SDValue Cond = getValue(I.getOperand(0));
2915 SDValue TrueVal = getValue(I.getOperand(1));
2916 SDValue FalseVal = getValue(I.getOperand(2));
2917 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2918 ISD::VSELECT : ISD::SELECT;
2920 for (unsigned i = 0; i != NumValues; ++i)
2921 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2922 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2924 SDValue(TrueVal.getNode(),
2925 TrueVal.getResNo() + i),
2926 SDValue(FalseVal.getNode(),
2927 FalseVal.getResNo() + i));
2929 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2930 DAG.getVTList(ValueVTs), Values));
2933 void SelectionDAGBuilder::visitTrunc(const User &I) {
2934 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2935 SDValue N = getValue(I.getOperand(0));
2936 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2937 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2940 void SelectionDAGBuilder::visitZExt(const User &I) {
2941 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2942 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2943 SDValue N = getValue(I.getOperand(0));
2944 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2945 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2948 void SelectionDAGBuilder::visitSExt(const User &I) {
2949 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2950 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2951 SDValue N = getValue(I.getOperand(0));
2952 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2953 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2956 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2957 // FPTrunc is never a no-op cast, no need to check
2958 SDValue N = getValue(I.getOperand(0));
2959 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2960 EVT DestVT = TLI.getValueType(I.getType());
2961 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
2962 DAG.getTargetConstant(0, TLI.getPointerTy())));
2965 void SelectionDAGBuilder::visitFPExt(const User &I) {
2966 // FPExt is never a no-op cast, no need to check
2967 SDValue N = getValue(I.getOperand(0));
2968 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2969 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2972 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2973 // FPToUI is never a no-op cast, no need to check
2974 SDValue N = getValue(I.getOperand(0));
2975 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2976 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2979 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2980 // FPToSI is never a no-op cast, no need to check
2981 SDValue N = getValue(I.getOperand(0));
2982 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2983 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2986 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2987 // UIToFP is never a no-op cast, no need to check
2988 SDValue N = getValue(I.getOperand(0));
2989 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2990 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2993 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2994 // SIToFP is never a no-op cast, no need to check
2995 SDValue N = getValue(I.getOperand(0));
2996 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2997 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3000 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3001 // What to do depends on the size of the integer and the size of the pointer.
3002 // We can either truncate, zero extend, or no-op, accordingly.
3003 SDValue N = getValue(I.getOperand(0));
3004 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3005 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3008 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3009 // What to do depends on the size of the integer and the size of the pointer.
3010 // We can either truncate, zero extend, or no-op, accordingly.
3011 SDValue N = getValue(I.getOperand(0));
3012 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3013 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3016 void SelectionDAGBuilder::visitBitCast(const User &I) {
3017 SDValue N = getValue(I.getOperand(0));
3018 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3020 // BitCast assures us that source and destination are the same size so this is
3021 // either a BITCAST or a no-op.
3022 if (DestVT != N.getValueType())
3023 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3024 DestVT, N)); // convert types.
3025 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3026 // might fold any kind of constant expression to an integer constant and that
3027 // is not what we are looking for. Only regcognize a bitcast of a genuine
3028 // constant integer as an opaque constant.
3029 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3030 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3033 setValue(&I, N); // noop cast.
3036 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3037 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3038 const Value *SV = I.getOperand(0);
3039 SDValue N = getValue(SV);
3040 EVT DestVT = TLI.getValueType(I.getType());
3042 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3043 unsigned DestAS = I.getType()->getPointerAddressSpace();
3045 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3046 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3051 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3052 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3053 SDValue InVec = getValue(I.getOperand(0));
3054 SDValue InVal = getValue(I.getOperand(1));
3055 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3056 getCurSDLoc(), TLI.getVectorIdxTy());
3057 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3058 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3061 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3063 SDValue InVec = getValue(I.getOperand(0));
3064 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3065 getCurSDLoc(), TLI.getVectorIdxTy());
3066 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3067 TLI.getValueType(I.getType()), InVec, InIdx));
3070 // Utility for visitShuffleVector - Return true if every element in Mask,
3071 // beginning from position Pos and ending in Pos+Size, falls within the
3072 // specified sequential range [L, L+Pos). or is undef.
3073 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3074 unsigned Pos, unsigned Size, int Low) {
3075 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3076 if (Mask[i] >= 0 && Mask[i] != Low)
3081 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3082 SDValue Src1 = getValue(I.getOperand(0));
3083 SDValue Src2 = getValue(I.getOperand(1));
3085 SmallVector<int, 8> Mask;
3086 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3087 unsigned MaskNumElts = Mask.size();
3089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3090 EVT VT = TLI.getValueType(I.getType());
3091 EVT SrcVT = Src1.getValueType();
3092 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3094 if (SrcNumElts == MaskNumElts) {
3095 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3100 // Normalize the shuffle vector since mask and vector length don't match.
3101 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3102 // Mask is longer than the source vectors and is a multiple of the source
3103 // vectors. We can use concatenate vector to make the mask and vectors
3105 if (SrcNumElts*2 == MaskNumElts) {
3106 // First check for Src1 in low and Src2 in high
3107 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3108 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3109 // The shuffle is concatenating two vectors together.
3110 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3114 // Then check for Src2 in low and Src1 in high
3115 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3116 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3117 // The shuffle is concatenating two vectors together.
3118 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3124 // Pad both vectors with undefs to make them the same length as the mask.
3125 unsigned NumConcat = MaskNumElts / SrcNumElts;
3126 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3127 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3128 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3130 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3131 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3135 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3136 getCurSDLoc(), VT, MOps1);
3137 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3138 getCurSDLoc(), VT, MOps2);
3140 // Readjust mask for new input vector length.
3141 SmallVector<int, 8> MappedOps;
3142 for (unsigned i = 0; i != MaskNumElts; ++i) {
3144 if (Idx >= (int)SrcNumElts)
3145 Idx -= SrcNumElts - MaskNumElts;
3146 MappedOps.push_back(Idx);
3149 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3154 if (SrcNumElts > MaskNumElts) {
3155 // Analyze the access pattern of the vector to see if we can extract
3156 // two subvectors and do the shuffle. The analysis is done by calculating
3157 // the range of elements the mask access on both vectors.
3158 int MinRange[2] = { static_cast<int>(SrcNumElts),
3159 static_cast<int>(SrcNumElts)};
3160 int MaxRange[2] = {-1, -1};
3162 for (unsigned i = 0; i != MaskNumElts; ++i) {
3168 if (Idx >= (int)SrcNumElts) {
3172 if (Idx > MaxRange[Input])
3173 MaxRange[Input] = Idx;
3174 if (Idx < MinRange[Input])
3175 MinRange[Input] = Idx;
3178 // Check if the access is smaller than the vector size and can we find
3179 // a reasonable extract index.
3180 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3182 int StartIdx[2]; // StartIdx to extract from
3183 for (unsigned Input = 0; Input < 2; ++Input) {
3184 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3185 RangeUse[Input] = 0; // Unused
3186 StartIdx[Input] = 0;
3190 // Find a good start index that is a multiple of the mask length. Then
3191 // see if the rest of the elements are in range.
3192 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3193 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3194 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3195 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3198 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3199 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3202 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3203 // Extract appropriate subvector and generate a vector shuffle
3204 for (unsigned Input = 0; Input < 2; ++Input) {
3205 SDValue &Src = Input == 0 ? Src1 : Src2;
3206 if (RangeUse[Input] == 0)
3207 Src = DAG.getUNDEF(VT);
3210 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3211 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3214 // Calculate new mask.
3215 SmallVector<int, 8> MappedOps;
3216 for (unsigned i = 0; i != MaskNumElts; ++i) {
3219 if (Idx < (int)SrcNumElts)
3222 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3224 MappedOps.push_back(Idx);
3227 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3233 // We can't use either concat vectors or extract subvectors so fall back to
3234 // replacing the shuffle with extract and build vector.
3235 // to insert and build vector.
3236 EVT EltVT = VT.getVectorElementType();
3237 EVT IdxVT = TLI.getVectorIdxTy();
3238 SmallVector<SDValue,8> Ops;
3239 for (unsigned i = 0; i != MaskNumElts; ++i) {
3244 Res = DAG.getUNDEF(EltVT);
3246 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3247 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3249 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3250 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3256 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3259 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3260 const Value *Op0 = I.getOperand(0);
3261 const Value *Op1 = I.getOperand(1);
3262 Type *AggTy = I.getType();
3263 Type *ValTy = Op1->getType();
3264 bool IntoUndef = isa<UndefValue>(Op0);
3265 bool FromUndef = isa<UndefValue>(Op1);
3267 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3269 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3270 SmallVector<EVT, 4> AggValueVTs;
3271 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3272 SmallVector<EVT, 4> ValValueVTs;
3273 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3275 unsigned NumAggValues = AggValueVTs.size();
3276 unsigned NumValValues = ValValueVTs.size();
3277 SmallVector<SDValue, 4> Values(NumAggValues);
3279 // Ignore an insertvalue that produces an empty object
3280 if (!NumAggValues) {
3281 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3285 SDValue Agg = getValue(Op0);
3287 // Copy the beginning value(s) from the original aggregate.
3288 for (; i != LinearIndex; ++i)
3289 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3290 SDValue(Agg.getNode(), Agg.getResNo() + i);
3291 // Copy values from the inserted value(s).
3293 SDValue Val = getValue(Op1);
3294 for (; i != LinearIndex + NumValValues; ++i)
3295 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3296 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3298 // Copy remaining value(s) from the original aggregate.
3299 for (; i != NumAggValues; ++i)
3300 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3301 SDValue(Agg.getNode(), Agg.getResNo() + i);
3303 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3304 DAG.getVTList(AggValueVTs), Values));
3307 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3308 const Value *Op0 = I.getOperand(0);
3309 Type *AggTy = Op0->getType();
3310 Type *ValTy = I.getType();
3311 bool OutOfUndef = isa<UndefValue>(Op0);
3313 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3316 SmallVector<EVT, 4> ValValueVTs;
3317 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3319 unsigned NumValValues = ValValueVTs.size();
3321 // Ignore a extractvalue that produces an empty object
3322 if (!NumValValues) {
3323 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3327 SmallVector<SDValue, 4> Values(NumValValues);
3329 SDValue Agg = getValue(Op0);
3330 // Copy out the selected value(s).
3331 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3332 Values[i - LinearIndex] =
3334 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3335 SDValue(Agg.getNode(), Agg.getResNo() + i);
3337 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3338 DAG.getVTList(ValValueVTs), Values));
3341 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3342 Value *Op0 = I.getOperand(0);
3343 // Note that the pointer operand may be a vector of pointers. Take the scalar
3344 // element which holds a pointer.
3345 Type *Ty = Op0->getType()->getScalarType();
3346 unsigned AS = Ty->getPointerAddressSpace();
3347 SDValue N = getValue(Op0);
3349 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3351 const Value *Idx = *OI;
3352 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3353 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3356 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3357 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3358 DAG.getConstant(Offset, N.getValueType()));
3361 Ty = StTy->getElementType(Field);
3363 Ty = cast<SequentialType>(Ty)->getElementType();
3365 // If this is a constant subscript, handle it quickly.
3366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3367 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3368 if (CI->isZero()) continue;
3370 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3372 EVT PTy = TLI.getPointerTy(AS);
3373 unsigned PtrBits = PTy.getSizeInBits();
3375 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3376 DAG.getConstant(Offs, MVT::i64));
3378 OffsVal = DAG.getConstant(Offs, PTy);
3380 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3385 // N = N + Idx * ElementSize;
3387 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3388 SDValue IdxN = getValue(Idx);
3390 // If the index is smaller or larger than intptr_t, truncate or extend
3392 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3394 // If this is a multiply by a power of two, turn it into a shl
3395 // immediately. This is a very common case.
3396 if (ElementSize != 1) {
3397 if (ElementSize.isPowerOf2()) {
3398 unsigned Amt = ElementSize.logBase2();
3399 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3400 N.getValueType(), IdxN,
3401 DAG.getConstant(Amt, IdxN.getValueType()));
3403 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3404 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3405 N.getValueType(), IdxN, Scale);
3409 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3410 N.getValueType(), N, IdxN);
3417 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3418 // If this is a fixed sized alloca in the entry block of the function,
3419 // allocate it statically on the stack.
3420 if (FuncInfo.StaticAllocaMap.count(&I))
3421 return; // getValue will auto-populate this.
3423 Type *Ty = I.getAllocatedType();
3424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3425 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3427 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3430 SDValue AllocSize = getValue(I.getArraySize());
3432 EVT IntPtr = TLI.getPointerTy();
3433 if (AllocSize.getValueType() != IntPtr)
3434 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3436 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3438 DAG.getConstant(TySize, IntPtr));
3440 // Handle alignment. If the requested alignment is less than or equal to
3441 // the stack alignment, ignore it. If the size is greater than or equal to
3442 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3443 unsigned StackAlign =
3444 TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
3445 if (Align <= StackAlign)
3448 // Round the size of the allocation up to the stack alignment size
3449 // by add SA-1 to the size.
3450 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3451 AllocSize.getValueType(), AllocSize,
3452 DAG.getIntPtrConstant(StackAlign-1));
3454 // Mask out the low bits for alignment purposes.
3455 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3456 AllocSize.getValueType(), AllocSize,
3457 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3459 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3460 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3461 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3463 DAG.setRoot(DSA.getValue(1));
3465 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3468 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3470 return visitAtomicLoad(I);
3472 const Value *SV = I.getOperand(0);
3473 SDValue Ptr = getValue(SV);
3475 Type *Ty = I.getType();
3477 bool isVolatile = I.isVolatile();
3478 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3479 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3480 unsigned Alignment = I.getAlignment();
3483 I.getAAMetadata(AAInfo);
3484 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3487 SmallVector<EVT, 4> ValueVTs;
3488 SmallVector<uint64_t, 4> Offsets;
3489 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3490 unsigned NumValues = ValueVTs.size();
3495 bool ConstantMemory = false;
3496 if (isVolatile || NumValues > MaxParallelChains)
3497 // Serialize volatile loads with other side effects.
3499 else if (AA->pointsToConstantMemory(
3500 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3501 // Do not serialize (non-volatile) loads of constant memory with anything.
3502 Root = DAG.getEntryNode();
3503 ConstantMemory = true;
3505 // Do not serialize non-volatile loads against each other.
3506 Root = DAG.getRoot();
3510 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3512 SmallVector<SDValue, 4> Values(NumValues);
3513 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3515 EVT PtrVT = Ptr.getValueType();
3516 unsigned ChainI = 0;
3517 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3518 // Serializing loads here may result in excessive register pressure, and
3519 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3520 // could recover a bit by hoisting nodes upward in the chain by recognizing
3521 // they are side-effect free or do not alias. The optimizer should really
3522 // avoid this case by converting large object/array copies to llvm.memcpy
3523 // (MaxParallelChains should always remain as failsafe).
3524 if (ChainI == MaxParallelChains) {
3525 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3526 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3527 makeArrayRef(Chains.data(), ChainI));
3531 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3533 DAG.getConstant(Offsets[i], PtrVT));
3534 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3535 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3536 isNonTemporal, isInvariant, Alignment, AAInfo,
3540 Chains[ChainI] = L.getValue(1);
3543 if (!ConstantMemory) {
3544 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3545 makeArrayRef(Chains.data(), ChainI));
3549 PendingLoads.push_back(Chain);
3552 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3553 DAG.getVTList(ValueVTs), Values));
3556 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3558 return visitAtomicStore(I);
3560 const Value *SrcV = I.getOperand(0);
3561 const Value *PtrV = I.getOperand(1);
3563 SmallVector<EVT, 4> ValueVTs;
3564 SmallVector<uint64_t, 4> Offsets;
3565 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3566 ValueVTs, &Offsets);
3567 unsigned NumValues = ValueVTs.size();
3571 // Get the lowered operands. Note that we do this after
3572 // checking if NumResults is zero, because with zero results
3573 // the operands won't have values in the map.
3574 SDValue Src = getValue(SrcV);
3575 SDValue Ptr = getValue(PtrV);
3577 SDValue Root = getRoot();
3578 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3580 EVT PtrVT = Ptr.getValueType();
3581 bool isVolatile = I.isVolatile();
3582 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3583 unsigned Alignment = I.getAlignment();
3586 I.getAAMetadata(AAInfo);
3588 unsigned ChainI = 0;
3589 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3590 // See visitLoad comments.
3591 if (ChainI == MaxParallelChains) {
3592 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3593 makeArrayRef(Chains.data(), ChainI));
3597 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3598 DAG.getConstant(Offsets[i], PtrVT));
3599 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3600 SDValue(Src.getNode(), Src.getResNo() + i),
3601 Add, MachinePointerInfo(PtrV, Offsets[i]),
3602 isVolatile, isNonTemporal, Alignment, AAInfo);
3603 Chains[ChainI] = St;
3606 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3607 makeArrayRef(Chains.data(), ChainI));
3608 DAG.setRoot(StoreNode);
3611 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3612 SynchronizationScope Scope,
3613 bool Before, SDLoc dl,
3615 const TargetLowering &TLI) {
3616 // Fence, if necessary
3618 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3620 else if (Order == Acquire || Order == Monotonic || Order == Unordered)
3623 if (Order == AcquireRelease)
3625 else if (Order == Release || Order == Monotonic || Order == Unordered)
3630 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3631 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3632 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
3635 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3636 SDLoc dl = getCurSDLoc();
3637 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3638 AtomicOrdering FailureOrder = I.getFailureOrdering();
3639 SynchronizationScope Scope = I.getSynchScope();
3641 SDValue InChain = getRoot();
3643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3644 if (TLI.getInsertFencesForAtomic())
3646 InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl, DAG, TLI);
3648 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3649 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3650 SDValue L = DAG.getAtomicCmpSwap(
3651 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3652 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3653 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3655 TLI.getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3656 TLI.getInsertFencesForAtomic() ? Monotonic : FailureOrder, Scope);
3658 SDValue OutChain = L.getValue(2);
3660 if (TLI.getInsertFencesForAtomic())
3661 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3665 DAG.setRoot(OutChain);
3668 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3669 SDLoc dl = getCurSDLoc();
3671 switch (I.getOperation()) {
3672 default: llvm_unreachable("Unknown atomicrmw operation");
3673 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3674 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3675 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3676 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3677 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3678 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3679 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3680 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3681 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3682 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3683 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3685 AtomicOrdering Order = I.getOrdering();
3686 SynchronizationScope Scope = I.getSynchScope();
3688 SDValue InChain = getRoot();
3690 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3691 if (TLI.getInsertFencesForAtomic())
3692 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, DAG, TLI);
3694 SDValue L = DAG.getAtomic(
3695 NT, dl, getValue(I.getValOperand()).getSimpleValueType(), InChain,
3696 getValue(I.getPointerOperand()), getValue(I.getValOperand()),
3697 I.getPointerOperand(), 0 /* Alignment */,
3698 TLI.getInsertFencesForAtomic() ? Monotonic : Order, Scope);
3700 SDValue OutChain = L.getValue(1);
3702 if (TLI.getInsertFencesForAtomic())
3704 InsertFenceForAtomic(OutChain, Order, Scope, false, dl, DAG, TLI);
3707 DAG.setRoot(OutChain);
3710 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3711 SDLoc dl = getCurSDLoc();
3712 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3715 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3716 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3717 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3720 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3721 SDLoc dl = getCurSDLoc();
3722 AtomicOrdering Order = I.getOrdering();
3723 SynchronizationScope Scope = I.getSynchScope();
3725 SDValue InChain = getRoot();
3727 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3728 EVT VT = TLI.getValueType(I.getType());
3730 if (I.getAlignment() < VT.getSizeInBits() / 8)
3731 report_fatal_error("Cannot generate unaligned atomic load");
3733 MachineMemOperand *MMO =
3734 DAG.getMachineFunction().
3735 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3736 MachineMemOperand::MOVolatile |
3737 MachineMemOperand::MOLoad,
3739 I.getAlignment() ? I.getAlignment() :
3740 DAG.getEVTAlignment(VT));
3742 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3743 SDValue L = DAG.getAtomic(
3744 ISD::ATOMIC_LOAD, dl, VT, VT, InChain, getValue(I.getPointerOperand()),
3745 MMO, TLI.getInsertFencesForAtomic() ? Monotonic : Order, Scope);
3747 SDValue OutChain = L.getValue(1);
3749 if (TLI.getInsertFencesForAtomic())
3750 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3754 DAG.setRoot(OutChain);
3757 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3758 SDLoc dl = getCurSDLoc();
3760 AtomicOrdering Order = I.getOrdering();
3761 SynchronizationScope Scope = I.getSynchScope();
3763 SDValue InChain = getRoot();
3765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3766 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3768 if (I.getAlignment() < VT.getSizeInBits() / 8)
3769 report_fatal_error("Cannot generate unaligned atomic store");
3771 if (TLI.getInsertFencesForAtomic())
3772 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, DAG, TLI);
3774 SDValue OutChain = DAG.getAtomic(
3775 ISD::ATOMIC_STORE, dl, VT, InChain, getValue(I.getPointerOperand()),
3776 getValue(I.getValueOperand()), I.getPointerOperand(), I.getAlignment(),
3777 TLI.getInsertFencesForAtomic() ? Monotonic : Order, Scope);
3779 if (TLI.getInsertFencesForAtomic())
3781 InsertFenceForAtomic(OutChain, Order, Scope, false, dl, DAG, TLI);
3783 DAG.setRoot(OutChain);
3786 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3788 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3789 unsigned Intrinsic) {
3790 bool HasChain = !I.doesNotAccessMemory();
3791 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3793 // Build the operand list.
3794 SmallVector<SDValue, 8> Ops;
3795 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3797 // We don't need to serialize loads against other loads.
3798 Ops.push_back(DAG.getRoot());
3800 Ops.push_back(getRoot());
3804 // Info is set by getTgtMemInstrinsic
3805 TargetLowering::IntrinsicInfo Info;
3806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3807 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3809 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3810 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3811 Info.opc == ISD::INTRINSIC_W_CHAIN)
3812 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3814 // Add all operands of the call to the operand list.
3815 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3816 SDValue Op = getValue(I.getArgOperand(i));
3820 SmallVector<EVT, 4> ValueVTs;
3821 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3824 ValueVTs.push_back(MVT::Other);
3826 SDVTList VTs = DAG.getVTList(ValueVTs);
3830 if (IsTgtIntrinsic) {
3831 // This is target intrinsic that touches memory
3832 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3833 VTs, Ops, Info.memVT,
3834 MachinePointerInfo(Info.ptrVal, Info.offset),
3835 Info.align, Info.vol,
3836 Info.readMem, Info.writeMem, Info.size);
3837 } else if (!HasChain) {
3838 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3839 } else if (!I.getType()->isVoidTy()) {
3840 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3842 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3846 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3848 PendingLoads.push_back(Chain);
3853 if (!I.getType()->isVoidTy()) {
3854 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3855 EVT VT = TLI.getValueType(PTy);
3856 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3859 setValue(&I, Result);
3863 /// GetSignificand - Get the significand and build it into a floating-point
3864 /// number with exponent of 1:
3866 /// Op = (Op & 0x007fffff) | 0x3f800000;
3868 /// where Op is the hexadecimal representation of floating point value.
3870 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3871 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3872 DAG.getConstant(0x007fffff, MVT::i32));
3873 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3874 DAG.getConstant(0x3f800000, MVT::i32));
3875 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3878 /// GetExponent - Get the exponent:
3880 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3882 /// where Op is the hexadecimal representation of floating point value.
3884 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3886 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3887 DAG.getConstant(0x7f800000, MVT::i32));
3888 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3889 DAG.getConstant(23, TLI.getPointerTy()));
3890 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3891 DAG.getConstant(127, MVT::i32));
3892 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3895 /// getF32Constant - Get 32-bit floating point constant.
3897 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3898 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3902 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3903 /// limited-precision mode.
3904 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3905 const TargetLowering &TLI) {
3906 if (Op.getValueType() == MVT::f32 &&
3907 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3909 // Put the exponent in the right bit position for later addition to the
3912 // #define LOG2OFe 1.4426950f
3913 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3914 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3915 getF32Constant(DAG, 0x3fb8aa3b));
3916 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3918 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3919 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3920 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3922 // IntegerPartOfX <<= 23;
3923 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3924 DAG.getConstant(23, TLI.getPointerTy()));
3926 SDValue TwoToFracPartOfX;
3927 if (LimitFloatPrecision <= 6) {
3928 // For floating-point precision of 6:
3930 // TwoToFractionalPartOfX =
3932 // (0.735607626f + 0.252464424f * x) * x;
3934 // error 0.0144103317, which is 6 bits
3935 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3936 getF32Constant(DAG, 0x3e814304));
3937 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3938 getF32Constant(DAG, 0x3f3c50c8));
3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3940 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3941 getF32Constant(DAG, 0x3f7f5e7e));
3942 } else if (LimitFloatPrecision <= 12) {
3943 // For floating-point precision of 12:
3945 // TwoToFractionalPartOfX =
3948 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3950 // 0.000107046256 error, which is 13 to 14 bits
3951 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3952 getF32Constant(DAG, 0x3da235e3));
3953 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3954 getF32Constant(DAG, 0x3e65b8f3));
3955 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3956 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3957 getF32Constant(DAG, 0x3f324b07));
3958 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3959 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3960 getF32Constant(DAG, 0x3f7ff8fd));
3961 } else { // LimitFloatPrecision <= 18
3962 // For floating-point precision of 18:
3964 // TwoToFractionalPartOfX =
3968 // (0.554906021e-1f +
3969 // (0.961591928e-2f +
3970 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3972 // error 2.47208000*10^(-7), which is better than 18 bits
3973 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3974 getF32Constant(DAG, 0x3924b03e));
3975 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3976 getF32Constant(DAG, 0x3ab24b87));
3977 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3978 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3979 getF32Constant(DAG, 0x3c1d8c17));
3980 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3981 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3982 getF32Constant(DAG, 0x3d634a1d));
3983 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3984 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3985 getF32Constant(DAG, 0x3e75fe14));
3986 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3987 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3988 getF32Constant(DAG, 0x3f317234));
3989 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3990 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3991 getF32Constant(DAG, 0x3f800000));
3994 // Add the exponent into the result in integer domain.
3995 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3996 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3997 DAG.getNode(ISD::ADD, dl, MVT::i32,
3998 t13, IntegerPartOfX));
4001 // No special expansion.
4002 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4005 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4006 /// limited-precision mode.
4007 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4008 const TargetLowering &TLI) {
4009 if (Op.getValueType() == MVT::f32 &&
4010 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4011 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4013 // Scale the exponent by log(2) [0.69314718f].
4014 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4015 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4016 getF32Constant(DAG, 0x3f317218));
4018 // Get the significand and build it into a floating-point number with
4020 SDValue X = GetSignificand(DAG, Op1, dl);
4022 SDValue LogOfMantissa;
4023 if (LimitFloatPrecision <= 6) {
4024 // For floating-point precision of 6:
4028 // (1.4034025f - 0.23903021f * x) * x;
4030 // error 0.0034276066, which is better than 8 bits
4031 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4032 getF32Constant(DAG, 0xbe74c456));
4033 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4034 getF32Constant(DAG, 0x3fb3a2b1));
4035 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4036 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4037 getF32Constant(DAG, 0x3f949a29));
4038 } else if (LimitFloatPrecision <= 12) {
4039 // For floating-point precision of 12:
4045 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4047 // error 0.000061011436, which is 14 bits
4048 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4049 getF32Constant(DAG, 0xbd67b6d6));
4050 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4051 getF32Constant(DAG, 0x3ee4f4b8));
4052 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4053 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4054 getF32Constant(DAG, 0x3fbc278b));
4055 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4056 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4057 getF32Constant(DAG, 0x40348e95));
4058 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4059 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4060 getF32Constant(DAG, 0x3fdef31a));
4061 } else { // LimitFloatPrecision <= 18
4062 // For floating-point precision of 18:
4070 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4072 // error 0.0000023660568, which is better than 18 bits
4073 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4074 getF32Constant(DAG, 0xbc91e5ac));
4075 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4076 getF32Constant(DAG, 0x3e4350aa));
4077 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4078 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4079 getF32Constant(DAG, 0x3f60d3e3));
4080 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4081 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4082 getF32Constant(DAG, 0x4011cdf0));
4083 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4084 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4085 getF32Constant(DAG, 0x406cfd1c));
4086 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4087 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4088 getF32Constant(DAG, 0x408797cb));
4089 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4090 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4091 getF32Constant(DAG, 0x4006dcab));
4094 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4097 // No special expansion.
4098 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4101 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4102 /// limited-precision mode.
4103 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4104 const TargetLowering &TLI) {
4105 if (Op.getValueType() == MVT::f32 &&
4106 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4107 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4109 // Get the exponent.
4110 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4112 // Get the significand and build it into a floating-point number with
4114 SDValue X = GetSignificand(DAG, Op1, dl);
4116 // Different possible minimax approximations of significand in
4117 // floating-point for various degrees of accuracy over [1,2].
4118 SDValue Log2ofMantissa;
4119 if (LimitFloatPrecision <= 6) {
4120 // For floating-point precision of 6:
4122 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4124 // error 0.0049451742, which is more than 7 bits
4125 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4126 getF32Constant(DAG, 0xbeb08fe0));
4127 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4128 getF32Constant(DAG, 0x40019463));
4129 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4130 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4131 getF32Constant(DAG, 0x3fd6633d));
4132 } else if (LimitFloatPrecision <= 12) {
4133 // For floating-point precision of 12:
4139 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4141 // error 0.0000876136000, which is better than 13 bits
4142 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4143 getF32Constant(DAG, 0xbda7262e));
4144 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4145 getF32Constant(DAG, 0x3f25280b));
4146 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4147 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4148 getF32Constant(DAG, 0x4007b923));
4149 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4150 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4151 getF32Constant(DAG, 0x40823e2f));
4152 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4153 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4154 getF32Constant(DAG, 0x4020d29c));
4155 } else { // LimitFloatPrecision <= 18
4156 // For floating-point precision of 18:
4165 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4167 // error 0.0000018516, which is better than 18 bits
4168 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4169 getF32Constant(DAG, 0xbcd2769e));
4170 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4171 getF32Constant(DAG, 0x3e8ce0b9));
4172 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4173 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4174 getF32Constant(DAG, 0x3fa22ae7));
4175 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4176 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4177 getF32Constant(DAG, 0x40525723));
4178 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4179 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4180 getF32Constant(DAG, 0x40aaf200));
4181 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4182 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4183 getF32Constant(DAG, 0x40c39dad));
4184 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4185 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4186 getF32Constant(DAG, 0x4042902c));
4189 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4192 // No special expansion.
4193 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4196 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4197 /// limited-precision mode.
4198 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4199 const TargetLowering &TLI) {
4200 if (Op.getValueType() == MVT::f32 &&
4201 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4202 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4204 // Scale the exponent by log10(2) [0.30102999f].
4205 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4206 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4207 getF32Constant(DAG, 0x3e9a209a));
4209 // Get the significand and build it into a floating-point number with
4211 SDValue X = GetSignificand(DAG, Op1, dl);
4213 SDValue Log10ofMantissa;
4214 if (LimitFloatPrecision <= 6) {
4215 // For floating-point precision of 6:
4217 // Log10ofMantissa =
4219 // (0.60948995f - 0.10380950f * x) * x;
4221 // error 0.0014886165, which is 6 bits
4222 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4223 getF32Constant(DAG, 0xbdd49a13));
4224 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4225 getF32Constant(DAG, 0x3f1c0789));
4226 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4227 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4228 getF32Constant(DAG, 0x3f011300));
4229 } else if (LimitFloatPrecision <= 12) {
4230 // For floating-point precision of 12:
4232 // Log10ofMantissa =
4235 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4237 // error 0.00019228036, which is better than 12 bits
4238 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4239 getF32Constant(DAG, 0x3d431f31));
4240 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4241 getF32Constant(DAG, 0x3ea21fb2));
4242 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4243 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4244 getF32Constant(DAG, 0x3f6ae232));
4245 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4246 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4247 getF32Constant(DAG, 0x3f25f7c3));
4248 } else { // LimitFloatPrecision <= 18
4249 // For floating-point precision of 18:
4251 // Log10ofMantissa =
4256 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4258 // error 0.0000037995730, which is better than 18 bits
4259 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4260 getF32Constant(DAG, 0x3c5d51ce));
4261 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4262 getF32Constant(DAG, 0x3e00685a));
4263 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4264 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4265 getF32Constant(DAG, 0x3efb6798));
4266 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4267 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4268 getF32Constant(DAG, 0x3f88d192));
4269 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4270 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4271 getF32Constant(DAG, 0x3fc4316c));
4272 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4273 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4274 getF32Constant(DAG, 0x3f57ce70));
4277 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4280 // No special expansion.
4281 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4284 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4285 /// limited-precision mode.
4286 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4287 const TargetLowering &TLI) {
4288 if (Op.getValueType() == MVT::f32 &&
4289 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4290 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4292 // FractionalPartOfX = x - (float)IntegerPartOfX;
4293 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4294 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4296 // IntegerPartOfX <<= 23;
4297 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4298 DAG.getConstant(23, TLI.getPointerTy()));
4300 SDValue TwoToFractionalPartOfX;
4301 if (LimitFloatPrecision <= 6) {
4302 // For floating-point precision of 6:
4304 // TwoToFractionalPartOfX =
4306 // (0.735607626f + 0.252464424f * x) * x;
4308 // error 0.0144103317, which is 6 bits
4309 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4310 getF32Constant(DAG, 0x3e814304));
4311 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4312 getF32Constant(DAG, 0x3f3c50c8));
4313 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4314 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4315 getF32Constant(DAG, 0x3f7f5e7e));
4316 } else if (LimitFloatPrecision <= 12) {
4317 // For floating-point precision of 12:
4319 // TwoToFractionalPartOfX =
4322 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4324 // error 0.000107046256, which is 13 to 14 bits
4325 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4326 getF32Constant(DAG, 0x3da235e3));
4327 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4328 getF32Constant(DAG, 0x3e65b8f3));
4329 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4330 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4331 getF32Constant(DAG, 0x3f324b07));
4332 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4333 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4334 getF32Constant(DAG, 0x3f7ff8fd));
4335 } else { // LimitFloatPrecision <= 18
4336 // For floating-point precision of 18:
4338 // TwoToFractionalPartOfX =
4342 // (0.554906021e-1f +
4343 // (0.961591928e-2f +
4344 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4345 // error 2.47208000*10^(-7), which is better than 18 bits
4346 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4347 getF32Constant(DAG, 0x3924b03e));
4348 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4349 getF32Constant(DAG, 0x3ab24b87));
4350 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4351 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4352 getF32Constant(DAG, 0x3c1d8c17));
4353 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4354 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4355 getF32Constant(DAG, 0x3d634a1d));
4356 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4357 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4358 getF32Constant(DAG, 0x3e75fe14));
4359 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4360 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4361 getF32Constant(DAG, 0x3f317234));
4362 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4363 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4364 getF32Constant(DAG, 0x3f800000));
4367 // Add the exponent into the result in integer domain.
4368 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4369 TwoToFractionalPartOfX);
4370 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4371 DAG.getNode(ISD::ADD, dl, MVT::i32,
4372 t13, IntegerPartOfX));
4375 // No special expansion.
4376 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4379 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4380 /// limited-precision mode with x == 10.0f.
4381 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4382 SelectionDAG &DAG, const TargetLowering &TLI) {
4383 bool IsExp10 = false;
4384 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4385 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4386 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4388 IsExp10 = LHSC->isExactlyValue(Ten);
4393 // Put the exponent in the right bit position for later addition to the
4396 // #define LOG2OF10 3.3219281f
4397 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4398 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4399 getF32Constant(DAG, 0x40549a78));
4400 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4402 // FractionalPartOfX = x - (float)IntegerPartOfX;
4403 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4404 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4406 // IntegerPartOfX <<= 23;
4407 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4408 DAG.getConstant(23, TLI.getPointerTy()));
4410 SDValue TwoToFractionalPartOfX;
4411 if (LimitFloatPrecision <= 6) {
4412 // For floating-point precision of 6:
4414 // twoToFractionalPartOfX =
4416 // (0.735607626f + 0.252464424f * x) * x;
4418 // error 0.0144103317, which is 6 bits
4419 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4420 getF32Constant(DAG, 0x3e814304));
4421 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4422 getF32Constant(DAG, 0x3f3c50c8));
4423 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4424 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4425 getF32Constant(DAG, 0x3f7f5e7e));
4426 } else if (LimitFloatPrecision <= 12) {
4427 // For floating-point precision of 12:
4429 // TwoToFractionalPartOfX =
4432 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4434 // error 0.000107046256, which is 13 to 14 bits
4435 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4436 getF32Constant(DAG, 0x3da235e3));
4437 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4438 getF32Constant(DAG, 0x3e65b8f3));
4439 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4440 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4441 getF32Constant(DAG, 0x3f324b07));
4442 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4443 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4444 getF32Constant(DAG, 0x3f7ff8fd));
4445 } else { // LimitFloatPrecision <= 18
4446 // For floating-point precision of 18:
4448 // TwoToFractionalPartOfX =
4452 // (0.554906021e-1f +
4453 // (0.961591928e-2f +
4454 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4455 // error 2.47208000*10^(-7), which is better than 18 bits
4456 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4457 getF32Constant(DAG, 0x3924b03e));
4458 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4459 getF32Constant(DAG, 0x3ab24b87));
4460 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4461 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4462 getF32Constant(DAG, 0x3c1d8c17));
4463 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4464 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4465 getF32Constant(DAG, 0x3d634a1d));
4466 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4467 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4468 getF32Constant(DAG, 0x3e75fe14));
4469 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4470 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4471 getF32Constant(DAG, 0x3f317234));
4472 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4473 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4474 getF32Constant(DAG, 0x3f800000));
4477 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4478 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4479 DAG.getNode(ISD::ADD, dl, MVT::i32,
4480 t13, IntegerPartOfX));
4483 // No special expansion.
4484 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4488 /// ExpandPowI - Expand a llvm.powi intrinsic.
4489 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4490 SelectionDAG &DAG) {
4491 // If RHS is a constant, we can expand this out to a multiplication tree,
4492 // otherwise we end up lowering to a call to __powidf2 (for example). When
4493 // optimizing for size, we only want to do this if the expansion would produce
4494 // a small number of multiplies, otherwise we do the full expansion.
4495 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4496 // Get the exponent as a positive value.
4497 unsigned Val = RHSC->getSExtValue();
4498 if ((int)Val < 0) Val = -Val;
4500 // powi(x, 0) -> 1.0
4502 return DAG.getConstantFP(1.0, LHS.getValueType());
4504 const Function *F = DAG.getMachineFunction().getFunction();
4505 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4506 Attribute::OptimizeForSize) ||
4507 // If optimizing for size, don't insert too many multiplies. This
4508 // inserts up to 5 multiplies.
4509 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4510 // We use the simple binary decomposition method to generate the multiply
4511 // sequence. There are more optimal ways to do this (for example,
4512 // powi(x,15) generates one more multiply than it should), but this has
4513 // the benefit of being both really simple and much better than a libcall.
4514 SDValue Res; // Logically starts equal to 1.0
4515 SDValue CurSquare = LHS;
4519 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4521 Res = CurSquare; // 1.0*CurSquare.
4524 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4525 CurSquare, CurSquare);
4529 // If the original was negative, invert the result, producing 1/(x*x*x).
4530 if (RHSC->getSExtValue() < 0)
4531 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4532 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4537 // Otherwise, expand to a libcall.
4538 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4541 // getTruncatedArgReg - Find underlying register used for an truncated
4543 static unsigned getTruncatedArgReg(const SDValue &N) {
4544 if (N.getOpcode() != ISD::TRUNCATE)
4547 const SDValue &Ext = N.getOperand(0);
4548 if (Ext.getOpcode() == ISD::AssertZext ||
4549 Ext.getOpcode() == ISD::AssertSext) {
4550 const SDValue &CFR = Ext.getOperand(0);
4551 if (CFR.getOpcode() == ISD::CopyFromReg)
4552 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4553 if (CFR.getOpcode() == ISD::TRUNCATE)
4554 return getTruncatedArgReg(CFR);
4559 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4560 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4561 /// At the end of instruction selection, they will be inserted to the entry BB.
4562 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4564 MDNode *Expr, int64_t Offset,
4567 const Argument *Arg = dyn_cast<Argument>(V);
4571 MachineFunction &MF = DAG.getMachineFunction();
4572 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4574 // Ignore inlined function arguments here.
4575 DIVariable DV(Variable);
4576 if (DV.isInlinedFnArgument(MF.getFunction()))
4579 Optional<MachineOperand> Op;
4580 // Some arguments' frame index is recorded during argument lowering.
4581 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4582 Op = MachineOperand::CreateFI(FI);
4584 if (!Op && N.getNode()) {
4586 if (N.getOpcode() == ISD::CopyFromReg)
4587 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4589 Reg = getTruncatedArgReg(N);
4590 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4591 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4592 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4597 Op = MachineOperand::CreateReg(Reg, false);
4601 // Check if ValueMap has reg number.
4602 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4603 if (VMI != FuncInfo.ValueMap.end())
4604 Op = MachineOperand::CreateReg(VMI->second, false);
4607 if (!Op && N.getNode())
4608 // Check if frame index is available.
4609 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4610 if (FrameIndexSDNode *FINode =
4611 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4612 Op = MachineOperand::CreateFI(FINode->getIndex());
4618 FuncInfo.ArgDbgValues.push_back(
4619 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4620 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4622 FuncInfo.ArgDbgValues.push_back(
4623 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4626 .addMetadata(Variable)
4627 .addMetadata(Expr));
4632 // VisualStudio defines setjmp as _setjmp
4633 #if defined(_MSC_VER) && defined(setjmp) && \
4634 !defined(setjmp_undefined_for_msvc)
4635 # pragma push_macro("setjmp")
4637 # define setjmp_undefined_for_msvc
4640 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4641 /// we want to emit this as a call to a named external function, return the name
4642 /// otherwise lower it and return null.
4644 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4645 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4646 SDLoc sdl = getCurSDLoc();
4647 DebugLoc dl = getCurDebugLoc();
4650 switch (Intrinsic) {
4652 // By default, turn this into a target intrinsic node.
4653 visitTargetIntrinsic(I, Intrinsic);
4655 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4656 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4657 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4658 case Intrinsic::returnaddress:
4659 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4660 getValue(I.getArgOperand(0))));
4662 case Intrinsic::frameaddress:
4663 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4664 getValue(I.getArgOperand(0))));
4666 case Intrinsic::read_register: {
4667 Value *Reg = I.getArgOperand(0);
4668 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4669 EVT VT = TLI.getValueType(I.getType());
4670 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4673 case Intrinsic::write_register: {
4674 Value *Reg = I.getArgOperand(0);
4675 Value *RegValue = I.getArgOperand(1);
4676 SDValue Chain = getValue(RegValue).getOperand(0);
4677 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4678 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4679 RegName, getValue(RegValue)));
4682 case Intrinsic::setjmp:
4683 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4684 case Intrinsic::longjmp:
4685 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4686 case Intrinsic::memcpy: {
4687 // Assert for address < 256 since we support only user defined address
4689 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4691 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4693 "Unknown address space");
4694 SDValue Op1 = getValue(I.getArgOperand(0));
4695 SDValue Op2 = getValue(I.getArgOperand(1));
4696 SDValue Op3 = getValue(I.getArgOperand(2));
4697 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4699 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4700 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4701 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4702 MachinePointerInfo(I.getArgOperand(0)),
4703 MachinePointerInfo(I.getArgOperand(1))));
4706 case Intrinsic::memset: {
4707 // Assert for address < 256 since we support only user defined address
4709 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4711 "Unknown address space");
4712 SDValue Op1 = getValue(I.getArgOperand(0));
4713 SDValue Op2 = getValue(I.getArgOperand(1));
4714 SDValue Op3 = getValue(I.getArgOperand(2));
4715 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4717 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4718 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4719 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4720 MachinePointerInfo(I.getArgOperand(0))));
4723 case Intrinsic::memmove: {
4724 // Assert for address < 256 since we support only user defined address
4726 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4728 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4730 "Unknown address space");
4731 SDValue Op1 = getValue(I.getArgOperand(0));
4732 SDValue Op2 = getValue(I.getArgOperand(1));
4733 SDValue Op3 = getValue(I.getArgOperand(2));
4734 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4736 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4737 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4738 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4739 MachinePointerInfo(I.getArgOperand(0)),
4740 MachinePointerInfo(I.getArgOperand(1))));
4743 case Intrinsic::dbg_declare: {
4744 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4745 MDNode *Variable = DI.getVariable();
4746 MDNode *Expression = DI.getExpression();
4747 const Value *Address = DI.getAddress();
4748 DIVariable DIVar(Variable);
4749 assert((!DIVar || DIVar.isVariable()) &&
4750 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4751 if (!Address || !DIVar) {
4752 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4756 // Check if address has undef value.
4757 if (isa<UndefValue>(Address) ||
4758 (Address->use_empty() && !isa<Argument>(Address))) {
4759 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4763 SDValue &N = NodeMap[Address];
4764 if (!N.getNode() && isa<Argument>(Address))
4765 // Check unused arguments map.
4766 N = UnusedArgNodeMap[Address];
4769 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4770 Address = BCI->getOperand(0);
4771 // Parameters are handled specially.
4773 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4774 isa<Argument>(Address));
4776 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4778 if (isParameter && !AI) {
4779 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4781 // Byval parameter. We have a frame index at this point.
4782 SDV = DAG.getFrameIndexDbgValue(
4783 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4785 // Address is an argument, so try to emit its dbg value using
4786 // virtual register info from the FuncInfo.ValueMap.
4787 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4791 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4792 true, 0, dl, SDNodeOrder);
4794 // Can't do anything with other non-AI cases yet.
4795 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4796 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4797 DEBUG(Address->dump());
4800 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4802 // If Address is an argument then try to emit its dbg value using
4803 // virtual register info from the FuncInfo.ValueMap.
4804 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4806 // If variable is pinned by a alloca in dominating bb then
4807 // use StaticAllocaMap.
4808 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4809 if (AI->getParent() != DI.getParent()) {
4810 DenseMap<const AllocaInst*, int>::iterator SI =
4811 FuncInfo.StaticAllocaMap.find(AI);
4812 if (SI != FuncInfo.StaticAllocaMap.end()) {
4813 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4814 0, dl, SDNodeOrder);
4815 DAG.AddDbgValue(SDV, nullptr, false);
4820 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4825 case Intrinsic::dbg_value: {
4826 const DbgValueInst &DI = cast<DbgValueInst>(I);
4827 DIVariable DIVar(DI.getVariable());
4828 assert((!DIVar || DIVar.isVariable()) &&
4829 "Variable in DbgValueInst should be either null or a DIVariable.");
4833 MDNode *Variable = DI.getVariable();
4834 MDNode *Expression = DI.getExpression();
4835 uint64_t Offset = DI.getOffset();
4836 const Value *V = DI.getValue();
4841 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4842 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4844 DAG.AddDbgValue(SDV, nullptr, false);
4846 // Do not use getValue() in here; we don't want to generate code at
4847 // this point if it hasn't been done yet.
4848 SDValue N = NodeMap[V];
4849 if (!N.getNode() && isa<Argument>(V))
4850 // Check unused arguments map.
4851 N = UnusedArgNodeMap[V];
4853 // A dbg.value for an alloca is always indirect.
4854 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4855 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4857 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4858 IsIndirect, Offset, dl, SDNodeOrder);
4859 DAG.AddDbgValue(SDV, N.getNode(), false);
4861 } else if (!V->use_empty() ) {
4862 // Do not call getValue(V) yet, as we don't want to generate code.
4863 // Remember it for later.
4864 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4865 DanglingDebugInfoMap[V] = DDI;
4867 // We may expand this to cover more cases. One case where we have no
4868 // data available is an unreferenced parameter.
4869 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4873 // Build a debug info table entry.
4874 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4875 V = BCI->getOperand(0);
4876 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4877 // Don't handle byval struct arguments or VLAs, for example.
4879 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4880 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4883 DenseMap<const AllocaInst*, int>::iterator SI =
4884 FuncInfo.StaticAllocaMap.find(AI);
4885 if (SI == FuncInfo.StaticAllocaMap.end())
4886 return nullptr; // VLAs.
4890 case Intrinsic::eh_typeid_for: {
4891 // Find the type id for the given typeinfo.
4892 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4893 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4894 Res = DAG.getConstant(TypeID, MVT::i32);
4899 case Intrinsic::eh_return_i32:
4900 case Intrinsic::eh_return_i64:
4901 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4902 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4905 getValue(I.getArgOperand(0)),
4906 getValue(I.getArgOperand(1))));
4908 case Intrinsic::eh_unwind_init:
4909 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4911 case Intrinsic::eh_dwarf_cfa: {
4912 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4913 TLI.getPointerTy());
4914 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4915 CfaArg.getValueType(),
4916 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4917 CfaArg.getValueType()),
4919 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4920 DAG.getConstant(0, TLI.getPointerTy()));
4921 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4925 case Intrinsic::eh_sjlj_callsite: {
4926 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4927 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4928 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4929 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4931 MMI.setCurrentCallSite(CI->getZExtValue());
4934 case Intrinsic::eh_sjlj_functioncontext: {
4935 // Get and store the index of the function context.
4936 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4938 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4939 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4940 MFI->setFunctionContextIndex(FI);
4943 case Intrinsic::eh_sjlj_setjmp: {
4946 Ops[1] = getValue(I.getArgOperand(0));
4947 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4948 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4949 setValue(&I, Op.getValue(0));
4950 DAG.setRoot(Op.getValue(1));
4953 case Intrinsic::eh_sjlj_longjmp: {
4954 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4955 getRoot(), getValue(I.getArgOperand(0))));
4959 case Intrinsic::x86_mmx_pslli_w:
4960 case Intrinsic::x86_mmx_pslli_d:
4961 case Intrinsic::x86_mmx_pslli_q:
4962 case Intrinsic::x86_mmx_psrli_w:
4963 case Intrinsic::x86_mmx_psrli_d:
4964 case Intrinsic::x86_mmx_psrli_q:
4965 case Intrinsic::x86_mmx_psrai_w:
4966 case Intrinsic::x86_mmx_psrai_d: {
4967 SDValue ShAmt = getValue(I.getArgOperand(1));
4968 if (isa<ConstantSDNode>(ShAmt)) {
4969 visitTargetIntrinsic(I, Intrinsic);
4972 unsigned NewIntrinsic = 0;
4973 EVT ShAmtVT = MVT::v2i32;
4974 switch (Intrinsic) {
4975 case Intrinsic::x86_mmx_pslli_w:
4976 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4978 case Intrinsic::x86_mmx_pslli_d:
4979 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4981 case Intrinsic::x86_mmx_pslli_q:
4982 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4984 case Intrinsic::x86_mmx_psrli_w:
4985 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4987 case Intrinsic::x86_mmx_psrli_d:
4988 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4990 case Intrinsic::x86_mmx_psrli_q:
4991 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4993 case Intrinsic::x86_mmx_psrai_w:
4994 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4996 case Intrinsic::x86_mmx_psrai_d:
4997 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4999 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5002 // The vector shift intrinsics with scalars uses 32b shift amounts but
5003 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5005 // We must do this early because v2i32 is not a legal type.
5008 ShOps[1] = DAG.getConstant(0, MVT::i32);
5009 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5010 EVT DestVT = TLI.getValueType(I.getType());
5011 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5012 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5013 DAG.getConstant(NewIntrinsic, MVT::i32),
5014 getValue(I.getArgOperand(0)), ShAmt);
5018 case Intrinsic::x86_avx_vinsertf128_pd_256:
5019 case Intrinsic::x86_avx_vinsertf128_ps_256:
5020 case Intrinsic::x86_avx_vinsertf128_si_256:
5021 case Intrinsic::x86_avx2_vinserti128: {
5022 EVT DestVT = TLI.getValueType(I.getType());
5023 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5024 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5025 ElVT.getVectorNumElements();
5027 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5028 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5029 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5033 case Intrinsic::x86_avx_vextractf128_pd_256:
5034 case Intrinsic::x86_avx_vextractf128_ps_256:
5035 case Intrinsic::x86_avx_vextractf128_si_256:
5036 case Intrinsic::x86_avx2_vextracti128: {
5037 EVT DestVT = TLI.getValueType(I.getType());
5038 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5039 DestVT.getVectorNumElements();
5040 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5041 getValue(I.getArgOperand(0)),
5042 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5046 case Intrinsic::convertff:
5047 case Intrinsic::convertfsi:
5048 case Intrinsic::convertfui:
5049 case Intrinsic::convertsif:
5050 case Intrinsic::convertuif:
5051 case Intrinsic::convertss:
5052 case Intrinsic::convertsu:
5053 case Intrinsic::convertus:
5054 case Intrinsic::convertuu: {
5055 ISD::CvtCode Code = ISD::CVT_INVALID;
5056 switch (Intrinsic) {
5057 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5058 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5059 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5060 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5061 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5062 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5063 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5064 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5065 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5066 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5068 EVT DestVT = TLI.getValueType(I.getType());
5069 const Value *Op1 = I.getArgOperand(0);
5070 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5071 DAG.getValueType(DestVT),
5072 DAG.getValueType(getValue(Op1).getValueType()),
5073 getValue(I.getArgOperand(1)),
5074 getValue(I.getArgOperand(2)),
5079 case Intrinsic::powi:
5080 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5081 getValue(I.getArgOperand(1)), DAG));
5083 case Intrinsic::log:
5084 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5086 case Intrinsic::log2:
5087 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5089 case Intrinsic::log10:
5090 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5092 case Intrinsic::exp:
5093 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5095 case Intrinsic::exp2:
5096 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5098 case Intrinsic::pow:
5099 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5100 getValue(I.getArgOperand(1)), DAG, TLI));
5102 case Intrinsic::sqrt:
5103 case Intrinsic::fabs:
5104 case Intrinsic::sin:
5105 case Intrinsic::cos:
5106 case Intrinsic::floor:
5107 case Intrinsic::ceil:
5108 case Intrinsic::trunc:
5109 case Intrinsic::rint:
5110 case Intrinsic::nearbyint:
5111 case Intrinsic::round: {
5113 switch (Intrinsic) {
5114 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5115 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5116 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5117 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5118 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5119 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5120 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5121 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5122 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5123 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5124 case Intrinsic::round: Opcode = ISD::FROUND; break;
5127 setValue(&I, DAG.getNode(Opcode, sdl,
5128 getValue(I.getArgOperand(0)).getValueType(),
5129 getValue(I.getArgOperand(0))));
5132 case Intrinsic::copysign:
5133 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5134 getValue(I.getArgOperand(0)).getValueType(),
5135 getValue(I.getArgOperand(0)),
5136 getValue(I.getArgOperand(1))));
5138 case Intrinsic::fma:
5139 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5140 getValue(I.getArgOperand(0)).getValueType(),
5141 getValue(I.getArgOperand(0)),
5142 getValue(I.getArgOperand(1)),
5143 getValue(I.getArgOperand(2))));
5145 case Intrinsic::fmuladd: {
5146 EVT VT = TLI.getValueType(I.getType());
5147 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5148 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5149 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5150 getValue(I.getArgOperand(0)).getValueType(),
5151 getValue(I.getArgOperand(0)),
5152 getValue(I.getArgOperand(1)),
5153 getValue(I.getArgOperand(2))));
5155 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5156 getValue(I.getArgOperand(0)).getValueType(),
5157 getValue(I.getArgOperand(0)),
5158 getValue(I.getArgOperand(1)));
5159 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5160 getValue(I.getArgOperand(0)).getValueType(),
5162 getValue(I.getArgOperand(2)));
5167 case Intrinsic::convert_to_fp16:
5168 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5169 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5170 getValue(I.getArgOperand(0)),
5171 DAG.getTargetConstant(0, MVT::i32))));
5173 case Intrinsic::convert_from_fp16:
5175 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5176 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5177 getValue(I.getArgOperand(0)))));
5179 case Intrinsic::pcmarker: {
5180 SDValue Tmp = getValue(I.getArgOperand(0));
5181 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5184 case Intrinsic::readcyclecounter: {
5185 SDValue Op = getRoot();
5186 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5187 DAG.getVTList(MVT::i64, MVT::Other), Op);
5189 DAG.setRoot(Res.getValue(1));
5192 case Intrinsic::bswap:
5193 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5194 getValue(I.getArgOperand(0)).getValueType(),
5195 getValue(I.getArgOperand(0))));
5197 case Intrinsic::cttz: {
5198 SDValue Arg = getValue(I.getArgOperand(0));
5199 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5200 EVT Ty = Arg.getValueType();
5201 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5205 case Intrinsic::ctlz: {
5206 SDValue Arg = getValue(I.getArgOperand(0));
5207 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5208 EVT Ty = Arg.getValueType();
5209 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5213 case Intrinsic::ctpop: {
5214 SDValue Arg = getValue(I.getArgOperand(0));
5215 EVT Ty = Arg.getValueType();
5216 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5219 case Intrinsic::stacksave: {
5220 SDValue Op = getRoot();
5221 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5222 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5224 DAG.setRoot(Res.getValue(1));
5227 case Intrinsic::stackrestore: {
5228 Res = getValue(I.getArgOperand(0));
5229 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5232 case Intrinsic::stackprotector: {
5233 // Emit code into the DAG to store the stack guard onto the stack.
5234 MachineFunction &MF = DAG.getMachineFunction();
5235 MachineFrameInfo *MFI = MF.getFrameInfo();
5236 EVT PtrTy = TLI.getPointerTy();
5237 SDValue Src, Chain = getRoot();
5238 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5239 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5241 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5242 // global variable __stack_chk_guard.
5244 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5245 if (BC->getOpcode() == Instruction::BitCast)
5246 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5248 if (GV && TLI.useLoadStackGuardNode()) {
5249 // Emit a LOAD_STACK_GUARD node.
5250 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5252 MachinePointerInfo MPInfo(GV);
5253 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5254 unsigned Flags = MachineMemOperand::MOLoad |
5255 MachineMemOperand::MOInvariant;
5256 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5257 PtrTy.getSizeInBits() / 8,
5258 DAG.getEVTAlignment(PtrTy));
5259 Node->setMemRefs(MemRefs, MemRefs + 1);
5261 // Copy the guard value to a virtual register so that it can be
5262 // retrieved in the epilogue.
5263 Src = SDValue(Node, 0);
5264 const TargetRegisterClass *RC =
5265 TLI.getRegClassFor(Src.getSimpleValueType());
5266 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5268 SPDescriptor.setGuardReg(Reg);
5269 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5271 Src = getValue(I.getArgOperand(0)); // The guard's value.
5274 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5276 int FI = FuncInfo.StaticAllocaMap[Slot];
5277 MFI->setStackProtectorIndex(FI);
5279 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5281 // Store the stack protector onto the stack.
5282 Res = DAG.getStore(Chain, sdl, Src, FIN,
5283 MachinePointerInfo::getFixedStack(FI),
5289 case Intrinsic::objectsize: {
5290 // If we don't know by now, we're never going to know.
5291 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5293 assert(CI && "Non-constant type in __builtin_object_size?");
5295 SDValue Arg = getValue(I.getCalledValue());
5296 EVT Ty = Arg.getValueType();
5299 Res = DAG.getConstant(-1ULL, Ty);
5301 Res = DAG.getConstant(0, Ty);
5306 case Intrinsic::annotation:
5307 case Intrinsic::ptr_annotation:
5308 // Drop the intrinsic, but forward the value
5309 setValue(&I, getValue(I.getOperand(0)));
5311 case Intrinsic::assume:
5312 case Intrinsic::var_annotation:
5313 // Discard annotate attributes and assumptions
5316 case Intrinsic::init_trampoline: {
5317 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5321 Ops[1] = getValue(I.getArgOperand(0));
5322 Ops[2] = getValue(I.getArgOperand(1));
5323 Ops[3] = getValue(I.getArgOperand(2));
5324 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5325 Ops[5] = DAG.getSrcValue(F);
5327 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5332 case Intrinsic::adjust_trampoline: {
5333 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5335 getValue(I.getArgOperand(0))));
5338 case Intrinsic::gcroot:
5340 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5341 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5343 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5344 GFI->addStackRoot(FI->getIndex(), TypeMap);
5347 case Intrinsic::gcread:
5348 case Intrinsic::gcwrite:
5349 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5350 case Intrinsic::flt_rounds:
5351 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5354 case Intrinsic::expect: {
5355 // Just replace __builtin_expect(exp, c) with EXP.
5356 setValue(&I, getValue(I.getArgOperand(0)));
5360 case Intrinsic::debugtrap:
5361 case Intrinsic::trap: {
5362 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5363 if (TrapFuncName.empty()) {
5364 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5365 ISD::TRAP : ISD::DEBUGTRAP;
5366 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5369 TargetLowering::ArgListTy Args;
5371 TargetLowering::CallLoweringInfo CLI(DAG);
5372 CLI.setDebugLoc(sdl).setChain(getRoot())
5373 .setCallee(CallingConv::C, I.getType(),
5374 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5375 std::move(Args), 0);
5377 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5378 DAG.setRoot(Result.second);
5382 case Intrinsic::uadd_with_overflow:
5383 case Intrinsic::sadd_with_overflow:
5384 case Intrinsic::usub_with_overflow:
5385 case Intrinsic::ssub_with_overflow:
5386 case Intrinsic::umul_with_overflow:
5387 case Intrinsic::smul_with_overflow: {
5389 switch (Intrinsic) {
5390 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5391 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5392 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5393 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5394 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5395 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5396 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5398 SDValue Op1 = getValue(I.getArgOperand(0));
5399 SDValue Op2 = getValue(I.getArgOperand(1));
5401 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5402 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5405 case Intrinsic::prefetch: {
5407 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5409 Ops[1] = getValue(I.getArgOperand(0));
5410 Ops[2] = getValue(I.getArgOperand(1));
5411 Ops[3] = getValue(I.getArgOperand(2));
5412 Ops[4] = getValue(I.getArgOperand(3));
5413 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5414 DAG.getVTList(MVT::Other), Ops,
5415 EVT::getIntegerVT(*Context, 8),
5416 MachinePointerInfo(I.getArgOperand(0)),
5418 false, /* volatile */
5420 rw==1)); /* write */
5423 case Intrinsic::lifetime_start:
5424 case Intrinsic::lifetime_end: {
5425 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5426 // Stack coloring is not enabled in O0, discard region information.
5427 if (TM.getOptLevel() == CodeGenOpt::None)
5430 SmallVector<Value *, 4> Allocas;
5431 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5433 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5434 E = Allocas.end(); Object != E; ++Object) {
5435 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5437 // Could not find an Alloca.
5438 if (!LifetimeObject)
5441 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5445 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5446 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5448 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5453 case Intrinsic::invariant_start:
5454 // Discard region information.
5455 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5457 case Intrinsic::invariant_end:
5458 // Discard region information.
5460 case Intrinsic::stackprotectorcheck: {
5461 // Do not actually emit anything for this basic block. Instead we initialize
5462 // the stack protector descriptor and export the guard variable so we can
5463 // access it in FinishBasicBlock.
5464 const BasicBlock *BB = I.getParent();
5465 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5466 ExportFromCurrentBlock(SPDescriptor.getGuard());
5468 // Flush our exports since we are going to process a terminator.
5469 (void)getControlRoot();
5472 case Intrinsic::clear_cache:
5473 return TLI.getClearCacheBuiltinName();
5474 case Intrinsic::donothing:
5477 case Intrinsic::experimental_stackmap: {
5481 case Intrinsic::experimental_patchpoint_void:
5482 case Intrinsic::experimental_patchpoint_i64: {
5489 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5491 MachineBasicBlock *LandingPad) {
5492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5493 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5494 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5495 Type *RetTy = FTy->getReturnType();
5496 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5497 MCSymbol *BeginLabel = nullptr;
5499 TargetLowering::ArgListTy Args;
5500 TargetLowering::ArgListEntry Entry;
5501 Args.reserve(CS.arg_size());
5503 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5505 const Value *V = *i;
5508 if (V->getType()->isEmptyTy())
5511 SDValue ArgNode = getValue(V);
5512 Entry.Node = ArgNode; Entry.Ty = V->getType();
5514 // Skip the first return-type Attribute to get to params.
5515 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5516 Args.push_back(Entry);
5520 // Insert a label before the invoke call to mark the try range. This can be
5521 // used to detect deletion of the invoke via the MachineModuleInfo.
5522 BeginLabel = MMI.getContext().CreateTempSymbol();
5524 // For SjLj, keep track of which landing pads go with which invokes
5525 // so as to maintain the ordering of pads in the LSDA.
5526 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5527 if (CallSiteIndex) {
5528 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5529 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5531 // Now that the call site is handled, stop tracking it.
5532 MMI.setCurrentCallSite(0);
5535 // Both PendingLoads and PendingExports must be flushed here;
5536 // this call might not return.
5538 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5541 // Check if target-independent constraints permit a tail call here.
5542 // Target-dependent constraints are checked within TLI.LowerCallTo.
5543 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5546 TargetLowering::CallLoweringInfo CLI(DAG);
5547 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5548 .setCallee(RetTy, FTy, Callee, std::move(Args), CS).setTailCall(isTailCall);
5550 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5551 assert((isTailCall || Result.second.getNode()) &&
5552 "Non-null chain expected with non-tail call!");
5553 assert((Result.second.getNode() || !Result.first.getNode()) &&
5554 "Null value expected with tail call!");
5555 if (Result.first.getNode())
5556 setValue(CS.getInstruction(), Result.first);
5558 if (!Result.second.getNode()) {
5559 // As a special case, a null chain means that a tail call has been emitted
5560 // and the DAG root is already updated.
5563 // Since there's no actual continuation from this block, nothing can be
5564 // relying on us setting vregs for them.
5565 PendingExports.clear();
5567 DAG.setRoot(Result.second);
5571 // Insert a label at the end of the invoke call to mark the try range. This
5572 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5573 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5574 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5576 // Inform MachineModuleInfo of range.
5577 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5581 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5582 /// value is equal or not-equal to zero.
5583 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5584 for (const User *U : V->users()) {
5585 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5586 if (IC->isEquality())
5587 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5588 if (C->isNullValue())
5590 // Unknown instruction.
5596 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5598 SelectionDAGBuilder &Builder) {
5600 // Check to see if this load can be trivially constant folded, e.g. if the
5601 // input is from a string literal.
5602 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5603 // Cast pointer to the type we really want to load.
5604 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5605 PointerType::getUnqual(LoadTy));
5607 if (const Constant *LoadCst =
5608 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5610 return Builder.getValue(LoadCst);
5613 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5614 // still constant memory, the input chain can be the entry node.
5616 bool ConstantMemory = false;
5618 // Do not serialize (non-volatile) loads of constant memory with anything.
5619 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5620 Root = Builder.DAG.getEntryNode();
5621 ConstantMemory = true;
5623 // Do not serialize non-volatile loads against each other.
5624 Root = Builder.DAG.getRoot();
5627 SDValue Ptr = Builder.getValue(PtrVal);
5628 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5629 Ptr, MachinePointerInfo(PtrVal),
5631 false /*nontemporal*/,
5632 false /*isinvariant*/, 1 /* align=1 */);
5634 if (!ConstantMemory)
5635 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5639 /// processIntegerCallValue - Record the value for an instruction that
5640 /// produces an integer result, converting the type where necessary.
5641 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5644 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5646 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5648 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5649 setValue(&I, Value);
5652 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5653 /// If so, return true and lower it, otherwise return false and it will be
5654 /// lowered like a normal call.
5655 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5656 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5657 if (I.getNumArgOperands() != 3)
5660 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5661 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5662 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5663 !I.getType()->isIntegerTy())
5666 const Value *Size = I.getArgOperand(2);
5667 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5668 if (CSize && CSize->getZExtValue() == 0) {
5669 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5670 setValue(&I, DAG.getConstant(0, CallVT));
5674 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5675 std::pair<SDValue, SDValue> Res =
5676 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5677 getValue(LHS), getValue(RHS), getValue(Size),
5678 MachinePointerInfo(LHS),
5679 MachinePointerInfo(RHS));
5680 if (Res.first.getNode()) {
5681 processIntegerCallValue(I, Res.first, true);
5682 PendingLoads.push_back(Res.second);
5686 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5687 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5688 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5689 bool ActuallyDoIt = true;
5692 switch (CSize->getZExtValue()) {
5694 LoadVT = MVT::Other;
5696 ActuallyDoIt = false;
5700 LoadTy = Type::getInt16Ty(CSize->getContext());
5704 LoadTy = Type::getInt32Ty(CSize->getContext());
5708 LoadTy = Type::getInt64Ty(CSize->getContext());
5712 LoadVT = MVT::v4i32;
5713 LoadTy = Type::getInt32Ty(CSize->getContext());
5714 LoadTy = VectorType::get(LoadTy, 4);
5719 // This turns into unaligned loads. We only do this if the target natively
5720 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5721 // we'll only produce a small number of byte loads.
5723 // Require that we can find a legal MVT, and only do this if the target
5724 // supports unaligned loads of that type. Expanding into byte loads would
5726 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5727 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5728 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5729 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5730 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5731 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5732 // TODO: Check alignment of src and dest ptrs.
5733 if (!TLI.isTypeLegal(LoadVT) ||
5734 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5735 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5736 ActuallyDoIt = false;
5740 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5741 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5743 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5745 processIntegerCallValue(I, Res, false);
5754 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5755 /// form. If so, return true and lower it, otherwise return false and it
5756 /// will be lowered like a normal call.
5757 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5758 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5759 if (I.getNumArgOperands() != 3)
5762 const Value *Src = I.getArgOperand(0);
5763 const Value *Char = I.getArgOperand(1);
5764 const Value *Length = I.getArgOperand(2);
5765 if (!Src->getType()->isPointerTy() ||
5766 !Char->getType()->isIntegerTy() ||
5767 !Length->getType()->isIntegerTy() ||
5768 !I.getType()->isPointerTy())
5771 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5772 std::pair<SDValue, SDValue> Res =
5773 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5774 getValue(Src), getValue(Char), getValue(Length),
5775 MachinePointerInfo(Src));
5776 if (Res.first.getNode()) {
5777 setValue(&I, Res.first);
5778 PendingLoads.push_back(Res.second);
5785 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5786 /// optimized form. If so, return true and lower it, otherwise return false
5787 /// and it will be lowered like a normal call.
5788 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5789 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5790 if (I.getNumArgOperands() != 2)
5793 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5794 if (!Arg0->getType()->isPointerTy() ||
5795 !Arg1->getType()->isPointerTy() ||
5796 !I.getType()->isPointerTy())
5799 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5800 std::pair<SDValue, SDValue> Res =
5801 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5802 getValue(Arg0), getValue(Arg1),
5803 MachinePointerInfo(Arg0),
5804 MachinePointerInfo(Arg1), isStpcpy);
5805 if (Res.first.getNode()) {
5806 setValue(&I, Res.first);
5807 DAG.setRoot(Res.second);
5814 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5815 /// If so, return true and lower it, otherwise return false and it will be
5816 /// lowered like a normal call.
5817 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5818 // Verify that the prototype makes sense. int strcmp(void*,void*)
5819 if (I.getNumArgOperands() != 2)
5822 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5823 if (!Arg0->getType()->isPointerTy() ||
5824 !Arg1->getType()->isPointerTy() ||
5825 !I.getType()->isIntegerTy())
5828 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5829 std::pair<SDValue, SDValue> Res =
5830 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5831 getValue(Arg0), getValue(Arg1),
5832 MachinePointerInfo(Arg0),
5833 MachinePointerInfo(Arg1));
5834 if (Res.first.getNode()) {
5835 processIntegerCallValue(I, Res.first, true);
5836 PendingLoads.push_back(Res.second);
5843 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5844 /// form. If so, return true and lower it, otherwise return false and it
5845 /// will be lowered like a normal call.
5846 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5847 // Verify that the prototype makes sense. size_t strlen(char *)
5848 if (I.getNumArgOperands() != 1)
5851 const Value *Arg0 = I.getArgOperand(0);
5852 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5855 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5856 std::pair<SDValue, SDValue> Res =
5857 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5858 getValue(Arg0), MachinePointerInfo(Arg0));
5859 if (Res.first.getNode()) {
5860 processIntegerCallValue(I, Res.first, false);
5861 PendingLoads.push_back(Res.second);
5868 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5869 /// form. If so, return true and lower it, otherwise return false and it
5870 /// will be lowered like a normal call.
5871 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5872 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5873 if (I.getNumArgOperands() != 2)
5876 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5877 if (!Arg0->getType()->isPointerTy() ||
5878 !Arg1->getType()->isIntegerTy() ||
5879 !I.getType()->isIntegerTy())
5882 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5883 std::pair<SDValue, SDValue> Res =
5884 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5885 getValue(Arg0), getValue(Arg1),
5886 MachinePointerInfo(Arg0));
5887 if (Res.first.getNode()) {
5888 processIntegerCallValue(I, Res.first, false);
5889 PendingLoads.push_back(Res.second);
5896 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5897 /// operation (as expected), translate it to an SDNode with the specified opcode
5898 /// and return true.
5899 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5901 // Sanity check that it really is a unary floating-point call.
5902 if (I.getNumArgOperands() != 1 ||
5903 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5904 I.getType() != I.getArgOperand(0)->getType() ||
5905 !I.onlyReadsMemory())
5908 SDValue Tmp = getValue(I.getArgOperand(0));
5909 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5913 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5914 // Handle inline assembly differently.
5915 if (isa<InlineAsm>(I.getCalledValue())) {
5920 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5921 ComputeUsesVAFloatArgument(I, &MMI);
5923 const char *RenameFn = nullptr;
5924 if (Function *F = I.getCalledFunction()) {
5925 if (F->isDeclaration()) {
5926 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5927 if (unsigned IID = II->getIntrinsicID(F)) {
5928 RenameFn = visitIntrinsicCall(I, IID);
5933 if (unsigned IID = F->getIntrinsicID()) {
5934 RenameFn = visitIntrinsicCall(I, IID);
5940 // Check for well-known libc/libm calls. If the function is internal, it
5941 // can't be a library call.
5943 if (!F->hasLocalLinkage() && F->hasName() &&
5944 LibInfo->getLibFunc(F->getName(), Func) &&
5945 LibInfo->hasOptimizedCodeGen(Func)) {
5948 case LibFunc::copysign:
5949 case LibFunc::copysignf:
5950 case LibFunc::copysignl:
5951 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5952 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5953 I.getType() == I.getArgOperand(0)->getType() &&
5954 I.getType() == I.getArgOperand(1)->getType() &&
5955 I.onlyReadsMemory()) {
5956 SDValue LHS = getValue(I.getArgOperand(0));
5957 SDValue RHS = getValue(I.getArgOperand(1));
5958 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5959 LHS.getValueType(), LHS, RHS));
5964 case LibFunc::fabsf:
5965 case LibFunc::fabsl:
5966 if (visitUnaryFloatCall(I, ISD::FABS))
5972 if (visitUnaryFloatCall(I, ISD::FSIN))
5978 if (visitUnaryFloatCall(I, ISD::FCOS))
5982 case LibFunc::sqrtf:
5983 case LibFunc::sqrtl:
5984 case LibFunc::sqrt_finite:
5985 case LibFunc::sqrtf_finite:
5986 case LibFunc::sqrtl_finite:
5987 if (visitUnaryFloatCall(I, ISD::FSQRT))
5990 case LibFunc::floor:
5991 case LibFunc::floorf:
5992 case LibFunc::floorl:
5993 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5996 case LibFunc::nearbyint:
5997 case LibFunc::nearbyintf:
5998 case LibFunc::nearbyintl:
5999 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6003 case LibFunc::ceilf:
6004 case LibFunc::ceill:
6005 if (visitUnaryFloatCall(I, ISD::FCEIL))
6009 case LibFunc::rintf:
6010 case LibFunc::rintl:
6011 if (visitUnaryFloatCall(I, ISD::FRINT))
6014 case LibFunc::round:
6015 case LibFunc::roundf:
6016 case LibFunc::roundl:
6017 if (visitUnaryFloatCall(I, ISD::FROUND))
6020 case LibFunc::trunc:
6021 case LibFunc::truncf:
6022 case LibFunc::truncl:
6023 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6027 case LibFunc::log2f:
6028 case LibFunc::log2l:
6029 if (visitUnaryFloatCall(I, ISD::FLOG2))
6033 case LibFunc::exp2f:
6034 case LibFunc::exp2l:
6035 if (visitUnaryFloatCall(I, ISD::FEXP2))
6038 case LibFunc::memcmp:
6039 if (visitMemCmpCall(I))
6042 case LibFunc::memchr:
6043 if (visitMemChrCall(I))
6046 case LibFunc::strcpy:
6047 if (visitStrCpyCall(I, false))
6050 case LibFunc::stpcpy:
6051 if (visitStrCpyCall(I, true))
6054 case LibFunc::strcmp:
6055 if (visitStrCmpCall(I))
6058 case LibFunc::strlen:
6059 if (visitStrLenCall(I))
6062 case LibFunc::strnlen:
6063 if (visitStrNLenCall(I))
6072 Callee = getValue(I.getCalledValue());
6074 Callee = DAG.getExternalSymbol(RenameFn,
6075 DAG.getTargetLoweringInfo().getPointerTy());
6077 // Check if we can potentially perform a tail call. More detailed checking is
6078 // be done within LowerCallTo, after more information about the call is known.
6079 LowerCallTo(&I, Callee, I.isTailCall());
6084 /// AsmOperandInfo - This contains information for each constraint that we are
6086 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6088 /// CallOperand - If this is the result output operand or a clobber
6089 /// this is null, otherwise it is the incoming operand to the CallInst.
6090 /// This gets modified as the asm is processed.
6091 SDValue CallOperand;
6093 /// AssignedRegs - If this is a register or register class operand, this
6094 /// contains the set of register corresponding to the operand.
6095 RegsForValue AssignedRegs;
6097 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6098 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6101 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6102 /// corresponds to. If there is no Value* for this operand, it returns
6104 EVT getCallOperandValEVT(LLVMContext &Context,
6105 const TargetLowering &TLI,
6106 const DataLayout *DL) const {
6107 if (!CallOperandVal) return MVT::Other;
6109 if (isa<BasicBlock>(CallOperandVal))
6110 return TLI.getPointerTy();
6112 llvm::Type *OpTy = CallOperandVal->getType();
6114 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6115 // If this is an indirect operand, the operand is a pointer to the
6118 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6120 report_fatal_error("Indirect operand for inline asm not a pointer!");
6121 OpTy = PtrTy->getElementType();
6124 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6125 if (StructType *STy = dyn_cast<StructType>(OpTy))
6126 if (STy->getNumElements() == 1)
6127 OpTy = STy->getElementType(0);
6129 // If OpTy is not a single value, it may be a struct/union that we
6130 // can tile with integers.
6131 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6132 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6141 OpTy = IntegerType::get(Context, BitSize);
6146 return TLI.getValueType(OpTy, true);
6150 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6152 } // end anonymous namespace
6154 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6155 /// specified operand. We prefer to assign virtual registers, to allow the
6156 /// register allocator to handle the assignment process. However, if the asm
6157 /// uses features that we can't model on machineinstrs, we have SDISel do the
6158 /// allocation. This produces generally horrible, but correct, code.
6160 /// OpInfo describes the operand.
6162 static void GetRegistersForValue(SelectionDAG &DAG,
6163 const TargetLowering &TLI,
6165 SDISelAsmOperandInfo &OpInfo) {
6166 LLVMContext &Context = *DAG.getContext();
6168 MachineFunction &MF = DAG.getMachineFunction();
6169 SmallVector<unsigned, 4> Regs;
6171 // If this is a constraint for a single physreg, or a constraint for a
6172 // register class, find it.
6173 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6174 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6175 OpInfo.ConstraintVT);
6177 unsigned NumRegs = 1;
6178 if (OpInfo.ConstraintVT != MVT::Other) {
6179 // If this is a FP input in an integer register (or visa versa) insert a bit
6180 // cast of the input value. More generally, handle any case where the input
6181 // value disagrees with the register class we plan to stick this in.
6182 if (OpInfo.Type == InlineAsm::isInput &&
6183 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6184 // Try to convert to the first EVT that the reg class contains. If the
6185 // types are identical size, use a bitcast to convert (e.g. two differing
6187 MVT RegVT = *PhysReg.second->vt_begin();
6188 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6189 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6190 RegVT, OpInfo.CallOperand);
6191 OpInfo.ConstraintVT = RegVT;
6192 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6193 // If the input is a FP value and we want it in FP registers, do a
6194 // bitcast to the corresponding integer type. This turns an f64 value
6195 // into i64, which can be passed with two i32 values on a 32-bit
6197 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6198 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6199 RegVT, OpInfo.CallOperand);
6200 OpInfo.ConstraintVT = RegVT;
6204 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6208 EVT ValueVT = OpInfo.ConstraintVT;
6210 // If this is a constraint for a specific physical register, like {r17},
6212 if (unsigned AssignedReg = PhysReg.first) {
6213 const TargetRegisterClass *RC = PhysReg.second;
6214 if (OpInfo.ConstraintVT == MVT::Other)
6215 ValueVT = *RC->vt_begin();
6217 // Get the actual register value type. This is important, because the user
6218 // may have asked for (e.g.) the AX register in i32 type. We need to
6219 // remember that AX is actually i16 to get the right extension.
6220 RegVT = *RC->vt_begin();
6222 // This is a explicit reference to a physical register.
6223 Regs.push_back(AssignedReg);
6225 // If this is an expanded reference, add the rest of the regs to Regs.
6227 TargetRegisterClass::iterator I = RC->begin();
6228 for (; *I != AssignedReg; ++I)
6229 assert(I != RC->end() && "Didn't find reg!");
6231 // Already added the first reg.
6233 for (; NumRegs; --NumRegs, ++I) {
6234 assert(I != RC->end() && "Ran out of registers to allocate!");
6239 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6243 // Otherwise, if this was a reference to an LLVM register class, create vregs
6244 // for this reference.
6245 if (const TargetRegisterClass *RC = PhysReg.second) {
6246 RegVT = *RC->vt_begin();
6247 if (OpInfo.ConstraintVT == MVT::Other)
6250 // Create the appropriate number of virtual registers.
6251 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6252 for (; NumRegs; --NumRegs)
6253 Regs.push_back(RegInfo.createVirtualRegister(RC));
6255 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6259 // Otherwise, we couldn't allocate enough registers for this.
6262 /// visitInlineAsm - Handle a call to an InlineAsm object.
6264 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6265 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6267 /// ConstraintOperands - Information about all of the constraints.
6268 SDISelAsmOperandInfoVector ConstraintOperands;
6270 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6271 TargetLowering::AsmOperandInfoVector
6272 TargetConstraints = TLI.ParseConstraints(CS);
6274 bool hasMemory = false;
6276 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6277 unsigned ResNo = 0; // ResNo - The result number of the next output.
6278 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6279 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6280 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6282 MVT OpVT = MVT::Other;
6284 // Compute the value type for each operand.
6285 switch (OpInfo.Type) {
6286 case InlineAsm::isOutput:
6287 // Indirect outputs just consume an argument.
6288 if (OpInfo.isIndirect) {
6289 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6293 // The return value of the call is this value. As such, there is no
6294 // corresponding argument.
6295 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6296 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6297 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6299 assert(ResNo == 0 && "Asm only has one result!");
6300 OpVT = TLI.getSimpleValueType(CS.getType());
6304 case InlineAsm::isInput:
6305 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6307 case InlineAsm::isClobber:
6312 // If this is an input or an indirect output, process the call argument.
6313 // BasicBlocks are labels, currently appearing only in asm's.
6314 if (OpInfo.CallOperandVal) {
6315 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6316 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6318 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6322 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6325 OpInfo.ConstraintVT = OpVT;
6327 // Indirect operand accesses access memory.
6328 if (OpInfo.isIndirect)
6331 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6332 TargetLowering::ConstraintType
6333 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6334 if (CType == TargetLowering::C_Memory) {
6342 SDValue Chain, Flag;
6344 // We won't need to flush pending loads if this asm doesn't touch
6345 // memory and is nonvolatile.
6346 if (hasMemory || IA->hasSideEffects())
6349 Chain = DAG.getRoot();
6351 // Second pass over the constraints: compute which constraint option to use
6352 // and assign registers to constraints that want a specific physreg.
6353 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6354 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6356 // If this is an output operand with a matching input operand, look up the
6357 // matching input. If their types mismatch, e.g. one is an integer, the
6358 // other is floating point, or their sizes are different, flag it as an
6360 if (OpInfo.hasMatchingInput()) {
6361 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6363 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6364 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6365 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6366 OpInfo.ConstraintVT);
6367 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6368 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6369 Input.ConstraintVT);
6370 if ((OpInfo.ConstraintVT.isInteger() !=
6371 Input.ConstraintVT.isInteger()) ||
6372 (MatchRC.second != InputRC.second)) {
6373 report_fatal_error("Unsupported asm: input constraint"
6374 " with a matching output constraint of"
6375 " incompatible type!");
6377 Input.ConstraintVT = OpInfo.ConstraintVT;
6381 // Compute the constraint code and ConstraintType to use.
6382 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6384 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6385 OpInfo.Type == InlineAsm::isClobber)
6388 // If this is a memory input, and if the operand is not indirect, do what we
6389 // need to to provide an address for the memory input.
6390 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6391 !OpInfo.isIndirect) {
6392 assert((OpInfo.isMultipleAlternative ||
6393 (OpInfo.Type == InlineAsm::isInput)) &&
6394 "Can only indirectify direct input operands!");
6396 // Memory operands really want the address of the value. If we don't have
6397 // an indirect input, put it in the constpool if we can, otherwise spill
6398 // it to a stack slot.
6399 // TODO: This isn't quite right. We need to handle these according to
6400 // the addressing mode that the constraint wants. Also, this may take
6401 // an additional register for the computation and we don't want that
6404 // If the operand is a float, integer, or vector constant, spill to a
6405 // constant pool entry to get its address.
6406 const Value *OpVal = OpInfo.CallOperandVal;
6407 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6408 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6409 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6410 TLI.getPointerTy());
6412 // Otherwise, create a stack slot and emit a store to it before the
6414 Type *Ty = OpVal->getType();
6415 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6416 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6417 MachineFunction &MF = DAG.getMachineFunction();
6418 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6419 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6420 Chain = DAG.getStore(Chain, getCurSDLoc(),
6421 OpInfo.CallOperand, StackSlot,
6422 MachinePointerInfo::getFixedStack(SSFI),
6424 OpInfo.CallOperand = StackSlot;
6427 // There is no longer a Value* corresponding to this operand.
6428 OpInfo.CallOperandVal = nullptr;
6430 // It is now an indirect operand.
6431 OpInfo.isIndirect = true;
6434 // If this constraint is for a specific register, allocate it before
6436 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6437 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6440 // Second pass - Loop over all of the operands, assigning virtual or physregs
6441 // to register class operands.
6442 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6443 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6445 // C_Register operands have already been allocated, Other/Memory don't need
6447 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6448 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6451 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6452 std::vector<SDValue> AsmNodeOperands;
6453 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6454 AsmNodeOperands.push_back(
6455 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6456 TLI.getPointerTy()));
6458 // If we have a !srcloc metadata node associated with it, we want to attach
6459 // this to the ultimately generated inline asm machineinstr. To do this, we
6460 // pass in the third operand as this (potentially null) inline asm MDNode.
6461 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6462 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6464 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6465 // bits as operand 3.
6466 unsigned ExtraInfo = 0;
6467 if (IA->hasSideEffects())
6468 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6469 if (IA->isAlignStack())
6470 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6471 // Set the asm dialect.
6472 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6474 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6475 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6476 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6478 // Compute the constraint code and ConstraintType to use.
6479 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6481 // Ideally, we would only check against memory constraints. However, the
6482 // meaning of an other constraint can be target-specific and we can't easily
6483 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6484 // for other constriants as well.
6485 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6486 OpInfo.ConstraintType == TargetLowering::C_Other) {
6487 if (OpInfo.Type == InlineAsm::isInput)
6488 ExtraInfo |= InlineAsm::Extra_MayLoad;
6489 else if (OpInfo.Type == InlineAsm::isOutput)
6490 ExtraInfo |= InlineAsm::Extra_MayStore;
6491 else if (OpInfo.Type == InlineAsm::isClobber)
6492 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6496 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6497 TLI.getPointerTy()));
6499 // Loop over all of the inputs, copying the operand values into the
6500 // appropriate registers and processing the output regs.
6501 RegsForValue RetValRegs;
6503 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6504 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6506 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6507 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6509 switch (OpInfo.Type) {
6510 case InlineAsm::isOutput: {
6511 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6512 OpInfo.ConstraintType != TargetLowering::C_Register) {
6513 // Memory output, or 'other' output (e.g. 'X' constraint).
6514 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6516 // Add information to the INLINEASM node to know about this output.
6517 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6518 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6519 TLI.getPointerTy()));
6520 AsmNodeOperands.push_back(OpInfo.CallOperand);
6524 // Otherwise, this is a register or register class output.
6526 // Copy the output from the appropriate register. Find a register that
6528 if (OpInfo.AssignedRegs.Regs.empty()) {
6529 LLVMContext &Ctx = *DAG.getContext();
6530 Ctx.emitError(CS.getInstruction(),
6531 "couldn't allocate output register for constraint '" +
6532 Twine(OpInfo.ConstraintCode) + "'");
6536 // If this is an indirect operand, store through the pointer after the
6538 if (OpInfo.isIndirect) {
6539 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6540 OpInfo.CallOperandVal));
6542 // This is the result value of the call.
6543 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6544 // Concatenate this output onto the outputs list.
6545 RetValRegs.append(OpInfo.AssignedRegs);
6548 // Add information to the INLINEASM node to know that this register is
6551 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6552 ? InlineAsm::Kind_RegDefEarlyClobber
6553 : InlineAsm::Kind_RegDef,
6554 false, 0, DAG, AsmNodeOperands);
6557 case InlineAsm::isInput: {
6558 SDValue InOperandVal = OpInfo.CallOperand;
6560 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6561 // If this is required to match an output register we have already set,
6562 // just use its register.
6563 unsigned OperandNo = OpInfo.getMatchedOperand();
6565 // Scan until we find the definition we already emitted of this operand.
6566 // When we find it, create a RegsForValue operand.
6567 unsigned CurOp = InlineAsm::Op_FirstOperand;
6568 for (; OperandNo; --OperandNo) {
6569 // Advance to the next operand.
6571 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6572 assert((InlineAsm::isRegDefKind(OpFlag) ||
6573 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6574 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6575 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6579 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6580 if (InlineAsm::isRegDefKind(OpFlag) ||
6581 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6582 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6583 if (OpInfo.isIndirect) {
6584 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6585 LLVMContext &Ctx = *DAG.getContext();
6586 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6587 " don't know how to handle tied "
6588 "indirect register inputs");
6592 RegsForValue MatchedRegs;
6593 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6594 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6595 MatchedRegs.RegVTs.push_back(RegVT);
6596 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6597 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6599 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6600 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6602 LLVMContext &Ctx = *DAG.getContext();
6603 Ctx.emitError(CS.getInstruction(),
6604 "inline asm error: This value"
6605 " type register class is not natively supported!");
6609 // Use the produced MatchedRegs object to
6610 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6611 Chain, &Flag, CS.getInstruction());
6612 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6613 true, OpInfo.getMatchedOperand(),
6614 DAG, AsmNodeOperands);
6618 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6619 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6620 "Unexpected number of operands");
6621 // Add information to the INLINEASM node to know about this input.
6622 // See InlineAsm.h isUseOperandTiedToDef.
6623 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6624 OpInfo.getMatchedOperand());
6625 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6626 TLI.getPointerTy()));
6627 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6631 // Treat indirect 'X' constraint as memory.
6632 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6634 OpInfo.ConstraintType = TargetLowering::C_Memory;
6636 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6637 std::vector<SDValue> Ops;
6638 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6641 LLVMContext &Ctx = *DAG.getContext();
6642 Ctx.emitError(CS.getInstruction(),
6643 "invalid operand for inline asm constraint '" +
6644 Twine(OpInfo.ConstraintCode) + "'");
6648 // Add information to the INLINEASM node to know about this input.
6649 unsigned ResOpType =
6650 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6651 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6652 TLI.getPointerTy()));
6653 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6657 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6658 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6659 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6660 "Memory operands expect pointer values");
6662 // Add information to the INLINEASM node to know about this input.
6663 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6664 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6665 TLI.getPointerTy()));
6666 AsmNodeOperands.push_back(InOperandVal);
6670 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6671 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6672 "Unknown constraint type!");
6674 // TODO: Support this.
6675 if (OpInfo.isIndirect) {
6676 LLVMContext &Ctx = *DAG.getContext();
6677 Ctx.emitError(CS.getInstruction(),
6678 "Don't know how to handle indirect register inputs yet "
6679 "for constraint '" +
6680 Twine(OpInfo.ConstraintCode) + "'");
6684 // Copy the input into the appropriate registers.
6685 if (OpInfo.AssignedRegs.Regs.empty()) {
6686 LLVMContext &Ctx = *DAG.getContext();
6687 Ctx.emitError(CS.getInstruction(),
6688 "couldn't allocate input reg for constraint '" +
6689 Twine(OpInfo.ConstraintCode) + "'");
6693 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6694 Chain, &Flag, CS.getInstruction());
6696 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6697 DAG, AsmNodeOperands);
6700 case InlineAsm::isClobber: {
6701 // Add the clobbered value to the operand list, so that the register
6702 // allocator is aware that the physreg got clobbered.
6703 if (!OpInfo.AssignedRegs.Regs.empty())
6704 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6712 // Finish up input operands. Set the input chain and add the flag last.
6713 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6714 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6716 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6717 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6718 Flag = Chain.getValue(1);
6720 // If this asm returns a register value, copy the result from that register
6721 // and set it as the value of the call.
6722 if (!RetValRegs.Regs.empty()) {
6723 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6724 Chain, &Flag, CS.getInstruction());
6726 // FIXME: Why don't we do this for inline asms with MRVs?
6727 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6728 EVT ResultType = TLI.getValueType(CS.getType());
6730 // If any of the results of the inline asm is a vector, it may have the
6731 // wrong width/num elts. This can happen for register classes that can
6732 // contain multiple different value types. The preg or vreg allocated may
6733 // not have the same VT as was expected. Convert it to the right type
6734 // with bit_convert.
6735 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6736 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6739 } else if (ResultType != Val.getValueType() &&
6740 ResultType.isInteger() && Val.getValueType().isInteger()) {
6741 // If a result value was tied to an input value, the computed result may
6742 // have a wider width than the expected result. Extract the relevant
6744 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6747 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6750 setValue(CS.getInstruction(), Val);
6751 // Don't need to use this as a chain in this case.
6752 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6756 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6758 // Process indirect outputs, first output all of the flagged copies out of
6760 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6761 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6762 const Value *Ptr = IndirectStoresToEmit[i].second;
6763 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6765 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6768 // Emit the non-flagged stores from the physregs.
6769 SmallVector<SDValue, 8> OutChains;
6770 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6771 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6772 StoresToEmit[i].first,
6773 getValue(StoresToEmit[i].second),
6774 MachinePointerInfo(StoresToEmit[i].second),
6776 OutChains.push_back(Val);
6779 if (!OutChains.empty())
6780 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6785 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6786 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6787 MVT::Other, getRoot(),
6788 getValue(I.getArgOperand(0)),
6789 DAG.getSrcValue(I.getArgOperand(0))));
6792 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6793 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6794 const DataLayout &DL = *TLI.getDataLayout();
6795 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6796 getRoot(), getValue(I.getOperand(0)),
6797 DAG.getSrcValue(I.getOperand(0)),
6798 DL.getABITypeAlignment(I.getType()));
6800 DAG.setRoot(V.getValue(1));
6803 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6804 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6805 MVT::Other, getRoot(),
6806 getValue(I.getArgOperand(0)),
6807 DAG.getSrcValue(I.getArgOperand(0))));
6810 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6811 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6812 MVT::Other, getRoot(),
6813 getValue(I.getArgOperand(0)),
6814 getValue(I.getArgOperand(1)),
6815 DAG.getSrcValue(I.getArgOperand(0)),
6816 DAG.getSrcValue(I.getArgOperand(1))));
6819 /// \brief Lower an argument list according to the target calling convention.
6821 /// \return A tuple of <return-value, token-chain>
6823 /// This is a helper for lowering intrinsics that follow a target calling
6824 /// convention or require stack pointer adjustment. Only a subset of the
6825 /// intrinsic's operands need to participate in the calling convention.
6826 std::pair<SDValue, SDValue>
6827 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6828 unsigned NumArgs, SDValue Callee,
6830 TargetLowering::ArgListTy Args;
6831 Args.reserve(NumArgs);
6833 // Populate the argument list.
6834 // Attributes for args start at offset 1, after the return attribute.
6835 ImmutableCallSite CS(&CI);
6836 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6837 ArgI != ArgE; ++ArgI) {
6838 const Value *V = CI.getOperand(ArgI);
6840 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6842 TargetLowering::ArgListEntry Entry;
6843 Entry.Node = getValue(V);
6844 Entry.Ty = V->getType();
6845 Entry.setAttributes(&CS, AttrI);
6846 Args.push_back(Entry);
6849 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6850 TargetLowering::CallLoweringInfo CLI(DAG);
6851 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6852 .setCallee(CI.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6853 .setDiscardResult(!CI.use_empty());
6855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6856 return TLI.LowerCallTo(CLI);
6859 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6860 /// or patchpoint target node's operand list.
6862 /// Constants are converted to TargetConstants purely as an optimization to
6863 /// avoid constant materialization and register allocation.
6865 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6866 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6867 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6868 /// address materialization and register allocation, but may also be required
6869 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6870 /// alloca in the entry block, then the runtime may assume that the alloca's
6871 /// StackMap location can be read immediately after compilation and that the
6872 /// location is valid at any point during execution (this is similar to the
6873 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6874 /// only available in a register, then the runtime would need to trap when
6875 /// execution reaches the StackMap in order to read the alloca's location.
6876 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6877 SmallVectorImpl<SDValue> &Ops,
6878 SelectionDAGBuilder &Builder) {
6879 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6880 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6881 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6883 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6885 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6886 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6887 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6889 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6891 Ops.push_back(OpVal);
6895 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6896 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6897 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6898 // [live variables...])
6900 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6902 SDValue Chain, InFlag, Callee, NullPtr;
6903 SmallVector<SDValue, 32> Ops;
6905 SDLoc DL = getCurSDLoc();
6906 Callee = getValue(CI.getCalledValue());
6907 NullPtr = DAG.getIntPtrConstant(0, true);
6909 // The stackmap intrinsic only records the live variables (the arguemnts
6910 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6911 // intrinsic, this won't be lowered to a function call. This means we don't
6912 // have to worry about calling conventions and target specific lowering code.
6913 // Instead we perform the call lowering right here.
6915 // chain, flag = CALLSEQ_START(chain, 0)
6916 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6917 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6919 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6920 InFlag = Chain.getValue(1);
6922 // Add the <id> and <numBytes> constants.
6923 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6924 Ops.push_back(DAG.getTargetConstant(
6925 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6926 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6927 Ops.push_back(DAG.getTargetConstant(
6928 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6930 // Push live variables for the stack map.
6931 addStackMapLiveVars(CI, 2, Ops, *this);
6933 // We are not pushing any register mask info here on the operands list,
6934 // because the stackmap doesn't clobber anything.
6936 // Push the chain and the glue flag.
6937 Ops.push_back(Chain);
6938 Ops.push_back(InFlag);
6940 // Create the STACKMAP node.
6941 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6942 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6943 Chain = SDValue(SM, 0);
6944 InFlag = Chain.getValue(1);
6946 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6948 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6950 // Set the root to the target-lowered call chain.
6953 // Inform the Frame Information that we have a stackmap in this function.
6954 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6957 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6958 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6959 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6964 // [live variables...])
6966 CallingConv::ID CC = CI.getCallingConv();
6967 bool isAnyRegCC = CC == CallingConv::AnyReg;
6968 bool hasDef = !CI.getType()->isVoidTy();
6969 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6971 // Get the real number of arguments participating in the call <numArgs>
6972 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6973 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6975 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6976 // Intrinsics include all meta-operands up to but not including CC.
6977 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6978 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6979 "Not enough arguments provided to the patchpoint intrinsic");
6981 // For AnyRegCC the arguments are lowered later on manually.
6982 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6983 std::pair<SDValue, SDValue> Result =
6984 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6986 // Set the root to the target-lowered call chain.
6987 SDValue Chain = Result.second;
6990 SDNode *CallEnd = Chain.getNode();
6991 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6992 CallEnd = CallEnd->getOperand(0).getNode();
6994 /// Get a call instruction from the call sequence chain.
6995 /// Tail calls are not allowed.
6996 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6997 "Expected a callseq node.");
6998 SDNode *Call = CallEnd->getOperand(0).getNode();
6999 bool hasGlue = Call->getGluedNode();
7001 // Replace the target specific call node with the patchable intrinsic.
7002 SmallVector<SDValue, 8> Ops;
7004 // Add the <id> and <numBytes> constants.
7005 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7006 Ops.push_back(DAG.getTargetConstant(
7007 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7008 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7009 Ops.push_back(DAG.getTargetConstant(
7010 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7012 // Assume that the Callee is a constant address.
7013 // FIXME: handle function symbols in the future.
7015 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7016 /*isTarget=*/true));
7018 // Adjust <numArgs> to account for any arguments that have been passed on the
7020 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7021 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7022 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7023 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7025 // Add the calling convention
7026 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7028 // Add the arguments we omitted previously. The register allocator should
7029 // place these in any free register.
7031 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7032 Ops.push_back(getValue(CI.getArgOperand(i)));
7034 // Push the arguments from the call instruction up to the register mask.
7035 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7036 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7039 // Push live variables for the stack map.
7040 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7042 // Push the register mask info.
7044 Ops.push_back(*(Call->op_end()-2));
7046 Ops.push_back(*(Call->op_end()-1));
7048 // Push the chain (this is originally the first operand of the call, but
7049 // becomes now the last or second to last operand).
7050 Ops.push_back(*(Call->op_begin()));
7052 // Push the glue flag (last operand).
7054 Ops.push_back(*(Call->op_end()-1));
7057 if (isAnyRegCC && hasDef) {
7058 // Create the return types based on the intrinsic definition
7059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7060 SmallVector<EVT, 3> ValueVTs;
7061 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7062 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7064 // There is always a chain and a glue type at the end
7065 ValueVTs.push_back(MVT::Other);
7066 ValueVTs.push_back(MVT::Glue);
7067 NodeTys = DAG.getVTList(ValueVTs);
7069 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7071 // Replace the target specific call node with a PATCHPOINT node.
7072 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7073 getCurSDLoc(), NodeTys, Ops);
7075 // Update the NodeMap.
7078 setValue(&CI, SDValue(MN, 0));
7080 setValue(&CI, Result.first);
7083 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7084 // call sequence. Furthermore the location of the chain and glue can change
7085 // when the AnyReg calling convention is used and the intrinsic returns a
7087 if (isAnyRegCC && hasDef) {
7088 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7089 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7090 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7092 DAG.ReplaceAllUsesWith(Call, MN);
7093 DAG.DeleteNode(Call);
7095 // Inform the Frame Information that we have a patchpoint in this function.
7096 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7099 /// Returns an AttributeSet representing the attributes applied to the return
7100 /// value of the given call.
7101 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7102 SmallVector<Attribute::AttrKind, 2> Attrs;
7104 Attrs.push_back(Attribute::SExt);
7106 Attrs.push_back(Attribute::ZExt);
7108 Attrs.push_back(Attribute::InReg);
7110 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7114 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7115 /// implementation, which just calls LowerCall.
7116 /// FIXME: When all targets are
7117 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7118 std::pair<SDValue, SDValue>
7119 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7120 // Handle the incoming return values from the call.
7122 Type *OrigRetTy = CLI.RetTy;
7123 SmallVector<EVT, 4> RetTys;
7124 SmallVector<uint64_t, 4> Offsets;
7125 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7127 SmallVector<ISD::OutputArg, 4> Outs;
7128 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7130 bool CanLowerReturn =
7131 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7132 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7134 SDValue DemoteStackSlot;
7135 int DemoteStackIdx = -100;
7136 if (!CanLowerReturn) {
7137 // FIXME: equivalent assert?
7138 // assert(!CS.hasInAllocaArgument() &&
7139 // "sret demotion is incompatible with inalloca");
7140 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7141 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7142 MachineFunction &MF = CLI.DAG.getMachineFunction();
7143 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7144 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7146 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7148 Entry.Node = DemoteStackSlot;
7149 Entry.Ty = StackSlotPtrType;
7150 Entry.isSExt = false;
7151 Entry.isZExt = false;
7152 Entry.isInReg = false;
7153 Entry.isSRet = true;
7154 Entry.isNest = false;
7155 Entry.isByVal = false;
7156 Entry.isReturned = false;
7157 Entry.Alignment = Align;
7158 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7159 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7161 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7163 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7164 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7165 for (unsigned i = 0; i != NumRegs; ++i) {
7166 ISD::InputArg MyFlags;
7167 MyFlags.VT = RegisterVT;
7169 MyFlags.Used = CLI.IsReturnValueUsed;
7171 MyFlags.Flags.setSExt();
7173 MyFlags.Flags.setZExt();
7175 MyFlags.Flags.setInReg();
7176 CLI.Ins.push_back(MyFlags);
7181 // Handle all of the outgoing arguments.
7183 CLI.OutVals.clear();
7184 ArgListTy &Args = CLI.getArgs();
7185 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7186 SmallVector<EVT, 4> ValueVTs;
7187 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7188 Type *FinalType = Args[i].Ty;
7189 if (Args[i].isByVal)
7190 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7191 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7192 FinalType, CLI.CallConv, CLI.IsVarArg);
7193 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7195 EVT VT = ValueVTs[Value];
7196 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7197 SDValue Op = SDValue(Args[i].Node.getNode(),
7198 Args[i].Node.getResNo() + Value);
7199 ISD::ArgFlagsTy Flags;
7200 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7206 if (Args[i].isInReg)
7210 if (Args[i].isByVal)
7212 if (Args[i].isInAlloca) {
7213 Flags.setInAlloca();
7214 // Set the byval flag for CCAssignFn callbacks that don't know about
7215 // inalloca. This way we can know how many bytes we should've allocated
7216 // and how many bytes a callee cleanup function will pop. If we port
7217 // inalloca to more targets, we'll have to add custom inalloca handling
7218 // in the various CC lowering callbacks.
7221 if (Args[i].isByVal || Args[i].isInAlloca) {
7222 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7223 Type *ElementTy = Ty->getElementType();
7224 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7225 // For ByVal, alignment should come from FE. BE will guess if this
7226 // info is not there but there are cases it cannot get right.
7227 unsigned FrameAlign;
7228 if (Args[i].Alignment)
7229 FrameAlign = Args[i].Alignment;
7231 FrameAlign = getByValTypeAlignment(ElementTy);
7232 Flags.setByValAlign(FrameAlign);
7236 if (NeedsRegBlock) {
7237 Flags.setInConsecutiveRegs();
7238 if (Value == NumValues - 1)
7239 Flags.setInConsecutiveRegsLast();
7241 Flags.setOrigAlign(OriginalAlignment);
7243 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7244 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7245 SmallVector<SDValue, 4> Parts(NumParts);
7246 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7249 ExtendKind = ISD::SIGN_EXTEND;
7250 else if (Args[i].isZExt)
7251 ExtendKind = ISD::ZERO_EXTEND;
7253 // Conservatively only handle 'returned' on non-vectors for now
7254 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7255 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7256 "unexpected use of 'returned'");
7257 // Before passing 'returned' to the target lowering code, ensure that
7258 // either the register MVT and the actual EVT are the same size or that
7259 // the return value and argument are extended in the same way; in these
7260 // cases it's safe to pass the argument register value unchanged as the
7261 // return register value (although it's at the target's option whether
7263 // TODO: allow code generation to take advantage of partially preserved
7264 // registers rather than clobbering the entire register when the
7265 // parameter extension method is not compatible with the return
7267 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7268 (ExtendKind != ISD::ANY_EXTEND &&
7269 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7270 Flags.setReturned();
7273 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7274 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7276 for (unsigned j = 0; j != NumParts; ++j) {
7277 // if it isn't first piece, alignment must be 1
7278 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7279 i < CLI.NumFixedArgs,
7280 i, j*Parts[j].getValueType().getStoreSize());
7281 if (NumParts > 1 && j == 0)
7282 MyFlags.Flags.setSplit();
7284 MyFlags.Flags.setOrigAlign(1);
7286 CLI.Outs.push_back(MyFlags);
7287 CLI.OutVals.push_back(Parts[j]);
7292 SmallVector<SDValue, 4> InVals;
7293 CLI.Chain = LowerCall(CLI, InVals);
7295 // Verify that the target's LowerCall behaved as expected.
7296 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7297 "LowerCall didn't return a valid chain!");
7298 assert((!CLI.IsTailCall || InVals.empty()) &&
7299 "LowerCall emitted a return value for a tail call!");
7300 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7301 "LowerCall didn't emit the correct number of values!");
7303 // For a tail call, the return value is merely live-out and there aren't
7304 // any nodes in the DAG representing it. Return a special value to
7305 // indicate that a tail call has been emitted and no more Instructions
7306 // should be processed in the current block.
7307 if (CLI.IsTailCall) {
7308 CLI.DAG.setRoot(CLI.Chain);
7309 return std::make_pair(SDValue(), SDValue());
7312 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7313 assert(InVals[i].getNode() &&
7314 "LowerCall emitted a null value!");
7315 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7316 "LowerCall emitted a value with the wrong type!");
7319 SmallVector<SDValue, 4> ReturnValues;
7320 if (!CanLowerReturn) {
7321 // The instruction result is the result of loading from the
7322 // hidden sret parameter.
7323 SmallVector<EVT, 1> PVTs;
7324 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7326 ComputeValueVTs(*this, PtrRetTy, PVTs);
7327 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7328 EVT PtrVT = PVTs[0];
7330 unsigned NumValues = RetTys.size();
7331 ReturnValues.resize(NumValues);
7332 SmallVector<SDValue, 4> Chains(NumValues);
7334 for (unsigned i = 0; i < NumValues; ++i) {
7335 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7336 CLI.DAG.getConstant(Offsets[i], PtrVT));
7337 SDValue L = CLI.DAG.getLoad(
7338 RetTys[i], CLI.DL, CLI.Chain, Add,
7339 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7341 ReturnValues[i] = L;
7342 Chains[i] = L.getValue(1);
7345 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7347 // Collect the legal value parts into potentially illegal values
7348 // that correspond to the original function's return values.
7349 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7351 AssertOp = ISD::AssertSext;
7352 else if (CLI.RetZExt)
7353 AssertOp = ISD::AssertZext;
7354 unsigned CurReg = 0;
7355 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7357 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7358 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7360 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7361 NumRegs, RegisterVT, VT, nullptr,
7366 // For a function returning void, there is no return value. We can't create
7367 // such a node, so we just return a null return value in that case. In
7368 // that case, nothing will actually look at the value.
7369 if (ReturnValues.empty())
7370 return std::make_pair(SDValue(), CLI.Chain);
7373 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7374 CLI.DAG.getVTList(RetTys), ReturnValues);
7375 return std::make_pair(Res, CLI.Chain);
7378 void TargetLowering::LowerOperationWrapper(SDNode *N,
7379 SmallVectorImpl<SDValue> &Results,
7380 SelectionDAG &DAG) const {
7381 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7383 Results.push_back(Res);
7386 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7387 llvm_unreachable("LowerOperation not implemented for this target!");
7391 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7392 SDValue Op = getNonRegisterValue(V);
7393 assert((Op.getOpcode() != ISD::CopyFromReg ||
7394 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7395 "Copy from a reg to the same reg!");
7396 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7398 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7399 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7400 SDValue Chain = DAG.getEntryNode();
7402 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7403 FuncInfo.PreferredExtendType.end())
7405 : FuncInfo.PreferredExtendType[V];
7406 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7407 PendingExports.push_back(Chain);
7410 #include "llvm/CodeGen/SelectionDAGISel.h"
7412 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7413 /// entry block, return true. This includes arguments used by switches, since
7414 /// the switch may expand into multiple basic blocks.
7415 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7416 // With FastISel active, we may be splitting blocks, so force creation
7417 // of virtual registers for all non-dead arguments.
7419 return A->use_empty();
7421 const BasicBlock *Entry = A->getParent()->begin();
7422 for (const User *U : A->users())
7423 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7424 return false; // Use not in entry block.
7429 void SelectionDAGISel::LowerArguments(const Function &F) {
7430 SelectionDAG &DAG = SDB->DAG;
7431 SDLoc dl = SDB->getCurSDLoc();
7432 const DataLayout *DL = TLI->getDataLayout();
7433 SmallVector<ISD::InputArg, 16> Ins;
7435 if (!FuncInfo->CanLowerReturn) {
7436 // Put in an sret pointer parameter before all the other parameters.
7437 SmallVector<EVT, 1> ValueVTs;
7438 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7440 // NOTE: Assuming that a pointer will never break down to more than one VT
7442 ISD::ArgFlagsTy Flags;
7444 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7445 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7446 Ins.push_back(RetArg);
7449 // Set up the incoming argument description vector.
7451 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7452 I != E; ++I, ++Idx) {
7453 SmallVector<EVT, 4> ValueVTs;
7454 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7455 bool isArgValueUsed = !I->use_empty();
7456 unsigned PartBase = 0;
7457 Type *FinalType = I->getType();
7458 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7459 FinalType = cast<PointerType>(FinalType)->getElementType();
7460 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7461 FinalType, F.getCallingConv(), F.isVarArg());
7462 for (unsigned Value = 0, NumValues = ValueVTs.size();
7463 Value != NumValues; ++Value) {
7464 EVT VT = ValueVTs[Value];
7465 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7466 ISD::ArgFlagsTy Flags;
7467 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7469 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7471 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7473 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7475 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7477 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7479 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7480 Flags.setInAlloca();
7481 // Set the byval flag for CCAssignFn callbacks that don't know about
7482 // inalloca. This way we can know how many bytes we should've allocated
7483 // and how many bytes a callee cleanup function will pop. If we port
7484 // inalloca to more targets, we'll have to add custom inalloca handling
7485 // in the various CC lowering callbacks.
7488 if (Flags.isByVal() || Flags.isInAlloca()) {
7489 PointerType *Ty = cast<PointerType>(I->getType());
7490 Type *ElementTy = Ty->getElementType();
7491 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7492 // For ByVal, alignment should be passed from FE. BE will guess if
7493 // this info is not there but there are cases it cannot get right.
7494 unsigned FrameAlign;
7495 if (F.getParamAlignment(Idx))
7496 FrameAlign = F.getParamAlignment(Idx);
7498 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7499 Flags.setByValAlign(FrameAlign);
7501 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7503 if (NeedsRegBlock) {
7504 Flags.setInConsecutiveRegs();
7505 if (Value == NumValues - 1)
7506 Flags.setInConsecutiveRegsLast();
7508 Flags.setOrigAlign(OriginalAlignment);
7510 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7511 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7512 for (unsigned i = 0; i != NumRegs; ++i) {
7513 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7514 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7515 if (NumRegs > 1 && i == 0)
7516 MyFlags.Flags.setSplit();
7517 // if it isn't first piece, alignment must be 1
7519 MyFlags.Flags.setOrigAlign(1);
7520 Ins.push_back(MyFlags);
7522 PartBase += VT.getStoreSize();
7526 // Call the target to set up the argument values.
7527 SmallVector<SDValue, 8> InVals;
7528 SDValue NewRoot = TLI->LowerFormalArguments(
7529 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7531 // Verify that the target's LowerFormalArguments behaved as expected.
7532 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7533 "LowerFormalArguments didn't return a valid chain!");
7534 assert(InVals.size() == Ins.size() &&
7535 "LowerFormalArguments didn't emit the correct number of values!");
7537 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7538 assert(InVals[i].getNode() &&
7539 "LowerFormalArguments emitted a null value!");
7540 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7541 "LowerFormalArguments emitted a value with the wrong type!");
7545 // Update the DAG with the new chain value resulting from argument lowering.
7546 DAG.setRoot(NewRoot);
7548 // Set up the argument values.
7551 if (!FuncInfo->CanLowerReturn) {
7552 // Create a virtual register for the sret pointer, and put in a copy
7553 // from the sret argument into it.
7554 SmallVector<EVT, 1> ValueVTs;
7555 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7556 MVT VT = ValueVTs[0].getSimpleVT();
7557 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7558 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7559 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7560 RegVT, VT, nullptr, AssertOp);
7562 MachineFunction& MF = SDB->DAG.getMachineFunction();
7563 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7564 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7565 FuncInfo->DemoteRegister = SRetReg;
7567 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7568 DAG.setRoot(NewRoot);
7570 // i indexes lowered arguments. Bump it past the hidden sret argument.
7571 // Idx indexes LLVM arguments. Don't touch it.
7575 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7577 SmallVector<SDValue, 4> ArgValues;
7578 SmallVector<EVT, 4> ValueVTs;
7579 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7580 unsigned NumValues = ValueVTs.size();
7582 // If this argument is unused then remember its value. It is used to generate
7583 // debugging information.
7584 if (I->use_empty() && NumValues) {
7585 SDB->setUnusedArgValue(I, InVals[i]);
7587 // Also remember any frame index for use in FastISel.
7588 if (FrameIndexSDNode *FI =
7589 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7590 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7593 for (unsigned Val = 0; Val != NumValues; ++Val) {
7594 EVT VT = ValueVTs[Val];
7595 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7596 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7598 if (!I->use_empty()) {
7599 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7600 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7601 AssertOp = ISD::AssertSext;
7602 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7603 AssertOp = ISD::AssertZext;
7605 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7606 NumParts, PartVT, VT,
7607 nullptr, AssertOp));
7613 // We don't need to do anything else for unused arguments.
7614 if (ArgValues.empty())
7617 // Note down frame index.
7618 if (FrameIndexSDNode *FI =
7619 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7620 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7622 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7623 SDB->getCurSDLoc());
7625 SDB->setValue(I, Res);
7626 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7627 if (LoadSDNode *LNode =
7628 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7629 if (FrameIndexSDNode *FI =
7630 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7631 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7634 // If this argument is live outside of the entry block, insert a copy from
7635 // wherever we got it to the vreg that other BB's will reference it as.
7636 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7637 // If we can, though, try to skip creating an unnecessary vreg.
7638 // FIXME: This isn't very clean... it would be nice to make this more
7639 // general. It's also subtly incompatible with the hacks FastISel
7641 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7642 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7643 FuncInfo->ValueMap[I] = Reg;
7647 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7648 FuncInfo->InitializeRegForValue(I);
7649 SDB->CopyToExportRegsIfNeeded(I);
7653 assert(i == InVals.size() && "Argument register count mismatch!");
7655 // Finally, if the target has anything special to do, allow it to do so.
7656 // FIXME: this should insert code into the DAG!
7657 EmitFunctionEntryCode();
7660 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7661 /// ensure constants are generated when needed. Remember the virtual registers
7662 /// that need to be added to the Machine PHI nodes as input. We cannot just
7663 /// directly add them, because expansion might result in multiple MBB's for one
7664 /// BB. As such, the start of the BB might correspond to a different MBB than
7668 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7669 const TerminatorInst *TI = LLVMBB->getTerminator();
7671 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7673 // Check successor nodes' PHI nodes that expect a constant to be available
7675 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7676 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7677 if (!isa<PHINode>(SuccBB->begin())) continue;
7678 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7680 // If this terminator has multiple identical successors (common for
7681 // switches), only handle each succ once.
7682 if (!SuccsHandled.insert(SuccMBB)) continue;
7684 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7686 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7687 // nodes and Machine PHI nodes, but the incoming operands have not been
7689 for (BasicBlock::const_iterator I = SuccBB->begin();
7690 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7691 // Ignore dead phi's.
7692 if (PN->use_empty()) continue;
7695 if (PN->getType()->isEmptyTy())
7699 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7701 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7702 unsigned &RegOut = ConstantsOut[C];
7704 RegOut = FuncInfo.CreateRegs(C->getType());
7705 CopyValueToVirtualRegister(C, RegOut);
7709 DenseMap<const Value *, unsigned>::iterator I =
7710 FuncInfo.ValueMap.find(PHIOp);
7711 if (I != FuncInfo.ValueMap.end())
7714 assert(isa<AllocaInst>(PHIOp) &&
7715 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7716 "Didn't codegen value into a register!??");
7717 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7718 CopyValueToVirtualRegister(PHIOp, Reg);
7722 // Remember that this register needs to added to the machine PHI node as
7723 // the input for this MBB.
7724 SmallVector<EVT, 4> ValueVTs;
7725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7726 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7727 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7728 EVT VT = ValueVTs[vti];
7729 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7730 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7731 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7732 Reg += NumRegisters;
7737 ConstantsOut.clear();
7740 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7743 SelectionDAGBuilder::StackProtectorDescriptor::
7744 AddSuccessorMBB(const BasicBlock *BB,
7745 MachineBasicBlock *ParentMBB,
7746 MachineBasicBlock *SuccMBB) {
7747 // If SuccBB has not been created yet, create it.
7749 MachineFunction *MF = ParentMBB->getParent();
7750 MachineFunction::iterator BBI = ParentMBB;
7751 SuccMBB = MF->CreateMachineBasicBlock(BB);
7752 MF->insert(++BBI, SuccMBB);
7754 // Add it as a successor of ParentMBB.
7755 ParentMBB->addSuccessor(SuccMBB);