1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
133 // If R is null, the sub-method took care of registering the result.
135 SetScalarizedVector(SDValue(N, ResNo), R);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
142 LHS.getValueType(), LHS, RHS);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
149 return DAG.getNode(N->getOpcode(), SDLoc(N),
150 Op0.getValueType(), Op0, Op1, Op2);
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
160 EVT NewVT = N->getValueType(0).getVectorElementType();
161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
162 NewVT, N->getOperand(0));
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
166 EVT EltVT = N->getValueType(0).getVectorElementType();
167 SDValue InOp = N->getOperand(0);
168 // The BUILD_VECTOR operands may be of wider element types and
169 // we may need to truncate them back to the requested return type.
170 if (EltVT.isInteger())
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
179 Op0, DAG.getValueType(NewVT),
180 DAG.getValueType(Op0.getValueType()),
183 cast<CvtRndSatSDNode>(N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
188 N->getValueType(0).getVectorElementType(),
189 N->getOperand(0), N->getOperand(1));
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
193 EVT NewVT = N->getValueType(0).getVectorElementType();
194 SDValue Op = GetScalarizedVector(N->getOperand(0));
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
196 NewVT, Op, N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
200 SDValue Op = GetScalarizedVector(N->getOperand(0));
201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
202 Op.getValueType(), Op, N->getOperand(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
206 // The value to insert may have a wider type than the vector element type,
207 // so be sure to truncate it to the element type if necessary.
208 SDValue Op = N->getOperand(1);
209 EVT EltVT = N->getValueType(0).getVectorElementType();
210 if (Op.getValueType() != EltVT)
211 // FIXME: Can this happen for floating point types?
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
217 assert(N->isUnindexed() && "Indexed vector load?");
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
220 N->getExtensionType(),
221 N->getValueType(0).getVectorElementType(),
223 N->getChain(), N->getBasePtr(),
224 DAG.getUNDEF(N->getBasePtr().getValueType()),
226 N->getMemoryVT().getVectorElementType(),
227 N->isVolatile(), N->isNonTemporal(),
228 N->isInvariant(), N->getOriginalAlignment(),
231 // Legalized the chain result - switch anything that used the old chain to
233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
239 EVT DestVT = N->getValueType(0).getVectorElementType();
240 SDValue Op = N->getOperand(0);
241 EVT OpVT = Op.getValueType();
243 // The result needs scalarizing, but it's not a given that the source does.
244 // This is a workaround for targets where it's impossible to scalarize the
245 // result of a conversion, because the source type is legal.
246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
248 // legal and was not scalarized.
249 // See the similar logic in ScalarizeVecRes_VSETCC
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
251 Op = GetScalarizedVector(Op);
253 EVT VT = OpVT.getVectorElementType();
254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
255 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
261 EVT EltVT = N->getValueType(0).getVectorElementType();
262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
265 LHS, DAG.getValueType(ExtVT));
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
269 // If the operand is wider than the vector element type then it is implicitly
270 // truncated. Make that explicit here.
271 EVT EltVT = N->getValueType(0).getVectorElementType();
272 SDValue InOp = N->getOperand(0);
273 if (InOp.getValueType() != EltVT)
274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
281 TargetLowering::BooleanContent ScalarBool =
282 TLI.getBooleanContents(false, false);
283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
285 // If integer and float booleans have different contents then we can't
286 // reliably optimize in all cases. There is a full explanation for this in
287 // DAGCombiner::visitSELECT() where the same issue affects folding
288 // (select C, 0, 1) to (xor C, 1).
289 if (TLI.getBooleanContents(false, false) !=
290 TLI.getBooleanContents(false, true)) {
291 // At least try the common case where the boolean is generated by a
293 if (Cond->getOpcode() == ISD::SETCC) {
294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
296 VecBool = TLI.getBooleanContents(OpVT);
298 ScalarBool = TargetLowering::UndefinedBooleanContent;
301 if (ScalarBool != VecBool) {
302 EVT CondVT = Cond.getValueType();
303 switch (ScalarBool) {
304 case TargetLowering::UndefinedBooleanContent:
306 case TargetLowering::ZeroOrOneBooleanContent:
307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
309 // Vector read from all ones, scalar expects a single 1 so mask.
310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
311 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
316 // Vector reads from a one, scalar from all ones so sign extend.
317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 Cond, DAG.getValueType(MVT::i1));
323 return DAG.getSelect(SDLoc(N),
324 LHS.getValueType(), Cond, LHS,
325 GetScalarizedVector(N->getOperand(2)));
328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
330 return DAG.getSelect(SDLoc(N),
331 LHS.getValueType(), N->getOperand(0), LHS,
332 GetScalarizedVector(N->getOperand(2)));
335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
338 N->getOperand(0), N->getOperand(1),
339 LHS, GetScalarizedVector(N->getOperand(3)),
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
344 assert(N->getValueType(0).isVector() ==
345 N->getOperand(0).getValueType().isVector() &&
346 "Scalar/Vector type mismatch");
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
354 // Turn it into a scalar SETCC.
355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
363 // Figure out if the scalar is the LHS or RHS and return it.
364 SDValue Arg = N->getOperand(2).getOperand(0);
365 if (Arg.getOpcode() == ISD::UNDEF)
366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
368 return GetScalarizedVector(N->getOperand(Op));
371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
372 assert(N->getValueType(0).isVector() &&
373 N->getOperand(0).getValueType().isVector() &&
374 "Operand types must be vectors");
375 SDValue LHS = N->getOperand(0);
376 SDValue RHS = N->getOperand(1);
377 EVT OpVT = LHS.getValueType();
378 EVT NVT = N->getValueType(0).getVectorElementType();
381 // The result needs scalarizing, but it's not a given that the source does.
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
383 LHS = GetScalarizedVector(LHS);
384 RHS = GetScalarizedVector(RHS);
386 EVT VT = OpVT.getVectorElementType();
387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
388 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
390 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
393 // Turn it into a scalar SETCC.
394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
396 // Vectors may have a different boolean contents to scalars. Promote the
397 // value appropriately.
398 ISD::NodeType ExtendCode =
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
400 return DAG.getNode(ExtendCode, DL, NVT, Res);
404 //===----------------------------------------------------------------------===//
405 // Operand Vector Scalarization <1 x ty> -> ty.
406 //===----------------------------------------------------------------------===//
408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
412 SDValue Res = SDValue();
414 if (!Res.getNode()) {
415 switch (N->getOpcode()) {
418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
424 Res = ScalarizeVecOp_BITCAST(N);
426 case ISD::ANY_EXTEND:
427 case ISD::ZERO_EXTEND:
428 case ISD::SIGN_EXTEND:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
434 Res = ScalarizeVecOp_UnaryOp(N);
436 case ISD::CONCAT_VECTORS:
437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
439 case ISD::EXTRACT_VECTOR_ELT:
440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
443 Res = ScalarizeVecOp_VSELECT(N);
446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
454 // If the result is null, the sub-method took care of registering results etc.
455 if (!Res.getNode()) return false;
457 // If the result is N, the sub-method updated N in place. Tell the legalizer
459 if (Res.getNode() == N)
462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
463 "Invalid operand expansion");
465 ReplaceValueWith(SDValue(N, 0), Res);
469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
474 N->getValueType(0), Elt);
477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
481 "Unexpected vector type!");
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
484 N->getValueType(0).getScalarType(), Elt);
485 // Revectorize the result so the types line up with what the uses of this
486 // expression expect.
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
491 /// use a BUILD_VECTOR instead.
492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
495 Ops[i] = GetScalarizedVector(N->getOperand(i));
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
503 SDValue Res = GetScalarizedVector(N->getOperand(0));
504 if (Res.getValueType() != N->getValueType(0))
505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
513 /// (still with vector output type since that was acceptable if we got here).
514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
516 EVT VT = N->getValueType(0);
518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
523 /// scalarized, it must be <1 x ty>. Just store the element.
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
529 if (N->isTruncatingStore())
530 return DAG.getTruncStore(N->getChain(), dl,
531 GetScalarizedVector(N->getOperand(1)),
532 N->getBasePtr(), N->getPointerInfo(),
533 N->getMemoryVT().getVectorElementType(),
534 N->isVolatile(), N->isNonTemporal(),
535 N->getAlignment(), N->getAAInfo());
537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getOriginalAlignment(), N->getAAInfo());
543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
548 N->getValueType(0).getVectorElementType(), Elt,
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
553 //===----------------------------------------------------------------------===//
554 // Result Vector Splitting
555 //===----------------------------------------------------------------------===//
557 /// SplitVectorResult - This method is called when the specified result of the
558 /// specified node is found to need vector splitting. At this point, the node
559 /// may also have invalid operands or may have other results that need
560 /// legalization, we just know that (at least) one result needs vector
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
563 DEBUG(dbgs() << "Split node result: ";
568 // See if the target wants to custom expand this node.
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
572 switch (N->getOpcode()) {
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
579 report_fatal_error("Do not know how to split the result of this "
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
604 SplitVecRes_SETCC(N, Lo, Hi);
606 case ISD::VECTOR_SHUFFLE:
607 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
611 case ISD::CONVERT_RNDSAT:
614 case ISD::CTLZ_ZERO_UNDEF:
615 case ISD::CTTZ_ZERO_UNDEF:
626 case ISD::FNEARBYINT:
630 case ISD::FP_TO_SINT:
631 case ISD::FP_TO_UINT:
637 case ISD::SINT_TO_FP:
639 case ISD::UINT_TO_FP:
640 SplitVecRes_UnaryOp(N, Lo, Hi);
643 case ISD::ANY_EXTEND:
644 case ISD::SIGN_EXTEND:
645 case ISD::ZERO_EXTEND:
646 SplitVecRes_ExtendOp(N, Lo, Hi);
671 SplitVecRes_BinOp(N, Lo, Hi);
674 SplitVecRes_TernaryOp(N, Lo, Hi);
678 // If Lo/Hi is null, the sub-method took care of registering results etc.
680 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
683 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
685 SDValue LHSLo, LHSHi;
686 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
687 SDValue RHSLo, RHSHi;
688 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
691 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
692 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
695 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
697 SDValue Op0Lo, Op0Hi;
698 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
699 SDValue Op1Lo, Op1Hi;
700 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
701 SDValue Op2Lo, Op2Hi;
702 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
705 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
706 Op0Lo, Op1Lo, Op2Lo);
707 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
708 Op0Hi, Op1Hi, Op2Hi);
711 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
713 // We know the result is a vector. The input may be either a vector or a
716 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
719 SDValue InOp = N->getOperand(0);
720 EVT InVT = InOp.getValueType();
722 // Handle some special cases efficiently.
723 switch (getTypeAction(InVT)) {
724 case TargetLowering::TypeLegal:
725 case TargetLowering::TypePromoteInteger:
726 case TargetLowering::TypePromoteFloat:
727 case TargetLowering::TypeSoftenFloat:
728 case TargetLowering::TypeScalarizeVector:
729 case TargetLowering::TypeWidenVector:
731 case TargetLowering::TypeExpandInteger:
732 case TargetLowering::TypeExpandFloat:
733 // A scalar to vector conversion, where the scalar needs expansion.
734 // If the vector is being split in two then we can just convert the
737 GetExpandedOp(InOp, Lo, Hi);
738 if (TLI.isBigEndian())
740 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
741 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
745 case TargetLowering::TypeSplitVector:
746 // If the input is a vector that needs to be split, convert each split
747 // piece of the input now.
748 GetSplitVector(InOp, Lo, Hi);
749 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
750 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
754 // In the general case, convert the input to an integer and split it by hand.
755 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
756 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
757 if (TLI.isBigEndian())
758 std::swap(LoIntVT, HiIntVT);
760 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
762 if (TLI.isBigEndian())
764 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
765 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
768 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
772 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
773 unsigned LoNumElts = LoVT.getVectorNumElements();
774 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
775 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
777 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
778 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
781 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
783 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
785 unsigned NumSubvectors = N->getNumOperands() / 2;
786 if (NumSubvectors == 1) {
787 Lo = N->getOperand(0);
788 Hi = N->getOperand(1);
793 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
795 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
796 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
798 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
799 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
802 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
804 SDValue Vec = N->getOperand(0);
805 SDValue Idx = N->getOperand(1);
809 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
811 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
812 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
813 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
814 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
815 TLI.getVectorIdxTy()));
818 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
820 SDValue Vec = N->getOperand(0);
821 SDValue SubVec = N->getOperand(1);
822 SDValue Idx = N->getOperand(2);
824 GetSplitVector(Vec, Lo, Hi);
826 // Spill the vector to the stack.
827 EVT VecVT = Vec.getValueType();
828 EVT SubVecVT = VecVT.getVectorElementType();
829 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
830 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
831 MachinePointerInfo(), false, false, 0);
833 // Store the new subvector into the specified index.
834 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
835 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
836 unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
837 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
840 // Load the Lo part from the stack slot.
841 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
842 false, false, false, 0);
844 // Increment the pointer to the other part.
845 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
847 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
848 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
850 // Load the Hi part from the stack slot.
851 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
852 false, false, false, MinAlign(Alignment, IncrementSize));
855 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
858 GetSplitVector(N->getOperand(0), Lo, Hi);
859 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
860 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
863 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
865 SDValue LHSLo, LHSHi;
866 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
870 std::tie(LoVT, HiVT) =
871 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
873 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
874 DAG.getValueType(LoVT));
875 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
876 DAG.getValueType(HiVT));
879 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
881 SDValue Vec = N->getOperand(0);
882 SDValue Elt = N->getOperand(1);
883 SDValue Idx = N->getOperand(2);
885 GetSplitVector(Vec, Lo, Hi);
887 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
888 unsigned IdxVal = CIdx->getZExtValue();
889 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
890 if (IdxVal < LoNumElts)
891 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
892 Lo.getValueType(), Lo, Elt, Idx);
894 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
895 DAG.getConstant(IdxVal - LoNumElts, dl,
896 TLI.getVectorIdxTy()));
900 // See if the target wants to custom expand this node.
901 if (CustomLowerNode(N, N->getValueType(0), true))
904 // Spill the vector to the stack.
905 EVT VecVT = Vec.getValueType();
906 EVT EltVT = VecVT.getVectorElementType();
907 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
908 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
909 MachinePointerInfo(), false, false, 0);
911 // Store the new element. This may be larger than the vector element type,
912 // so use a truncating store.
913 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
914 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
916 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
917 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
920 // Load the Lo part from the stack slot.
921 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
922 false, false, false, 0);
924 // Increment the pointer to the other part.
925 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
926 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
927 DAG.getConstant(IncrementSize, dl,
928 StackPtr.getValueType()));
930 // Load the Hi part from the stack slot.
931 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
932 false, false, false, MinAlign(Alignment, IncrementSize));
935 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
939 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
940 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
941 Hi = DAG.getUNDEF(HiVT);
944 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
946 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
949 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
951 ISD::LoadExtType ExtType = LD->getExtensionType();
952 SDValue Ch = LD->getChain();
953 SDValue Ptr = LD->getBasePtr();
954 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
955 EVT MemoryVT = LD->getMemoryVT();
956 unsigned Alignment = LD->getOriginalAlignment();
957 bool isVolatile = LD->isVolatile();
958 bool isNonTemporal = LD->isNonTemporal();
959 bool isInvariant = LD->isInvariant();
960 AAMDNodes AAInfo = LD->getAAInfo();
962 EVT LoMemVT, HiMemVT;
963 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
965 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
966 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
967 isInvariant, Alignment, AAInfo);
969 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
970 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
971 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
972 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
973 LD->getPointerInfo().getWithOffset(IncrementSize),
974 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
977 // Build a factor node to remember that this load is independent of the
979 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
982 // Legalized the chain result - switch anything that used the old chain to
984 ReplaceValueWith(SDValue(LD, 1), Ch);
987 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
988 SDValue &Lo, SDValue &Hi) {
991 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
993 SDValue Ch = MLD->getChain();
994 SDValue Ptr = MLD->getBasePtr();
995 SDValue Mask = MLD->getMask();
996 unsigned Alignment = MLD->getOriginalAlignment();
997 ISD::LoadExtType ExtType = MLD->getExtensionType();
999 // if Alignment is equal to the vector size,
1000 // take the half of it for the second part
1001 unsigned SecondHalfAlignment =
1002 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1003 Alignment/2 : Alignment;
1005 SDValue MaskLo, MaskHi;
1006 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1008 EVT MemoryVT = MLD->getMemoryVT();
1009 EVT LoMemVT, HiMemVT;
1010 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1012 SDValue Src0 = MLD->getSrc0();
1013 SDValue Src0Lo, Src0Hi;
1014 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1016 MachineMemOperand *MMO = DAG.getMachineFunction().
1017 getMachineMemOperand(MLD->getPointerInfo(),
1018 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1019 Alignment, MLD->getAAInfo(), MLD->getRanges());
1021 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1024 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1025 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1026 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1028 MMO = DAG.getMachineFunction().
1029 getMachineMemOperand(MLD->getPointerInfo(),
1030 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1031 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1033 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1037 // Build a factor node to remember that this load is independent of the
1039 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1042 // Legalized the chain result - switch anything that used the old chain to
1044 ReplaceValueWith(SDValue(MLD, 1), Ch);
1048 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1049 assert(N->getValueType(0).isVector() &&
1050 N->getOperand(0).getValueType().isVector() &&
1051 "Operand types must be vectors");
1055 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1058 SDValue LL, LH, RL, RH;
1059 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1060 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1062 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1063 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1066 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1068 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1071 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1073 // If the input also splits, handle it directly for a compile time speedup.
1074 // Otherwise split it by hand.
1075 EVT InVT = N->getOperand(0).getValueType();
1076 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1077 GetSplitVector(N->getOperand(0), Lo, Hi);
1079 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1081 if (N->getOpcode() == ISD::FP_ROUND) {
1082 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1083 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1084 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1085 SDValue DTyOpLo = DAG.getValueType(LoVT);
1086 SDValue DTyOpHi = DAG.getValueType(HiVT);
1087 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1088 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1089 SDValue RndOp = N->getOperand(3);
1090 SDValue SatOp = N->getOperand(4);
1091 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1092 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1094 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1097 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1098 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1102 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1105 EVT SrcVT = N->getOperand(0).getValueType();
1106 EVT DestVT = N->getValueType(0);
1108 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1110 // We can do better than a generic split operation if the extend is doing
1111 // more than just doubling the width of the elements and the following are
1113 // - The number of vector elements is even,
1114 // - the source type is legal,
1115 // - the type of a split source is illegal,
1116 // - the type of an extended (by doubling element size) source is legal, and
1117 // - the type of that extended source when split is legal.
1119 // This won't necessarily completely legalize the operation, but it will
1120 // more effectively move in the right direction and prevent falling down
1121 // to scalarization in many cases due to the input vector being split too
1123 unsigned NumElements = SrcVT.getVectorNumElements();
1124 if ((NumElements & 1) == 0 &&
1125 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1126 LLVMContext &Ctx = *DAG.getContext();
1127 EVT NewSrcVT = EVT::getVectorVT(
1128 Ctx, EVT::getIntegerVT(
1129 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1132 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1133 EVT SplitLoVT, SplitHiVT;
1134 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1135 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1136 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1137 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1138 N->dump(&DAG); dbgs() << "\n");
1139 // Extend the source vector by one step.
1141 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1142 // Get the low and high halves of the new, extended one step, vector.
1143 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1144 // Extend those vector halves the rest of the way.
1145 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1146 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1150 // Fall back to the generic unary operator splitting otherwise.
1151 SplitVecRes_UnaryOp(N, Lo, Hi);
1154 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1155 SDValue &Lo, SDValue &Hi) {
1156 // The low and high parts of the original input give four input vectors.
1159 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1160 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1161 EVT NewVT = Inputs[0].getValueType();
1162 unsigned NewElts = NewVT.getVectorNumElements();
1164 // If Lo or Hi uses elements from at most two of the four input vectors, then
1165 // express it as a vector shuffle of those two inputs. Otherwise extract the
1166 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1167 SmallVector<int, 16> Ops;
1168 for (unsigned High = 0; High < 2; ++High) {
1169 SDValue &Output = High ? Hi : Lo;
1171 // Build a shuffle mask for the output, discovering on the fly which
1172 // input vectors to use as shuffle operands (recorded in InputUsed).
1173 // If building a suitable shuffle vector proves too hard, then bail
1174 // out with useBuildVector set.
1175 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1176 unsigned FirstMaskIdx = High * NewElts;
1177 bool useBuildVector = false;
1178 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1179 // The mask element. This indexes into the input.
1180 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1182 // The input vector this mask element indexes into.
1183 unsigned Input = (unsigned)Idx / NewElts;
1185 if (Input >= array_lengthof(Inputs)) {
1186 // The mask element does not index into any input vector.
1191 // Turn the index into an offset from the start of the input vector.
1192 Idx -= Input * NewElts;
1194 // Find or create a shuffle vector operand to hold this input.
1196 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1197 if (InputUsed[OpNo] == Input) {
1198 // This input vector is already an operand.
1200 } else if (InputUsed[OpNo] == -1U) {
1201 // Create a new operand for this input vector.
1202 InputUsed[OpNo] = Input;
1207 if (OpNo >= array_lengthof(InputUsed)) {
1208 // More than two input vectors used! Give up on trying to create a
1209 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1210 useBuildVector = true;
1214 // Add the mask index for the new shuffle vector.
1215 Ops.push_back(Idx + OpNo * NewElts);
1218 if (useBuildVector) {
1219 EVT EltVT = NewVT.getVectorElementType();
1220 SmallVector<SDValue, 16> SVOps;
1222 // Extract the input elements by hand.
1223 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1224 // The mask element. This indexes into the input.
1225 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1227 // The input vector this mask element indexes into.
1228 unsigned Input = (unsigned)Idx / NewElts;
1230 if (Input >= array_lengthof(Inputs)) {
1231 // The mask element is "undef" or indexes off the end of the input.
1232 SVOps.push_back(DAG.getUNDEF(EltVT));
1236 // Turn the index into an offset from the start of the input vector.
1237 Idx -= Input * NewElts;
1239 // Extract the vector element by hand.
1240 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1242 DAG.getConstant(Idx, dl,
1243 TLI.getVectorIdxTy())));
1246 // Construct the Lo/Hi output using a BUILD_VECTOR.
1247 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1248 } else if (InputUsed[0] == -1U) {
1249 // No input vectors were used! The result is undefined.
1250 Output = DAG.getUNDEF(NewVT);
1252 SDValue Op0 = Inputs[InputUsed[0]];
1253 // If only one input was used, use an undefined vector for the other.
1254 SDValue Op1 = InputUsed[1] == -1U ?
1255 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1256 // At least one input vector was used. Create a new shuffle vector.
1257 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1265 //===----------------------------------------------------------------------===//
1266 // Operand Vector Splitting
1267 //===----------------------------------------------------------------------===//
1269 /// SplitVectorOperand - This method is called when the specified operand of the
1270 /// specified node is found to need vector splitting. At this point, all of the
1271 /// result types of the node are known to be legal, but other operands of the
1272 /// node may need legalization as well as the specified one.
1273 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1274 DEBUG(dbgs() << "Split node operand: ";
1277 SDValue Res = SDValue();
1279 // See if the target wants to custom split this node.
1280 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1283 if (!Res.getNode()) {
1284 switch (N->getOpcode()) {
1287 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1291 report_fatal_error("Do not know how to split this operator's "
1294 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1295 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1296 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1297 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1298 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1300 Res = SplitVecOp_TruncateHelper(N);
1302 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1304 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1307 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1310 Res = SplitVecOp_VSELECT(N, OpNo);
1312 case ISD::FP_TO_SINT:
1313 case ISD::FP_TO_UINT:
1314 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1315 Res = SplitVecOp_TruncateHelper(N);
1317 Res = SplitVecOp_UnaryOp(N);
1319 case ISD::SINT_TO_FP:
1320 case ISD::UINT_TO_FP:
1321 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1322 Res = SplitVecOp_TruncateHelper(N);
1324 Res = SplitVecOp_UnaryOp(N);
1329 case ISD::FP_EXTEND:
1330 case ISD::SIGN_EXTEND:
1331 case ISD::ZERO_EXTEND:
1332 case ISD::ANY_EXTEND:
1334 Res = SplitVecOp_UnaryOp(N);
1339 // If the result is null, the sub-method took care of registering results etc.
1340 if (!Res.getNode()) return false;
1342 // If the result is N, the sub-method updated N in place. Tell the legalizer
1344 if (Res.getNode() == N)
1347 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1348 "Invalid operand expansion");
1350 ReplaceValueWith(SDValue(N, 0), Res);
1354 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1355 // The only possibility for an illegal operand is the mask, since result type
1356 // legalization would have handled this node already otherwise.
1357 assert(OpNo == 0 && "Illegal operand must be mask");
1359 SDValue Mask = N->getOperand(0);
1360 SDValue Src0 = N->getOperand(1);
1361 SDValue Src1 = N->getOperand(2);
1362 EVT Src0VT = Src0.getValueType();
1364 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1367 GetSplitVector(N->getOperand(0), Lo, Hi);
1368 assert(Lo.getValueType() == Hi.getValueType() &&
1369 "Lo and Hi have differing types");
1372 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1373 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1375 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1376 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1377 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1378 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1381 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1383 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1385 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1388 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1389 // The result has a legal vector type, but the input needs splitting.
1390 EVT ResVT = N->getValueType(0);
1393 GetSplitVector(N->getOperand(0), Lo, Hi);
1394 EVT InVT = Lo.getValueType();
1396 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1397 InVT.getVectorNumElements());
1399 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1400 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1402 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1405 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1406 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1407 // end up being split all the way down to individual components. Convert the
1408 // split pieces into integers and reassemble.
1410 GetSplitVector(N->getOperand(0), Lo, Hi);
1411 Lo = BitConvertToInteger(Lo);
1412 Hi = BitConvertToInteger(Hi);
1414 if (TLI.isBigEndian())
1417 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1418 JoinIntegers(Lo, Hi));
1421 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1422 // We know that the extracted result type is legal.
1423 EVT SubVT = N->getValueType(0);
1424 SDValue Idx = N->getOperand(1);
1427 GetSplitVector(N->getOperand(0), Lo, Hi);
1429 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1430 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1432 if (IdxVal < LoElts) {
1433 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1434 "Extracted subvector crosses vector split!");
1435 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1437 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1438 DAG.getConstant(IdxVal - LoElts, dl,
1439 Idx.getValueType()));
1443 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1444 SDValue Vec = N->getOperand(0);
1445 SDValue Idx = N->getOperand(1);
1446 EVT VecVT = Vec.getValueType();
1448 if (isa<ConstantSDNode>(Idx)) {
1449 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1450 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1453 GetSplitVector(Vec, Lo, Hi);
1455 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1457 if (IdxVal < LoElts)
1458 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1459 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1460 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1461 Idx.getValueType())), 0);
1464 // See if the target wants to custom expand this node.
1465 if (CustomLowerNode(N, N->getValueType(0), true))
1468 // Store the vector to the stack.
1469 EVT EltVT = VecVT.getVectorElementType();
1471 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1472 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1473 MachinePointerInfo(), false, false, 0);
1475 // Load back the required element.
1476 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1477 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1478 MachinePointerInfo(), EltVT, false, false, false, 0);
1481 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1483 SDValue Ch = N->getChain();
1484 SDValue Ptr = N->getBasePtr();
1485 SDValue Mask = N->getMask();
1486 SDValue Data = N->getValue();
1487 EVT MemoryVT = N->getMemoryVT();
1488 unsigned Alignment = N->getOriginalAlignment();
1491 EVT LoMemVT, HiMemVT;
1492 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1494 SDValue DataLo, DataHi;
1495 GetSplitVector(Data, DataLo, DataHi);
1496 SDValue MaskLo, MaskHi;
1497 GetSplitVector(Mask, MaskLo, MaskHi);
1499 // if Alignment is equal to the vector size,
1500 // take the half of it for the second part
1501 unsigned SecondHalfAlignment =
1502 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1503 Alignment/2 : Alignment;
1506 MachineMemOperand *MMO = DAG.getMachineFunction().
1507 getMachineMemOperand(N->getPointerInfo(),
1508 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1509 Alignment, N->getAAInfo(), N->getRanges());
1511 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1512 N->isTruncatingStore());
1514 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1515 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1516 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1518 MMO = DAG.getMachineFunction().
1519 getMachineMemOperand(N->getPointerInfo(),
1520 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1521 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1523 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1524 N->isTruncatingStore());
1527 // Build a factor node to remember that this store is independent of the
1529 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1533 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1534 assert(N->isUnindexed() && "Indexed store of vector?");
1535 assert(OpNo == 1 && "Can only split the stored value");
1538 bool isTruncating = N->isTruncatingStore();
1539 SDValue Ch = N->getChain();
1540 SDValue Ptr = N->getBasePtr();
1541 EVT MemoryVT = N->getMemoryVT();
1542 unsigned Alignment = N->getOriginalAlignment();
1543 bool isVol = N->isVolatile();
1544 bool isNT = N->isNonTemporal();
1545 AAMDNodes AAInfo = N->getAAInfo();
1547 GetSplitVector(N->getOperand(1), Lo, Hi);
1549 EVT LoMemVT, HiMemVT;
1550 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1552 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1555 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1556 LoMemVT, isVol, isNT, Alignment, AAInfo);
1558 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1559 isVol, isNT, Alignment, AAInfo);
1561 // Increment the pointer to the other half.
1562 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1563 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1566 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1567 N->getPointerInfo().getWithOffset(IncrementSize),
1568 HiMemVT, isVol, isNT, Alignment, AAInfo);
1570 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1571 N->getPointerInfo().getWithOffset(IncrementSize),
1572 isVol, isNT, Alignment, AAInfo);
1574 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1577 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1580 // The input operands all must have the same type, and we know the result
1581 // type is valid. Convert this to a buildvector which extracts all the
1583 // TODO: If the input elements are power-two vectors, we could convert this to
1584 // a new CONCAT_VECTORS node with elements that are half-wide.
1585 SmallVector<SDValue, 32> Elts;
1586 EVT EltVT = N->getValueType(0).getVectorElementType();
1587 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1588 SDValue Op = N->getOperand(op);
1589 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1591 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1592 Op, DAG.getConstant(i, DL, TLI.getVectorIdxTy())));
1597 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1600 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1601 // The result type is legal, but the input type is illegal. If splitting
1602 // ends up with the result type of each half still being legal, just
1603 // do that. If, however, that would result in an illegal result type,
1604 // we can try to get more clever with power-two vectors. Specifically,
1605 // split the input type, but also widen the result element size, then
1606 // concatenate the halves and truncate again. For example, consider a target
1607 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1608 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1609 // %inlo = v4i32 extract_subvector %in, 0
1610 // %inhi = v4i32 extract_subvector %in, 4
1611 // %lo16 = v4i16 trunc v4i32 %inlo
1612 // %hi16 = v4i16 trunc v4i32 %inhi
1613 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1614 // %res = v8i8 trunc v8i16 %in16
1616 // Without this transform, the original truncate would end up being
1617 // scalarized, which is pretty much always a last resort.
1618 SDValue InVec = N->getOperand(0);
1619 EVT InVT = InVec->getValueType(0);
1620 EVT OutVT = N->getValueType(0);
1621 unsigned NumElements = OutVT.getVectorNumElements();
1622 bool IsFloat = OutVT.isFloatingPoint();
1624 // Widening should have already made sure this is a power-two vector
1625 // if we're trying to split it at all. assert() that's true, just in case.
1626 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1628 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1629 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1631 // If the input elements are only 1/2 the width of the result elements,
1632 // just use the normal splitting. Our trick only work if there's room
1633 // to split more than once.
1634 if (InElementSize <= OutElementSize * 2)
1635 return SplitVecOp_UnaryOp(N);
1638 // Extract the halves of the input via extract_subvector.
1639 SDValue InLoVec, InHiVec;
1640 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1641 // Truncate them to 1/2 the element size.
1642 EVT HalfElementVT = IsFloat ?
1643 EVT::getFloatingPointVT(InElementSize/2) :
1644 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1645 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1647 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1648 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1649 // Concatenate them to get the full intermediate truncation result.
1650 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1651 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1653 // Now finish up by truncating all the way down to the original result
1654 // type. This should normally be something that ends up being legal directly,
1655 // but in theory if a target has very wide vectors and an annoyingly
1656 // restricted set of legal types, this split can chain to build things up.
1658 DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1659 DAG.getTargetConstant(0, DL, TLI.getPointerTy())) :
1660 DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1663 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1664 assert(N->getValueType(0).isVector() &&
1665 N->getOperand(0).getValueType().isVector() &&
1666 "Operand types must be vectors");
1667 // The result has a legal vector type, but the input needs splitting.
1668 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1670 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1671 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1672 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1673 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1674 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1676 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1677 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1678 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1679 return PromoteTargetBoolean(Con, N->getValueType(0));
1683 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1684 // The result has a legal vector type, but the input needs splitting.
1685 EVT ResVT = N->getValueType(0);
1688 GetSplitVector(N->getOperand(0), Lo, Hi);
1689 EVT InVT = Lo.getValueType();
1691 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1692 InVT.getVectorNumElements());
1694 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1695 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1697 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1702 //===----------------------------------------------------------------------===//
1703 // Result Vector Widening
1704 //===----------------------------------------------------------------------===//
1706 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1707 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1711 // See if the target wants to custom widen this node.
1712 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1715 SDValue Res = SDValue();
1716 switch (N->getOpcode()) {
1719 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1723 llvm_unreachable("Do not know how to widen the result of this operator!");
1725 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1726 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1727 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1728 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1729 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1730 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1731 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1732 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1733 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1734 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1735 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1737 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1738 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1739 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1740 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1741 case ISD::VECTOR_SHUFFLE:
1742 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1745 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1758 Res = WidenVecRes_Binary(N);
1762 case ISD::FCOPYSIGN:
1772 Res = WidenVecRes_BinaryCanTrap(N);
1776 Res = WidenVecRes_POWI(N);
1782 Res = WidenVecRes_Shift(N);
1785 case ISD::ANY_EXTEND:
1786 case ISD::FP_EXTEND:
1788 case ISD::FP_TO_SINT:
1789 case ISD::FP_TO_UINT:
1790 case ISD::SIGN_EXTEND:
1791 case ISD::SINT_TO_FP:
1793 case ISD::UINT_TO_FP:
1794 case ISD::ZERO_EXTEND:
1795 Res = WidenVecRes_Convert(N);
1811 case ISD::FNEARBYINT:
1818 Res = WidenVecRes_Unary(N);
1821 Res = WidenVecRes_Ternary(N);
1825 // If Res is null, the sub-method took care of registering the result.
1827 SetWidenedVector(SDValue(N, ResNo), Res);
1830 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
1831 // Ternary op widening.
1833 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1834 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1835 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1836 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
1837 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
1840 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1841 // Binary op widening.
1843 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1844 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1845 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1846 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1849 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
1850 // Binary op widening for operations that can trap.
1851 unsigned Opcode = N->getOpcode();
1853 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1854 EVT WidenEltVT = WidenVT.getVectorElementType();
1856 unsigned NumElts = VT.getVectorNumElements();
1857 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1858 NumElts = NumElts / 2;
1859 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1862 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1863 // Operation doesn't trap so just widen as normal.
1864 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1865 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1866 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1869 // No legal vector version so unroll the vector operation and then widen.
1871 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1873 // Since the operation can trap, apply operation on the original vector.
1875 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1876 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1877 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1879 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1880 unsigned ConcatEnd = 0; // Current ConcatOps index.
1881 int Idx = 0; // Current Idx into input vectors.
1883 // NumElts := greatest legal vector size (at most WidenVT)
1884 // while (orig. vector has unhandled elements) {
1885 // take munches of size NumElts from the beginning and add to ConcatOps
1886 // NumElts := next smaller supported vector size or 1
1888 while (CurNumElts != 0) {
1889 while (CurNumElts >= NumElts) {
1890 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1891 DAG.getConstant(Idx, dl,
1892 TLI.getVectorIdxTy()));
1893 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1894 DAG.getConstant(Idx, dl,
1895 TLI.getVectorIdxTy()));
1896 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1898 CurNumElts -= NumElts;
1901 NumElts = NumElts / 2;
1902 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1903 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1906 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1907 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1909 DAG.getConstant(Idx, dl,
1910 TLI.getVectorIdxTy()));
1911 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1913 DAG.getConstant(Idx, dl,
1914 TLI.getVectorIdxTy()));
1915 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1922 // Check to see if we have a single operation with the widen type.
1923 if (ConcatEnd == 1) {
1924 VT = ConcatOps[0].getValueType();
1926 return ConcatOps[0];
1929 // while (Some element of ConcatOps is not of type MaxVT) {
1930 // From the end of ConcatOps, collect elements of the same type and put
1931 // them into an op of the next larger supported type
1933 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1934 Idx = ConcatEnd - 1;
1935 VT = ConcatOps[Idx--].getValueType();
1936 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1939 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1943 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1944 } while (!TLI.isTypeLegal(NextVT));
1946 if (!VT.isVector()) {
1947 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1948 SDValue VecOp = DAG.getUNDEF(NextVT);
1949 unsigned NumToInsert = ConcatEnd - Idx - 1;
1950 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1951 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1953 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
1955 ConcatOps[Idx+1] = VecOp;
1956 ConcatEnd = Idx + 2;
1958 // Vector type, create a CONCAT_VECTORS of type NextVT
1959 SDValue undefVec = DAG.getUNDEF(VT);
1960 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1961 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1962 unsigned RealVals = ConcatEnd - Idx - 1;
1963 unsigned SubConcatEnd = 0;
1964 unsigned SubConcatIdx = Idx + 1;
1965 while (SubConcatEnd < RealVals)
1966 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1967 while (SubConcatEnd < OpsToConcat)
1968 SubConcatOps[SubConcatEnd++] = undefVec;
1969 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1970 NextVT, SubConcatOps);
1971 ConcatEnd = SubConcatIdx + 1;
1975 // Check to see if we have a single operation with the widen type.
1976 if (ConcatEnd == 1) {
1977 VT = ConcatOps[0].getValueType();
1979 return ConcatOps[0];
1982 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1983 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1984 if (NumOps != ConcatEnd ) {
1985 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1986 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1987 ConcatOps[j] = UndefVal;
1989 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
1990 makeArrayRef(ConcatOps.data(), NumOps));
1993 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1994 SDValue InOp = N->getOperand(0);
1997 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1998 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2000 EVT InVT = InOp.getValueType();
2001 EVT InEltVT = InVT.getVectorElementType();
2002 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2004 unsigned Opcode = N->getOpcode();
2005 unsigned InVTNumElts = InVT.getVectorNumElements();
2007 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2008 InOp = GetWidenedVector(N->getOperand(0));
2009 InVT = InOp.getValueType();
2010 InVTNumElts = InVT.getVectorNumElements();
2011 if (InVTNumElts == WidenNumElts) {
2012 if (N->getNumOperands() == 1)
2013 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2014 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
2018 if (TLI.isTypeLegal(InWidenVT)) {
2019 // Because the result and the input are different vector types, widening
2020 // the result could create a legal type but widening the input might make
2021 // it an illegal type that might lead to repeatedly splitting the input
2022 // and then widening it. To avoid this, we widen the input only if
2023 // it results in a legal type.
2024 if (WidenNumElts % InVTNumElts == 0) {
2025 // Widen the input and call convert on the widened input vector.
2026 unsigned NumConcat = WidenNumElts/InVTNumElts;
2027 SmallVector<SDValue, 16> Ops(NumConcat);
2029 SDValue UndefVal = DAG.getUNDEF(InVT);
2030 for (unsigned i = 1; i != NumConcat; ++i)
2032 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2033 if (N->getNumOperands() == 1)
2034 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2035 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2038 if (InVTNumElts % WidenNumElts == 0) {
2039 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2040 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2041 // Extract the input and convert the shorten input vector.
2042 if (N->getNumOperands() == 1)
2043 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2044 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2048 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2049 SmallVector<SDValue, 16> Ops(WidenNumElts);
2050 EVT EltVT = WidenVT.getVectorElementType();
2051 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2053 for (i=0; i < MinElts; ++i) {
2054 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2055 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
2056 if (N->getNumOperands() == 1)
2057 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2059 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2062 SDValue UndefVal = DAG.getUNDEF(EltVT);
2063 for (; i < WidenNumElts; ++i)
2066 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2069 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2070 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2071 SDValue InOp = GetWidenedVector(N->getOperand(0));
2072 SDValue ShOp = N->getOperand(1);
2073 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2076 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2077 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2078 SDValue InOp = GetWidenedVector(N->getOperand(0));
2079 SDValue ShOp = N->getOperand(1);
2081 EVT ShVT = ShOp.getValueType();
2082 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2083 ShOp = GetWidenedVector(ShOp);
2084 ShVT = ShOp.getValueType();
2086 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2087 ShVT.getVectorElementType(),
2088 WidenVT.getVectorNumElements());
2089 if (ShVT != ShWidenVT)
2090 ShOp = ModifyToType(ShOp, ShWidenVT);
2092 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2095 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2096 // Unary op widening.
2097 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2098 SDValue InOp = GetWidenedVector(N->getOperand(0));
2099 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2102 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2103 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2104 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2105 cast<VTSDNode>(N->getOperand(1))->getVT()
2106 .getVectorElementType(),
2107 WidenVT.getVectorNumElements());
2108 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2109 return DAG.getNode(N->getOpcode(), SDLoc(N),
2110 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2113 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2114 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2115 return GetWidenedVector(WidenVec);
2118 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2119 SDValue InOp = N->getOperand(0);
2120 EVT InVT = InOp.getValueType();
2121 EVT VT = N->getValueType(0);
2122 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2125 switch (getTypeAction(InVT)) {
2126 case TargetLowering::TypeLegal:
2128 case TargetLowering::TypePromoteInteger:
2129 // If the incoming type is a vector that is being promoted, then
2130 // we know that the elements are arranged differently and that we
2131 // must perform the conversion using a stack slot.
2132 if (InVT.isVector())
2135 // If the InOp is promoted to the same size, convert it. Otherwise,
2136 // fall out of the switch and widen the promoted input.
2137 InOp = GetPromotedInteger(InOp);
2138 InVT = InOp.getValueType();
2139 if (WidenVT.bitsEq(InVT))
2140 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2142 case TargetLowering::TypeSoftenFloat:
2143 case TargetLowering::TypePromoteFloat:
2144 case TargetLowering::TypeExpandInteger:
2145 case TargetLowering::TypeExpandFloat:
2146 case TargetLowering::TypeScalarizeVector:
2147 case TargetLowering::TypeSplitVector:
2149 case TargetLowering::TypeWidenVector:
2150 // If the InOp is widened to the same size, convert it. Otherwise, fall
2151 // out of the switch and widen the widened input.
2152 InOp = GetWidenedVector(InOp);
2153 InVT = InOp.getValueType();
2154 if (WidenVT.bitsEq(InVT))
2155 // The input widens to the same size. Convert to the widen value.
2156 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2160 unsigned WidenSize = WidenVT.getSizeInBits();
2161 unsigned InSize = InVT.getSizeInBits();
2162 // x86mmx is not an acceptable vector element type, so don't try.
2163 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2164 // Determine new input vector type. The new input vector type will use
2165 // the same element type (if its a vector) or use the input type as a
2166 // vector. It is the same size as the type to widen to.
2168 unsigned NewNumElts = WidenSize / InSize;
2169 if (InVT.isVector()) {
2170 EVT InEltVT = InVT.getVectorElementType();
2171 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2172 WidenSize / InEltVT.getSizeInBits());
2174 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2177 if (TLI.isTypeLegal(NewInVT)) {
2178 // Because the result and the input are different vector types, widening
2179 // the result could create a legal type but widening the input might make
2180 // it an illegal type that might lead to repeatedly splitting the input
2181 // and then widening it. To avoid this, we widen the input only if
2182 // it results in a legal type.
2183 SmallVector<SDValue, 16> Ops(NewNumElts);
2184 SDValue UndefVal = DAG.getUNDEF(InVT);
2186 for (unsigned i = 1; i < NewNumElts; ++i)
2190 if (InVT.isVector())
2191 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2193 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2194 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2198 return CreateStackStoreLoad(InOp, WidenVT);
2201 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2203 // Build a vector with undefined for the new nodes.
2204 EVT VT = N->getValueType(0);
2206 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2207 // type. The UNDEFs need to have the same type as the existing operands.
2208 EVT EltVT = N->getOperand(0).getValueType();
2209 unsigned NumElts = VT.getVectorNumElements();
2211 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2212 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2214 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2215 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2216 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2218 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2221 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2222 EVT InVT = N->getOperand(0).getValueType();
2223 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2225 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2226 unsigned NumInElts = InVT.getVectorNumElements();
2227 unsigned NumOperands = N->getNumOperands();
2229 bool InputWidened = false; // Indicates we need to widen the input.
2230 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2231 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2232 // Add undef vectors to widen to correct length.
2233 unsigned NumConcat = WidenVT.getVectorNumElements() /
2234 InVT.getVectorNumElements();
2235 SDValue UndefVal = DAG.getUNDEF(InVT);
2236 SmallVector<SDValue, 16> Ops(NumConcat);
2237 for (unsigned i=0; i < NumOperands; ++i)
2238 Ops[i] = N->getOperand(i);
2239 for (unsigned i = NumOperands; i != NumConcat; ++i)
2241 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2244 InputWidened = true;
2245 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2246 // The inputs and the result are widen to the same value.
2248 for (i=1; i < NumOperands; ++i)
2249 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2252 if (i == NumOperands)
2253 // Everything but the first operand is an UNDEF so just return the
2254 // widened first operand.
2255 return GetWidenedVector(N->getOperand(0));
2257 if (NumOperands == 2) {
2258 // Replace concat of two operands with a shuffle.
2259 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2260 for (unsigned i = 0; i < NumInElts; ++i) {
2262 MaskOps[i + NumInElts] = i + WidenNumElts;
2264 return DAG.getVectorShuffle(WidenVT, dl,
2265 GetWidenedVector(N->getOperand(0)),
2266 GetWidenedVector(N->getOperand(1)),
2272 // Fall back to use extracts and build vector.
2273 EVT EltVT = WidenVT.getVectorElementType();
2274 SmallVector<SDValue, 16> Ops(WidenNumElts);
2276 for (unsigned i=0; i < NumOperands; ++i) {
2277 SDValue InOp = N->getOperand(i);
2279 InOp = GetWidenedVector(InOp);
2280 for (unsigned j=0; j < NumInElts; ++j)
2281 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2282 DAG.getConstant(j, dl, TLI.getVectorIdxTy()));
2284 SDValue UndefVal = DAG.getUNDEF(EltVT);
2285 for (; Idx < WidenNumElts; ++Idx)
2286 Ops[Idx] = UndefVal;
2287 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2290 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2292 SDValue InOp = N->getOperand(0);
2293 SDValue RndOp = N->getOperand(3);
2294 SDValue SatOp = N->getOperand(4);
2296 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2297 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2299 EVT InVT = InOp.getValueType();
2300 EVT InEltVT = InVT.getVectorElementType();
2301 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2303 SDValue DTyOp = DAG.getValueType(WidenVT);
2304 SDValue STyOp = DAG.getValueType(InWidenVT);
2305 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2307 unsigned InVTNumElts = InVT.getVectorNumElements();
2308 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2309 InOp = GetWidenedVector(InOp);
2310 InVT = InOp.getValueType();
2311 InVTNumElts = InVT.getVectorNumElements();
2312 if (InVTNumElts == WidenNumElts)
2313 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2317 if (TLI.isTypeLegal(InWidenVT)) {
2318 // Because the result and the input are different vector types, widening
2319 // the result could create a legal type but widening the input might make
2320 // it an illegal type that might lead to repeatedly splitting the input
2321 // and then widening it. To avoid this, we widen the input only if
2322 // it results in a legal type.
2323 if (WidenNumElts % InVTNumElts == 0) {
2324 // Widen the input and call convert on the widened input vector.
2325 unsigned NumConcat = WidenNumElts/InVTNumElts;
2326 SmallVector<SDValue, 16> Ops(NumConcat);
2328 SDValue UndefVal = DAG.getUNDEF(InVT);
2329 for (unsigned i = 1; i != NumConcat; ++i)
2332 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2333 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2337 if (InVTNumElts % WidenNumElts == 0) {
2338 // Extract the input and convert the shorten input vector.
2339 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2340 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
2341 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2346 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2347 SmallVector<SDValue, 16> Ops(WidenNumElts);
2348 EVT EltVT = WidenVT.getVectorElementType();
2349 DTyOp = DAG.getValueType(EltVT);
2350 STyOp = DAG.getValueType(InEltVT);
2352 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2354 for (i=0; i < MinElts; ++i) {
2355 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2356 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
2357 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2361 SDValue UndefVal = DAG.getUNDEF(EltVT);
2362 for (; i < WidenNumElts; ++i)
2365 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2368 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2369 EVT VT = N->getValueType(0);
2370 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2371 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2372 SDValue InOp = N->getOperand(0);
2373 SDValue Idx = N->getOperand(1);
2376 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2377 InOp = GetWidenedVector(InOp);
2379 EVT InVT = InOp.getValueType();
2381 // Check if we can just return the input vector after widening.
2382 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2383 if (IdxVal == 0 && InVT == WidenVT)
2386 // Check if we can extract from the vector.
2387 unsigned InNumElts = InVT.getVectorNumElements();
2388 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2389 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2391 // We could try widening the input to the right length but for now, extract
2392 // the original elements, fill the rest with undefs and build a vector.
2393 SmallVector<SDValue, 16> Ops(WidenNumElts);
2394 EVT EltVT = VT.getVectorElementType();
2395 unsigned NumElts = VT.getVectorNumElements();
2397 for (i=0; i < NumElts; ++i)
2398 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2399 DAG.getConstant(IdxVal + i, dl, TLI.getVectorIdxTy()));
2401 SDValue UndefVal = DAG.getUNDEF(EltVT);
2402 for (; i < WidenNumElts; ++i)
2404 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2407 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2408 SDValue InOp = GetWidenedVector(N->getOperand(0));
2409 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2410 InOp.getValueType(), InOp,
2411 N->getOperand(1), N->getOperand(2));
2414 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2415 LoadSDNode *LD = cast<LoadSDNode>(N);
2416 ISD::LoadExtType ExtType = LD->getExtensionType();
2419 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2420 if (ExtType != ISD::NON_EXTLOAD)
2421 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2423 Result = GenWidenVectorLoads(LdChain, LD);
2425 // If we generate a single load, we can use that for the chain. Otherwise,
2426 // build a factor node to remember the multiple loads are independent and
2429 if (LdChain.size() == 1)
2430 NewChain = LdChain[0];
2432 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2434 // Modified the chain - switch anything that used the old chain to use
2436 ReplaceValueWith(SDValue(N, 1), NewChain);
2441 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2443 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2444 SDValue Mask = N->getMask();
2445 EVT MaskVT = Mask.getValueType();
2446 SDValue Src0 = GetWidenedVector(N->getSrc0());
2447 ISD::LoadExtType ExtType = N->getExtensionType();
2450 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2451 Mask = GetWidenedVector(Mask);
2453 EVT BoolVT = getSetCCResultType(WidenVT);
2455 // We can't use ModifyToType() because we should fill the mask with
2457 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2458 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2460 unsigned NumConcat = WidenNumElts / MaskNumElts;
2461 SmallVector<SDValue, 16> Ops(NumConcat);
2462 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2464 for (unsigned i = 1; i != NumConcat; ++i)
2467 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2470 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2471 Mask, Src0, N->getMemoryVT(),
2472 N->getMemOperand(), ExtType);
2473 // Legalized the chain result - switch anything that used the old chain to
2475 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2479 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2480 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2481 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2482 WidenVT, N->getOperand(0));
2485 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2486 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2487 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2489 SDValue Cond1 = N->getOperand(0);
2490 EVT CondVT = Cond1.getValueType();
2491 if (CondVT.isVector()) {
2492 EVT CondEltVT = CondVT.getVectorElementType();
2493 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2494 CondEltVT, WidenNumElts);
2495 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2496 Cond1 = GetWidenedVector(Cond1);
2498 // If we have to split the condition there is no point in widening the
2499 // select. This would result in an cycle of widening the select ->
2500 // widening the condition operand -> splitting the condition operand ->
2501 // splitting the select -> widening the select. Instead split this select
2502 // further and widen the resulting type.
2503 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2504 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2505 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2509 if (Cond1.getValueType() != CondWidenVT)
2510 Cond1 = ModifyToType(Cond1, CondWidenVT);
2513 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2514 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2515 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2516 return DAG.getNode(N->getOpcode(), SDLoc(N),
2517 WidenVT, Cond1, InOp1, InOp2);
2520 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2521 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2522 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2523 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2524 InOp1.getValueType(), N->getOperand(0),
2525 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2528 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2529 assert(N->getValueType(0).isVector() ==
2530 N->getOperand(0).getValueType().isVector() &&
2531 "Scalar/Vector type mismatch");
2532 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2534 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2535 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2536 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2537 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2538 InOp1, InOp2, N->getOperand(2));
2541 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2542 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2543 return DAG.getUNDEF(WidenVT);
2546 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2547 EVT VT = N->getValueType(0);
2550 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2551 unsigned NumElts = VT.getVectorNumElements();
2552 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2554 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2555 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2557 // Adjust mask based on new input vector length.
2558 SmallVector<int, 16> NewMask;
2559 for (unsigned i = 0; i != NumElts; ++i) {
2560 int Idx = N->getMaskElt(i);
2561 if (Idx < (int)NumElts)
2562 NewMask.push_back(Idx);
2564 NewMask.push_back(Idx - NumElts + WidenNumElts);
2566 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2567 NewMask.push_back(-1);
2568 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2571 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2572 assert(N->getValueType(0).isVector() &&
2573 N->getOperand(0).getValueType().isVector() &&
2574 "Operands must be vectors");
2575 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2576 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2578 SDValue InOp1 = N->getOperand(0);
2579 EVT InVT = InOp1.getValueType();
2580 assert(InVT.isVector() && "can not widen non-vector type");
2581 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2582 InVT.getVectorElementType(), WidenNumElts);
2584 // The input and output types often differ here, and it could be that while
2585 // we'd prefer to widen the result type, the input operands have been split.
2586 // In this case, we also need to split the result of this node as well.
2587 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2588 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2589 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2593 InOp1 = GetWidenedVector(InOp1);
2594 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2596 // Assume that the input and output will be widen appropriately. If not,
2597 // we will have to unroll it at some point.
2598 assert(InOp1.getValueType() == WidenInVT &&
2599 InOp2.getValueType() == WidenInVT &&
2600 "Input not widened to expected type!");
2602 return DAG.getNode(ISD::SETCC, SDLoc(N),
2603 WidenVT, InOp1, InOp2, N->getOperand(2));
2607 //===----------------------------------------------------------------------===//
2608 // Widen Vector Operand
2609 //===----------------------------------------------------------------------===//
2610 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2611 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2614 SDValue Res = SDValue();
2616 // See if the target wants to custom widen this node.
2617 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2620 switch (N->getOpcode()) {
2623 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2627 llvm_unreachable("Do not know how to widen this operator's operand!");
2629 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2630 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2631 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2632 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2633 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2634 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2635 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2637 case ISD::ANY_EXTEND:
2638 case ISD::SIGN_EXTEND:
2639 case ISD::ZERO_EXTEND:
2640 Res = WidenVecOp_EXTEND(N);
2643 case ISD::FP_EXTEND:
2644 case ISD::FP_TO_SINT:
2645 case ISD::FP_TO_UINT:
2646 case ISD::SINT_TO_FP:
2647 case ISD::UINT_TO_FP:
2649 Res = WidenVecOp_Convert(N);
2653 // If Res is null, the sub-method took care of registering the result.
2654 if (!Res.getNode()) return false;
2656 // If the result is N, the sub-method updated N in place. Tell the legalizer
2658 if (Res.getNode() == N)
2662 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2663 "Invalid operand expansion");
2665 ReplaceValueWith(SDValue(N, 0), Res);
2669 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2671 EVT VT = N->getValueType(0);
2673 SDValue InOp = N->getOperand(0);
2674 // If some legalization strategy other than widening is used on the operand,
2675 // we can't safely assume that just extending the low lanes is the correct
2677 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2678 return WidenVecOp_Convert(N);
2679 InOp = GetWidenedVector(InOp);
2680 assert(VT.getVectorNumElements() <
2681 InOp.getValueType().getVectorNumElements() &&
2682 "Input wasn't widened!");
2684 // We may need to further widen the operand until it has the same total
2685 // vector size as the result.
2686 EVT InVT = InOp.getValueType();
2687 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2688 EVT InEltVT = InVT.getVectorElementType();
2689 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2690 EVT FixedVT = (MVT::SimpleValueType)i;
2691 EVT FixedEltVT = FixedVT.getVectorElementType();
2692 if (TLI.isTypeLegal(FixedVT) &&
2693 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2694 FixedEltVT == InEltVT) {
2695 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2696 "Not enough elements in the fixed type for the operand!");
2697 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2698 "We can't have the same type as we started with!");
2699 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2700 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2701 DAG.getUNDEF(FixedVT), InOp,
2702 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2704 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2705 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2709 InVT = InOp.getValueType();
2710 if (InVT.getSizeInBits() != VT.getSizeInBits())
2711 // We couldn't find a legal vector type that was a widening of the input
2712 // and could be extended in-register to the result type, so we have to
2714 return WidenVecOp_Convert(N);
2717 // Use special DAG nodes to represent the operation of extending the
2719 switch (N->getOpcode()) {
2721 llvm_unreachable("Extend legalization on on extend operation!");
2722 case ISD::ANY_EXTEND:
2723 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2724 case ISD::SIGN_EXTEND:
2725 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2726 case ISD::ZERO_EXTEND:
2727 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2731 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2732 // Since the result is legal and the input is illegal, it is unlikely
2733 // that we can fix the input to a legal type so unroll the convert
2734 // into some scalar code and create a nasty build vector.
2735 EVT VT = N->getValueType(0);
2736 EVT EltVT = VT.getVectorElementType();
2738 unsigned NumElts = VT.getVectorNumElements();
2739 SDValue InOp = N->getOperand(0);
2740 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2741 InOp = GetWidenedVector(InOp);
2742 EVT InVT = InOp.getValueType();
2743 EVT InEltVT = InVT.getVectorElementType();
2745 unsigned Opcode = N->getOpcode();
2746 SmallVector<SDValue, 16> Ops(NumElts);
2747 for (unsigned i=0; i < NumElts; ++i)
2748 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2749 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2750 DAG.getConstant(i, dl,
2751 TLI.getVectorIdxTy())));
2753 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2756 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2757 EVT VT = N->getValueType(0);
2758 SDValue InOp = GetWidenedVector(N->getOperand(0));
2759 EVT InWidenVT = InOp.getValueType();
2762 // Check if we can convert between two legal vector types and extract.
2763 unsigned InWidenSize = InWidenVT.getSizeInBits();
2764 unsigned Size = VT.getSizeInBits();
2765 // x86mmx is not an acceptable vector element type, so don't try.
2766 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2767 unsigned NewNumElts = InWidenSize / Size;
2768 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2769 if (TLI.isTypeLegal(NewVT)) {
2770 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2771 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2772 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
2776 return CreateStackStoreLoad(InOp, VT);
2779 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2780 // If the input vector is not legal, it is likely that we will not find a
2781 // legal vector of the same size. Replace the concatenate vector with a
2782 // nasty build vector.
2783 EVT VT = N->getValueType(0);
2784 EVT EltVT = VT.getVectorElementType();
2786 unsigned NumElts = VT.getVectorNumElements();
2787 SmallVector<SDValue, 16> Ops(NumElts);
2789 EVT InVT = N->getOperand(0).getValueType();
2790 unsigned NumInElts = InVT.getVectorNumElements();
2793 unsigned NumOperands = N->getNumOperands();
2794 for (unsigned i=0; i < NumOperands; ++i) {
2795 SDValue InOp = N->getOperand(i);
2796 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2797 InOp = GetWidenedVector(InOp);
2798 for (unsigned j=0; j < NumInElts; ++j)
2799 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2800 DAG.getConstant(j, dl, TLI.getVectorIdxTy()));
2802 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2805 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2806 SDValue InOp = GetWidenedVector(N->getOperand(0));
2807 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2808 N->getValueType(0), InOp, N->getOperand(1));
2811 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2812 SDValue InOp = GetWidenedVector(N->getOperand(0));
2813 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2814 N->getValueType(0), InOp, N->getOperand(1));
2817 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2818 // We have to widen the value but we want only to store the original
2820 StoreSDNode *ST = cast<StoreSDNode>(N);
2822 SmallVector<SDValue, 16> StChain;
2823 if (ST->isTruncatingStore())
2824 GenWidenVectorTruncStores(StChain, ST);
2826 GenWidenVectorStores(StChain, ST);
2828 if (StChain.size() == 1)
2831 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
2834 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
2835 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
2836 SDValue Mask = MST->getMask();
2837 EVT MaskVT = Mask.getValueType();
2838 SDValue StVal = MST->getValue();
2840 SDValue WideVal = GetWidenedVector(StVal);
2843 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2844 Mask = GetWidenedVector(Mask);
2846 // The mask should be widened as well
2847 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
2848 // We can't use ModifyToType() because we should fill the mask with
2850 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2851 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2853 unsigned NumConcat = WidenNumElts / MaskNumElts;
2854 SmallVector<SDValue, 16> Ops(NumConcat);
2855 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2857 for (unsigned i = 1; i != NumConcat; ++i)
2860 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2862 assert(Mask.getValueType().getVectorNumElements() ==
2863 WideVal.getValueType().getVectorNumElements() &&
2864 "Mask and data vectors should have the same number of elements");
2865 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
2866 Mask, MST->getMemoryVT(), MST->getMemOperand(),
2870 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2871 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2872 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2875 // WARNING: In this code we widen the compare instruction with garbage.
2876 // This garbage may contain denormal floats which may be slow. Is this a real
2877 // concern ? Should we zero the unused lanes if this is a float compare ?
2879 // Get a new SETCC node to compare the newly widened operands.
2880 // Only some of the compared elements are legal.
2881 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
2882 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
2883 SVT, InOp0, InOp1, N->getOperand(2));
2885 // Extract the needed results from the result vector.
2886 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2887 SVT.getVectorElementType(),
2888 N->getValueType(0).getVectorNumElements());
2889 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2891 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
2893 return PromoteTargetBoolean(CC, N->getValueType(0));
2897 //===----------------------------------------------------------------------===//
2898 // Vector Widening Utilities
2899 //===----------------------------------------------------------------------===//
2901 // Utility function to find the type to chop up a widen vector for load/store
2902 // TLI: Target lowering used to determine legal types.
2903 // Width: Width left need to load/store.
2904 // WidenVT: The widen vector type to load to/store from
2905 // Align: If 0, don't allow use of a wider type
2906 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2908 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2909 unsigned Width, EVT WidenVT,
2910 unsigned Align = 0, unsigned WidenEx = 0) {
2911 EVT WidenEltVT = WidenVT.getVectorElementType();
2912 unsigned WidenWidth = WidenVT.getSizeInBits();
2913 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2914 unsigned AlignInBits = Align*8;
2916 // If we have one element to load/store, return it.
2917 EVT RetVT = WidenEltVT;
2918 if (Width == WidenEltWidth)
2921 // See if there is larger legal integer than the element type to load/store
2923 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2924 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2925 EVT MemVT((MVT::SimpleValueType) VT);
2926 unsigned MemVTWidth = MemVT.getSizeInBits();
2927 if (MemVT.getSizeInBits() <= WidenEltWidth)
2929 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2930 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2931 (MemVTWidth <= Width ||
2932 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2938 // See if there is a larger vector type to load/store that has the same vector
2939 // element type and is evenly divisible with the WidenVT.
2940 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2941 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2942 EVT MemVT = (MVT::SimpleValueType) VT;
2943 unsigned MemVTWidth = MemVT.getSizeInBits();
2944 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2945 (WidenWidth % MemVTWidth) == 0 &&
2946 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2947 (MemVTWidth <= Width ||
2948 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2949 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2957 // Builds a vector type from scalar loads
2958 // VecTy: Resulting Vector type
2959 // LDOps: Load operators to build a vector type
2960 // [Start,End) the list of loads to use.
2961 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2962 SmallVectorImpl<SDValue> &LdOps,
2963 unsigned Start, unsigned End) {
2964 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2965 SDLoc dl(LdOps[Start]);
2966 EVT LdTy = LdOps[Start].getValueType();
2967 unsigned Width = VecTy.getSizeInBits();
2968 unsigned NumElts = Width / LdTy.getSizeInBits();
2969 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2972 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2974 for (unsigned i = Start + 1; i != End; ++i) {
2975 EVT NewLdTy = LdOps[i].getValueType();
2976 if (NewLdTy != LdTy) {
2977 NumElts = Width / NewLdTy.getSizeInBits();
2978 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2979 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2980 // Readjust position and vector position based on new load type
2981 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2984 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2985 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy()));
2987 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2990 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
2992 // The strategy assumes that we can efficiently load powers of two widths.
2993 // The routines chops the vector into the largest vector loads with the same
2994 // element type or scalar loads and then recombines it to the widen vector
2996 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2997 unsigned WidenWidth = WidenVT.getSizeInBits();
2998 EVT LdVT = LD->getMemoryVT();
3000 assert(LdVT.isVector() && WidenVT.isVector());
3001 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3004 SDValue Chain = LD->getChain();
3005 SDValue BasePtr = LD->getBasePtr();
3006 unsigned Align = LD->getAlignment();
3007 bool isVolatile = LD->isVolatile();
3008 bool isNonTemporal = LD->isNonTemporal();
3009 bool isInvariant = LD->isInvariant();
3010 AAMDNodes AAInfo = LD->getAAInfo();
3012 int LdWidth = LdVT.getSizeInBits();
3013 int WidthDiff = WidenWidth - LdWidth; // Difference
3014 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3016 // Find the vector type that can load from.
3017 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3018 int NewVTWidth = NewVT.getSizeInBits();
3019 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3020 isVolatile, isNonTemporal, isInvariant, Align,
3022 LdChain.push_back(LdOp.getValue(1));
3024 // Check if we can load the element with one instruction
3025 if (LdWidth <= NewVTWidth) {
3026 if (!NewVT.isVector()) {
3027 unsigned NumElts = WidenWidth / NewVTWidth;
3028 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3029 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3030 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3032 if (NewVT == WidenVT)
3035 assert(WidenWidth % NewVTWidth == 0);
3036 unsigned NumConcat = WidenWidth / NewVTWidth;
3037 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3038 SDValue UndefVal = DAG.getUNDEF(NewVT);
3039 ConcatOps[0] = LdOp;
3040 for (unsigned i = 1; i != NumConcat; ++i)
3041 ConcatOps[i] = UndefVal;
3042 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3045 // Load vector by using multiple loads from largest vector to scalar
3046 SmallVector<SDValue, 16> LdOps;
3047 LdOps.push_back(LdOp);
3049 LdWidth -= NewVTWidth;
3050 unsigned Offset = 0;
3052 while (LdWidth > 0) {
3053 unsigned Increment = NewVTWidth / 8;
3054 Offset += Increment;
3055 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3056 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3059 if (LdWidth < NewVTWidth) {
3060 // Our current type we are using is too large, find a better size
3061 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3062 NewVTWidth = NewVT.getSizeInBits();
3063 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3064 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3065 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3067 LdChain.push_back(L.getValue(1));
3068 if (L->getValueType(0).isVector()) {
3069 SmallVector<SDValue, 16> Loads;
3071 unsigned size = L->getValueSizeInBits(0);
3072 while (size < LdOp->getValueSizeInBits(0)) {
3073 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3074 size += L->getValueSizeInBits(0);
3076 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3079 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3080 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3081 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3083 LdChain.push_back(L.getValue(1));
3089 LdWidth -= NewVTWidth;
3092 // Build the vector from the loads operations
3093 unsigned End = LdOps.size();
3094 if (!LdOps[0].getValueType().isVector())
3095 // All the loads are scalar loads.
3096 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3098 // If the load contains vectors, build the vector using concat vector.
3099 // All of the vectors used to loads are power of 2 and the scalars load
3100 // can be combined to make a power of 2 vector.
3101 SmallVector<SDValue, 16> ConcatOps(End);
3104 EVT LdTy = LdOps[i].getValueType();
3105 // First combine the scalar loads to a vector
3106 if (!LdTy.isVector()) {
3107 for (--i; i >= 0; --i) {
3108 LdTy = LdOps[i].getValueType();
3109 if (LdTy.isVector())
3112 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3114 ConcatOps[--Idx] = LdOps[i];
3115 for (--i; i >= 0; --i) {
3116 EVT NewLdTy = LdOps[i].getValueType();
3117 if (NewLdTy != LdTy) {
3118 // Create a larger vector
3119 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3120 makeArrayRef(&ConcatOps[Idx], End - Idx));
3124 ConcatOps[--Idx] = LdOps[i];
3127 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3128 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3129 makeArrayRef(&ConcatOps[Idx], End - Idx));
3131 // We need to fill the rest with undefs to build the vector
3132 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3133 SmallVector<SDValue, 16> WidenOps(NumOps);
3134 SDValue UndefVal = DAG.getUNDEF(LdTy);
3137 for (; i != End-Idx; ++i)
3138 WidenOps[i] = ConcatOps[Idx+i];
3139 for (; i != NumOps; ++i)
3140 WidenOps[i] = UndefVal;
3142 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3146 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3148 ISD::LoadExtType ExtType) {
3149 // For extension loads, it may not be more efficient to chop up the vector
3150 // and then extended it. Instead, we unroll the load and build a new vector.
3151 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3152 EVT LdVT = LD->getMemoryVT();
3154 assert(LdVT.isVector() && WidenVT.isVector());
3157 SDValue Chain = LD->getChain();
3158 SDValue BasePtr = LD->getBasePtr();
3159 unsigned Align = LD->getAlignment();
3160 bool isVolatile = LD->isVolatile();
3161 bool isNonTemporal = LD->isNonTemporal();
3162 bool isInvariant = LD->isInvariant();
3163 AAMDNodes AAInfo = LD->getAAInfo();
3165 EVT EltVT = WidenVT.getVectorElementType();
3166 EVT LdEltVT = LdVT.getVectorElementType();
3167 unsigned NumElts = LdVT.getVectorNumElements();
3169 // Load each element and widen
3170 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3171 SmallVector<SDValue, 16> Ops(WidenNumElts);
3172 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3173 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3174 LD->getPointerInfo(),
3175 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3177 LdChain.push_back(Ops[0].getValue(1));
3178 unsigned i = 0, Offset = Increment;
3179 for (i=1; i < NumElts; ++i, Offset += Increment) {
3180 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3182 DAG.getConstant(Offset, dl,
3183 BasePtr.getValueType()));
3184 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3185 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3186 isVolatile, isNonTemporal, isInvariant, Align,
3188 LdChain.push_back(Ops[i].getValue(1));
3191 // Fill the rest with undefs
3192 SDValue UndefVal = DAG.getUNDEF(EltVT);
3193 for (; i != WidenNumElts; ++i)
3196 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3200 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3202 // The strategy assumes that we can efficiently store powers of two widths.
3203 // The routines chops the vector into the largest vector stores with the same
3204 // element type or scalar stores.
3205 SDValue Chain = ST->getChain();
3206 SDValue BasePtr = ST->getBasePtr();
3207 unsigned Align = ST->getAlignment();
3208 bool isVolatile = ST->isVolatile();
3209 bool isNonTemporal = ST->isNonTemporal();
3210 AAMDNodes AAInfo = ST->getAAInfo();
3211 SDValue ValOp = GetWidenedVector(ST->getValue());
3214 EVT StVT = ST->getMemoryVT();
3215 unsigned StWidth = StVT.getSizeInBits();
3216 EVT ValVT = ValOp.getValueType();
3217 unsigned ValWidth = ValVT.getSizeInBits();
3218 EVT ValEltVT = ValVT.getVectorElementType();
3219 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3220 assert(StVT.getVectorElementType() == ValEltVT);
3222 int Idx = 0; // current index to store
3223 unsigned Offset = 0; // offset from base to store
3224 while (StWidth != 0) {
3225 // Find the largest vector type we can store with
3226 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3227 unsigned NewVTWidth = NewVT.getSizeInBits();
3228 unsigned Increment = NewVTWidth / 8;
3229 if (NewVT.isVector()) {
3230 unsigned NumVTElts = NewVT.getVectorNumElements();
3232 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3233 DAG.getConstant(Idx, dl,
3234 TLI.getVectorIdxTy()));
3235 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3236 ST->getPointerInfo().getWithOffset(Offset),
3237 isVolatile, isNonTemporal,
3238 MinAlign(Align, Offset), AAInfo));
3239 StWidth -= NewVTWidth;
3240 Offset += Increment;
3242 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3243 DAG.getConstant(Increment, dl,
3244 BasePtr.getValueType()));
3245 } while (StWidth != 0 && StWidth >= NewVTWidth);
3247 // Cast the vector to the scalar type we can store
3248 unsigned NumElts = ValWidth / NewVTWidth;
3249 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3250 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3251 // Readjust index position based on new vector type
3252 Idx = Idx * ValEltWidth / NewVTWidth;
3254 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3255 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy()));
3256 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3257 ST->getPointerInfo().getWithOffset(Offset),
3258 isVolatile, isNonTemporal,
3259 MinAlign(Align, Offset), AAInfo));
3260 StWidth -= NewVTWidth;
3261 Offset += Increment;
3262 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3263 DAG.getConstant(Increment, dl,
3264 BasePtr.getValueType()));
3265 } while (StWidth != 0 && StWidth >= NewVTWidth);
3266 // Restore index back to be relative to the original widen element type
3267 Idx = Idx * NewVTWidth / ValEltWidth;
3273 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3275 // For extension loads, it may not be more efficient to truncate the vector
3276 // and then store it. Instead, we extract each element and then store it.
3277 SDValue Chain = ST->getChain();
3278 SDValue BasePtr = ST->getBasePtr();
3279 unsigned Align = ST->getAlignment();
3280 bool isVolatile = ST->isVolatile();
3281 bool isNonTemporal = ST->isNonTemporal();
3282 AAMDNodes AAInfo = ST->getAAInfo();
3283 SDValue ValOp = GetWidenedVector(ST->getValue());
3286 EVT StVT = ST->getMemoryVT();
3287 EVT ValVT = ValOp.getValueType();
3289 // It must be true that we the widen vector type is bigger than where
3290 // we need to store.
3291 assert(StVT.isVector() && ValOp.getValueType().isVector());
3292 assert(StVT.bitsLT(ValOp.getValueType()));
3294 // For truncating stores, we can not play the tricks of chopping legal
3295 // vector types and bit cast it to the right type. Instead, we unroll
3297 EVT StEltVT = StVT.getVectorElementType();
3298 EVT ValEltVT = ValVT.getVectorElementType();
3299 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3300 unsigned NumElts = StVT.getVectorNumElements();
3301 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3302 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3303 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3304 ST->getPointerInfo(), StEltVT,
3305 isVolatile, isNonTemporal, Align,
3307 unsigned Offset = Increment;
3308 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3309 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3311 DAG.getConstant(Offset, dl,
3312 BasePtr.getValueType()));
3313 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3314 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3315 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3316 ST->getPointerInfo().getWithOffset(Offset),
3317 StEltVT, isVolatile, isNonTemporal,
3318 MinAlign(Align, Offset), AAInfo));
3322 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3323 /// input vector must have the same element type as NVT.
3324 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3325 // Note that InOp might have been widened so it might already have
3326 // the right width or it might need be narrowed.
3327 EVT InVT = InOp.getValueType();
3328 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3329 "input and widen element type must match");
3332 // Check if InOp already has the right width.
3336 unsigned InNumElts = InVT.getVectorNumElements();
3337 unsigned WidenNumElts = NVT.getVectorNumElements();
3338 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3339 unsigned NumConcat = WidenNumElts / InNumElts;
3340 SmallVector<SDValue, 16> Ops(NumConcat);
3341 SDValue UndefVal = DAG.getUNDEF(InVT);
3343 for (unsigned i = 1; i != NumConcat; ++i)
3346 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3349 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3350 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3351 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3353 // Fall back to extract and build.
3354 SmallVector<SDValue, 16> Ops(WidenNumElts);
3355 EVT EltVT = NVT.getVectorElementType();
3356 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3358 for (Idx = 0; Idx < MinNumElts; ++Idx)
3359 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3360 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
3362 SDValue UndefVal = DAG.getUNDEF(EltVT);
3363 for ( ; Idx < WidenNumElts; ++Idx)
3364 Ops[Idx] = UndefVal;
3365 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);