1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
133 // If R is null, the sub-method took care of registering the result.
135 SetScalarizedVector(SDValue(N, ResNo), R);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
142 LHS.getValueType(), LHS, RHS);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
149 return DAG.getNode(N->getOpcode(), SDLoc(N),
150 Op0.getValueType(), Op0, Op1, Op2);
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
160 EVT NewVT = N->getValueType(0).getVectorElementType();
161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
162 NewVT, N->getOperand(0));
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
166 EVT EltVT = N->getValueType(0).getVectorElementType();
167 SDValue InOp = N->getOperand(0);
168 // The BUILD_VECTOR operands may be of wider element types and
169 // we may need to truncate them back to the requested return type.
170 if (EltVT.isInteger())
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
179 Op0, DAG.getValueType(NewVT),
180 DAG.getValueType(Op0.getValueType()),
183 cast<CvtRndSatSDNode>(N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
188 N->getValueType(0).getVectorElementType(),
189 N->getOperand(0), N->getOperand(1));
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
193 EVT NewVT = N->getValueType(0).getVectorElementType();
194 SDValue Op = GetScalarizedVector(N->getOperand(0));
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
196 NewVT, Op, N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
200 SDValue Op = GetScalarizedVector(N->getOperand(0));
201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
202 Op.getValueType(), Op, N->getOperand(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
206 // The value to insert may have a wider type than the vector element type,
207 // so be sure to truncate it to the element type if necessary.
208 SDValue Op = N->getOperand(1);
209 EVT EltVT = N->getValueType(0).getVectorElementType();
210 if (Op.getValueType() != EltVT)
211 // FIXME: Can this happen for floating point types?
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
217 assert(N->isUnindexed() && "Indexed vector load?");
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
220 N->getExtensionType(),
221 N->getValueType(0).getVectorElementType(),
223 N->getChain(), N->getBasePtr(),
224 DAG.getUNDEF(N->getBasePtr().getValueType()),
226 N->getMemoryVT().getVectorElementType(),
227 N->isVolatile(), N->isNonTemporal(),
228 N->isInvariant(), N->getOriginalAlignment(),
231 // Legalized the chain result - switch anything that used the old chain to
233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
239 EVT DestVT = N->getValueType(0).getVectorElementType();
240 SDValue Op = N->getOperand(0);
241 EVT OpVT = Op.getValueType();
243 // The result needs scalarizing, but it's not a given that the source does.
244 // This is a workaround for targets where it's impossible to scalarize the
245 // result of a conversion, because the source type is legal.
246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
248 // legal and was not scalarized.
249 // See the similar logic in ScalarizeVecRes_VSETCC
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
251 Op = GetScalarizedVector(Op);
253 EVT VT = OpVT.getVectorElementType();
254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
255 DAG.getConstant(0, TLI.getVectorIdxTy()));
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
261 EVT EltVT = N->getValueType(0).getVectorElementType();
262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
265 LHS, DAG.getValueType(ExtVT));
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
269 // If the operand is wider than the vector element type then it is implicitly
270 // truncated. Make that explicit here.
271 EVT EltVT = N->getValueType(0).getVectorElementType();
272 SDValue InOp = N->getOperand(0);
273 if (InOp.getValueType() != EltVT)
274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
281 TargetLowering::BooleanContent ScalarBool =
282 TLI.getBooleanContents(false, false);
283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
285 // If integer and float booleans have different contents then we can't
286 // reliably optimize in all cases. There is a full explanation for this in
287 // DAGCombiner::visitSELECT() where the same issue affects folding
288 // (select C, 0, 1) to (xor C, 1).
289 if (TLI.getBooleanContents(false, false) !=
290 TLI.getBooleanContents(false, true)) {
291 // At least try the common case where the boolean is generated by a
293 if (Cond->getOpcode() == ISD::SETCC) {
294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
296 VecBool = TLI.getBooleanContents(OpVT);
298 ScalarBool = TargetLowering::UndefinedBooleanContent;
301 if (ScalarBool != VecBool) {
302 EVT CondVT = Cond.getValueType();
303 switch (ScalarBool) {
304 case TargetLowering::UndefinedBooleanContent:
306 case TargetLowering::ZeroOrOneBooleanContent:
307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
309 // Vector read from all ones, scalar expects a single 1 so mask.
310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
311 Cond, DAG.getConstant(1, CondVT));
313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
316 // Vector reads from a one, scalar from all ones so sign extend.
317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 Cond, DAG.getValueType(MVT::i1));
323 return DAG.getSelect(SDLoc(N),
324 LHS.getValueType(), Cond, LHS,
325 GetScalarizedVector(N->getOperand(2)));
328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
330 return DAG.getSelect(SDLoc(N),
331 LHS.getValueType(), N->getOperand(0), LHS,
332 GetScalarizedVector(N->getOperand(2)));
335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
338 N->getOperand(0), N->getOperand(1),
339 LHS, GetScalarizedVector(N->getOperand(3)),
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
344 assert(N->getValueType(0).isVector() ==
345 N->getOperand(0).getValueType().isVector() &&
346 "Scalar/Vector type mismatch");
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
354 // Turn it into a scalar SETCC.
355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
363 // Figure out if the scalar is the LHS or RHS and return it.
364 SDValue Arg = N->getOperand(2).getOperand(0);
365 if (Arg.getOpcode() == ISD::UNDEF)
366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
368 return GetScalarizedVector(N->getOperand(Op));
371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
372 assert(N->getValueType(0).isVector() &&
373 N->getOperand(0).getValueType().isVector() &&
374 "Operand types must be vectors");
375 SDValue LHS = N->getOperand(0);
376 SDValue RHS = N->getOperand(1);
377 EVT OpVT = LHS.getValueType();
378 EVT NVT = N->getValueType(0).getVectorElementType();
381 // The result needs scalarizing, but it's not a given that the source does.
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
383 LHS = GetScalarizedVector(LHS);
384 RHS = GetScalarizedVector(RHS);
386 EVT VT = OpVT.getVectorElementType();
387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
388 DAG.getConstant(0, TLI.getVectorIdxTy()));
389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
390 DAG.getConstant(0, TLI.getVectorIdxTy()));
393 // Turn it into a scalar SETCC.
394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
396 // Vectors may have a different boolean contents to scalars. Promote the
397 // value appropriately.
398 ISD::NodeType ExtendCode =
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
400 return DAG.getNode(ExtendCode, DL, NVT, Res);
404 //===----------------------------------------------------------------------===//
405 // Operand Vector Scalarization <1 x ty> -> ty.
406 //===----------------------------------------------------------------------===//
408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
412 SDValue Res = SDValue();
414 if (!Res.getNode()) {
415 switch (N->getOpcode()) {
418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
424 Res = ScalarizeVecOp_BITCAST(N);
426 case ISD::ANY_EXTEND:
427 case ISD::ZERO_EXTEND:
428 case ISD::SIGN_EXTEND:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
434 Res = ScalarizeVecOp_UnaryOp(N);
436 case ISD::CONCAT_VECTORS:
437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
439 case ISD::EXTRACT_VECTOR_ELT:
440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
443 Res = ScalarizeVecOp_VSELECT(N);
446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
454 // If the result is null, the sub-method took care of registering results etc.
455 if (!Res.getNode()) return false;
457 // If the result is N, the sub-method updated N in place. Tell the legalizer
459 if (Res.getNode() == N)
462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
463 "Invalid operand expansion");
465 ReplaceValueWith(SDValue(N, 0), Res);
469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
474 N->getValueType(0), Elt);
477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
481 "Unexpected vector type!");
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
484 N->getValueType(0).getScalarType(), Elt);
485 // Revectorize the result so the types line up with what the uses of this
486 // expression expect.
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
491 /// use a BUILD_VECTOR instead.
492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
495 Ops[i] = GetScalarizedVector(N->getOperand(i));
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
503 SDValue Res = GetScalarizedVector(N->getOperand(0));
504 if (Res.getValueType() != N->getValueType(0))
505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
513 /// (still with vector output type since that was acceptable if we got here).
514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
516 EVT VT = N->getValueType(0);
518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
523 /// scalarized, it must be <1 x ty>. Just store the element.
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
529 if (N->isTruncatingStore())
530 return DAG.getTruncStore(N->getChain(), dl,
531 GetScalarizedVector(N->getOperand(1)),
532 N->getBasePtr(), N->getPointerInfo(),
533 N->getMemoryVT().getVectorElementType(),
534 N->isVolatile(), N->isNonTemporal(),
535 N->getAlignment(), N->getAAInfo());
537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getOriginalAlignment(), N->getAAInfo());
543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
548 N->getValueType(0).getVectorElementType(), Elt,
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
553 //===----------------------------------------------------------------------===//
554 // Result Vector Splitting
555 //===----------------------------------------------------------------------===//
557 /// SplitVectorResult - This method is called when the specified result of the
558 /// specified node is found to need vector splitting. At this point, the node
559 /// may also have invalid operands or may have other results that need
560 /// legalization, we just know that (at least) one result needs vector
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
563 DEBUG(dbgs() << "Split node result: ";
568 // See if the target wants to custom expand this node.
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
572 switch (N->getOpcode()) {
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
579 report_fatal_error("Do not know how to split the result of this "
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
604 SplitVecRes_SETCC(N, Lo, Hi);
606 case ISD::VECTOR_SHUFFLE:
607 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
611 case ISD::CONVERT_RNDSAT:
614 case ISD::CTLZ_ZERO_UNDEF:
615 case ISD::CTTZ_ZERO_UNDEF:
626 case ISD::FNEARBYINT:
630 case ISD::FP_TO_SINT:
631 case ISD::FP_TO_UINT:
637 case ISD::SINT_TO_FP:
639 case ISD::UINT_TO_FP:
640 SplitVecRes_UnaryOp(N, Lo, Hi);
643 case ISD::ANY_EXTEND:
644 case ISD::SIGN_EXTEND:
645 case ISD::ZERO_EXTEND:
646 SplitVecRes_ExtendOp(N, Lo, Hi);
671 SplitVecRes_BinOp(N, Lo, Hi);
674 SplitVecRes_TernaryOp(N, Lo, Hi);
678 // If Lo/Hi is null, the sub-method took care of registering results etc.
680 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
683 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
685 SDValue LHSLo, LHSHi;
686 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
687 SDValue RHSLo, RHSHi;
688 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
691 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
692 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
695 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
697 SDValue Op0Lo, Op0Hi;
698 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
699 SDValue Op1Lo, Op1Hi;
700 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
701 SDValue Op2Lo, Op2Hi;
702 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
705 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
706 Op0Lo, Op1Lo, Op2Lo);
707 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
708 Op0Hi, Op1Hi, Op2Hi);
711 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
713 // We know the result is a vector. The input may be either a vector or a
716 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
719 SDValue InOp = N->getOperand(0);
720 EVT InVT = InOp.getValueType();
722 // Handle some special cases efficiently.
723 switch (getTypeAction(InVT)) {
724 case TargetLowering::TypeLegal:
725 case TargetLowering::TypePromoteInteger:
726 case TargetLowering::TypeSoftenFloat:
727 case TargetLowering::TypeScalarizeVector:
728 case TargetLowering::TypeWidenVector:
730 case TargetLowering::TypeExpandInteger:
731 case TargetLowering::TypeExpandFloat:
732 // A scalar to vector conversion, where the scalar needs expansion.
733 // If the vector is being split in two then we can just convert the
736 GetExpandedOp(InOp, Lo, Hi);
737 if (TLI.isBigEndian())
739 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
740 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
744 case TargetLowering::TypeSplitVector:
745 // If the input is a vector that needs to be split, convert each split
746 // piece of the input now.
747 GetSplitVector(InOp, Lo, Hi);
748 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
749 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
753 // In the general case, convert the input to an integer and split it by hand.
754 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
755 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
756 if (TLI.isBigEndian())
757 std::swap(LoIntVT, HiIntVT);
759 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
761 if (TLI.isBigEndian())
763 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
764 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
767 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
771 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
772 unsigned LoNumElts = LoVT.getVectorNumElements();
773 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
774 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
776 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
777 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
780 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
782 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
784 unsigned NumSubvectors = N->getNumOperands() / 2;
785 if (NumSubvectors == 1) {
786 Lo = N->getOperand(0);
787 Hi = N->getOperand(1);
792 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
794 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
795 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
797 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
798 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
801 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
803 SDValue Vec = N->getOperand(0);
804 SDValue Idx = N->getOperand(1);
808 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
810 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
811 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
812 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
813 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),
814 TLI.getVectorIdxTy()));
817 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
819 SDValue Vec = N->getOperand(0);
820 SDValue SubVec = N->getOperand(1);
821 SDValue Idx = N->getOperand(2);
823 GetSplitVector(Vec, Lo, Hi);
825 // Spill the vector to the stack.
826 EVT VecVT = Vec.getValueType();
827 EVT SubVecVT = VecVT.getVectorElementType();
828 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
829 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
830 MachinePointerInfo(), false, false, 0);
832 // Store the new subvector into the specified index.
833 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
834 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
835 unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
836 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
839 // Load the Lo part from the stack slot.
840 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
841 false, false, false, 0);
843 // Increment the pointer to the other part.
844 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
846 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
847 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
849 // Load the Hi part from the stack slot.
850 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
851 false, false, false, MinAlign(Alignment, IncrementSize));
854 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
857 GetSplitVector(N->getOperand(0), Lo, Hi);
858 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
859 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
862 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
864 SDValue LHSLo, LHSHi;
865 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
869 std::tie(LoVT, HiVT) =
870 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
872 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
873 DAG.getValueType(LoVT));
874 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
875 DAG.getValueType(HiVT));
878 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
880 SDValue Vec = N->getOperand(0);
881 SDValue Elt = N->getOperand(1);
882 SDValue Idx = N->getOperand(2);
884 GetSplitVector(Vec, Lo, Hi);
886 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
887 unsigned IdxVal = CIdx->getZExtValue();
888 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
889 if (IdxVal < LoNumElts)
890 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
891 Lo.getValueType(), Lo, Elt, Idx);
893 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
894 DAG.getConstant(IdxVal - LoNumElts,
895 TLI.getVectorIdxTy()));
899 // See if the target wants to custom expand this node.
900 if (CustomLowerNode(N, N->getValueType(0), true))
903 // Spill the vector to the stack.
904 EVT VecVT = Vec.getValueType();
905 EVT EltVT = VecVT.getVectorElementType();
906 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
907 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
908 MachinePointerInfo(), false, false, 0);
910 // Store the new element. This may be larger than the vector element type,
911 // so use a truncating store.
912 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
913 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
915 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
916 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
919 // Load the Lo part from the stack slot.
920 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
921 false, false, false, 0);
923 // Increment the pointer to the other part.
924 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
925 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
926 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
928 // Load the Hi part from the stack slot.
929 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
930 false, false, false, MinAlign(Alignment, IncrementSize));
933 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
937 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
938 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
939 Hi = DAG.getUNDEF(HiVT);
942 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
944 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
947 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
949 ISD::LoadExtType ExtType = LD->getExtensionType();
950 SDValue Ch = LD->getChain();
951 SDValue Ptr = LD->getBasePtr();
952 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
953 EVT MemoryVT = LD->getMemoryVT();
954 unsigned Alignment = LD->getOriginalAlignment();
955 bool isVolatile = LD->isVolatile();
956 bool isNonTemporal = LD->isNonTemporal();
957 bool isInvariant = LD->isInvariant();
958 AAMDNodes AAInfo = LD->getAAInfo();
960 EVT LoMemVT, HiMemVT;
961 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
963 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
964 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
965 isInvariant, Alignment, AAInfo);
967 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
968 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
969 DAG.getConstant(IncrementSize, Ptr.getValueType()));
970 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
971 LD->getPointerInfo().getWithOffset(IncrementSize),
972 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
975 // Build a factor node to remember that this load is independent of the
977 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
980 // Legalized the chain result - switch anything that used the old chain to
982 ReplaceValueWith(SDValue(LD, 1), Ch);
985 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
986 SDValue &Lo, SDValue &Hi) {
989 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
991 SDValue Ch = MLD->getChain();
992 SDValue Ptr = MLD->getBasePtr();
993 SDValue Mask = MLD->getMask();
994 unsigned Alignment = MLD->getOriginalAlignment();
995 ISD::LoadExtType ExtType = MLD->getExtensionType();
997 // if Alignment is equal to the vector size,
998 // take the half of it for the second part
999 unsigned SecondHalfAlignment =
1000 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1001 Alignment/2 : Alignment;
1003 SDValue MaskLo, MaskHi;
1004 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1006 EVT MemoryVT = MLD->getMemoryVT();
1007 EVT LoMemVT, HiMemVT;
1008 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1010 SDValue Src0 = MLD->getSrc0();
1011 SDValue Src0Lo, Src0Hi;
1012 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1014 MachineMemOperand *MMO = DAG.getMachineFunction().
1015 getMachineMemOperand(MLD->getPointerInfo(),
1016 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1017 Alignment, MLD->getAAInfo(), MLD->getRanges());
1019 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1022 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1023 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1024 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1026 MMO = DAG.getMachineFunction().
1027 getMachineMemOperand(MLD->getPointerInfo(),
1028 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1029 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1031 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1035 // Build a factor node to remember that this load is independent of the
1037 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1040 // Legalized the chain result - switch anything that used the old chain to
1042 ReplaceValueWith(SDValue(MLD, 1), Ch);
1046 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1047 assert(N->getValueType(0).isVector() &&
1048 N->getOperand(0).getValueType().isVector() &&
1049 "Operand types must be vectors");
1053 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1056 SDValue LL, LH, RL, RH;
1057 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1058 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1060 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1061 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1064 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1066 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1069 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1071 // If the input also splits, handle it directly for a compile time speedup.
1072 // Otherwise split it by hand.
1073 EVT InVT = N->getOperand(0).getValueType();
1074 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1075 GetSplitVector(N->getOperand(0), Lo, Hi);
1077 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1079 if (N->getOpcode() == ISD::FP_ROUND) {
1080 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1081 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1082 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1083 SDValue DTyOpLo = DAG.getValueType(LoVT);
1084 SDValue DTyOpHi = DAG.getValueType(HiVT);
1085 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1086 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1087 SDValue RndOp = N->getOperand(3);
1088 SDValue SatOp = N->getOperand(4);
1089 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1090 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1092 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1095 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1096 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1100 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1103 EVT SrcVT = N->getOperand(0).getValueType();
1104 EVT DestVT = N->getValueType(0);
1106 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1108 // We can do better than a generic split operation if the extend is doing
1109 // more than just doubling the width of the elements and the following are
1111 // - The number of vector elements is even,
1112 // - the source type is legal,
1113 // - the type of a split source is illegal,
1114 // - the type of an extended (by doubling element size) source is legal, and
1115 // - the type of that extended source when split is legal.
1117 // This won't necessarily completely legalize the operation, but it will
1118 // more effectively move in the right direction and prevent falling down
1119 // to scalarization in many cases due to the input vector being split too
1121 unsigned NumElements = SrcVT.getVectorNumElements();
1122 if ((NumElements & 1) == 0 &&
1123 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1124 LLVMContext &Ctx = *DAG.getContext();
1125 EVT NewSrcVT = EVT::getVectorVT(
1126 Ctx, EVT::getIntegerVT(
1127 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1130 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1131 EVT SplitLoVT, SplitHiVT;
1132 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1133 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1134 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1135 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1136 N->dump(&DAG); dbgs() << "\n");
1137 // Extend the source vector by one step.
1139 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1140 // Get the low and high halves of the new, extended one step, vector.
1141 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1142 // Extend those vector halves the rest of the way.
1143 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1144 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1148 // Fall back to the generic unary operator splitting otherwise.
1149 SplitVecRes_UnaryOp(N, Lo, Hi);
1152 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1153 SDValue &Lo, SDValue &Hi) {
1154 // The low and high parts of the original input give four input vectors.
1157 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1158 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1159 EVT NewVT = Inputs[0].getValueType();
1160 unsigned NewElts = NewVT.getVectorNumElements();
1162 // If Lo or Hi uses elements from at most two of the four input vectors, then
1163 // express it as a vector shuffle of those two inputs. Otherwise extract the
1164 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1165 SmallVector<int, 16> Ops;
1166 for (unsigned High = 0; High < 2; ++High) {
1167 SDValue &Output = High ? Hi : Lo;
1169 // Build a shuffle mask for the output, discovering on the fly which
1170 // input vectors to use as shuffle operands (recorded in InputUsed).
1171 // If building a suitable shuffle vector proves too hard, then bail
1172 // out with useBuildVector set.
1173 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1174 unsigned FirstMaskIdx = High * NewElts;
1175 bool useBuildVector = false;
1176 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1177 // The mask element. This indexes into the input.
1178 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1180 // The input vector this mask element indexes into.
1181 unsigned Input = (unsigned)Idx / NewElts;
1183 if (Input >= array_lengthof(Inputs)) {
1184 // The mask element does not index into any input vector.
1189 // Turn the index into an offset from the start of the input vector.
1190 Idx -= Input * NewElts;
1192 // Find or create a shuffle vector operand to hold this input.
1194 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1195 if (InputUsed[OpNo] == Input) {
1196 // This input vector is already an operand.
1198 } else if (InputUsed[OpNo] == -1U) {
1199 // Create a new operand for this input vector.
1200 InputUsed[OpNo] = Input;
1205 if (OpNo >= array_lengthof(InputUsed)) {
1206 // More than two input vectors used! Give up on trying to create a
1207 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1208 useBuildVector = true;
1212 // Add the mask index for the new shuffle vector.
1213 Ops.push_back(Idx + OpNo * NewElts);
1216 if (useBuildVector) {
1217 EVT EltVT = NewVT.getVectorElementType();
1218 SmallVector<SDValue, 16> SVOps;
1220 // Extract the input elements by hand.
1221 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1222 // The mask element. This indexes into the input.
1223 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1225 // The input vector this mask element indexes into.
1226 unsigned Input = (unsigned)Idx / NewElts;
1228 if (Input >= array_lengthof(Inputs)) {
1229 // The mask element is "undef" or indexes off the end of the input.
1230 SVOps.push_back(DAG.getUNDEF(EltVT));
1234 // Turn the index into an offset from the start of the input vector.
1235 Idx -= Input * NewElts;
1237 // Extract the vector element by hand.
1238 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1239 Inputs[Input], DAG.getConstant(Idx,
1240 TLI.getVectorIdxTy())));
1243 // Construct the Lo/Hi output using a BUILD_VECTOR.
1244 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1245 } else if (InputUsed[0] == -1U) {
1246 // No input vectors were used! The result is undefined.
1247 Output = DAG.getUNDEF(NewVT);
1249 SDValue Op0 = Inputs[InputUsed[0]];
1250 // If only one input was used, use an undefined vector for the other.
1251 SDValue Op1 = InputUsed[1] == -1U ?
1252 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1253 // At least one input vector was used. Create a new shuffle vector.
1254 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1262 //===----------------------------------------------------------------------===//
1263 // Operand Vector Splitting
1264 //===----------------------------------------------------------------------===//
1266 /// SplitVectorOperand - This method is called when the specified operand of the
1267 /// specified node is found to need vector splitting. At this point, all of the
1268 /// result types of the node are known to be legal, but other operands of the
1269 /// node may need legalization as well as the specified one.
1270 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1271 DEBUG(dbgs() << "Split node operand: ";
1274 SDValue Res = SDValue();
1276 // See if the target wants to custom split this node.
1277 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1280 if (!Res.getNode()) {
1281 switch (N->getOpcode()) {
1284 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1288 report_fatal_error("Do not know how to split this operator's "
1291 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1292 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1293 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1294 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1295 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1296 case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break;
1297 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1299 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1302 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1305 Res = SplitVecOp_VSELECT(N, OpNo);
1310 case ISD::FP_EXTEND:
1311 case ISD::FP_TO_SINT:
1312 case ISD::FP_TO_UINT:
1313 case ISD::SINT_TO_FP:
1314 case ISD::UINT_TO_FP:
1316 case ISD::SIGN_EXTEND:
1317 case ISD::ZERO_EXTEND:
1318 case ISD::ANY_EXTEND:
1319 Res = SplitVecOp_UnaryOp(N);
1324 // If the result is null, the sub-method took care of registering results etc.
1325 if (!Res.getNode()) return false;
1327 // If the result is N, the sub-method updated N in place. Tell the legalizer
1329 if (Res.getNode() == N)
1332 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1333 "Invalid operand expansion");
1335 ReplaceValueWith(SDValue(N, 0), Res);
1339 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1340 // The only possibility for an illegal operand is the mask, since result type
1341 // legalization would have handled this node already otherwise.
1342 assert(OpNo == 0 && "Illegal operand must be mask");
1344 SDValue Mask = N->getOperand(0);
1345 SDValue Src0 = N->getOperand(1);
1346 SDValue Src1 = N->getOperand(2);
1347 EVT Src0VT = Src0.getValueType();
1349 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1352 GetSplitVector(N->getOperand(0), Lo, Hi);
1353 assert(Lo.getValueType() == Hi.getValueType() &&
1354 "Lo and Hi have differing types");
1357 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1358 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1360 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1361 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1362 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1363 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1366 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1368 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1370 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1373 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1374 // The result has a legal vector type, but the input needs splitting.
1375 EVT ResVT = N->getValueType(0);
1378 GetSplitVector(N->getOperand(0), Lo, Hi);
1379 EVT InVT = Lo.getValueType();
1381 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1382 InVT.getVectorNumElements());
1384 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1385 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1387 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1390 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1391 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1392 // end up being split all the way down to individual components. Convert the
1393 // split pieces into integers and reassemble.
1395 GetSplitVector(N->getOperand(0), Lo, Hi);
1396 Lo = BitConvertToInteger(Lo);
1397 Hi = BitConvertToInteger(Hi);
1399 if (TLI.isBigEndian())
1402 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1403 JoinIntegers(Lo, Hi));
1406 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1407 // We know that the extracted result type is legal.
1408 EVT SubVT = N->getValueType(0);
1409 SDValue Idx = N->getOperand(1);
1412 GetSplitVector(N->getOperand(0), Lo, Hi);
1414 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1415 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1417 if (IdxVal < LoElts) {
1418 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1419 "Extracted subvector crosses vector split!");
1420 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1422 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1423 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1427 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1428 SDValue Vec = N->getOperand(0);
1429 SDValue Idx = N->getOperand(1);
1430 EVT VecVT = Vec.getValueType();
1432 if (isa<ConstantSDNode>(Idx)) {
1433 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1434 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1437 GetSplitVector(Vec, Lo, Hi);
1439 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1441 if (IdxVal < LoElts)
1442 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1443 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1444 DAG.getConstant(IdxVal - LoElts,
1445 Idx.getValueType())), 0);
1448 // See if the target wants to custom expand this node.
1449 if (CustomLowerNode(N, N->getValueType(0), true))
1452 // Store the vector to the stack.
1453 EVT EltVT = VecVT.getVectorElementType();
1455 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1456 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1457 MachinePointerInfo(), false, false, 0);
1459 // Load back the required element.
1460 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1461 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1462 MachinePointerInfo(), EltVT, false, false, false, 0);
1465 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1467 SDValue Ch = N->getChain();
1468 SDValue Ptr = N->getBasePtr();
1469 SDValue Mask = N->getMask();
1470 SDValue Data = N->getValue();
1471 EVT MemoryVT = N->getMemoryVT();
1472 unsigned Alignment = N->getOriginalAlignment();
1475 EVT LoMemVT, HiMemVT;
1476 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1478 SDValue DataLo, DataHi;
1479 GetSplitVector(Data, DataLo, DataHi);
1480 SDValue MaskLo, MaskHi;
1481 GetSplitVector(Mask, MaskLo, MaskHi);
1483 // if Alignment is equal to the vector size,
1484 // take the half of it for the second part
1485 unsigned SecondHalfAlignment =
1486 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1487 Alignment/2 : Alignment;
1490 MachineMemOperand *MMO = DAG.getMachineFunction().
1491 getMachineMemOperand(N->getPointerInfo(),
1492 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1493 Alignment, N->getAAInfo(), N->getRanges());
1495 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1496 N->isTruncatingStore());
1498 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1499 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1500 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1502 MMO = DAG.getMachineFunction().
1503 getMachineMemOperand(N->getPointerInfo(),
1504 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1505 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1507 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1508 N->isTruncatingStore());
1511 // Build a factor node to remember that this store is independent of the
1513 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1517 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1518 assert(N->isUnindexed() && "Indexed store of vector?");
1519 assert(OpNo == 1 && "Can only split the stored value");
1522 bool isTruncating = N->isTruncatingStore();
1523 SDValue Ch = N->getChain();
1524 SDValue Ptr = N->getBasePtr();
1525 EVT MemoryVT = N->getMemoryVT();
1526 unsigned Alignment = N->getOriginalAlignment();
1527 bool isVol = N->isVolatile();
1528 bool isNT = N->isNonTemporal();
1529 AAMDNodes AAInfo = N->getAAInfo();
1531 GetSplitVector(N->getOperand(1), Lo, Hi);
1533 EVT LoMemVT, HiMemVT;
1534 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1536 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1539 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1540 LoMemVT, isVol, isNT, Alignment, AAInfo);
1542 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1543 isVol, isNT, Alignment, AAInfo);
1545 // Increment the pointer to the other half.
1546 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1547 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1550 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1551 N->getPointerInfo().getWithOffset(IncrementSize),
1552 HiMemVT, isVol, isNT, Alignment, AAInfo);
1554 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1555 N->getPointerInfo().getWithOffset(IncrementSize),
1556 isVol, isNT, Alignment, AAInfo);
1558 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1561 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1564 // The input operands all must have the same type, and we know the result
1565 // type is valid. Convert this to a buildvector which extracts all the
1567 // TODO: If the input elements are power-two vectors, we could convert this to
1568 // a new CONCAT_VECTORS node with elements that are half-wide.
1569 SmallVector<SDValue, 32> Elts;
1570 EVT EltVT = N->getValueType(0).getVectorElementType();
1571 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1572 SDValue Op = N->getOperand(op);
1573 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1575 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1576 Op, DAG.getConstant(i, TLI.getVectorIdxTy())));
1581 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1584 SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {
1585 // The result type is legal, but the input type is illegal. If splitting
1586 // ends up with the result type of each half still being legal, just
1587 // do that. If, however, that would result in an illegal result type,
1588 // we can try to get more clever with power-two vectors. Specifically,
1589 // split the input type, but also widen the result element size, then
1590 // concatenate the halves and truncate again. For example, consider a target
1591 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1592 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1593 // %inlo = v4i32 extract_subvector %in, 0
1594 // %inhi = v4i32 extract_subvector %in, 4
1595 // %lo16 = v4i16 trunc v4i32 %inlo
1596 // %hi16 = v4i16 trunc v4i32 %inhi
1597 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1598 // %res = v8i8 trunc v8i16 %in16
1600 // Without this transform, the original truncate would end up being
1601 // scalarized, which is pretty much always a last resort.
1602 SDValue InVec = N->getOperand(0);
1603 EVT InVT = InVec->getValueType(0);
1604 EVT OutVT = N->getValueType(0);
1605 unsigned NumElements = OutVT.getVectorNumElements();
1606 // Widening should have already made sure this is a power-two vector
1607 // if we're trying to split it at all. assert() that's true, just in case.
1608 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1610 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1611 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1613 // If the input elements are only 1/2 the width of the result elements,
1614 // just use the normal splitting. Our trick only work if there's room
1615 // to split more than once.
1616 if (InElementSize <= OutElementSize * 2)
1617 return SplitVecOp_UnaryOp(N);
1620 // Extract the halves of the input via extract_subvector.
1621 SDValue InLoVec, InHiVec;
1622 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1623 // Truncate them to 1/2 the element size.
1624 EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1625 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1627 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec);
1628 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);
1629 // Concatenate them to get the full intermediate truncation result.
1630 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1631 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1633 // Now finish up by truncating all the way down to the original result
1634 // type. This should normally be something that ends up being legal directly,
1635 // but in theory if a target has very wide vectors and an annoyingly
1636 // restricted set of legal types, this split can chain to build things up.
1637 return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1640 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1641 assert(N->getValueType(0).isVector() &&
1642 N->getOperand(0).getValueType().isVector() &&
1643 "Operand types must be vectors");
1644 // The result has a legal vector type, but the input needs splitting.
1645 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1647 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1648 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1649 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1650 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1651 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1653 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1654 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1655 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1656 return PromoteTargetBoolean(Con, N->getValueType(0));
1660 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1661 // The result has a legal vector type, but the input needs splitting.
1662 EVT ResVT = N->getValueType(0);
1665 GetSplitVector(N->getOperand(0), Lo, Hi);
1666 EVT InVT = Lo.getValueType();
1668 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1669 InVT.getVectorNumElements());
1671 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1672 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1674 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1679 //===----------------------------------------------------------------------===//
1680 // Result Vector Widening
1681 //===----------------------------------------------------------------------===//
1683 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1684 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1688 // See if the target wants to custom widen this node.
1689 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1692 SDValue Res = SDValue();
1693 switch (N->getOpcode()) {
1696 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1700 llvm_unreachable("Do not know how to widen the result of this operator!");
1702 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1703 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1704 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1705 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1706 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1707 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1708 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1709 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1710 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1711 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1712 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1714 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1715 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1716 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1717 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1718 case ISD::VECTOR_SHUFFLE:
1719 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1722 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1735 Res = WidenVecRes_Binary(N);
1739 case ISD::FCOPYSIGN:
1749 Res = WidenVecRes_BinaryCanTrap(N);
1753 Res = WidenVecRes_POWI(N);
1759 Res = WidenVecRes_Shift(N);
1762 case ISD::ANY_EXTEND:
1763 case ISD::FP_EXTEND:
1765 case ISD::FP_TO_SINT:
1766 case ISD::FP_TO_UINT:
1767 case ISD::SIGN_EXTEND:
1768 case ISD::SINT_TO_FP:
1770 case ISD::UINT_TO_FP:
1771 case ISD::ZERO_EXTEND:
1772 Res = WidenVecRes_Convert(N);
1788 case ISD::FNEARBYINT:
1795 Res = WidenVecRes_Unary(N);
1798 Res = WidenVecRes_Ternary(N);
1802 // If Res is null, the sub-method took care of registering the result.
1804 SetWidenedVector(SDValue(N, ResNo), Res);
1807 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
1808 // Ternary op widening.
1810 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1811 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1812 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1813 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
1814 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
1817 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1818 // Binary op widening.
1820 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1821 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1822 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1823 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1826 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
1827 // Binary op widening for operations that can trap.
1828 unsigned Opcode = N->getOpcode();
1830 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1831 EVT WidenEltVT = WidenVT.getVectorElementType();
1833 unsigned NumElts = VT.getVectorNumElements();
1834 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1835 NumElts = NumElts / 2;
1836 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1839 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1840 // Operation doesn't trap so just widen as normal.
1841 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1842 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1843 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1846 // No legal vector version so unroll the vector operation and then widen.
1848 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1850 // Since the operation can trap, apply operation on the original vector.
1852 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1853 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1854 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1856 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1857 unsigned ConcatEnd = 0; // Current ConcatOps index.
1858 int Idx = 0; // Current Idx into input vectors.
1860 // NumElts := greatest legal vector size (at most WidenVT)
1861 // while (orig. vector has unhandled elements) {
1862 // take munches of size NumElts from the beginning and add to ConcatOps
1863 // NumElts := next smaller supported vector size or 1
1865 while (CurNumElts != 0) {
1866 while (CurNumElts >= NumElts) {
1867 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1868 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1869 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1870 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1871 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1873 CurNumElts -= NumElts;
1876 NumElts = NumElts / 2;
1877 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1878 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1881 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1882 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1883 InOp1, DAG.getConstant(Idx,
1884 TLI.getVectorIdxTy()));
1885 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1886 InOp2, DAG.getConstant(Idx,
1887 TLI.getVectorIdxTy()));
1888 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1895 // Check to see if we have a single operation with the widen type.
1896 if (ConcatEnd == 1) {
1897 VT = ConcatOps[0].getValueType();
1899 return ConcatOps[0];
1902 // while (Some element of ConcatOps is not of type MaxVT) {
1903 // From the end of ConcatOps, collect elements of the same type and put
1904 // them into an op of the next larger supported type
1906 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1907 Idx = ConcatEnd - 1;
1908 VT = ConcatOps[Idx--].getValueType();
1909 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1912 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1916 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1917 } while (!TLI.isTypeLegal(NextVT));
1919 if (!VT.isVector()) {
1920 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1921 SDValue VecOp = DAG.getUNDEF(NextVT);
1922 unsigned NumToInsert = ConcatEnd - Idx - 1;
1923 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1924 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1925 ConcatOps[OpIdx], DAG.getConstant(i,
1926 TLI.getVectorIdxTy()));
1928 ConcatOps[Idx+1] = VecOp;
1929 ConcatEnd = Idx + 2;
1931 // Vector type, create a CONCAT_VECTORS of type NextVT
1932 SDValue undefVec = DAG.getUNDEF(VT);
1933 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1934 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1935 unsigned RealVals = ConcatEnd - Idx - 1;
1936 unsigned SubConcatEnd = 0;
1937 unsigned SubConcatIdx = Idx + 1;
1938 while (SubConcatEnd < RealVals)
1939 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1940 while (SubConcatEnd < OpsToConcat)
1941 SubConcatOps[SubConcatEnd++] = undefVec;
1942 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1943 NextVT, SubConcatOps);
1944 ConcatEnd = SubConcatIdx + 1;
1948 // Check to see if we have a single operation with the widen type.
1949 if (ConcatEnd == 1) {
1950 VT = ConcatOps[0].getValueType();
1952 return ConcatOps[0];
1955 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1956 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1957 if (NumOps != ConcatEnd ) {
1958 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1959 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1960 ConcatOps[j] = UndefVal;
1962 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
1963 makeArrayRef(ConcatOps.data(), NumOps));
1966 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1967 SDValue InOp = N->getOperand(0);
1970 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1971 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1973 EVT InVT = InOp.getValueType();
1974 EVT InEltVT = InVT.getVectorElementType();
1975 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1977 unsigned Opcode = N->getOpcode();
1978 unsigned InVTNumElts = InVT.getVectorNumElements();
1980 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1981 InOp = GetWidenedVector(N->getOperand(0));
1982 InVT = InOp.getValueType();
1983 InVTNumElts = InVT.getVectorNumElements();
1984 if (InVTNumElts == WidenNumElts) {
1985 if (N->getNumOperands() == 1)
1986 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1987 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1991 if (TLI.isTypeLegal(InWidenVT)) {
1992 // Because the result and the input are different vector types, widening
1993 // the result could create a legal type but widening the input might make
1994 // it an illegal type that might lead to repeatedly splitting the input
1995 // and then widening it. To avoid this, we widen the input only if
1996 // it results in a legal type.
1997 if (WidenNumElts % InVTNumElts == 0) {
1998 // Widen the input and call convert on the widened input vector.
1999 unsigned NumConcat = WidenNumElts/InVTNumElts;
2000 SmallVector<SDValue, 16> Ops(NumConcat);
2002 SDValue UndefVal = DAG.getUNDEF(InVT);
2003 for (unsigned i = 1; i != NumConcat; ++i)
2005 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2006 if (N->getNumOperands() == 1)
2007 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2008 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2011 if (InVTNumElts % WidenNumElts == 0) {
2012 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
2013 InOp, DAG.getConstant(0,
2014 TLI.getVectorIdxTy()));
2015 // Extract the input and convert the shorten input vector.
2016 if (N->getNumOperands() == 1)
2017 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2018 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2022 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2023 SmallVector<SDValue, 16> Ops(WidenNumElts);
2024 EVT EltVT = WidenVT.getVectorElementType();
2025 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2027 for (i=0; i < MinElts; ++i) {
2028 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2029 DAG.getConstant(i, TLI.getVectorIdxTy()));
2030 if (N->getNumOperands() == 1)
2031 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2033 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2036 SDValue UndefVal = DAG.getUNDEF(EltVT);
2037 for (; i < WidenNumElts; ++i)
2040 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2043 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2044 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2045 SDValue InOp = GetWidenedVector(N->getOperand(0));
2046 SDValue ShOp = N->getOperand(1);
2047 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2050 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2051 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2052 SDValue InOp = GetWidenedVector(N->getOperand(0));
2053 SDValue ShOp = N->getOperand(1);
2055 EVT ShVT = ShOp.getValueType();
2056 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2057 ShOp = GetWidenedVector(ShOp);
2058 ShVT = ShOp.getValueType();
2060 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2061 ShVT.getVectorElementType(),
2062 WidenVT.getVectorNumElements());
2063 if (ShVT != ShWidenVT)
2064 ShOp = ModifyToType(ShOp, ShWidenVT);
2066 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2069 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2070 // Unary op widening.
2071 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2072 SDValue InOp = GetWidenedVector(N->getOperand(0));
2073 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2076 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2077 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2078 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2079 cast<VTSDNode>(N->getOperand(1))->getVT()
2080 .getVectorElementType(),
2081 WidenVT.getVectorNumElements());
2082 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2083 return DAG.getNode(N->getOpcode(), SDLoc(N),
2084 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2087 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2088 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2089 return GetWidenedVector(WidenVec);
2092 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2093 SDValue InOp = N->getOperand(0);
2094 EVT InVT = InOp.getValueType();
2095 EVT VT = N->getValueType(0);
2096 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2099 switch (getTypeAction(InVT)) {
2100 case TargetLowering::TypeLegal:
2102 case TargetLowering::TypePromoteInteger:
2103 // If the incoming type is a vector that is being promoted, then
2104 // we know that the elements are arranged differently and that we
2105 // must perform the conversion using a stack slot.
2106 if (InVT.isVector())
2109 // If the InOp is promoted to the same size, convert it. Otherwise,
2110 // fall out of the switch and widen the promoted input.
2111 InOp = GetPromotedInteger(InOp);
2112 InVT = InOp.getValueType();
2113 if (WidenVT.bitsEq(InVT))
2114 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2116 case TargetLowering::TypeSoftenFloat:
2117 case TargetLowering::TypeExpandInteger:
2118 case TargetLowering::TypeExpandFloat:
2119 case TargetLowering::TypeScalarizeVector:
2120 case TargetLowering::TypeSplitVector:
2122 case TargetLowering::TypeWidenVector:
2123 // If the InOp is widened to the same size, convert it. Otherwise, fall
2124 // out of the switch and widen the widened input.
2125 InOp = GetWidenedVector(InOp);
2126 InVT = InOp.getValueType();
2127 if (WidenVT.bitsEq(InVT))
2128 // The input widens to the same size. Convert to the widen value.
2129 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2133 unsigned WidenSize = WidenVT.getSizeInBits();
2134 unsigned InSize = InVT.getSizeInBits();
2135 // x86mmx is not an acceptable vector element type, so don't try.
2136 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2137 // Determine new input vector type. The new input vector type will use
2138 // the same element type (if its a vector) or use the input type as a
2139 // vector. It is the same size as the type to widen to.
2141 unsigned NewNumElts = WidenSize / InSize;
2142 if (InVT.isVector()) {
2143 EVT InEltVT = InVT.getVectorElementType();
2144 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2145 WidenSize / InEltVT.getSizeInBits());
2147 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2150 if (TLI.isTypeLegal(NewInVT)) {
2151 // Because the result and the input are different vector types, widening
2152 // the result could create a legal type but widening the input might make
2153 // it an illegal type that might lead to repeatedly splitting the input
2154 // and then widening it. To avoid this, we widen the input only if
2155 // it results in a legal type.
2156 SmallVector<SDValue, 16> Ops(NewNumElts);
2157 SDValue UndefVal = DAG.getUNDEF(InVT);
2159 for (unsigned i = 1; i < NewNumElts; ++i)
2163 if (InVT.isVector())
2164 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2166 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2167 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2171 return CreateStackStoreLoad(InOp, WidenVT);
2174 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2176 // Build a vector with undefined for the new nodes.
2177 EVT VT = N->getValueType(0);
2179 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2180 // type. The UNDEFs need to have the same type as the existing operands.
2181 EVT EltVT = N->getOperand(0).getValueType();
2182 unsigned NumElts = VT.getVectorNumElements();
2184 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2185 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2187 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2188 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2189 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2191 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2194 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2195 EVT InVT = N->getOperand(0).getValueType();
2196 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2198 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2199 unsigned NumInElts = InVT.getVectorNumElements();
2200 unsigned NumOperands = N->getNumOperands();
2202 bool InputWidened = false; // Indicates we need to widen the input.
2203 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2204 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2205 // Add undef vectors to widen to correct length.
2206 unsigned NumConcat = WidenVT.getVectorNumElements() /
2207 InVT.getVectorNumElements();
2208 SDValue UndefVal = DAG.getUNDEF(InVT);
2209 SmallVector<SDValue, 16> Ops(NumConcat);
2210 for (unsigned i=0; i < NumOperands; ++i)
2211 Ops[i] = N->getOperand(i);
2212 for (unsigned i = NumOperands; i != NumConcat; ++i)
2214 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2217 InputWidened = true;
2218 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2219 // The inputs and the result are widen to the same value.
2221 for (i=1; i < NumOperands; ++i)
2222 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2225 if (i == NumOperands)
2226 // Everything but the first operand is an UNDEF so just return the
2227 // widened first operand.
2228 return GetWidenedVector(N->getOperand(0));
2230 if (NumOperands == 2) {
2231 // Replace concat of two operands with a shuffle.
2232 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2233 for (unsigned i = 0; i < NumInElts; ++i) {
2235 MaskOps[i + NumInElts] = i + WidenNumElts;
2237 return DAG.getVectorShuffle(WidenVT, dl,
2238 GetWidenedVector(N->getOperand(0)),
2239 GetWidenedVector(N->getOperand(1)),
2245 // Fall back to use extracts and build vector.
2246 EVT EltVT = WidenVT.getVectorElementType();
2247 SmallVector<SDValue, 16> Ops(WidenNumElts);
2249 for (unsigned i=0; i < NumOperands; ++i) {
2250 SDValue InOp = N->getOperand(i);
2252 InOp = GetWidenedVector(InOp);
2253 for (unsigned j=0; j < NumInElts; ++j)
2254 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2255 DAG.getConstant(j, TLI.getVectorIdxTy()));
2257 SDValue UndefVal = DAG.getUNDEF(EltVT);
2258 for (; Idx < WidenNumElts; ++Idx)
2259 Ops[Idx] = UndefVal;
2260 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2263 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2265 SDValue InOp = N->getOperand(0);
2266 SDValue RndOp = N->getOperand(3);
2267 SDValue SatOp = N->getOperand(4);
2269 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2270 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2272 EVT InVT = InOp.getValueType();
2273 EVT InEltVT = InVT.getVectorElementType();
2274 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2276 SDValue DTyOp = DAG.getValueType(WidenVT);
2277 SDValue STyOp = DAG.getValueType(InWidenVT);
2278 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2280 unsigned InVTNumElts = InVT.getVectorNumElements();
2281 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2282 InOp = GetWidenedVector(InOp);
2283 InVT = InOp.getValueType();
2284 InVTNumElts = InVT.getVectorNumElements();
2285 if (InVTNumElts == WidenNumElts)
2286 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2290 if (TLI.isTypeLegal(InWidenVT)) {
2291 // Because the result and the input are different vector types, widening
2292 // the result could create a legal type but widening the input might make
2293 // it an illegal type that might lead to repeatedly splitting the input
2294 // and then widening it. To avoid this, we widen the input only if
2295 // it results in a legal type.
2296 if (WidenNumElts % InVTNumElts == 0) {
2297 // Widen the input and call convert on the widened input vector.
2298 unsigned NumConcat = WidenNumElts/InVTNumElts;
2299 SmallVector<SDValue, 16> Ops(NumConcat);
2301 SDValue UndefVal = DAG.getUNDEF(InVT);
2302 for (unsigned i = 1; i != NumConcat; ++i)
2305 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2306 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2310 if (InVTNumElts % WidenNumElts == 0) {
2311 // Extract the input and convert the shorten input vector.
2312 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2313 DAG.getConstant(0, TLI.getVectorIdxTy()));
2314 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2319 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2320 SmallVector<SDValue, 16> Ops(WidenNumElts);
2321 EVT EltVT = WidenVT.getVectorElementType();
2322 DTyOp = DAG.getValueType(EltVT);
2323 STyOp = DAG.getValueType(InEltVT);
2325 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2327 for (i=0; i < MinElts; ++i) {
2328 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2329 DAG.getConstant(i, TLI.getVectorIdxTy()));
2330 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2334 SDValue UndefVal = DAG.getUNDEF(EltVT);
2335 for (; i < WidenNumElts; ++i)
2338 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2341 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2342 EVT VT = N->getValueType(0);
2343 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2344 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2345 SDValue InOp = N->getOperand(0);
2346 SDValue Idx = N->getOperand(1);
2349 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2350 InOp = GetWidenedVector(InOp);
2352 EVT InVT = InOp.getValueType();
2354 // Check if we can just return the input vector after widening.
2355 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2356 if (IdxVal == 0 && InVT == WidenVT)
2359 // Check if we can extract from the vector.
2360 unsigned InNumElts = InVT.getVectorNumElements();
2361 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2362 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2364 // We could try widening the input to the right length but for now, extract
2365 // the original elements, fill the rest with undefs and build a vector.
2366 SmallVector<SDValue, 16> Ops(WidenNumElts);
2367 EVT EltVT = VT.getVectorElementType();
2368 unsigned NumElts = VT.getVectorNumElements();
2370 for (i=0; i < NumElts; ++i)
2371 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2372 DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));
2374 SDValue UndefVal = DAG.getUNDEF(EltVT);
2375 for (; i < WidenNumElts; ++i)
2377 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2380 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2381 SDValue InOp = GetWidenedVector(N->getOperand(0));
2382 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2383 InOp.getValueType(), InOp,
2384 N->getOperand(1), N->getOperand(2));
2387 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2388 LoadSDNode *LD = cast<LoadSDNode>(N);
2389 ISD::LoadExtType ExtType = LD->getExtensionType();
2392 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2393 if (ExtType != ISD::NON_EXTLOAD)
2394 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2396 Result = GenWidenVectorLoads(LdChain, LD);
2398 // If we generate a single load, we can use that for the chain. Otherwise,
2399 // build a factor node to remember the multiple loads are independent and
2402 if (LdChain.size() == 1)
2403 NewChain = LdChain[0];
2405 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2407 // Modified the chain - switch anything that used the old chain to use
2409 ReplaceValueWith(SDValue(N, 1), NewChain);
2414 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2416 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2417 SDValue Mask = N->getMask();
2418 EVT MaskVT = Mask.getValueType();
2419 SDValue Src0 = GetWidenedVector(N->getSrc0());
2420 ISD::LoadExtType ExtType = N->getExtensionType();
2423 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2424 Mask = GetWidenedVector(Mask);
2426 EVT BoolVT = getSetCCResultType(WidenVT);
2428 // We can't use ModifyToType() because we should fill the mask with
2430 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2431 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2433 unsigned NumConcat = WidenNumElts / MaskNumElts;
2434 SmallVector<SDValue, 16> Ops(NumConcat);
2435 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
2437 for (unsigned i = 1; i != NumConcat; ++i)
2440 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2443 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2444 Mask, Src0, N->getMemoryVT(),
2445 N->getMemOperand(), ExtType);
2446 // Legalized the chain result - switch anything that used the old chain to
2448 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2452 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2453 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2454 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2455 WidenVT, N->getOperand(0));
2458 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2459 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2460 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2462 SDValue Cond1 = N->getOperand(0);
2463 EVT CondVT = Cond1.getValueType();
2464 if (CondVT.isVector()) {
2465 EVT CondEltVT = CondVT.getVectorElementType();
2466 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2467 CondEltVT, WidenNumElts);
2468 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2469 Cond1 = GetWidenedVector(Cond1);
2471 // If we have to split the condition there is no point in widening the
2472 // select. This would result in an cycle of widening the select ->
2473 // widening the condition operand -> splitting the condition operand ->
2474 // splitting the select -> widening the select. Instead split this select
2475 // further and widen the resulting type.
2476 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2477 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2478 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2482 if (Cond1.getValueType() != CondWidenVT)
2483 Cond1 = ModifyToType(Cond1, CondWidenVT);
2486 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2487 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2488 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2489 return DAG.getNode(N->getOpcode(), SDLoc(N),
2490 WidenVT, Cond1, InOp1, InOp2);
2493 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2494 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2495 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2496 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2497 InOp1.getValueType(), N->getOperand(0),
2498 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2501 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2502 assert(N->getValueType(0).isVector() ==
2503 N->getOperand(0).getValueType().isVector() &&
2504 "Scalar/Vector type mismatch");
2505 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2507 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2508 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2509 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2510 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2511 InOp1, InOp2, N->getOperand(2));
2514 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2515 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2516 return DAG.getUNDEF(WidenVT);
2519 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2520 EVT VT = N->getValueType(0);
2523 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2524 unsigned NumElts = VT.getVectorNumElements();
2525 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2527 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2528 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2530 // Adjust mask based on new input vector length.
2531 SmallVector<int, 16> NewMask;
2532 for (unsigned i = 0; i != NumElts; ++i) {
2533 int Idx = N->getMaskElt(i);
2534 if (Idx < (int)NumElts)
2535 NewMask.push_back(Idx);
2537 NewMask.push_back(Idx - NumElts + WidenNumElts);
2539 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2540 NewMask.push_back(-1);
2541 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2544 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2545 assert(N->getValueType(0).isVector() &&
2546 N->getOperand(0).getValueType().isVector() &&
2547 "Operands must be vectors");
2548 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2549 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2551 SDValue InOp1 = N->getOperand(0);
2552 EVT InVT = InOp1.getValueType();
2553 assert(InVT.isVector() && "can not widen non-vector type");
2554 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2555 InVT.getVectorElementType(), WidenNumElts);
2556 InOp1 = GetWidenedVector(InOp1);
2557 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2559 // Assume that the input and output will be widen appropriately. If not,
2560 // we will have to unroll it at some point.
2561 assert(InOp1.getValueType() == WidenInVT &&
2562 InOp2.getValueType() == WidenInVT &&
2563 "Input not widened to expected type!");
2565 return DAG.getNode(ISD::SETCC, SDLoc(N),
2566 WidenVT, InOp1, InOp2, N->getOperand(2));
2570 //===----------------------------------------------------------------------===//
2571 // Widen Vector Operand
2572 //===----------------------------------------------------------------------===//
2573 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2574 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2577 SDValue Res = SDValue();
2579 // See if the target wants to custom widen this node.
2580 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2583 switch (N->getOpcode()) {
2586 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2590 llvm_unreachable("Do not know how to widen this operator's operand!");
2592 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2593 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2594 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2595 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2596 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2597 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2598 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2600 case ISD::ANY_EXTEND:
2601 case ISD::SIGN_EXTEND:
2602 case ISD::ZERO_EXTEND:
2603 Res = WidenVecOp_EXTEND(N);
2606 case ISD::FP_EXTEND:
2607 case ISD::FP_TO_SINT:
2608 case ISD::FP_TO_UINT:
2609 case ISD::SINT_TO_FP:
2610 case ISD::UINT_TO_FP:
2612 Res = WidenVecOp_Convert(N);
2616 // If Res is null, the sub-method took care of registering the result.
2617 if (!Res.getNode()) return false;
2619 // If the result is N, the sub-method updated N in place. Tell the legalizer
2621 if (Res.getNode() == N)
2625 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2626 "Invalid operand expansion");
2628 ReplaceValueWith(SDValue(N, 0), Res);
2632 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2634 EVT VT = N->getValueType(0);
2636 SDValue InOp = N->getOperand(0);
2637 // If some legalization strategy other than widening is used on the operand,
2638 // we can't safely assume that just extending the low lanes is the correct
2640 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2641 return WidenVecOp_Convert(N);
2642 InOp = GetWidenedVector(InOp);
2643 assert(VT.getVectorNumElements() <
2644 InOp.getValueType().getVectorNumElements() &&
2645 "Input wasn't widened!");
2647 // We may need to further widen the operand until it has the same total
2648 // vector size as the result.
2649 EVT InVT = InOp.getValueType();
2650 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2651 EVT InEltVT = InVT.getVectorElementType();
2652 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2653 EVT FixedVT = (MVT::SimpleValueType)i;
2654 EVT FixedEltVT = FixedVT.getVectorElementType();
2655 if (TLI.isTypeLegal(FixedVT) &&
2656 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2657 FixedEltVT == InEltVT) {
2658 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2659 "Not enough elements in the fixed type for the operand!");
2660 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2661 "We can't have the same type as we started with!");
2662 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2663 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2664 DAG.getUNDEF(FixedVT), InOp,
2665 DAG.getConstant(0, TLI.getVectorIdxTy()));
2667 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2668 DAG.getConstant(0, TLI.getVectorIdxTy()));
2672 InVT = InOp.getValueType();
2673 if (InVT.getSizeInBits() != VT.getSizeInBits())
2674 // We couldn't find a legal vector type that was a widening of the input
2675 // and could be extended in-register to the result type, so we have to
2677 return WidenVecOp_Convert(N);
2680 // Use special DAG nodes to represent the operation of extending the
2682 switch (N->getOpcode()) {
2684 llvm_unreachable("Extend legalization on on extend operation!");
2685 case ISD::ANY_EXTEND:
2686 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2687 case ISD::SIGN_EXTEND:
2688 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2689 case ISD::ZERO_EXTEND:
2690 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2694 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2695 // Since the result is legal and the input is illegal, it is unlikely
2696 // that we can fix the input to a legal type so unroll the convert
2697 // into some scalar code and create a nasty build vector.
2698 EVT VT = N->getValueType(0);
2699 EVT EltVT = VT.getVectorElementType();
2701 unsigned NumElts = VT.getVectorNumElements();
2702 SDValue InOp = N->getOperand(0);
2703 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2704 InOp = GetWidenedVector(InOp);
2705 EVT InVT = InOp.getValueType();
2706 EVT InEltVT = InVT.getVectorElementType();
2708 unsigned Opcode = N->getOpcode();
2709 SmallVector<SDValue, 16> Ops(NumElts);
2710 for (unsigned i=0; i < NumElts; ++i)
2711 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2712 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2713 DAG.getConstant(i, TLI.getVectorIdxTy())));
2715 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2718 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2719 EVT VT = N->getValueType(0);
2720 SDValue InOp = GetWidenedVector(N->getOperand(0));
2721 EVT InWidenVT = InOp.getValueType();
2724 // Check if we can convert between two legal vector types and extract.
2725 unsigned InWidenSize = InWidenVT.getSizeInBits();
2726 unsigned Size = VT.getSizeInBits();
2727 // x86mmx is not an acceptable vector element type, so don't try.
2728 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2729 unsigned NewNumElts = InWidenSize / Size;
2730 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2731 if (TLI.isTypeLegal(NewVT)) {
2732 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2733 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2734 DAG.getConstant(0, TLI.getVectorIdxTy()));
2738 return CreateStackStoreLoad(InOp, VT);
2741 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2742 // If the input vector is not legal, it is likely that we will not find a
2743 // legal vector of the same size. Replace the concatenate vector with a
2744 // nasty build vector.
2745 EVT VT = N->getValueType(0);
2746 EVT EltVT = VT.getVectorElementType();
2748 unsigned NumElts = VT.getVectorNumElements();
2749 SmallVector<SDValue, 16> Ops(NumElts);
2751 EVT InVT = N->getOperand(0).getValueType();
2752 unsigned NumInElts = InVT.getVectorNumElements();
2755 unsigned NumOperands = N->getNumOperands();
2756 for (unsigned i=0; i < NumOperands; ++i) {
2757 SDValue InOp = N->getOperand(i);
2758 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2759 InOp = GetWidenedVector(InOp);
2760 for (unsigned j=0; j < NumInElts; ++j)
2761 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2762 DAG.getConstant(j, TLI.getVectorIdxTy()));
2764 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2767 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2768 SDValue InOp = GetWidenedVector(N->getOperand(0));
2769 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2770 N->getValueType(0), InOp, N->getOperand(1));
2773 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2774 SDValue InOp = GetWidenedVector(N->getOperand(0));
2775 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2776 N->getValueType(0), InOp, N->getOperand(1));
2779 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2780 // We have to widen the value but we want only to store the original
2782 StoreSDNode *ST = cast<StoreSDNode>(N);
2784 SmallVector<SDValue, 16> StChain;
2785 if (ST->isTruncatingStore())
2786 GenWidenVectorTruncStores(StChain, ST);
2788 GenWidenVectorStores(StChain, ST);
2790 if (StChain.size() == 1)
2793 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
2796 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
2797 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
2798 SDValue Mask = MST->getMask();
2799 EVT MaskVT = Mask.getValueType();
2800 SDValue StVal = MST->getValue();
2802 SDValue WideVal = GetWidenedVector(StVal);
2805 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2806 Mask = GetWidenedVector(Mask);
2808 // The mask should be widened as well
2809 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
2810 // We can't use ModifyToType() because we should fill the mask with
2812 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2813 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2815 unsigned NumConcat = WidenNumElts / MaskNumElts;
2816 SmallVector<SDValue, 16> Ops(NumConcat);
2817 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
2819 for (unsigned i = 1; i != NumConcat; ++i)
2822 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2824 assert(Mask.getValueType().getVectorNumElements() ==
2825 WideVal.getValueType().getVectorNumElements() &&
2826 "Mask and data vectors should have the same number of elements");
2827 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
2828 Mask, MST->getMemoryVT(), MST->getMemOperand(),
2832 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2833 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2834 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2837 // WARNING: In this code we widen the compare instruction with garbage.
2838 // This garbage may contain denormal floats which may be slow. Is this a real
2839 // concern ? Should we zero the unused lanes if this is a float compare ?
2841 // Get a new SETCC node to compare the newly widened operands.
2842 // Only some of the compared elements are legal.
2843 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
2844 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
2845 SVT, InOp0, InOp1, N->getOperand(2));
2847 // Extract the needed results from the result vector.
2848 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2849 SVT.getVectorElementType(),
2850 N->getValueType(0).getVectorNumElements());
2851 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2852 ResVT, WideSETCC, DAG.getConstant(0,
2853 TLI.getVectorIdxTy()));
2855 return PromoteTargetBoolean(CC, N->getValueType(0));
2859 //===----------------------------------------------------------------------===//
2860 // Vector Widening Utilities
2861 //===----------------------------------------------------------------------===//
2863 // Utility function to find the type to chop up a widen vector for load/store
2864 // TLI: Target lowering used to determine legal types.
2865 // Width: Width left need to load/store.
2866 // WidenVT: The widen vector type to load to/store from
2867 // Align: If 0, don't allow use of a wider type
2868 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2870 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2871 unsigned Width, EVT WidenVT,
2872 unsigned Align = 0, unsigned WidenEx = 0) {
2873 EVT WidenEltVT = WidenVT.getVectorElementType();
2874 unsigned WidenWidth = WidenVT.getSizeInBits();
2875 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2876 unsigned AlignInBits = Align*8;
2878 // If we have one element to load/store, return it.
2879 EVT RetVT = WidenEltVT;
2880 if (Width == WidenEltWidth)
2883 // See if there is larger legal integer than the element type to load/store
2885 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2886 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2887 EVT MemVT((MVT::SimpleValueType) VT);
2888 unsigned MemVTWidth = MemVT.getSizeInBits();
2889 if (MemVT.getSizeInBits() <= WidenEltWidth)
2891 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2892 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2893 (MemVTWidth <= Width ||
2894 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2900 // See if there is a larger vector type to load/store that has the same vector
2901 // element type and is evenly divisible with the WidenVT.
2902 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2903 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2904 EVT MemVT = (MVT::SimpleValueType) VT;
2905 unsigned MemVTWidth = MemVT.getSizeInBits();
2906 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2907 (WidenWidth % MemVTWidth) == 0 &&
2908 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2909 (MemVTWidth <= Width ||
2910 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2911 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2919 // Builds a vector type from scalar loads
2920 // VecTy: Resulting Vector type
2921 // LDOps: Load operators to build a vector type
2922 // [Start,End) the list of loads to use.
2923 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2924 SmallVectorImpl<SDValue> &LdOps,
2925 unsigned Start, unsigned End) {
2926 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2927 SDLoc dl(LdOps[Start]);
2928 EVT LdTy = LdOps[Start].getValueType();
2929 unsigned Width = VecTy.getSizeInBits();
2930 unsigned NumElts = Width / LdTy.getSizeInBits();
2931 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2934 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2936 for (unsigned i = Start + 1; i != End; ++i) {
2937 EVT NewLdTy = LdOps[i].getValueType();
2938 if (NewLdTy != LdTy) {
2939 NumElts = Width / NewLdTy.getSizeInBits();
2940 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2941 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2942 // Readjust position and vector position based on new load type
2943 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2946 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2947 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
2949 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2952 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
2954 // The strategy assumes that we can efficiently load powers of two widths.
2955 // The routines chops the vector into the largest vector loads with the same
2956 // element type or scalar loads and then recombines it to the widen vector
2958 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2959 unsigned WidenWidth = WidenVT.getSizeInBits();
2960 EVT LdVT = LD->getMemoryVT();
2962 assert(LdVT.isVector() && WidenVT.isVector());
2963 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2966 SDValue Chain = LD->getChain();
2967 SDValue BasePtr = LD->getBasePtr();
2968 unsigned Align = LD->getAlignment();
2969 bool isVolatile = LD->isVolatile();
2970 bool isNonTemporal = LD->isNonTemporal();
2971 bool isInvariant = LD->isInvariant();
2972 AAMDNodes AAInfo = LD->getAAInfo();
2974 int LdWidth = LdVT.getSizeInBits();
2975 int WidthDiff = WidenWidth - LdWidth; // Difference
2976 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2978 // Find the vector type that can load from.
2979 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2980 int NewVTWidth = NewVT.getSizeInBits();
2981 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2982 isVolatile, isNonTemporal, isInvariant, Align,
2984 LdChain.push_back(LdOp.getValue(1));
2986 // Check if we can load the element with one instruction
2987 if (LdWidth <= NewVTWidth) {
2988 if (!NewVT.isVector()) {
2989 unsigned NumElts = WidenWidth / NewVTWidth;
2990 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2991 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2992 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2994 if (NewVT == WidenVT)
2997 assert(WidenWidth % NewVTWidth == 0);
2998 unsigned NumConcat = WidenWidth / NewVTWidth;
2999 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3000 SDValue UndefVal = DAG.getUNDEF(NewVT);
3001 ConcatOps[0] = LdOp;
3002 for (unsigned i = 1; i != NumConcat; ++i)
3003 ConcatOps[i] = UndefVal;
3004 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3007 // Load vector by using multiple loads from largest vector to scalar
3008 SmallVector<SDValue, 16> LdOps;
3009 LdOps.push_back(LdOp);
3011 LdWidth -= NewVTWidth;
3012 unsigned Offset = 0;
3014 while (LdWidth > 0) {
3015 unsigned Increment = NewVTWidth / 8;
3016 Offset += Increment;
3017 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3018 DAG.getConstant(Increment, BasePtr.getValueType()));
3021 if (LdWidth < NewVTWidth) {
3022 // Our current type we are using is too large, find a better size
3023 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3024 NewVTWidth = NewVT.getSizeInBits();
3025 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3026 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3027 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3029 LdChain.push_back(L.getValue(1));
3030 if (L->getValueType(0).isVector()) {
3031 SmallVector<SDValue, 16> Loads;
3033 unsigned size = L->getValueSizeInBits(0);
3034 while (size < LdOp->getValueSizeInBits(0)) {
3035 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3036 size += L->getValueSizeInBits(0);
3038 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3041 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3042 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3043 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3045 LdChain.push_back(L.getValue(1));
3051 LdWidth -= NewVTWidth;
3054 // Build the vector from the loads operations
3055 unsigned End = LdOps.size();
3056 if (!LdOps[0].getValueType().isVector())
3057 // All the loads are scalar loads.
3058 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3060 // If the load contains vectors, build the vector using concat vector.
3061 // All of the vectors used to loads are power of 2 and the scalars load
3062 // can be combined to make a power of 2 vector.
3063 SmallVector<SDValue, 16> ConcatOps(End);
3066 EVT LdTy = LdOps[i].getValueType();
3067 // First combine the scalar loads to a vector
3068 if (!LdTy.isVector()) {
3069 for (--i; i >= 0; --i) {
3070 LdTy = LdOps[i].getValueType();
3071 if (LdTy.isVector())
3074 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3076 ConcatOps[--Idx] = LdOps[i];
3077 for (--i; i >= 0; --i) {
3078 EVT NewLdTy = LdOps[i].getValueType();
3079 if (NewLdTy != LdTy) {
3080 // Create a larger vector
3081 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3082 makeArrayRef(&ConcatOps[Idx], End - Idx));
3086 ConcatOps[--Idx] = LdOps[i];
3089 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3090 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3091 makeArrayRef(&ConcatOps[Idx], End - Idx));
3093 // We need to fill the rest with undefs to build the vector
3094 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3095 SmallVector<SDValue, 16> WidenOps(NumOps);
3096 SDValue UndefVal = DAG.getUNDEF(LdTy);
3099 for (; i != End-Idx; ++i)
3100 WidenOps[i] = ConcatOps[Idx+i];
3101 for (; i != NumOps; ++i)
3102 WidenOps[i] = UndefVal;
3104 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3108 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3110 ISD::LoadExtType ExtType) {
3111 // For extension loads, it may not be more efficient to chop up the vector
3112 // and then extended it. Instead, we unroll the load and build a new vector.
3113 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3114 EVT LdVT = LD->getMemoryVT();
3116 assert(LdVT.isVector() && WidenVT.isVector());
3119 SDValue Chain = LD->getChain();
3120 SDValue BasePtr = LD->getBasePtr();
3121 unsigned Align = LD->getAlignment();
3122 bool isVolatile = LD->isVolatile();
3123 bool isNonTemporal = LD->isNonTemporal();
3124 bool isInvariant = LD->isInvariant();
3125 AAMDNodes AAInfo = LD->getAAInfo();
3127 EVT EltVT = WidenVT.getVectorElementType();
3128 EVT LdEltVT = LdVT.getVectorElementType();
3129 unsigned NumElts = LdVT.getVectorNumElements();
3131 // Load each element and widen
3132 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3133 SmallVector<SDValue, 16> Ops(WidenNumElts);
3134 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3135 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3136 LD->getPointerInfo(),
3137 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3139 LdChain.push_back(Ops[0].getValue(1));
3140 unsigned i = 0, Offset = Increment;
3141 for (i=1; i < NumElts; ++i, Offset += Increment) {
3142 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3144 DAG.getConstant(Offset,
3145 BasePtr.getValueType()));
3146 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3147 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3148 isVolatile, isNonTemporal, isInvariant, Align,
3150 LdChain.push_back(Ops[i].getValue(1));
3153 // Fill the rest with undefs
3154 SDValue UndefVal = DAG.getUNDEF(EltVT);
3155 for (; i != WidenNumElts; ++i)
3158 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3162 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3164 // The strategy assumes that we can efficiently store powers of two widths.
3165 // The routines chops the vector into the largest vector stores with the same
3166 // element type or scalar stores.
3167 SDValue Chain = ST->getChain();
3168 SDValue BasePtr = ST->getBasePtr();
3169 unsigned Align = ST->getAlignment();
3170 bool isVolatile = ST->isVolatile();
3171 bool isNonTemporal = ST->isNonTemporal();
3172 AAMDNodes AAInfo = ST->getAAInfo();
3173 SDValue ValOp = GetWidenedVector(ST->getValue());
3176 EVT StVT = ST->getMemoryVT();
3177 unsigned StWidth = StVT.getSizeInBits();
3178 EVT ValVT = ValOp.getValueType();
3179 unsigned ValWidth = ValVT.getSizeInBits();
3180 EVT ValEltVT = ValVT.getVectorElementType();
3181 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3182 assert(StVT.getVectorElementType() == ValEltVT);
3184 int Idx = 0; // current index to store
3185 unsigned Offset = 0; // offset from base to store
3186 while (StWidth != 0) {
3187 // Find the largest vector type we can store with
3188 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3189 unsigned NewVTWidth = NewVT.getSizeInBits();
3190 unsigned Increment = NewVTWidth / 8;
3191 if (NewVT.isVector()) {
3192 unsigned NumVTElts = NewVT.getVectorNumElements();
3194 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3195 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3196 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3197 ST->getPointerInfo().getWithOffset(Offset),
3198 isVolatile, isNonTemporal,
3199 MinAlign(Align, Offset), AAInfo));
3200 StWidth -= NewVTWidth;
3201 Offset += Increment;
3203 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3204 DAG.getConstant(Increment, BasePtr.getValueType()));
3205 } while (StWidth != 0 && StWidth >= NewVTWidth);
3207 // Cast the vector to the scalar type we can store
3208 unsigned NumElts = ValWidth / NewVTWidth;
3209 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3210 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3211 // Readjust index position based on new vector type
3212 Idx = Idx * ValEltWidth / NewVTWidth;
3214 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3215 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
3216 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3217 ST->getPointerInfo().getWithOffset(Offset),
3218 isVolatile, isNonTemporal,
3219 MinAlign(Align, Offset), AAInfo));
3220 StWidth -= NewVTWidth;
3221 Offset += Increment;
3222 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3223 DAG.getConstant(Increment, BasePtr.getValueType()));
3224 } while (StWidth != 0 && StWidth >= NewVTWidth);
3225 // Restore index back to be relative to the original widen element type
3226 Idx = Idx * NewVTWidth / ValEltWidth;
3232 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3234 // For extension loads, it may not be more efficient to truncate the vector
3235 // and then store it. Instead, we extract each element and then store it.
3236 SDValue Chain = ST->getChain();
3237 SDValue BasePtr = ST->getBasePtr();
3238 unsigned Align = ST->getAlignment();
3239 bool isVolatile = ST->isVolatile();
3240 bool isNonTemporal = ST->isNonTemporal();
3241 AAMDNodes AAInfo = ST->getAAInfo();
3242 SDValue ValOp = GetWidenedVector(ST->getValue());
3245 EVT StVT = ST->getMemoryVT();
3246 EVT ValVT = ValOp.getValueType();
3248 // It must be true that we the widen vector type is bigger than where
3249 // we need to store.
3250 assert(StVT.isVector() && ValOp.getValueType().isVector());
3251 assert(StVT.bitsLT(ValOp.getValueType()));
3253 // For truncating stores, we can not play the tricks of chopping legal
3254 // vector types and bit cast it to the right type. Instead, we unroll
3256 EVT StEltVT = StVT.getVectorElementType();
3257 EVT ValEltVT = ValVT.getVectorElementType();
3258 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3259 unsigned NumElts = StVT.getVectorNumElements();
3260 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3261 DAG.getConstant(0, TLI.getVectorIdxTy()));
3262 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3263 ST->getPointerInfo(), StEltVT,
3264 isVolatile, isNonTemporal, Align,
3266 unsigned Offset = Increment;
3267 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3268 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3269 BasePtr, DAG.getConstant(Offset,
3270 BasePtr.getValueType()));
3271 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3272 DAG.getConstant(0, TLI.getVectorIdxTy()));
3273 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3274 ST->getPointerInfo().getWithOffset(Offset),
3275 StEltVT, isVolatile, isNonTemporal,
3276 MinAlign(Align, Offset), AAInfo));
3280 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3281 /// input vector must have the same element type as NVT.
3282 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3283 // Note that InOp might have been widened so it might already have
3284 // the right width or it might need be narrowed.
3285 EVT InVT = InOp.getValueType();
3286 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3287 "input and widen element type must match");
3290 // Check if InOp already has the right width.
3294 unsigned InNumElts = InVT.getVectorNumElements();
3295 unsigned WidenNumElts = NVT.getVectorNumElements();
3296 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3297 unsigned NumConcat = WidenNumElts / InNumElts;
3298 SmallVector<SDValue, 16> Ops(NumConcat);
3299 SDValue UndefVal = DAG.getUNDEF(InVT);
3301 for (unsigned i = 1; i != NumConcat; ++i)
3304 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3307 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3308 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3309 DAG.getConstant(0, TLI.getVectorIdxTy()));
3311 // Fall back to extract and build.
3312 SmallVector<SDValue, 16> Ops(WidenNumElts);
3313 EVT EltVT = NVT.getVectorElementType();
3314 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3316 for (Idx = 0; Idx < MinNumElts; ++Idx)
3317 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3318 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3320 SDValue UndefVal = DAG.getUNDEF(EltVT);
3321 for ( ; Idx < WidenNumElts; ++Idx)
3322 Ops[Idx] = UndefVal;
3323 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);