1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
60 case ISD::CONVERT_RNDSAT:
61 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
62 case ISD::CTLZ_ZERO_UNDEF:
63 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
64 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
65 case ISD::CTTZ_ZERO_UNDEF:
66 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
67 case ISD::EXTRACT_VECTOR_ELT:
68 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
69 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
70 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
72 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
74 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
75 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
76 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
81 case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N); break;
82 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
83 case ISD::SIGN_EXTEND_INREG:
84 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
85 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
86 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
87 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
88 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
89 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
91 case ISD::EXTRACT_SUBVECTOR:
92 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
93 case ISD::VECTOR_SHUFFLE:
94 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
95 case ISD::INSERT_VECTOR_ELT:
96 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
97 case ISD::BUILD_VECTOR:
98 Res = PromoteIntRes_BUILD_VECTOR(N); break;
99 case ISD::SCALAR_TO_VECTOR:
100 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
101 case ISD::CONCAT_VECTORS:
102 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
104 case ISD::SIGN_EXTEND:
105 case ISD::ZERO_EXTEND:
106 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
108 case ISD::FP_TO_SINT:
109 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
111 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
118 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
121 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
124 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
127 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
129 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
131 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
133 case ISD::ATOMIC_LOAD:
134 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
136 case ISD::ATOMIC_LOAD_ADD:
137 case ISD::ATOMIC_LOAD_SUB:
138 case ISD::ATOMIC_LOAD_AND:
139 case ISD::ATOMIC_LOAD_OR:
140 case ISD::ATOMIC_LOAD_XOR:
141 case ISD::ATOMIC_LOAD_NAND:
142 case ISD::ATOMIC_LOAD_MIN:
143 case ISD::ATOMIC_LOAD_MAX:
144 case ISD::ATOMIC_LOAD_UMIN:
145 case ISD::ATOMIC_LOAD_UMAX:
146 case ISD::ATOMIC_SWAP:
147 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
149 case ISD::ATOMIC_CMP_SWAP:
150 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
151 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
155 // If the result is null then the sub-method took care of registering it.
157 SetPromotedInteger(SDValue(N, ResNo), Res);
160 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
162 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
163 return GetPromotedInteger(Op);
166 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
167 // Sign-extend the new bits, and continue the assertion.
168 SDValue Op = SExtPromotedInteger(N->getOperand(0));
169 return DAG.getNode(ISD::AssertSext, SDLoc(N),
170 Op.getValueType(), Op, N->getOperand(1));
173 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
174 // Zero the new bits, and continue the assertion.
175 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
176 return DAG.getNode(ISD::AssertZext, SDLoc(N),
177 Op.getValueType(), Op, N->getOperand(1));
180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
181 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
182 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
183 N->getMemoryVT(), ResVT,
184 N->getChain(), N->getBasePtr(),
185 N->getMemOperand(), N->getOrdering(),
187 // Legalize the chain result - switch anything that used the old chain to
189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
197 N->getChain(), N->getBasePtr(),
198 Op2, N->getMemOperand(), N->getOrdering(),
200 // Legalize the chain result - switch anything that used the old chain to
202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
206 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
209 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
210 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
211 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
213 // Only use the result of getSetCCResultType if it is legal,
214 // otherwise just use the promoted result type (NVT).
215 if (!TLI.isTypeLegal(SVT))
218 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
219 SDValue Res = DAG.getAtomicCmpSwap(
220 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
221 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
222 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
224 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
225 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
226 return Res.getValue(1);
229 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
230 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
232 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
233 SDValue Res = DAG.getAtomicCmpSwap(
234 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
235 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
236 N->getFailureOrdering(), N->getSynchScope());
237 // Update the use to N with the newly created Res.
238 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
239 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
243 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
244 SDValue InOp = N->getOperand(0);
245 EVT InVT = InOp.getValueType();
246 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
247 EVT OutVT = N->getValueType(0);
248 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
251 switch (getTypeAction(InVT)) {
252 case TargetLowering::TypeLegal:
254 case TargetLowering::TypePromoteInteger:
255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
256 // The input promotes to the same size. Convert the promoted value.
257 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
259 case TargetLowering::TypeSoftenFloat:
260 // Promote the integer operand by hand.
261 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
262 case TargetLowering::TypePromoteFloat: {
263 // Convert the promoted float by hand.
264 if (NOutVT.bitsEq(NInVT)) {
265 SDValue PromotedOp = GetPromotedFloat(InOp);
266 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
267 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
268 DAG.getValueType(OutVT));
272 case TargetLowering::TypeExpandInteger:
273 case TargetLowering::TypeExpandFloat:
275 case TargetLowering::TypeScalarizeVector:
276 // Convert the element to an integer and promote it by hand.
277 if (!NOutVT.isVector())
278 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
279 BitConvertToInteger(GetScalarizedVector(InOp)));
281 case TargetLowering::TypeSplitVector: {
282 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
283 // pieces of the input into integers and reassemble in the final type.
285 GetSplitVector(N->getOperand(0), Lo, Hi);
286 Lo = BitConvertToInteger(Lo);
287 Hi = BitConvertToInteger(Hi);
289 if (DAG.getDataLayout().isBigEndian())
292 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
293 EVT::getIntegerVT(*DAG.getContext(),
294 NOutVT.getSizeInBits()),
295 JoinIntegers(Lo, Hi));
296 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
298 case TargetLowering::TypeWidenVector:
299 // The input is widened to the same size. Convert to the widened value.
300 // Make sure that the outgoing value is not a vector, because this would
301 // make us bitcast between two vectors which are legalized in different ways.
302 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
303 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
306 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
307 CreateStackStoreLoad(InOp, OutVT));
310 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
311 SDValue Op = GetPromotedInteger(N->getOperand(0));
312 EVT OVT = N->getValueType(0);
313 EVT NVT = Op.getValueType();
316 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
318 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
319 DAG.getConstant(DiffBits, dl,
320 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
323 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
324 SDValue Op = GetPromotedInteger(N->getOperand(0));
325 EVT OVT = N->getValueType(0);
326 EVT NVT = Op.getValueType();
329 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
331 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
332 DAG.getConstant(DiffBits, dl,
333 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
336 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
337 // The pair element type may be legal, or may not promote to the same type as
338 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
339 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
340 TLI.getTypeToTransformTo(*DAG.getContext(),
341 N->getValueType(0)), JoinIntegers(N->getOperand(0),
345 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
346 EVT VT = N->getValueType(0);
347 // FIXME there is no actual debug info here
349 // Zero extend things like i1, sign extend everything else. It shouldn't
350 // matter in theory which one we pick, but this tends to give better code?
351 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
352 SDValue Result = DAG.getNode(Opc, dl,
353 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
355 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
359 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
360 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
361 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
362 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
363 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
364 "can only promote integers");
365 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
366 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
367 N->getOperand(1), N->getOperand(2),
368 N->getOperand(3), N->getOperand(4), CvtCode);
371 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
372 // Zero extend to the promoted type and do the count there.
373 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
375 EVT OVT = N->getValueType(0);
376 EVT NVT = Op.getValueType();
377 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
378 // Subtract off the extra leading bits in the bigger type.
380 ISD::SUB, dl, NVT, Op,
381 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
385 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
386 // Zero extend to the promoted type and do the count there.
387 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
388 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
391 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
392 SDValue Op = GetPromotedInteger(N->getOperand(0));
393 EVT OVT = N->getValueType(0);
394 EVT NVT = Op.getValueType();
396 if (N->getOpcode() == ISD::CTTZ) {
397 // The count is the same in the promoted type except if the original
398 // value was zero. This can be handled by setting the bit just off
399 // the top of the original type.
400 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
401 OVT.getScalarSizeInBits());
402 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
404 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
407 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
409 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
410 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
414 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
416 unsigned NewOpc = N->getOpcode();
419 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
420 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
421 // and SINT conversions are Custom, there is no way to tell which is
422 // preferable. We choose SINT because that's the right thing on PPC.)
423 if (N->getOpcode() == ISD::FP_TO_UINT &&
424 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
425 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
426 NewOpc = ISD::FP_TO_SINT;
428 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
430 // Assert that the converted value fits in the original type. If it doesn't
431 // (eg: because the value being converted is too big), then the result of the
432 // original operation was undefined anyway, so the assert is still correct.
433 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
434 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
435 DAG.getValueType(N->getValueType(0).getScalarType()));
438 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
439 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
442 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
444 return DAG.getNode(ISD::AssertZext, dl,
445 NVT, Res, DAG.getValueType(N->getValueType(0)));
448 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
449 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
452 if (getTypeAction(N->getOperand(0).getValueType())
453 == TargetLowering::TypePromoteInteger) {
454 SDValue Res = GetPromotedInteger(N->getOperand(0));
455 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
457 // If the result and operand types are the same after promotion, simplify
458 // to an in-register extension.
459 if (NVT == Res.getValueType()) {
460 // The high bits are not guaranteed to be anything. Insert an extend.
461 if (N->getOpcode() == ISD::SIGN_EXTEND)
462 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
463 DAG.getValueType(N->getOperand(0).getValueType()));
464 if (N->getOpcode() == ISD::ZERO_EXTEND)
465 return DAG.getZeroExtendInReg(Res, dl,
466 N->getOperand(0).getValueType().getScalarType());
467 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
472 // Otherwise, just extend the original operand all the way to the larger type.
473 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
476 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
477 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
478 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
479 ISD::LoadExtType ExtType =
480 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
482 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
483 N->getMemoryVT(), N->getMemOperand());
485 // Legalize the chain result - switch anything that used the old chain to
487 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
491 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
492 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
493 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
496 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
497 N->getMask(), ExtSrc0, N->getMemoryVT(),
498 N->getMemOperand(), ISD::SEXTLOAD);
499 // Legalize the chain result - switch anything that used the old chain to
501 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
505 SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
506 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
507 SDValue ExtSrc0 = GetPromotedInteger(N->getValue());
508 assert(NVT == ExtSrc0.getValueType() &&
509 "Gather result type and the passThru agrument type should be the same");
512 SDValue Ops[] = {N->getChain(), ExtSrc0, N->getMask(), N->getBasePtr(),
514 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
515 N->getMemoryVT(), dl, Ops,
517 // Legalize the chain result - switch anything that used the old chain to
519 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
523 /// Promote the overflow flag of an overflowing arithmetic node.
524 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
525 // Simply change the return type of the boolean result.
526 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
527 EVT ValueVTs[] = { N->getValueType(0), NVT };
528 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
529 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
530 DAG.getVTList(ValueVTs), Ops);
532 // Modified the sum result - switch anything that used the old sum to use
534 ReplaceValueWith(SDValue(N, 0), Res);
536 return SDValue(Res.getNode(), 1);
539 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
541 return PromoteIntRes_Overflow(N);
543 // The operation overflowed iff the result in the larger type is not the
544 // sign extension of its truncation to the original type.
545 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
546 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
547 EVT OVT = N->getOperand(0).getValueType();
548 EVT NVT = LHS.getValueType();
551 // Do the arithmetic in the larger type.
552 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
553 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
555 // Calculate the overflow flag: sign extend the arithmetic result from
556 // the original type.
557 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
558 DAG.getValueType(OVT));
559 // Overflowed if and only if this is not equal to Res.
560 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
562 // Use the calculated overflow everywhere.
563 ReplaceValueWith(SDValue(N, 1), Ofl);
568 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
569 // Sign extend the input.
570 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
571 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
572 return DAG.getNode(N->getOpcode(), SDLoc(N),
573 LHS.getValueType(), LHS, RHS);
576 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
577 SDValue LHS = GetPromotedInteger(N->getOperand(1));
578 SDValue RHS = GetPromotedInteger(N->getOperand(2));
579 return DAG.getSelect(SDLoc(N),
580 LHS.getValueType(), N->getOperand(0), LHS, RHS);
583 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
584 SDValue Mask = N->getOperand(0);
585 EVT OpTy = N->getOperand(1).getValueType();
587 // Promote all the way up to the canonical SetCC type.
588 Mask = PromoteTargetBoolean(Mask, OpTy);
589 SDValue LHS = GetPromotedInteger(N->getOperand(1));
590 SDValue RHS = GetPromotedInteger(N->getOperand(2));
591 return DAG.getNode(ISD::VSELECT, SDLoc(N),
592 LHS.getValueType(), Mask, LHS, RHS);
595 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
596 SDValue LHS = GetPromotedInteger(N->getOperand(2));
597 SDValue RHS = GetPromotedInteger(N->getOperand(3));
598 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
599 LHS.getValueType(), N->getOperand(0),
600 N->getOperand(1), LHS, RHS, N->getOperand(4));
603 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
604 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
606 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
608 // Only use the result of getSetCCResultType if it is legal,
609 // otherwise just use the promoted result type (NVT).
610 if (!TLI.isTypeLegal(SVT))
614 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
615 "Vector compare must return a vector result!");
617 SDValue LHS = N->getOperand(0);
618 SDValue RHS = N->getOperand(1);
619 if (LHS.getValueType() != RHS.getValueType()) {
620 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
621 !LHS.getValueType().isVector())
622 LHS = GetPromotedInteger(LHS);
623 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
624 !RHS.getValueType().isVector())
625 RHS = GetPromotedInteger(RHS);
628 // Get the SETCC result using the canonical SETCC type.
629 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
632 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
633 // Convert to the expected type.
634 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
637 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
638 SDValue LHS = N->getOperand(0);
639 SDValue RHS = N->getOperand(1);
640 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
641 LHS = GetPromotedInteger(LHS);
642 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
643 RHS = ZExtPromotedInteger(RHS);
644 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
647 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
648 SDValue Op = GetPromotedInteger(N->getOperand(0));
649 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
650 Op.getValueType(), Op, N->getOperand(1));
653 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
654 // The input may have strange things in the top bits of the registers, but
655 // these operations don't care. They may have weird bits going out, but
656 // that too is okay if they are integer operations.
657 SDValue LHS = GetPromotedInteger(N->getOperand(0));
658 SDValue RHS = GetPromotedInteger(N->getOperand(1));
659 return DAG.getNode(N->getOpcode(), SDLoc(N),
660 LHS.getValueType(), LHS, RHS);
663 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
664 SDValue LHS = N->getOperand(0);
665 SDValue RHS = N->getOperand(1);
666 // The input value must be properly sign extended.
667 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
668 LHS = SExtPromotedInteger(LHS);
669 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
670 RHS = ZExtPromotedInteger(RHS);
671 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
674 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
675 SDValue LHS = N->getOperand(0);
676 SDValue RHS = N->getOperand(1);
677 // The input value must be properly zero extended.
678 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
679 LHS = ZExtPromotedInteger(LHS);
680 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
681 RHS = ZExtPromotedInteger(RHS);
682 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
685 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
686 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
688 SDValue InOp = N->getOperand(0);
691 switch (getTypeAction(InOp.getValueType())) {
692 default: llvm_unreachable("Unknown type action!");
693 case TargetLowering::TypeLegal:
694 case TargetLowering::TypeExpandInteger:
697 case TargetLowering::TypePromoteInteger:
698 Res = GetPromotedInteger(InOp);
700 case TargetLowering::TypeSplitVector:
701 EVT InVT = InOp.getValueType();
702 assert(InVT.isVector() && "Cannot split scalar types");
703 unsigned NumElts = InVT.getVectorNumElements();
704 assert(NumElts == NVT.getVectorNumElements() &&
705 "Dst and Src must have the same number of elements");
706 assert(isPowerOf2_32(NumElts) &&
707 "Promoted vector type must be a power of two");
710 GetSplitVector(InOp, EOp1, EOp2);
712 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
714 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
715 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
717 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
720 // Truncate to NVT instead of VT
721 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
724 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
726 return PromoteIntRes_Overflow(N);
728 // The operation overflowed iff the result in the larger type is not the
729 // zero extension of its truncation to the original type.
730 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
731 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
732 EVT OVT = N->getOperand(0).getValueType();
733 EVT NVT = LHS.getValueType();
736 // Do the arithmetic in the larger type.
737 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
738 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
740 // Calculate the overflow flag: zero extend the arithmetic result from
741 // the original type.
742 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
743 // Overflowed if and only if this is not equal to Res.
744 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
746 // Use the calculated overflow everywhere.
747 ReplaceValueWith(SDValue(N, 1), Ofl);
752 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
753 // Promote the overflow bit trivially.
755 return PromoteIntRes_Overflow(N);
757 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
759 EVT SmallVT = LHS.getValueType();
761 // To determine if the result overflowed in a larger type, we extend the
762 // input to the larger type, do the multiply (checking if it overflows),
763 // then also check the high bits of the result to see if overflow happened
765 if (N->getOpcode() == ISD::SMULO) {
766 LHS = SExtPromotedInteger(LHS);
767 RHS = SExtPromotedInteger(RHS);
769 LHS = ZExtPromotedInteger(LHS);
770 RHS = ZExtPromotedInteger(RHS);
772 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
773 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
775 // Overflow occurred if it occurred in the larger type, or if the high part
776 // of the result does not zero/sign-extend the low part. Check this second
777 // possibility first.
779 if (N->getOpcode() == ISD::UMULO) {
780 // Unsigned overflow occurred if the high part is non-zero.
781 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
782 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
784 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
785 DAG.getConstant(0, DL, Hi.getValueType()),
788 // Signed overflow occurred if the high part does not sign extend the low.
789 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
790 Mul, DAG.getValueType(SmallVT));
791 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
794 // The only other way for overflow to occur is if the multiplication in the
795 // larger type itself overflowed.
796 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
797 SDValue(Mul.getNode(), 1));
799 // Use the calculated overflow everywhere.
800 ReplaceValueWith(SDValue(N, 1), Overflow);
804 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
805 // Zero extend the input.
806 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
807 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
808 return DAG.getNode(N->getOpcode(), SDLoc(N),
809 LHS.getValueType(), LHS, RHS);
812 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
813 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
814 N->getValueType(0)));
817 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
818 SDValue Chain = N->getOperand(0); // Get the chain.
819 SDValue Ptr = N->getOperand(1); // Get the pointer.
820 EVT VT = N->getValueType(0);
823 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
824 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
825 // The argument is passed as NumRegs registers of type RegVT.
827 SmallVector<SDValue, 8> Parts(NumRegs);
828 for (unsigned i = 0; i < NumRegs; ++i) {
829 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
830 N->getConstantOperandVal(3));
831 Chain = Parts[i].getValue(1);
834 // Handle endianness of the load.
835 if (DAG.getDataLayout().isBigEndian())
836 std::reverse(Parts.begin(), Parts.end());
838 // Assemble the parts in the promoted type.
839 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
840 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
841 for (unsigned i = 1; i < NumRegs; ++i) {
842 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
843 // Shift it to the right position and "or" it in.
844 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
845 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
846 TLI.getPointerTy(DAG.getDataLayout())));
847 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
850 // Modified the chain result - switch anything that used the old chain to
852 ReplaceValueWith(SDValue(N, 1), Chain);
857 //===----------------------------------------------------------------------===//
858 // Integer Operand Promotion
859 //===----------------------------------------------------------------------===//
861 /// PromoteIntegerOperand - This method is called when the specified operand of
862 /// the specified node is found to need promotion. At this point, all of the
863 /// result types of the node are known to be legal, but other operands of the
864 /// node may need promotion or expansion as well as the specified one.
865 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
866 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
867 SDValue Res = SDValue();
869 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
872 switch (N->getOpcode()) {
875 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
876 N->dump(&DAG); dbgs() << "\n";
878 llvm_unreachable("Do not know how to promote this operator's operand!");
880 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
881 case ISD::ATOMIC_STORE:
882 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
884 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
885 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
886 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
887 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
888 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
889 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
890 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
891 case ISD::CONVERT_RNDSAT:
892 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
893 case ISD::INSERT_VECTOR_ELT:
894 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
895 case ISD::SCALAR_TO_VECTOR:
896 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
898 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
899 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
900 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
901 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
902 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
903 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
905 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
907 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
909 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
911 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
913 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
914 case ISD::FP16_TO_FP:
915 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
916 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
917 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
923 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
926 // If the result is null, the sub-method took care of registering results etc.
927 if (!Res.getNode()) return false;
929 // If the result is N, the sub-method updated N in place. Tell the legalizer
931 if (Res.getNode() == N)
934 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
935 "Invalid operand expansion");
937 ReplaceValueWith(SDValue(N, 0), Res);
941 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
942 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
943 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
944 ISD::CondCode CCCode) {
945 // We have to insert explicit sign or zero extends. Note that we could
946 // insert sign extends for ALL conditions, but zero extend is cheaper on
947 // many machines (an AND instead of two shifts), so prefer it.
949 default: llvm_unreachable("Unknown integer comparison!");
952 SDValue OpL = GetPromotedInteger(NewLHS);
953 SDValue OpR = GetPromotedInteger(NewRHS);
955 // We would prefer to promote the comparison operand with sign extension,
956 // if we find the operand is actually to truncate an AssertSext. With this
957 // optimization, we can avoid inserting real truncate instruction, which
958 // is redudant eventually.
959 if (OpL->getOpcode() == ISD::AssertSext &&
960 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
961 OpR->getOpcode() == ISD::AssertSext &&
962 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
966 NewLHS = ZExtPromotedInteger(NewLHS);
967 NewRHS = ZExtPromotedInteger(NewRHS);
975 // ALL of these operations will work if we either sign or zero extend
976 // the operands (including the unsigned comparisons!). Zero extend is
977 // usually a simpler/cheaper operation, so prefer it.
978 NewLHS = ZExtPromotedInteger(NewLHS);
979 NewRHS = ZExtPromotedInteger(NewRHS);
985 NewLHS = SExtPromotedInteger(NewLHS);
986 NewRHS = SExtPromotedInteger(NewRHS);
991 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
992 SDValue Op = GetPromotedInteger(N->getOperand(0));
993 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
996 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
997 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
998 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
999 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
1000 N->getOrdering(), N->getSynchScope());
1003 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1004 // This should only occur in unusual situations like bitcasting to an
1005 // x86_fp80, so just turn it into a store+load
1006 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1009 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1010 assert(OpNo == 2 && "Don't know how to promote this operand!");
1012 SDValue LHS = N->getOperand(2);
1013 SDValue RHS = N->getOperand(3);
1014 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1016 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1018 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1019 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1023 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1024 assert(OpNo == 1 && "only know how to promote condition");
1026 // Promote all the way up to the canonical SetCC type.
1027 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1029 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1030 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1031 N->getOperand(2)), 0);
1034 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1035 // Since the result type is legal, the operands must promote to it.
1036 EVT OVT = N->getOperand(0).getValueType();
1037 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1038 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1039 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1042 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1043 DAG.getConstant(OVT.getSizeInBits(), dl,
1044 TLI.getPointerTy(DAG.getDataLayout())));
1045 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1048 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1049 // The vector type is legal but the element type is not. This implies
1050 // that the vector is a power-of-two in length and that the element
1051 // type does not have a strange size (eg: it is not i1).
1052 EVT VecVT = N->getValueType(0);
1053 unsigned NumElts = VecVT.getVectorNumElements();
1054 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1055 "Legal vector of one illegal element?");
1057 // Promote the inserted value. The type does not need to match the
1058 // vector element type. Check that any extra bits introduced will be
1060 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1061 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1062 "Type of inserted value narrower than vector element type!");
1064 SmallVector<SDValue, 16> NewOps;
1065 for (unsigned i = 0; i < NumElts; ++i)
1066 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1068 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1071 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1072 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1073 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1074 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1075 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1076 "can only promote integer arguments");
1077 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1078 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1079 N->getOperand(1), N->getOperand(2),
1080 N->getOperand(3), N->getOperand(4), CvtCode);
1083 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1086 // Promote the inserted value. This is valid because the type does not
1087 // have to match the vector element type.
1089 // Check that any extra bits introduced will be truncated away.
1090 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1091 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1092 "Type of inserted value narrower than vector element type!");
1093 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1094 GetPromotedInteger(N->getOperand(1)),
1099 assert(OpNo == 2 && "Different operand and result vector types?");
1101 // Promote the index.
1102 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1103 TLI.getVectorIdxTy(DAG.getDataLayout()));
1104 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1105 N->getOperand(1), Idx), 0);
1108 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1109 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1110 // the operand in place.
1111 return SDValue(DAG.UpdateNodeOperands(N,
1112 GetPromotedInteger(N->getOperand(0))), 0);
1115 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1116 assert(OpNo == 0 && "Only know how to promote the condition!");
1117 SDValue Cond = N->getOperand(0);
1118 EVT OpTy = N->getOperand(1).getValueType();
1120 // Promote all the way up to the canonical SetCC type.
1121 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1122 Cond = PromoteTargetBoolean(Cond, OpVT);
1124 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1125 N->getOperand(2)), 0);
1128 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1129 assert(OpNo == 0 && "Don't know how to promote this operand!");
1131 SDValue LHS = N->getOperand(0);
1132 SDValue RHS = N->getOperand(1);
1133 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1135 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1136 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1137 N->getOperand(3), N->getOperand(4)), 0);
1140 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1141 assert(OpNo == 0 && "Don't know how to promote this operand!");
1143 SDValue LHS = N->getOperand(0);
1144 SDValue RHS = N->getOperand(1);
1145 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1147 // The CC (#2) is always legal.
1148 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1151 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1152 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1153 ZExtPromotedInteger(N->getOperand(1))), 0);
1156 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1157 SDValue Op = GetPromotedInteger(N->getOperand(0));
1159 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1160 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1161 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1164 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1165 return SDValue(DAG.UpdateNodeOperands(N,
1166 SExtPromotedInteger(N->getOperand(0))), 0);
1169 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1170 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1171 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1174 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1176 // Truncate the value and store the result.
1177 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1178 N->getMemoryVT(), N->getMemOperand());
1181 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1184 SDValue DataOp = N->getValue();
1185 EVT DataVT = DataOp.getValueType();
1186 SDValue Mask = N->getMask();
1189 bool TruncateStore = false;
1191 // Mask comes before the data operand. If the data operand is legal, we just
1192 // promote the mask.
1193 // When the data operand has illegal type, we should legalize the data
1194 // operand first. The mask will be promoted/splitted/widened according to
1195 // the data operand type.
1196 if (TLI.isTypeLegal(DataVT))
1197 Mask = PromoteTargetBoolean(Mask, DataVT);
1199 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger)
1200 return PromoteIntOp_MSTORE(N, 3);
1202 else if (getTypeAction(DataVT) == TargetLowering::TypeWidenVector)
1203 return WidenVecOp_MSTORE(N, 3);
1206 assert (getTypeAction(DataVT) == TargetLowering::TypeSplitVector);
1207 return SplitVecOp_MSTORE(N, 3);
1210 } else { // Data operand
1211 assert(OpNo == 3 && "Unexpected operand for promotion");
1212 DataOp = GetPromotedInteger(DataOp);
1213 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1214 TruncateStore = true;
1217 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1218 N->getMemoryVT(), N->getMemOperand(),
1222 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1224 assert(OpNo == 2 && "Only know how to promote the mask!");
1225 EVT DataVT = N->getValueType(0);
1226 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1227 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1228 NewOps[OpNo] = Mask;
1229 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1232 SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1235 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1238 EVT DataVT = N->getValueType(0);
1239 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1241 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1242 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1245 SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1247 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1250 EVT DataVT = N->getValue().getValueType();
1251 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1253 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1254 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1257 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1258 SDValue Op = GetPromotedInteger(N->getOperand(0));
1259 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1262 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1263 return SDValue(DAG.UpdateNodeOperands(N,
1264 ZExtPromotedInteger(N->getOperand(0))), 0);
1267 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1269 SDValue Op = GetPromotedInteger(N->getOperand(0));
1270 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1271 return DAG.getZeroExtendInReg(Op, dl,
1272 N->getOperand(0).getValueType().getScalarType());
1276 //===----------------------------------------------------------------------===//
1277 // Integer Result Expansion
1278 //===----------------------------------------------------------------------===//
1280 /// ExpandIntegerResult - This method is called when the specified result of the
1281 /// specified node is found to need expansion. At this point, the node may also
1282 /// have invalid operands or may have other results that need promotion, we just
1283 /// know that (at least) one result needs expansion.
1284 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1285 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1287 Lo = Hi = SDValue();
1289 // See if the target wants to custom expand this node.
1290 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1293 switch (N->getOpcode()) {
1296 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1297 N->dump(&DAG); dbgs() << "\n";
1299 llvm_unreachable("Do not know how to expand the result of this operator!");
1301 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1302 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1303 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1304 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1306 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1307 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1308 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1309 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1310 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1312 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1313 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1314 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1315 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1316 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1317 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1318 case ISD::CTLZ_ZERO_UNDEF:
1319 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1320 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1321 case ISD::CTTZ_ZERO_UNDEF:
1322 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1323 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1324 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1325 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1326 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1327 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1328 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1329 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1330 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1331 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1332 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1333 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1334 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1335 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1336 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1338 case ISD::ATOMIC_LOAD_ADD:
1339 case ISD::ATOMIC_LOAD_SUB:
1340 case ISD::ATOMIC_LOAD_AND:
1341 case ISD::ATOMIC_LOAD_OR:
1342 case ISD::ATOMIC_LOAD_XOR:
1343 case ISD::ATOMIC_LOAD_NAND:
1344 case ISD::ATOMIC_LOAD_MIN:
1345 case ISD::ATOMIC_LOAD_MAX:
1346 case ISD::ATOMIC_LOAD_UMIN:
1347 case ISD::ATOMIC_LOAD_UMAX:
1348 case ISD::ATOMIC_SWAP:
1349 case ISD::ATOMIC_CMP_SWAP: {
1350 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1351 SplitInteger(Tmp.first, Lo, Hi);
1352 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1355 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1356 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1357 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1358 SDValue Tmp = DAG.getAtomicCmpSwap(
1359 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1360 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1361 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1362 AN->getSynchScope());
1364 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1365 // success simply by comparing the loaded value against the ingoing
1367 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1368 N->getOperand(2), ISD::SETEQ);
1370 SplitInteger(Tmp, Lo, Hi);
1371 ReplaceValueWith(SDValue(N, 1), Success);
1372 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1378 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1381 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1384 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1387 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1391 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1394 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1396 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1398 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1401 // If Lo/Hi is null, the sub-method took care of registering results etc.
1403 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1406 /// Lower an atomic node to the appropriate builtin call.
1407 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1408 unsigned Opc = Node->getOpcode();
1409 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1410 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1411 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1413 return ExpandChainLibCall(LC, Node, false);
1416 /// N is a shift by a value that needs to be expanded,
1417 /// and the shift amount is a constant 'Amt'. Expand the operation.
1418 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1419 SDValue &Lo, SDValue &Hi) {
1421 // Expand the incoming operand to be shifted, so that we have its parts
1423 GetExpandedInteger(N->getOperand(0), InL, InH);
1425 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1426 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1433 EVT NVT = InL.getValueType();
1434 unsigned VTBits = N->getValueType(0).getSizeInBits();
1435 unsigned NVTBits = NVT.getSizeInBits();
1436 EVT ShTy = N->getOperand(1).getValueType();
1438 if (N->getOpcode() == ISD::SHL) {
1439 if (Amt.ugt(VTBits)) {
1440 Lo = Hi = DAG.getConstant(0, DL, NVT);
1441 } else if (Amt.ugt(NVTBits)) {
1442 Lo = DAG.getConstant(0, DL, NVT);
1443 Hi = DAG.getNode(ISD::SHL, DL,
1444 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1445 } else if (Amt == NVTBits) {
1446 Lo = DAG.getConstant(0, DL, NVT);
1448 } else if (Amt == 1 &&
1449 TLI.isOperationLegalOrCustom(ISD::ADDC,
1450 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1451 // Emit this X << 1 as X+X.
1452 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1453 SDValue LoOps[2] = { InL, InL };
1454 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1455 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1456 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1458 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1459 Hi = DAG.getNode(ISD::OR, DL, NVT,
1460 DAG.getNode(ISD::SHL, DL, NVT, InH,
1461 DAG.getConstant(Amt, DL, ShTy)),
1462 DAG.getNode(ISD::SRL, DL, NVT, InL,
1463 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1468 if (N->getOpcode() == ISD::SRL) {
1469 if (Amt.ugt(VTBits)) {
1470 Lo = Hi = DAG.getConstant(0, DL, NVT);
1471 } else if (Amt.ugt(NVTBits)) {
1472 Lo = DAG.getNode(ISD::SRL, DL,
1473 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1474 Hi = DAG.getConstant(0, DL, NVT);
1475 } else if (Amt == NVTBits) {
1477 Hi = DAG.getConstant(0, DL, NVT);
1479 Lo = DAG.getNode(ISD::OR, DL, NVT,
1480 DAG.getNode(ISD::SRL, DL, NVT, InL,
1481 DAG.getConstant(Amt, DL, ShTy)),
1482 DAG.getNode(ISD::SHL, DL, NVT, InH,
1483 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1484 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1489 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1490 if (Amt.ugt(VTBits)) {
1491 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1492 DAG.getConstant(NVTBits - 1, DL, ShTy));
1493 } else if (Amt.ugt(NVTBits)) {
1494 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1495 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1496 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1497 DAG.getConstant(NVTBits - 1, DL, ShTy));
1498 } else if (Amt == NVTBits) {
1500 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1501 DAG.getConstant(NVTBits - 1, DL, ShTy));
1503 Lo = DAG.getNode(ISD::OR, DL, NVT,
1504 DAG.getNode(ISD::SRL, DL, NVT, InL,
1505 DAG.getConstant(Amt, DL, ShTy)),
1506 DAG.getNode(ISD::SHL, DL, NVT, InH,
1507 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1508 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1512 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1513 /// this shift based on knowledge of the high bit of the shift amount. If we
1514 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1516 bool DAGTypeLegalizer::
1517 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1518 SDValue Amt = N->getOperand(1);
1519 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1520 EVT ShTy = Amt.getValueType();
1521 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1522 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1523 assert(isPowerOf2_32(NVTBits) &&
1524 "Expanded integer type size not a power of two!");
1527 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1528 APInt KnownZero, KnownOne;
1529 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1531 // If we don't know anything about the high bits, exit.
1532 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1535 // Get the incoming operand to be shifted.
1537 GetExpandedInteger(N->getOperand(0), InL, InH);
1539 // If we know that any of the high bits of the shift amount are one, then we
1540 // can do this as a couple of simple shifts.
1541 if (KnownOne.intersects(HighBitMask)) {
1542 // Mask out the high bit, which we know is set.
1543 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1544 DAG.getConstant(~HighBitMask, dl, ShTy));
1546 switch (N->getOpcode()) {
1547 default: llvm_unreachable("Unknown shift");
1549 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1550 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1553 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1554 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1557 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1558 DAG.getConstant(NVTBits - 1, dl, ShTy));
1559 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1564 // If we know that all of the high bits of the shift amount are zero, then we
1565 // can do this as a couple of simple shifts.
1566 if ((KnownZero & HighBitMask) == HighBitMask) {
1567 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1568 // shift if x is zero. We can use XOR here because x is known to be smaller
1570 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1571 DAG.getConstant(NVTBits - 1, dl, ShTy));
1574 switch (N->getOpcode()) {
1575 default: llvm_unreachable("Unknown shift");
1576 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1578 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1581 // When shifting right the arithmetic for Lo and Hi is swapped.
1582 if (N->getOpcode() != ISD::SHL)
1583 std::swap(InL, InH);
1585 // Use a little trick to get the bits that move from Lo to Hi. First
1586 // shift by one bit.
1587 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1588 // Then compute the remaining shift with amount-1.
1589 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1591 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1592 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1594 if (N->getOpcode() != ISD::SHL)
1602 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1604 bool DAGTypeLegalizer::
1605 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1606 SDValue Amt = N->getOperand(1);
1607 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1608 EVT ShTy = Amt.getValueType();
1609 unsigned NVTBits = NVT.getSizeInBits();
1610 assert(isPowerOf2_32(NVTBits) &&
1611 "Expanded integer type size not a power of two!");
1614 // Get the incoming operand to be shifted.
1616 GetExpandedInteger(N->getOperand(0), InL, InH);
1618 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1619 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1620 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1621 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1622 Amt, NVBitsNode, ISD::SETULT);
1623 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1624 Amt, DAG.getConstant(0, dl, ShTy),
1627 SDValue LoS, HiS, LoL, HiL;
1628 switch (N->getOpcode()) {
1629 default: llvm_unreachable("Unknown shift");
1631 // Short: ShAmt < NVTBits
1632 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1633 HiS = DAG.getNode(ISD::OR, dl, NVT,
1634 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1635 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1637 // Long: ShAmt >= NVTBits
1638 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1639 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1641 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1642 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1643 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1646 // Short: ShAmt < NVTBits
1647 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1648 LoS = DAG.getNode(ISD::OR, dl, NVT,
1649 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1650 // FIXME: If Amt is zero, the following shift generates an undefined result
1651 // on some architectures.
1652 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1654 // Long: ShAmt >= NVTBits
1655 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1656 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1658 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1659 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1660 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1663 // Short: ShAmt < NVTBits
1664 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1665 LoS = DAG.getNode(ISD::OR, dl, NVT,
1666 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1667 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1669 // Long: ShAmt >= NVTBits
1670 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1671 DAG.getConstant(NVTBits - 1, dl, ShTy));
1672 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1674 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1675 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1676 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1681 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1682 SDValue &Lo, SDValue &Hi) {
1684 // Expand the subcomponents.
1685 SDValue LHSL, LHSH, RHSL, RHSH;
1686 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1687 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1689 EVT NVT = LHSL.getValueType();
1690 SDValue LoOps[2] = { LHSL, RHSL };
1691 SDValue HiOps[3] = { LHSH, RHSH };
1693 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1694 // them. TODO: Teach operation legalization how to expand unsupported
1695 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1696 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1697 // generate a value of this type in the expanded code sequence.
1699 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1700 ISD::ADDC : ISD::SUBC,
1701 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1704 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1705 if (N->getOpcode() == ISD::ADD) {
1706 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1707 HiOps[2] = Lo.getValue(1);
1708 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1710 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1711 HiOps[2] = Lo.getValue(1);
1712 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1718 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1719 ISD::UADDO : ISD::USUBO,
1720 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1722 SDVTList VTList = DAG.getVTList(NVT, NVT);
1723 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1725 if (N->getOpcode() == ISD::ADD) {
1727 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1728 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1731 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1732 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1734 SDValue OVF = Lo.getValue(1);
1737 case TargetLoweringBase::UndefinedBooleanContent:
1738 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1740 case TargetLoweringBase::ZeroOrOneBooleanContent:
1741 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1743 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1744 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1749 if (N->getOpcode() == ISD::ADD) {
1750 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1751 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1752 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1754 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1755 DAG.getConstant(1, dl, NVT),
1756 DAG.getConstant(0, dl, NVT));
1757 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1759 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1760 DAG.getConstant(1, dl, NVT), Carry1);
1761 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1763 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1764 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1766 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1767 LoOps[0], LoOps[1], ISD::SETULT);
1768 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1769 DAG.getConstant(1, dl, NVT),
1770 DAG.getConstant(0, dl, NVT));
1771 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1775 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1776 SDValue &Lo, SDValue &Hi) {
1777 // Expand the subcomponents.
1778 SDValue LHSL, LHSH, RHSL, RHSH;
1780 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1781 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1782 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1783 SDValue LoOps[2] = { LHSL, RHSL };
1784 SDValue HiOps[3] = { LHSH, RHSH };
1786 if (N->getOpcode() == ISD::ADDC) {
1787 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1788 HiOps[2] = Lo.getValue(1);
1789 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1791 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1792 HiOps[2] = Lo.getValue(1);
1793 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1796 // Legalized the flag result - switch anything that used the old flag to
1798 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1801 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1802 SDValue &Lo, SDValue &Hi) {
1803 // Expand the subcomponents.
1804 SDValue LHSL, LHSH, RHSL, RHSH;
1806 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1807 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1808 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1809 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1810 SDValue HiOps[3] = { LHSH, RHSH };
1812 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1813 HiOps[2] = Lo.getValue(1);
1814 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1816 // Legalized the flag result - switch anything that used the old flag to
1818 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1821 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1822 SDValue &Lo, SDValue &Hi) {
1823 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1825 SDValue Op = N->getOperand(0);
1826 if (Op.getValueType().bitsLE(NVT)) {
1827 // The low part is any extension of the input (which degenerates to a copy).
1828 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1829 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1831 // For example, extension of an i48 to an i64. The operand type necessarily
1832 // promotes to the result type, so will end up being expanded too.
1833 assert(getTypeAction(Op.getValueType()) ==
1834 TargetLowering::TypePromoteInteger &&
1835 "Only know how to promote this result!");
1836 SDValue Res = GetPromotedInteger(Op);
1837 assert(Res.getValueType() == N->getValueType(0) &&
1838 "Operand over promoted?");
1839 // Split the promoted operand. This will simplify when it is expanded.
1840 SplitInteger(Res, Lo, Hi);
1844 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1845 SDValue &Lo, SDValue &Hi) {
1847 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1848 EVT NVT = Lo.getValueType();
1849 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1850 unsigned NVTBits = NVT.getSizeInBits();
1851 unsigned EVTBits = EVT.getSizeInBits();
1853 if (NVTBits < EVTBits) {
1854 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1855 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1856 EVTBits - NVTBits)));
1858 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1859 // The high part replicates the sign bit of Lo, make it explicit.
1860 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1861 DAG.getConstant(NVTBits - 1, dl,
1862 TLI.getPointerTy(DAG.getDataLayout())));
1866 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1867 SDValue &Lo, SDValue &Hi) {
1869 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1870 EVT NVT = Lo.getValueType();
1871 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1872 unsigned NVTBits = NVT.getSizeInBits();
1873 unsigned EVTBits = EVT.getSizeInBits();
1875 if (NVTBits < EVTBits) {
1876 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1877 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1878 EVTBits - NVTBits)));
1880 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1881 // The high part must be zero, make it explicit.
1882 Hi = DAG.getConstant(0, dl, NVT);
1886 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
1887 SDValue &Lo, SDValue &Hi) {
1889 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1890 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
1891 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
1894 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1895 SDValue &Lo, SDValue &Hi) {
1897 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1898 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1899 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1902 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1903 SDValue &Lo, SDValue &Hi) {
1904 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1905 unsigned NBitWidth = NVT.getSizeInBits();
1906 auto Constant = cast<ConstantSDNode>(N);
1907 const APInt &Cst = Constant->getAPIntValue();
1908 bool IsTarget = Constant->isTargetOpcode();
1909 bool IsOpaque = Constant->isOpaque();
1911 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1912 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1916 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1917 SDValue &Lo, SDValue &Hi) {
1919 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1920 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1921 EVT NVT = Lo.getValueType();
1923 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1924 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1926 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1927 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1929 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1930 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1931 DAG.getConstant(NVT.getSizeInBits(), dl,
1933 Hi = DAG.getConstant(0, dl, NVT);
1936 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1937 SDValue &Lo, SDValue &Hi) {
1939 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1940 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1941 EVT NVT = Lo.getValueType();
1942 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1943 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1944 Hi = DAG.getConstant(0, dl, NVT);
1947 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1948 SDValue &Lo, SDValue &Hi) {
1950 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1951 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1952 EVT NVT = Lo.getValueType();
1954 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1955 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1957 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1958 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1960 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1961 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1962 DAG.getConstant(NVT.getSizeInBits(), dl,
1964 Hi = DAG.getConstant(0, dl, NVT);
1967 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1970 EVT VT = N->getValueType(0);
1972 SDValue Op = N->getOperand(0);
1973 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1974 Op = GetPromotedFloat(Op);
1976 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1977 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1978 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, true/*irrelevant*/, dl).first,
1982 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1985 EVT VT = N->getValueType(0);
1987 SDValue Op = N->getOperand(0);
1988 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1989 Op = GetPromotedFloat(Op);
1991 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1992 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1993 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, false/*irrelevant*/, dl).first,
1997 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1998 SDValue &Lo, SDValue &Hi) {
1999 if (ISD::isNormalLoad(N)) {
2000 ExpandRes_NormalLoad(N, Lo, Hi);
2004 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
2006 EVT VT = N->getValueType(0);
2007 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2008 SDValue Ch = N->getChain();
2009 SDValue Ptr = N->getBasePtr();
2010 ISD::LoadExtType ExtType = N->getExtensionType();
2011 unsigned Alignment = N->getAlignment();
2012 bool isVolatile = N->isVolatile();
2013 bool isNonTemporal = N->isNonTemporal();
2014 bool isInvariant = N->isInvariant();
2015 AAMDNodes AAInfo = N->getAAInfo();
2018 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2020 if (N->getMemoryVT().bitsLE(NVT)) {
2021 EVT MemVT = N->getMemoryVT();
2023 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2024 MemVT, isVolatile, isNonTemporal, isInvariant,
2027 // Remember the chain.
2028 Ch = Lo.getValue(1);
2030 if (ExtType == ISD::SEXTLOAD) {
2031 // The high part is obtained by SRA'ing all but one of the bits of the
2033 unsigned LoSize = Lo.getValueType().getSizeInBits();
2034 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2035 DAG.getConstant(LoSize - 1, dl,
2036 TLI.getPointerTy(DAG.getDataLayout())));
2037 } else if (ExtType == ISD::ZEXTLOAD) {
2038 // The high part is just a zero.
2039 Hi = DAG.getConstant(0, dl, NVT);
2041 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
2042 // The high part is undefined.
2043 Hi = DAG.getUNDEF(NVT);
2045 } else if (DAG.getDataLayout().isLittleEndian()) {
2046 // Little-endian - low bits are at low addresses.
2047 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
2048 isVolatile, isNonTemporal, isInvariant, Alignment,
2051 unsigned ExcessBits =
2052 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2053 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2055 // Increment the pointer to the other half.
2056 unsigned IncrementSize = NVT.getSizeInBits()/8;
2057 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2058 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2059 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2060 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2061 isVolatile, isNonTemporal, isInvariant,
2062 MinAlign(Alignment, IncrementSize), AAInfo);
2064 // Build a factor node to remember that this load is independent of the
2066 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2069 // Big-endian - high bits are at low addresses. Favor aligned loads at
2070 // the cost of some bit-fiddling.
2071 EVT MemVT = N->getMemoryVT();
2072 unsigned EBytes = MemVT.getStoreSize();
2073 unsigned IncrementSize = NVT.getSizeInBits()/8;
2074 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2076 // Load both the high bits and maybe some of the low bits.
2077 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2078 EVT::getIntegerVT(*DAG.getContext(),
2079 MemVT.getSizeInBits() - ExcessBits),
2080 isVolatile, isNonTemporal, isInvariant, Alignment,
2083 // Increment the pointer to the other half.
2084 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2085 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2086 // Load the rest of the low bits.
2087 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2088 N->getPointerInfo().getWithOffset(IncrementSize),
2089 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2090 isVolatile, isNonTemporal, isInvariant,
2091 MinAlign(Alignment, IncrementSize), AAInfo);
2093 // Build a factor node to remember that this load is independent of the
2095 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2098 if (ExcessBits < NVT.getSizeInBits()) {
2099 // Transfer low bits from the bottom of Hi to the top of Lo.
2101 ISD::OR, dl, NVT, Lo,
2102 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2103 DAG.getConstant(ExcessBits, dl,
2104 TLI.getPointerTy(DAG.getDataLayout()))));
2105 // Move high bits to the right position in Hi.
2106 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2108 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2109 TLI.getPointerTy(DAG.getDataLayout())));
2113 // Legalize the chain result - switch anything that used the old chain to
2115 ReplaceValueWith(SDValue(N, 1), Ch);
2118 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2119 SDValue &Lo, SDValue &Hi) {
2121 SDValue LL, LH, RL, RH;
2122 GetExpandedInteger(N->getOperand(0), LL, LH);
2123 GetExpandedInteger(N->getOperand(1), RL, RH);
2124 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2125 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2128 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2129 SDValue &Lo, SDValue &Hi) {
2130 EVT VT = N->getValueType(0);
2131 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2134 SDValue LL, LH, RL, RH;
2135 GetExpandedInteger(N->getOperand(0), LL, LH);
2136 GetExpandedInteger(N->getOperand(1), RL, RH);
2138 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2141 // If nothing else, we can make a libcall.
2142 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2144 LC = RTLIB::MUL_I16;
2145 else if (VT == MVT::i32)
2146 LC = RTLIB::MUL_I32;
2147 else if (VT == MVT::i64)
2148 LC = RTLIB::MUL_I64;
2149 else if (VT == MVT::i128)
2150 LC = RTLIB::MUL_I128;
2151 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2153 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2154 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true/*irrelevant*/, dl).first,
2158 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2161 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2162 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2163 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2166 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2169 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2170 SDValue &Lo, SDValue &Hi) {
2171 SDValue LHS = Node->getOperand(0);
2172 SDValue RHS = Node->getOperand(1);
2175 // Expand the result by simply replacing it with the equivalent
2176 // non-overflow-checking operation.
2177 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2178 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2180 SplitInteger(Sum, Lo, Hi);
2182 // Compute the overflow.
2184 // LHSSign -> LHS >= 0
2185 // RHSSign -> RHS >= 0
2186 // SumSign -> Sum >= 0
2189 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2191 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2193 EVT OType = Node->getValueType(1);
2194 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2196 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2197 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2198 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2199 Node->getOpcode() == ISD::SADDO ?
2200 ISD::SETEQ : ISD::SETNE);
2202 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2203 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2205 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2207 // Use the calculated overflow everywhere.
2208 ReplaceValueWith(SDValue(Node, 1), Cmp);
2211 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2212 SDValue &Lo, SDValue &Hi) {
2213 EVT VT = N->getValueType(0);
2215 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2217 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2218 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2219 SplitInteger(Res.getValue(0), Lo, Hi);
2223 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2225 LC = RTLIB::SDIV_I16;
2226 else if (VT == MVT::i32)
2227 LC = RTLIB::SDIV_I32;
2228 else if (VT == MVT::i64)
2229 LC = RTLIB::SDIV_I64;
2230 else if (VT == MVT::i128)
2231 LC = RTLIB::SDIV_I128;
2232 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2234 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2237 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2238 SDValue &Lo, SDValue &Hi) {
2239 EVT VT = N->getValueType(0);
2242 // If we can emit an efficient shift operation, do so now. Check to see if
2243 // the RHS is a constant.
2244 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2245 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
2247 // If we can determine that the high bit of the shift is zero or one, even if
2248 // the low bits are variable, emit this shift in an optimized form.
2249 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2252 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2254 if (N->getOpcode() == ISD::SHL) {
2255 PartsOpc = ISD::SHL_PARTS;
2256 } else if (N->getOpcode() == ISD::SRL) {
2257 PartsOpc = ISD::SRL_PARTS;
2259 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2260 PartsOpc = ISD::SRA_PARTS;
2263 // Next check to see if the target supports this SHL_PARTS operation or if it
2264 // will custom expand it.
2265 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2266 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2267 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2268 Action == TargetLowering::Custom) {
2269 // Expand the subcomponents.
2271 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2272 EVT VT = LHSL.getValueType();
2274 // If the shift amount operand is coming from a vector legalization it may
2275 // have an illegal type. Fix that first by casting the operand, otherwise
2276 // the new SHL_PARTS operation would need further legalization.
2277 SDValue ShiftOp = N->getOperand(1);
2278 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2279 assert(ShiftTy.getScalarType().getSizeInBits() >=
2280 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2281 "ShiftAmountTy is too small to cover the range of this type!");
2282 if (ShiftOp.getValueType() != ShiftTy)
2283 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2285 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2286 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2287 Hi = Lo.getValue(1);
2291 // Otherwise, emit a libcall.
2292 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2294 if (N->getOpcode() == ISD::SHL) {
2295 isSigned = false; /*sign irrelevant*/
2297 LC = RTLIB::SHL_I16;
2298 else if (VT == MVT::i32)
2299 LC = RTLIB::SHL_I32;
2300 else if (VT == MVT::i64)
2301 LC = RTLIB::SHL_I64;
2302 else if (VT == MVT::i128)
2303 LC = RTLIB::SHL_I128;
2304 } else if (N->getOpcode() == ISD::SRL) {
2307 LC = RTLIB::SRL_I16;
2308 else if (VT == MVT::i32)
2309 LC = RTLIB::SRL_I32;
2310 else if (VT == MVT::i64)
2311 LC = RTLIB::SRL_I64;
2312 else if (VT == MVT::i128)
2313 LC = RTLIB::SRL_I128;
2315 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2318 LC = RTLIB::SRA_I16;
2319 else if (VT == MVT::i32)
2320 LC = RTLIB::SRA_I32;
2321 else if (VT == MVT::i64)
2322 LC = RTLIB::SRA_I64;
2323 else if (VT == MVT::i128)
2324 LC = RTLIB::SRA_I128;
2327 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2328 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2329 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, isSigned, dl).first, Lo, Hi);
2333 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2334 llvm_unreachable("Unsupported shift!");
2337 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2338 SDValue &Lo, SDValue &Hi) {
2339 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2341 SDValue Op = N->getOperand(0);
2342 if (Op.getValueType().bitsLE(NVT)) {
2343 // The low part is sign extension of the input (degenerates to a copy).
2344 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2345 // The high part is obtained by SRA'ing all but one of the bits of low part.
2346 unsigned LoSize = NVT.getSizeInBits();
2348 ISD::SRA, dl, NVT, Lo,
2349 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2351 // For example, extension of an i48 to an i64. The operand type necessarily
2352 // promotes to the result type, so will end up being expanded too.
2353 assert(getTypeAction(Op.getValueType()) ==
2354 TargetLowering::TypePromoteInteger &&
2355 "Only know how to promote this result!");
2356 SDValue Res = GetPromotedInteger(Op);
2357 assert(Res.getValueType() == N->getValueType(0) &&
2358 "Operand over promoted?");
2359 // Split the promoted operand. This will simplify when it is expanded.
2360 SplitInteger(Res, Lo, Hi);
2361 unsigned ExcessBits =
2362 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2363 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2364 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2369 void DAGTypeLegalizer::
2370 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2372 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2373 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2375 if (EVT.bitsLE(Lo.getValueType())) {
2376 // sext_inreg the low part if needed.
2377 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2380 // The high part gets the sign extension from the lo-part. This handles
2381 // things like sextinreg V:i64 from i8.
2382 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2383 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2384 TLI.getPointerTy(DAG.getDataLayout())));
2386 // For example, extension of an i48 to an i64. Leave the low part alone,
2387 // sext_inreg the high part.
2388 unsigned ExcessBits =
2389 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2390 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2391 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2396 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2397 SDValue &Lo, SDValue &Hi) {
2398 EVT VT = N->getValueType(0);
2400 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2402 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2403 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2404 SplitInteger(Res.getValue(1), Lo, Hi);
2408 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2410 LC = RTLIB::SREM_I16;
2411 else if (VT == MVT::i32)
2412 LC = RTLIB::SREM_I32;
2413 else if (VT == MVT::i64)
2414 LC = RTLIB::SREM_I64;
2415 else if (VT == MVT::i128)
2416 LC = RTLIB::SREM_I128;
2417 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2419 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2422 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2423 SDValue &Lo, SDValue &Hi) {
2424 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2426 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2427 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2429 DAG.getConstant(NVT.getSizeInBits(), dl,
2430 TLI.getPointerTy(DAG.getDataLayout())));
2431 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2434 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2435 SDValue &Lo, SDValue &Hi) {
2436 SDValue LHS = N->getOperand(0);
2437 SDValue RHS = N->getOperand(1);
2440 // Expand the result by simply replacing it with the equivalent
2441 // non-overflow-checking operation.
2442 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2443 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2445 SplitInteger(Sum, Lo, Hi);
2447 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2448 // overflows iff a - b > a.
2449 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2450 N->getOpcode () == ISD::UADDO ?
2451 ISD::SETULT : ISD::SETUGT);
2453 // Use the calculated overflow everywhere.
2454 ReplaceValueWith(SDValue(N, 1), Ofl);
2457 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2458 SDValue &Lo, SDValue &Hi) {
2459 EVT VT = N->getValueType(0);
2462 // A divide for UMULO should be faster than a function call.
2463 if (N->getOpcode() == ISD::UMULO) {
2464 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2466 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2467 SplitInteger(MUL, Lo, Hi);
2469 // A divide for UMULO will be faster than a function call. Select to
2470 // make sure we aren't using 0.
2471 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2472 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2473 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2474 DAG.getConstant(1, dl, VT), RHS);
2475 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2476 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2478 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2479 DAG.getConstant(0, dl, N->getValueType(1)),
2481 ReplaceValueWith(SDValue(N, 1), Overflow);
2485 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2486 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2487 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2489 // Replace this with a libcall that will check overflow.
2490 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2492 LC = RTLIB::MULO_I32;
2493 else if (VT == MVT::i64)
2494 LC = RTLIB::MULO_I64;
2495 else if (VT == MVT::i128)
2496 LC = RTLIB::MULO_I128;
2497 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2499 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2500 // Temporary for the overflow value, default it to zero.
2501 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2502 DAG.getConstant(0, dl, PtrVT), Temp,
2503 MachinePointerInfo(), false, false, 0);
2505 TargetLowering::ArgListTy Args;
2506 TargetLowering::ArgListEntry Entry;
2507 for (const SDValue &Op : N->op_values()) {
2508 EVT ArgVT = Op.getValueType();
2509 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2512 Entry.isSExt = true;
2513 Entry.isZExt = false;
2514 Args.push_back(Entry);
2517 // Also pass the address of the overflow check.
2519 Entry.Ty = PtrTy->getPointerTo();
2520 Entry.isSExt = true;
2521 Entry.isZExt = false;
2522 Args.push_back(Entry);
2524 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2526 TargetLowering::CallLoweringInfo CLI(DAG);
2527 CLI.setDebugLoc(dl).setChain(Chain)
2528 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2531 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2533 SplitInteger(CallInfo.first, Lo, Hi);
2534 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2535 MachinePointerInfo(), false, false, false, 0);
2536 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2537 DAG.getConstant(0, dl, PtrVT),
2539 // Use the overflow from the libcall everywhere.
2540 ReplaceValueWith(SDValue(N, 1), Ofl);
2543 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2544 SDValue &Lo, SDValue &Hi) {
2545 EVT VT = N->getValueType(0);
2547 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2549 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2550 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2551 SplitInteger(Res.getValue(0), Lo, Hi);
2555 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2557 LC = RTLIB::UDIV_I16;
2558 else if (VT == MVT::i32)
2559 LC = RTLIB::UDIV_I32;
2560 else if (VT == MVT::i64)
2561 LC = RTLIB::UDIV_I64;
2562 else if (VT == MVT::i128)
2563 LC = RTLIB::UDIV_I128;
2564 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2566 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2569 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2570 SDValue &Lo, SDValue &Hi) {
2571 EVT VT = N->getValueType(0);
2573 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2575 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2576 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2577 SplitInteger(Res.getValue(1), Lo, Hi);
2581 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2583 LC = RTLIB::UREM_I16;
2584 else if (VT == MVT::i32)
2585 LC = RTLIB::UREM_I32;
2586 else if (VT == MVT::i64)
2587 LC = RTLIB::UREM_I64;
2588 else if (VT == MVT::i128)
2589 LC = RTLIB::UREM_I128;
2590 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2592 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2595 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2596 SDValue &Lo, SDValue &Hi) {
2597 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2599 SDValue Op = N->getOperand(0);
2600 if (Op.getValueType().bitsLE(NVT)) {
2601 // The low part is zero extension of the input (degenerates to a copy).
2602 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2603 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2605 // For example, extension of an i48 to an i64. The operand type necessarily
2606 // promotes to the result type, so will end up being expanded too.
2607 assert(getTypeAction(Op.getValueType()) ==
2608 TargetLowering::TypePromoteInteger &&
2609 "Only know how to promote this result!");
2610 SDValue Res = GetPromotedInteger(Op);
2611 assert(Res.getValueType() == N->getValueType(0) &&
2612 "Operand over promoted?");
2613 // Split the promoted operand. This will simplify when it is expanded.
2614 SplitInteger(Res, Lo, Hi);
2615 unsigned ExcessBits =
2616 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2617 Hi = DAG.getZeroExtendInReg(Hi, dl,
2618 EVT::getIntegerVT(*DAG.getContext(),
2623 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2624 SDValue &Lo, SDValue &Hi) {
2626 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2627 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2628 SDValue Zero = DAG.getConstant(0, dl, VT);
2629 SDValue Swap = DAG.getAtomicCmpSwap(
2630 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2631 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2632 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2633 cast<AtomicSDNode>(N)->getOrdering(),
2634 cast<AtomicSDNode>(N)->getOrdering(),
2635 cast<AtomicSDNode>(N)->getSynchScope());
2637 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2638 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2641 //===----------------------------------------------------------------------===//
2642 // Integer Operand Expansion
2643 //===----------------------------------------------------------------------===//
2645 /// ExpandIntegerOperand - This method is called when the specified operand of
2646 /// the specified node is found to need expansion. At this point, all of the
2647 /// result types of the node are known to be legal, but other operands of the
2648 /// node may need promotion or expansion as well as the specified one.
2649 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2650 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2651 SDValue Res = SDValue();
2653 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2656 switch (N->getOpcode()) {
2659 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2660 N->dump(&DAG); dbgs() << "\n";
2662 llvm_unreachable("Do not know how to expand this operator's operand!");
2664 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2665 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2666 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2667 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2668 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2669 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2670 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2671 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2672 case ISD::SETCCE: Res = ExpandIntOp_SETCCE(N); break;
2673 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2674 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2675 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2676 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2682 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2683 case ISD::RETURNADDR:
2684 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2686 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2689 // If the result is null, the sub-method took care of registering results etc.
2690 if (!Res.getNode()) return false;
2692 // If the result is N, the sub-method updated N in place. Tell the legalizer
2694 if (Res.getNode() == N)
2697 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2698 "Invalid operand expansion");
2700 ReplaceValueWith(SDValue(N, 0), Res);
2704 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2705 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2706 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2708 ISD::CondCode &CCCode,
2710 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2711 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2712 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2714 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2715 if (RHSLo == RHSHi) {
2716 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2717 if (RHSCST->isAllOnesValue()) {
2718 // Equality comparison to -1.
2719 NewLHS = DAG.getNode(ISD::AND, dl,
2720 LHSLo.getValueType(), LHSLo, LHSHi);
2727 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2728 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2729 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2730 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2734 // If this is a comparison of the sign bit, just look at the top part.
2736 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2737 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2738 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2744 // FIXME: This generated code sucks.
2745 ISD::CondCode LowCC;
2747 default: llvm_unreachable("Unknown integer setcc!");
2749 case ISD::SETULT: LowCC = ISD::SETULT; break;
2751 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2753 case ISD::SETULE: LowCC = ISD::SETULE; break;
2755 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2758 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2759 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2760 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2762 // NOTE: on targets without efficient SELECT of bools, we can always use
2763 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2764 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2767 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2768 TLI.isTypeLegal(RHSLo.getValueType()))
2769 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2770 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2771 if (!Tmp1.getNode())
2772 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2773 LHSLo, RHSLo, LowCC);
2774 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2775 TLI.isTypeLegal(RHSHi.getValueType()))
2776 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2777 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2778 if (!Tmp2.getNode())
2779 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2780 getSetCCResultType(LHSHi.getValueType()),
2781 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2783 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2784 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2785 if ((Tmp1C && Tmp1C->isNullValue()) ||
2786 (Tmp2C && Tmp2C->isNullValue() &&
2787 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2788 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2789 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2790 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2791 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2792 // low part is known false, returns high part.
2793 // For LE / GE, if high part is known false, ignore the low part.
2794 // For LT / GT, if high part is known true, ignore the low part.
2800 if (LHSHi == RHSHi) {
2801 // Comparing the low bits is enough.
2807 // Lower with SETCCE if the target supports it.
2808 // FIXME: Make all targets support this, then remove the other lowering.
2809 if (TLI.getOperationAction(
2811 TLI.getTypeToExpandTo(*DAG.getContext(), LHSLo.getValueType())) ==
2812 TargetLowering::Custom) {
2813 // SETCCE can detect < and >= directly. For > and <=, flip operands and
2815 bool FlipOperands = false;
2817 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
2818 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
2819 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
2820 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
2824 std::swap(LHSLo, RHSLo);
2825 std::swap(LHSHi, RHSHi);
2827 // Perform a wide subtraction, feeding the carry from the low part into
2828 // SETCCE. The SETCCE operation is essentially looking at the high part of
2829 // the result of LHS - RHS. It is negative iff LHS < RHS. It is zero or
2830 // positive iff LHS >= RHS.
2831 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2832 SDValue LowCmp = DAG.getNode(ISD::SUBC, dl, VTList, LHSLo, RHSLo);
2834 DAG.getNode(ISD::SETCCE, dl, getSetCCResultType(LHSLo.getValueType()),
2835 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode));
2841 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2842 LHSHi, RHSHi, ISD::SETEQ, false,
2843 DagCombineInfo, dl);
2844 if (!NewLHS.getNode())
2845 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2846 LHSHi, RHSHi, ISD::SETEQ);
2847 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2848 NewLHS, Tmp1, Tmp2);
2852 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2853 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2854 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2855 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2857 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2858 // against zero to select between true and false values.
2859 if (!NewRHS.getNode()) {
2860 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2861 CCCode = ISD::SETNE;
2864 // Update N to have the operands specified.
2865 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2866 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2867 N->getOperand(4)), 0);
2870 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2871 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2872 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2873 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2875 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2876 // against zero to select between true and false values.
2877 if (!NewRHS.getNode()) {
2878 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2879 CCCode = ISD::SETNE;
2882 // Update N to have the operands specified.
2883 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2884 N->getOperand(2), N->getOperand(3),
2885 DAG.getCondCode(CCCode)), 0);
2888 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2889 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2890 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2891 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2893 // If ExpandSetCCOperands returned a scalar, use it.
2894 if (!NewRHS.getNode()) {
2895 assert(NewLHS.getValueType() == N->getValueType(0) &&
2896 "Unexpected setcc expansion!");
2900 // Otherwise, update N to have the operands specified.
2901 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2902 DAG.getCondCode(CCCode)), 0);
2905 SDValue DAGTypeLegalizer::ExpandIntOp_SETCCE(SDNode *N) {
2906 SDValue LHS = N->getOperand(0);
2907 SDValue RHS = N->getOperand(1);
2908 SDValue Carry = N->getOperand(2);
2909 SDValue Cond = N->getOperand(3);
2910 SDLoc dl = SDLoc(N);
2912 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2913 GetExpandedInteger(LHS, LHSLo, LHSHi);
2914 GetExpandedInteger(RHS, RHSLo, RHSHi);
2916 // Expand to a SUBE for the low part and a smaller SETCCE for the high.
2917 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2918 SDValue LowCmp = DAG.getNode(ISD::SUBE, dl, VTList, LHSLo, RHSLo, Carry);
2919 return DAG.getNode(ISD::SETCCE, dl, N->getValueType(0), LHSHi, RHSHi,
2920 LowCmp.getValue(1), Cond);
2923 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2924 // The value being shifted is legal, but the shift amount is too big.
2925 // It follows that either the result of the shift is undefined, or the
2926 // upper half of the shift amount is zero. Just use the lower half.
2928 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2929 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2932 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2933 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2934 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2935 // constant to valid type.
2937 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2938 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2941 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2942 SDValue Op = N->getOperand(0);
2943 EVT DstVT = N->getValueType(0);
2944 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2945 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2946 "Don't know how to expand this SINT_TO_FP!");
2947 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first;
2950 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2951 if (ISD::isNormalStore(N))
2952 return ExpandOp_NormalStore(N, OpNo);
2954 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2955 assert(OpNo == 1 && "Can only expand the stored value so far");
2957 EVT VT = N->getOperand(1).getValueType();
2958 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2959 SDValue Ch = N->getChain();
2960 SDValue Ptr = N->getBasePtr();
2961 unsigned Alignment = N->getAlignment();
2962 bool isVolatile = N->isVolatile();
2963 bool isNonTemporal = N->isNonTemporal();
2964 AAMDNodes AAInfo = N->getAAInfo();
2968 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2970 if (N->getMemoryVT().bitsLE(NVT)) {
2971 GetExpandedInteger(N->getValue(), Lo, Hi);
2972 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2973 N->getMemoryVT(), isVolatile, isNonTemporal,
2977 if (DAG.getDataLayout().isLittleEndian()) {
2978 // Little-endian - low bits are at low addresses.
2979 GetExpandedInteger(N->getValue(), Lo, Hi);
2981 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2982 isVolatile, isNonTemporal, Alignment, AAInfo);
2984 unsigned ExcessBits =
2985 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2986 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2988 // Increment the pointer to the other half.
2989 unsigned IncrementSize = NVT.getSizeInBits()/8;
2990 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2991 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2992 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2993 N->getPointerInfo().getWithOffset(IncrementSize),
2994 NEVT, isVolatile, isNonTemporal,
2995 MinAlign(Alignment, IncrementSize), AAInfo);
2996 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2999 // Big-endian - high bits are at low addresses. Favor aligned stores at
3000 // the cost of some bit-fiddling.
3001 GetExpandedInteger(N->getValue(), Lo, Hi);
3003 EVT ExtVT = N->getMemoryVT();
3004 unsigned EBytes = ExtVT.getStoreSize();
3005 unsigned IncrementSize = NVT.getSizeInBits()/8;
3006 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3007 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
3008 ExtVT.getSizeInBits() - ExcessBits);
3010 if (ExcessBits < NVT.getSizeInBits()) {
3011 // Transfer high bits from the top of Lo to the bottom of Hi.
3012 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
3013 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3014 TLI.getPointerTy(DAG.getDataLayout())));
3016 ISD::OR, dl, NVT, Hi,
3017 DAG.getNode(ISD::SRL, dl, NVT, Lo,
3018 DAG.getConstant(ExcessBits, dl,
3019 TLI.getPointerTy(DAG.getDataLayout()))));
3022 // Store both the high bits and maybe some of the low bits.
3023 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
3024 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
3026 // Increment the pointer to the other half.
3027 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
3028 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
3029 // Store the lowest ExcessBits bits in the second half.
3030 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
3031 N->getPointerInfo().getWithOffset(IncrementSize),
3032 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3033 isVolatile, isNonTemporal,
3034 MinAlign(Alignment, IncrementSize), AAInfo);
3035 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3038 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
3040 GetExpandedInteger(N->getOperand(0), InL, InH);
3041 // Just truncate the low part of the source.
3042 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
3045 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
3046 SDValue Op = N->getOperand(0);
3047 EVT SrcVT = Op.getValueType();
3048 EVT DstVT = N->getValueType(0);
3051 // The following optimization is valid only if every value in SrcVT (when
3052 // treated as signed) is representable in DstVT. Check that the mantissa
3053 // size of DstVT is >= than the number of bits in SrcVT -1.
3054 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
3055 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
3056 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
3057 // Do a signed conversion then adjust the result.
3058 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
3059 SignedConv = TLI.LowerOperation(SignedConv, DAG);
3061 // The result of the signed conversion needs adjusting if the 'sign bit' of
3062 // the incoming integer was set. To handle this, we dynamically test to see
3063 // if it is set, and, if so, add a fudge factor.
3065 const uint64_t F32TwoE32 = 0x4F800000ULL;
3066 const uint64_t F32TwoE64 = 0x5F800000ULL;
3067 const uint64_t F32TwoE128 = 0x7F800000ULL;
3070 if (SrcVT == MVT::i32)
3071 FF = APInt(32, F32TwoE32);
3072 else if (SrcVT == MVT::i64)
3073 FF = APInt(32, F32TwoE64);
3074 else if (SrcVT == MVT::i128)
3075 FF = APInt(32, F32TwoE128);
3077 llvm_unreachable("Unsupported UINT_TO_FP!");
3079 // Check whether the sign bit is set.
3081 GetExpandedInteger(Op, Lo, Hi);
3082 SDValue SignSet = DAG.getSetCC(dl,
3083 getSetCCResultType(Hi.getValueType()),
3085 DAG.getConstant(0, dl, Hi.getValueType()),
3088 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
3090 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
3091 TLI.getPointerTy(DAG.getDataLayout()));
3093 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
3094 SDValue Zero = DAG.getIntPtrConstant(0, dl);
3095 SDValue Four = DAG.getIntPtrConstant(4, dl);
3096 if (DAG.getDataLayout().isBigEndian())
3097 std::swap(Zero, Four);
3098 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
3100 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
3101 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
3103 Alignment = std::min(Alignment, 4u);
3105 // Load the value out, extending it from f32 to the destination float type.
3106 // FIXME: Avoid the extend by constructing the right constant pool?
3107 SDValue Fudge = DAG.getExtLoad(
3108 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
3109 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
3110 false, false, false, Alignment);
3111 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
3114 // Otherwise, use a libcall.
3115 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
3116 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3117 "Don't know how to expand this UINT_TO_FP!");
3118 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first;
3121 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
3123 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3124 cast<AtomicSDNode>(N)->getMemoryVT(),
3126 N->getOperand(1), N->getOperand(2),
3127 cast<AtomicSDNode>(N)->getMemOperand(),
3128 cast<AtomicSDNode>(N)->getOrdering(),
3129 cast<AtomicSDNode>(N)->getSynchScope());
3130 return Swap.getValue(1);
3134 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3135 SDValue InOp0 = N->getOperand(0);
3136 EVT InVT = InOp0.getValueType();
3138 EVT OutVT = N->getValueType(0);
3139 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3140 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3141 unsigned OutNumElems = OutVT.getVectorNumElements();
3142 EVT NOutVTElem = NOutVT.getVectorElementType();
3145 SDValue BaseIdx = N->getOperand(1);
3147 SmallVector<SDValue, 8> Ops;
3148 Ops.reserve(OutNumElems);
3149 for (unsigned i = 0; i != OutNumElems; ++i) {
3151 // Extract the element from the original vector.
3152 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3153 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3154 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3155 InVT.getVectorElementType(), N->getOperand(0), Index);
3157 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3158 // Insert the converted element to the new vector.
3162 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3166 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3167 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3168 EVT VT = N->getValueType(0);
3171 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3173 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3174 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3175 EVT OutVT = V0.getValueType();
3177 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3181 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3182 EVT OutVT = N->getValueType(0);
3183 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3184 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3185 unsigned NumElems = N->getNumOperands();
3186 EVT NOutVTElem = NOutVT.getVectorElementType();
3190 SmallVector<SDValue, 8> Ops;
3191 Ops.reserve(NumElems);
3192 for (unsigned i = 0; i != NumElems; ++i) {
3194 // BUILD_VECTOR integer operand types are allowed to be larger than the
3195 // result's element type. This may still be true after the promotion. For
3196 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3197 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3198 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3199 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3201 Op = N->getOperand(i);
3205 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3208 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3212 assert(!N->getOperand(0).getValueType().isVector() &&
3213 "Input must be a scalar");
3215 EVT OutVT = N->getValueType(0);
3216 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3217 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3218 EVT NOutVTElem = NOutVT.getVectorElementType();
3220 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3222 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3225 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3228 EVT OutVT = N->getValueType(0);
3229 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3230 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3232 EVT InElemTy = OutVT.getVectorElementType();
3233 EVT OutElemTy = NOutVT.getVectorElementType();
3235 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3236 unsigned NumOutElem = NOutVT.getVectorNumElements();
3237 unsigned NumOperands = N->getNumOperands();
3238 assert(NumElem * NumOperands == NumOutElem &&
3239 "Unexpected number of elements");
3241 // Take the elements from the first vector.
3242 SmallVector<SDValue, 8> Ops(NumOutElem);
3243 for (unsigned i = 0; i < NumOperands; ++i) {
3244 SDValue Op = N->getOperand(i);
3245 for (unsigned j = 0; j < NumElem; ++j) {
3246 SDValue Ext = DAG.getNode(
3247 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op,
3248 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3249 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3253 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3256 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3257 EVT OutVT = N->getValueType(0);
3258 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3259 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3261 EVT NOutVTElem = NOutVT.getVectorElementType();
3264 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3266 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3267 NOutVTElem, N->getOperand(1));
3268 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3269 V0, ConvElem, N->getOperand(2));
3272 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3274 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3275 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3276 TLI.getVectorIdxTy(DAG.getDataLayout()));
3277 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3278 V0->getValueType(0).getScalarType(), V0, V1);
3280 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3281 // element types. If this is the case then we need to expand the outgoing
3282 // value and not truncate it.
3283 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3286 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3288 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3289 MVT InVT = V0.getValueType().getSimpleVT();
3290 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3291 N->getValueType(0).getVectorNumElements());
3292 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3293 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3296 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3298 unsigned NumElems = N->getNumOperands();
3300 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3302 SmallVector<SDValue, 8> NewOps;
3303 NewOps.reserve(NumElems);
3305 // For each incoming vector
3306 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3307 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3308 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3309 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3311 for (unsigned i=0; i<NumElem; ++i) {
3312 // Extract element from incoming vector
3313 SDValue Ex = DAG.getNode(
3314 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3315 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3316 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3317 NewOps.push_back(Tr);
3321 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);