1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
60 case ISD::CONVERT_RNDSAT:
61 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
62 case ISD::CTLZ_ZERO_UNDEF:
63 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
64 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
65 case ISD::CTTZ_ZERO_UNDEF:
66 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
67 case ISD::EXTRACT_VECTOR_ELT:
68 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
69 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
70 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
71 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
72 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
73 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
74 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
78 case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N); break;
79 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
80 case ISD::SIGN_EXTEND_INREG:
81 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
82 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
83 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
84 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
85 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
86 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
88 case ISD::EXTRACT_SUBVECTOR:
89 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
90 case ISD::VECTOR_SHUFFLE:
91 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
92 case ISD::INSERT_VECTOR_ELT:
93 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
94 case ISD::BUILD_VECTOR:
95 Res = PromoteIntRes_BUILD_VECTOR(N); break;
96 case ISD::SCALAR_TO_VECTOR:
97 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
98 case ISD::CONCAT_VECTORS:
99 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
101 case ISD::SIGN_EXTEND:
102 case ISD::ZERO_EXTEND:
103 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
105 case ISD::FP_TO_SINT:
106 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
108 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
115 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
118 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
121 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
124 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
126 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
128 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
130 case ISD::ATOMIC_LOAD:
131 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
133 case ISD::ATOMIC_LOAD_ADD:
134 case ISD::ATOMIC_LOAD_SUB:
135 case ISD::ATOMIC_LOAD_AND:
136 case ISD::ATOMIC_LOAD_OR:
137 case ISD::ATOMIC_LOAD_XOR:
138 case ISD::ATOMIC_LOAD_NAND:
139 case ISD::ATOMIC_LOAD_MIN:
140 case ISD::ATOMIC_LOAD_MAX:
141 case ISD::ATOMIC_LOAD_UMIN:
142 case ISD::ATOMIC_LOAD_UMAX:
143 case ISD::ATOMIC_SWAP:
144 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
146 case ISD::ATOMIC_CMP_SWAP:
147 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
148 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
152 Res = PromoteIntRes_SimpleIntBinOp(N);
156 // If the result is null then the sub-method took care of registering it.
158 SetPromotedInteger(SDValue(N, ResNo), Res);
161 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
163 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
164 return GetPromotedInteger(Op);
167 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
168 // Sign-extend the new bits, and continue the assertion.
169 SDValue Op = SExtPromotedInteger(N->getOperand(0));
170 return DAG.getNode(ISD::AssertSext, SDLoc(N),
171 Op.getValueType(), Op, N->getOperand(1));
174 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
175 // Zero the new bits, and continue the assertion.
176 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
177 return DAG.getNode(ISD::AssertZext, SDLoc(N),
178 Op.getValueType(), Op, N->getOperand(1));
181 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
182 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
183 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
184 N->getMemoryVT(), ResVT,
185 N->getChain(), N->getBasePtr(),
186 N->getMemOperand(), N->getOrdering(),
188 // Legalized the chain result - switch anything that used the old chain to
190 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
194 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
195 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
196 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
198 N->getChain(), N->getBasePtr(),
199 Op2, N->getMemOperand(), N->getOrdering(),
201 // Legalized the chain result - switch anything that used the old chain to
203 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
207 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
210 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
211 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
212 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
214 // Only use the result of getSetCCResultType if it is legal,
215 // otherwise just use the promoted result type (NVT).
216 if (!TLI.isTypeLegal(SVT))
219 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
220 SDValue Res = DAG.getAtomicCmpSwap(
221 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
222 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
223 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
225 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
226 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
227 return Res.getValue(1);
230 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
231 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
233 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
234 SDValue Res = DAG.getAtomicCmpSwap(
235 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
236 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
237 N->getFailureOrdering(), N->getSynchScope());
238 // Update the use to N with the newly created Res.
239 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
240 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
244 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
245 SDValue InOp = N->getOperand(0);
246 EVT InVT = InOp.getValueType();
247 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
248 EVT OutVT = N->getValueType(0);
249 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
252 switch (getTypeAction(InVT)) {
253 case TargetLowering::TypeLegal:
255 case TargetLowering::TypePromoteInteger:
256 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
257 // The input promotes to the same size. Convert the promoted value.
258 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
260 case TargetLowering::TypeSoftenFloat:
261 // Promote the integer operand by hand.
262 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
263 case TargetLowering::TypePromoteFloat: {
264 // Convert the promoted float by hand.
265 if (NOutVT.bitsEq(NInVT)) {
266 SDValue PromotedOp = GetPromotedFloat(InOp);
267 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
268 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
269 DAG.getValueType(OutVT));
273 case TargetLowering::TypeExpandInteger:
274 case TargetLowering::TypeExpandFloat:
276 case TargetLowering::TypeScalarizeVector:
277 // Convert the element to an integer and promote it by hand.
278 if (!NOutVT.isVector())
279 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
280 BitConvertToInteger(GetScalarizedVector(InOp)));
282 case TargetLowering::TypeSplitVector: {
283 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
284 // pieces of the input into integers and reassemble in the final type.
286 GetSplitVector(N->getOperand(0), Lo, Hi);
287 Lo = BitConvertToInteger(Lo);
288 Hi = BitConvertToInteger(Hi);
290 if (DAG.getDataLayout().isBigEndian())
293 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
294 EVT::getIntegerVT(*DAG.getContext(),
295 NOutVT.getSizeInBits()),
296 JoinIntegers(Lo, Hi));
297 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
299 case TargetLowering::TypeWidenVector:
300 // The input is widened to the same size. Convert to the widened value.
301 // Make sure that the outgoing value is not a vector, because this would
302 // make us bitcast between two vectors which are legalized in different ways.
303 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
304 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
307 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
308 CreateStackStoreLoad(InOp, OutVT));
311 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
312 SDValue Op = GetPromotedInteger(N->getOperand(0));
313 EVT OVT = N->getValueType(0);
314 EVT NVT = Op.getValueType();
317 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
319 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
320 DAG.getConstant(DiffBits, dl,
321 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
324 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
325 SDValue Op = GetPromotedInteger(N->getOperand(0));
326 EVT OVT = N->getValueType(0);
327 EVT NVT = Op.getValueType();
330 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
332 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
333 DAG.getConstant(DiffBits, dl,
334 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
337 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
338 // The pair element type may be legal, or may not promote to the same type as
339 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
340 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
341 TLI.getTypeToTransformTo(*DAG.getContext(),
342 N->getValueType(0)), JoinIntegers(N->getOperand(0),
346 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
347 EVT VT = N->getValueType(0);
348 // FIXME there is no actual debug info here
350 // Zero extend things like i1, sign extend everything else. It shouldn't
351 // matter in theory which one we pick, but this tends to give better code?
352 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
353 SDValue Result = DAG.getNode(Opc, dl,
354 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
356 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
360 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
361 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
362 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
363 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
364 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
365 "can only promote integers");
366 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
367 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
368 N->getOperand(1), N->getOperand(2),
369 N->getOperand(3), N->getOperand(4), CvtCode);
372 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
373 // Zero extend to the promoted type and do the count there.
374 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
376 EVT OVT = N->getValueType(0);
377 EVT NVT = Op.getValueType();
378 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
379 // Subtract off the extra leading bits in the bigger type.
381 ISD::SUB, dl, NVT, Op,
382 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
386 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
387 // Zero extend to the promoted type and do the count there.
388 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
389 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
392 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
393 SDValue Op = GetPromotedInteger(N->getOperand(0));
394 EVT OVT = N->getValueType(0);
395 EVT NVT = Op.getValueType();
397 if (N->getOpcode() == ISD::CTTZ) {
398 // The count is the same in the promoted type except if the original
399 // value was zero. This can be handled by setting the bit just off
400 // the top of the original type.
401 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
402 OVT.getScalarSizeInBits());
403 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
405 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
408 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
410 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
411 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
415 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
416 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
417 unsigned NewOpc = N->getOpcode();
420 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
421 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
422 // and SINT conversions are Custom, there is no way to tell which is
423 // preferable. We choose SINT because that's the right thing on PPC.)
424 if (N->getOpcode() == ISD::FP_TO_UINT &&
425 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
426 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
427 NewOpc = ISD::FP_TO_SINT;
429 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
431 // Assert that the converted value fits in the original type. If it doesn't
432 // (eg: because the value being converted is too big), then the result of the
433 // original operation was undefined anyway, so the assert is still correct.
434 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
435 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
436 DAG.getValueType(N->getValueType(0).getScalarType()));
439 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
440 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
443 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
445 return DAG.getNode(ISD::AssertZext, dl,
446 NVT, Res, DAG.getValueType(N->getValueType(0)));
449 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
450 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
453 if (getTypeAction(N->getOperand(0).getValueType())
454 == TargetLowering::TypePromoteInteger) {
455 SDValue Res = GetPromotedInteger(N->getOperand(0));
456 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
458 // If the result and operand types are the same after promotion, simplify
459 // to an in-register extension.
460 if (NVT == Res.getValueType()) {
461 // The high bits are not guaranteed to be anything. Insert an extend.
462 if (N->getOpcode() == ISD::SIGN_EXTEND)
463 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
464 DAG.getValueType(N->getOperand(0).getValueType()));
465 if (N->getOpcode() == ISD::ZERO_EXTEND)
466 return DAG.getZeroExtendInReg(Res, dl,
467 N->getOperand(0).getValueType().getScalarType());
468 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
473 // Otherwise, just extend the original operand all the way to the larger type.
474 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
477 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
478 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
479 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
480 ISD::LoadExtType ExtType =
481 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
483 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
484 N->getMemoryVT(), N->getMemOperand());
486 // Legalized the chain result - switch anything that used the old chain to
488 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
492 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
493 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
494 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
496 SDValue Mask = N->getMask();
497 EVT NewMaskVT = getSetCCResultType(NVT);
498 if (NewMaskVT != N->getMask().getValueType())
499 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
502 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
503 Mask, ExtSrc0, N->getMemoryVT(),
504 N->getMemOperand(), ISD::SEXTLOAD);
505 // Legalized the chain result - switch anything that used the old chain to
507 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
510 /// Promote the overflow flag of an overflowing arithmetic node.
511 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
512 // Simply change the return type of the boolean result.
513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
514 EVT ValueVTs[] = { N->getValueType(0), NVT };
515 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
516 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
517 DAG.getVTList(ValueVTs), Ops);
519 // Modified the sum result - switch anything that used the old sum to use
521 ReplaceValueWith(SDValue(N, 0), Res);
523 return SDValue(Res.getNode(), 1);
526 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
528 return PromoteIntRes_Overflow(N);
530 // The operation overflowed iff the result in the larger type is not the
531 // sign extension of its truncation to the original type.
532 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
533 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
534 EVT OVT = N->getOperand(0).getValueType();
535 EVT NVT = LHS.getValueType();
538 // Do the arithmetic in the larger type.
539 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
540 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
542 // Calculate the overflow flag: sign extend the arithmetic result from
543 // the original type.
544 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
545 DAG.getValueType(OVT));
546 // Overflowed if and only if this is not equal to Res.
547 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
549 // Use the calculated overflow everywhere.
550 ReplaceValueWith(SDValue(N, 1), Ofl);
555 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
556 // Sign extend the input.
557 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
558 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
559 return DAG.getNode(N->getOpcode(), SDLoc(N),
560 LHS.getValueType(), LHS, RHS);
563 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
564 SDValue LHS = GetPromotedInteger(N->getOperand(1));
565 SDValue RHS = GetPromotedInteger(N->getOperand(2));
566 return DAG.getSelect(SDLoc(N),
567 LHS.getValueType(), N->getOperand(0), LHS, RHS);
570 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
571 SDValue Mask = N->getOperand(0);
572 EVT OpTy = N->getOperand(1).getValueType();
574 // Promote all the way up to the canonical SetCC type.
575 Mask = PromoteTargetBoolean(Mask, OpTy);
576 SDValue LHS = GetPromotedInteger(N->getOperand(1));
577 SDValue RHS = GetPromotedInteger(N->getOperand(2));
578 return DAG.getNode(ISD::VSELECT, SDLoc(N),
579 LHS.getValueType(), Mask, LHS, RHS);
582 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
583 SDValue LHS = GetPromotedInteger(N->getOperand(2));
584 SDValue RHS = GetPromotedInteger(N->getOperand(3));
585 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
586 LHS.getValueType(), N->getOperand(0),
587 N->getOperand(1), LHS, RHS, N->getOperand(4));
590 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
591 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
593 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
595 // Only use the result of getSetCCResultType if it is legal,
596 // otherwise just use the promoted result type (NVT).
597 if (!TLI.isTypeLegal(SVT))
601 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
602 "Vector compare must return a vector result!");
604 SDValue LHS = N->getOperand(0);
605 SDValue RHS = N->getOperand(1);
606 if (LHS.getValueType() != RHS.getValueType()) {
607 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
608 !LHS.getValueType().isVector())
609 LHS = GetPromotedInteger(LHS);
610 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
611 !RHS.getValueType().isVector())
612 RHS = GetPromotedInteger(RHS);
615 // Get the SETCC result using the canonical SETCC type.
616 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
619 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
620 // Convert to the expected type.
621 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
624 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
625 SDValue LHS = N->getOperand(0);
626 SDValue RHS = N->getOperand(1);
627 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
628 LHS = GetPromotedInteger(LHS);
629 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
630 RHS = ZExtPromotedInteger(RHS);
631 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
634 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
635 SDValue Op = GetPromotedInteger(N->getOperand(0));
636 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
637 Op.getValueType(), Op, N->getOperand(1));
640 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
641 // The input may have strange things in the top bits of the registers, but
642 // these operations don't care. They may have weird bits going out, but
643 // that too is okay if they are integer operations.
644 SDValue LHS = GetPromotedInteger(N->getOperand(0));
645 SDValue RHS = GetPromotedInteger(N->getOperand(1));
646 return DAG.getNode(N->getOpcode(), SDLoc(N),
647 LHS.getValueType(), LHS, RHS);
650 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
651 SDValue LHS = N->getOperand(0);
652 SDValue RHS = N->getOperand(1);
653 // The input value must be properly sign extended.
654 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
655 LHS = SExtPromotedInteger(LHS);
656 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
657 RHS = ZExtPromotedInteger(RHS);
658 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
661 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
662 SDValue LHS = N->getOperand(0);
663 SDValue RHS = N->getOperand(1);
664 // The input value must be properly zero extended.
665 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
666 LHS = ZExtPromotedInteger(LHS);
667 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
668 RHS = ZExtPromotedInteger(RHS);
669 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
672 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
673 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
675 SDValue InOp = N->getOperand(0);
678 switch (getTypeAction(InOp.getValueType())) {
679 default: llvm_unreachable("Unknown type action!");
680 case TargetLowering::TypeLegal:
681 case TargetLowering::TypeExpandInteger:
684 case TargetLowering::TypePromoteInteger:
685 Res = GetPromotedInteger(InOp);
687 case TargetLowering::TypeSplitVector:
688 EVT InVT = InOp.getValueType();
689 assert(InVT.isVector() && "Cannot split scalar types");
690 unsigned NumElts = InVT.getVectorNumElements();
691 assert(NumElts == NVT.getVectorNumElements() &&
692 "Dst and Src must have the same number of elements");
693 assert(isPowerOf2_32(NumElts) &&
694 "Promoted vector type must be a power of two");
697 GetSplitVector(InOp, EOp1, EOp2);
699 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
701 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
702 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
704 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
707 // Truncate to NVT instead of VT
708 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
711 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
713 return PromoteIntRes_Overflow(N);
715 // The operation overflowed iff the result in the larger type is not the
716 // zero extension of its truncation to the original type.
717 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
718 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
719 EVT OVT = N->getOperand(0).getValueType();
720 EVT NVT = LHS.getValueType();
723 // Do the arithmetic in the larger type.
724 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
725 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
727 // Calculate the overflow flag: zero extend the arithmetic result from
728 // the original type.
729 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
730 // Overflowed if and only if this is not equal to Res.
731 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
733 // Use the calculated overflow everywhere.
734 ReplaceValueWith(SDValue(N, 1), Ofl);
739 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
740 // Promote the overflow bit trivially.
742 return PromoteIntRes_Overflow(N);
744 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
746 EVT SmallVT = LHS.getValueType();
748 // To determine if the result overflowed in a larger type, we extend the
749 // input to the larger type, do the multiply (checking if it overflows),
750 // then also check the high bits of the result to see if overflow happened
752 if (N->getOpcode() == ISD::SMULO) {
753 LHS = SExtPromotedInteger(LHS);
754 RHS = SExtPromotedInteger(RHS);
756 LHS = ZExtPromotedInteger(LHS);
757 RHS = ZExtPromotedInteger(RHS);
759 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
760 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
762 // Overflow occurred if it occurred in the larger type, or if the high part
763 // of the result does not zero/sign-extend the low part. Check this second
764 // possibility first.
766 if (N->getOpcode() == ISD::UMULO) {
767 // Unsigned overflow occurred if the high part is non-zero.
768 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
769 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
771 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
772 DAG.getConstant(0, DL, Hi.getValueType()),
775 // Signed overflow occurred if the high part does not sign extend the low.
776 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
777 Mul, DAG.getValueType(SmallVT));
778 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
781 // The only other way for overflow to occur is if the multiplication in the
782 // larger type itself overflowed.
783 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
784 SDValue(Mul.getNode(), 1));
786 // Use the calculated overflow everywhere.
787 ReplaceValueWith(SDValue(N, 1), Overflow);
791 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
792 // Zero extend the input.
793 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
794 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
795 return DAG.getNode(N->getOpcode(), SDLoc(N),
796 LHS.getValueType(), LHS, RHS);
799 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
800 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
801 N->getValueType(0)));
804 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
805 SDValue Chain = N->getOperand(0); // Get the chain.
806 SDValue Ptr = N->getOperand(1); // Get the pointer.
807 EVT VT = N->getValueType(0);
810 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
811 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
812 // The argument is passed as NumRegs registers of type RegVT.
814 SmallVector<SDValue, 8> Parts(NumRegs);
815 for (unsigned i = 0; i < NumRegs; ++i) {
816 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
817 N->getConstantOperandVal(3));
818 Chain = Parts[i].getValue(1);
821 // Handle endianness of the load.
822 if (DAG.getDataLayout().isBigEndian())
823 std::reverse(Parts.begin(), Parts.end());
825 // Assemble the parts in the promoted type.
826 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
827 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
828 for (unsigned i = 1; i < NumRegs; ++i) {
829 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
830 // Shift it to the right position and "or" it in.
831 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
832 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
833 TLI.getPointerTy(DAG.getDataLayout())));
834 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
837 // Modified the chain result - switch anything that used the old chain to
839 ReplaceValueWith(SDValue(N, 1), Chain);
844 //===----------------------------------------------------------------------===//
845 // Integer Operand Promotion
846 //===----------------------------------------------------------------------===//
848 /// PromoteIntegerOperand - This method is called when the specified operand of
849 /// the specified node is found to need promotion. At this point, all of the
850 /// result types of the node are known to be legal, but other operands of the
851 /// node may need promotion or expansion as well as the specified one.
852 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
853 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
854 SDValue Res = SDValue();
856 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
859 switch (N->getOpcode()) {
862 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
863 N->dump(&DAG); dbgs() << "\n";
865 llvm_unreachable("Do not know how to promote this operator's operand!");
867 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
868 case ISD::ATOMIC_STORE:
869 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
871 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
872 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
873 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
874 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
875 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
876 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
877 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
878 case ISD::CONVERT_RNDSAT:
879 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
880 case ISD::INSERT_VECTOR_ELT:
881 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
882 case ISD::SCALAR_TO_VECTOR:
883 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
885 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
886 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
887 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
888 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
889 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
890 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
892 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
894 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
896 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
897 case ISD::FP16_TO_FP:
898 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
899 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
900 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
906 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
909 // If the result is null, the sub-method took care of registering results etc.
910 if (!Res.getNode()) return false;
912 // If the result is N, the sub-method updated N in place. Tell the legalizer
914 if (Res.getNode() == N)
917 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
918 "Invalid operand expansion");
920 ReplaceValueWith(SDValue(N, 0), Res);
924 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
925 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
926 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
927 ISD::CondCode CCCode) {
928 // We have to insert explicit sign or zero extends. Note that we could
929 // insert sign extends for ALL conditions, but zero extend is cheaper on
930 // many machines (an AND instead of two shifts), so prefer it.
932 default: llvm_unreachable("Unknown integer comparison!");
935 SDValue OpL = GetPromotedInteger(NewLHS);
936 SDValue OpR = GetPromotedInteger(NewRHS);
938 // We would prefer to promote the comparison operand with sign extension,
939 // if we find the operand is actually to truncate an AssertSext. With this
940 // optimization, we can avoid inserting real truncate instruction, which
941 // is redudant eventually.
942 if (OpL->getOpcode() == ISD::AssertSext &&
943 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
944 OpR->getOpcode() == ISD::AssertSext &&
945 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
949 NewLHS = ZExtPromotedInteger(NewLHS);
950 NewRHS = ZExtPromotedInteger(NewRHS);
958 // ALL of these operations will work if we either sign or zero extend
959 // the operands (including the unsigned comparisons!). Zero extend is
960 // usually a simpler/cheaper operation, so prefer it.
961 NewLHS = ZExtPromotedInteger(NewLHS);
962 NewRHS = ZExtPromotedInteger(NewRHS);
968 NewLHS = SExtPromotedInteger(NewLHS);
969 NewRHS = SExtPromotedInteger(NewRHS);
974 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
975 SDValue Op = GetPromotedInteger(N->getOperand(0));
976 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
979 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
980 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
981 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
982 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
983 N->getOrdering(), N->getSynchScope());
986 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
987 // This should only occur in unusual situations like bitcasting to an
988 // x86_fp80, so just turn it into a store+load
989 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
992 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
993 assert(OpNo == 2 && "Don't know how to promote this operand!");
995 SDValue LHS = N->getOperand(2);
996 SDValue RHS = N->getOperand(3);
997 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
999 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1001 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1002 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1006 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1007 assert(OpNo == 1 && "only know how to promote condition");
1009 // Promote all the way up to the canonical SetCC type.
1010 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1012 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1013 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1014 N->getOperand(2)), 0);
1017 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1018 // Since the result type is legal, the operands must promote to it.
1019 EVT OVT = N->getOperand(0).getValueType();
1020 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1021 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1022 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1025 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1026 DAG.getConstant(OVT.getSizeInBits(), dl,
1027 TLI.getPointerTy(DAG.getDataLayout())));
1028 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1031 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1032 // The vector type is legal but the element type is not. This implies
1033 // that the vector is a power-of-two in length and that the element
1034 // type does not have a strange size (eg: it is not i1).
1035 EVT VecVT = N->getValueType(0);
1036 unsigned NumElts = VecVT.getVectorNumElements();
1037 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1038 "Legal vector of one illegal element?");
1040 // Promote the inserted value. The type does not need to match the
1041 // vector element type. Check that any extra bits introduced will be
1043 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1044 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1045 "Type of inserted value narrower than vector element type!");
1047 SmallVector<SDValue, 16> NewOps;
1048 for (unsigned i = 0; i < NumElts; ++i)
1049 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1051 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1054 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1055 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1056 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1057 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1058 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1059 "can only promote integer arguments");
1060 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1061 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1062 N->getOperand(1), N->getOperand(2),
1063 N->getOperand(3), N->getOperand(4), CvtCode);
1066 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1069 // Promote the inserted value. This is valid because the type does not
1070 // have to match the vector element type.
1072 // Check that any extra bits introduced will be truncated away.
1073 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1074 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1075 "Type of inserted value narrower than vector element type!");
1076 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1077 GetPromotedInteger(N->getOperand(1)),
1082 assert(OpNo == 2 && "Different operand and result vector types?");
1084 // Promote the index.
1085 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1086 TLI.getVectorIdxTy(DAG.getDataLayout()));
1087 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1088 N->getOperand(1), Idx), 0);
1091 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1092 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1093 // the operand in place.
1094 return SDValue(DAG.UpdateNodeOperands(N,
1095 GetPromotedInteger(N->getOperand(0))), 0);
1098 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1099 assert(OpNo == 0 && "Only know how to promote the condition!");
1100 SDValue Cond = N->getOperand(0);
1101 EVT OpTy = N->getOperand(1).getValueType();
1103 // Promote all the way up to the canonical SetCC type.
1104 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1105 Cond = PromoteTargetBoolean(Cond, OpVT);
1107 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1108 N->getOperand(2)), 0);
1111 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1112 assert(OpNo == 0 && "Don't know how to promote this operand!");
1114 SDValue LHS = N->getOperand(0);
1115 SDValue RHS = N->getOperand(1);
1116 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1118 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1119 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1120 N->getOperand(3), N->getOperand(4)), 0);
1123 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1124 assert(OpNo == 0 && "Don't know how to promote this operand!");
1126 SDValue LHS = N->getOperand(0);
1127 SDValue RHS = N->getOperand(1);
1128 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1130 // The CC (#2) is always legal.
1131 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1134 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1135 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1136 ZExtPromotedInteger(N->getOperand(1))), 0);
1139 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1140 SDValue Op = GetPromotedInteger(N->getOperand(0));
1142 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1143 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1144 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1147 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1148 return SDValue(DAG.UpdateNodeOperands(N,
1149 SExtPromotedInteger(N->getOperand(0))), 0);
1152 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1153 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1154 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1157 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1159 // Truncate the value and store the result.
1160 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1161 N->getMemoryVT(), N->getMemOperand());
1164 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1166 SDValue DataOp = N->getValue();
1167 EVT DataVT = DataOp.getValueType();
1168 SDValue Mask = N->getMask();
1169 EVT MaskVT = Mask.getValueType();
1172 bool TruncateStore = false;
1173 if (!TLI.isTypeLegal(DataVT)) {
1174 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) {
1175 DataOp = GetPromotedInteger(DataOp);
1176 if (!TLI.isTypeLegal(MaskVT))
1177 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1178 TruncateStore = true;
1181 assert(getTypeAction(DataVT) == TargetLowering::TypeWidenVector &&
1182 "Unexpected data legalization in MSTORE");
1183 DataOp = GetWidenedVector(DataOp);
1185 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
1186 Mask = GetWidenedVector(Mask);
1188 EVT BoolVT = getSetCCResultType(DataOp.getValueType());
1190 // We can't use ModifyToType() because we should fill the mask with
1192 unsigned WidenNumElts = BoolVT.getVectorNumElements();
1193 unsigned MaskNumElts = MaskVT.getVectorNumElements();
1195 unsigned NumConcat = WidenNumElts / MaskNumElts;
1196 SmallVector<SDValue, 16> Ops(NumConcat);
1197 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
1199 for (unsigned i = 1; i != NumConcat; ++i)
1202 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1207 Mask = PromoteTargetBoolean(N->getMask(), DataOp.getValueType());
1208 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1209 N->getMemoryVT(), N->getMemOperand(),
1213 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1214 assert(OpNo == 2 && "Only know how to promote the mask!");
1215 EVT DataVT = N->getValueType(0);
1216 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1217 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1218 NewOps[OpNo] = Mask;
1219 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1222 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1223 SDValue Op = GetPromotedInteger(N->getOperand(0));
1224 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1227 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1228 return SDValue(DAG.UpdateNodeOperands(N,
1229 ZExtPromotedInteger(N->getOperand(0))), 0);
1232 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1234 SDValue Op = GetPromotedInteger(N->getOperand(0));
1235 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1236 return DAG.getZeroExtendInReg(Op, dl,
1237 N->getOperand(0).getValueType().getScalarType());
1241 //===----------------------------------------------------------------------===//
1242 // Integer Result Expansion
1243 //===----------------------------------------------------------------------===//
1245 /// ExpandIntegerResult - This method is called when the specified result of the
1246 /// specified node is found to need expansion. At this point, the node may also
1247 /// have invalid operands or may have other results that need promotion, we just
1248 /// know that (at least) one result needs expansion.
1249 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1250 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1252 Lo = Hi = SDValue();
1254 // See if the target wants to custom expand this node.
1255 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1258 switch (N->getOpcode()) {
1261 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1262 N->dump(&DAG); dbgs() << "\n";
1264 llvm_unreachable("Do not know how to expand the result of this operator!");
1266 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1267 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1268 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1269 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1271 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1272 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1273 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1274 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1275 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1277 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1278 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1279 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1280 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1281 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1282 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1283 case ISD::CTLZ_ZERO_UNDEF:
1284 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1285 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1286 case ISD::CTTZ_ZERO_UNDEF:
1287 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1288 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1289 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1290 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1291 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1292 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1293 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1294 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1295 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1296 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1297 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1298 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1299 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1300 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1301 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1303 case ISD::ATOMIC_LOAD_ADD:
1304 case ISD::ATOMIC_LOAD_SUB:
1305 case ISD::ATOMIC_LOAD_AND:
1306 case ISD::ATOMIC_LOAD_OR:
1307 case ISD::ATOMIC_LOAD_XOR:
1308 case ISD::ATOMIC_LOAD_NAND:
1309 case ISD::ATOMIC_LOAD_MIN:
1310 case ISD::ATOMIC_LOAD_MAX:
1311 case ISD::ATOMIC_LOAD_UMIN:
1312 case ISD::ATOMIC_LOAD_UMAX:
1313 case ISD::ATOMIC_SWAP:
1314 case ISD::ATOMIC_CMP_SWAP: {
1315 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1316 SplitInteger(Tmp.first, Lo, Hi);
1317 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1320 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1321 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1322 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1323 SDValue Tmp = DAG.getAtomicCmpSwap(
1324 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1325 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1326 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1327 AN->getSynchScope());
1329 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1330 // success simply by comparing the loaded value against the ingoing
1332 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1333 N->getOperand(2), ISD::SETEQ);
1335 SplitInteger(Tmp, Lo, Hi);
1336 ReplaceValueWith(SDValue(N, 1), Success);
1337 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1343 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1346 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1349 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1352 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1356 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1359 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1361 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1363 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1366 // If Lo/Hi is null, the sub-method took care of registering results etc.
1368 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1371 /// Lower an atomic node to the appropriate builtin call.
1372 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1373 unsigned Opc = Node->getOpcode();
1374 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1375 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1376 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1378 return ExpandChainLibCall(LC, Node, false);
1381 /// N is a shift by a value that needs to be expanded,
1382 /// and the shift amount is a constant 'Amt'. Expand the operation.
1383 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1384 SDValue &Lo, SDValue &Hi) {
1386 // Expand the incoming operand to be shifted, so that we have its parts
1388 GetExpandedInteger(N->getOperand(0), InL, InH);
1390 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1391 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1398 EVT NVT = InL.getValueType();
1399 unsigned VTBits = N->getValueType(0).getSizeInBits();
1400 unsigned NVTBits = NVT.getSizeInBits();
1401 EVT ShTy = N->getOperand(1).getValueType();
1403 if (N->getOpcode() == ISD::SHL) {
1404 if (Amt.ugt(VTBits)) {
1405 Lo = Hi = DAG.getConstant(0, DL, NVT);
1406 } else if (Amt.ugt(NVTBits)) {
1407 Lo = DAG.getConstant(0, DL, NVT);
1408 Hi = DAG.getNode(ISD::SHL, DL,
1409 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1410 } else if (Amt == NVTBits) {
1411 Lo = DAG.getConstant(0, DL, NVT);
1413 } else if (Amt == 1 &&
1414 TLI.isOperationLegalOrCustom(ISD::ADDC,
1415 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1416 // Emit this X << 1 as X+X.
1417 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1418 SDValue LoOps[2] = { InL, InL };
1419 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1420 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1421 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1423 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1424 Hi = DAG.getNode(ISD::OR, DL, NVT,
1425 DAG.getNode(ISD::SHL, DL, NVT, InH,
1426 DAG.getConstant(Amt, DL, ShTy)),
1427 DAG.getNode(ISD::SRL, DL, NVT, InL,
1428 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1433 if (N->getOpcode() == ISD::SRL) {
1434 if (Amt.ugt(VTBits)) {
1435 Lo = Hi = DAG.getConstant(0, DL, NVT);
1436 } else if (Amt.ugt(NVTBits)) {
1437 Lo = DAG.getNode(ISD::SRL, DL,
1438 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1439 Hi = DAG.getConstant(0, DL, NVT);
1440 } else if (Amt == NVTBits) {
1442 Hi = DAG.getConstant(0, DL, NVT);
1444 Lo = DAG.getNode(ISD::OR, DL, NVT,
1445 DAG.getNode(ISD::SRL, DL, NVT, InL,
1446 DAG.getConstant(Amt, DL, ShTy)),
1447 DAG.getNode(ISD::SHL, DL, NVT, InH,
1448 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1449 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1454 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1455 if (Amt.ugt(VTBits)) {
1456 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1457 DAG.getConstant(NVTBits - 1, DL, ShTy));
1458 } else if (Amt.ugt(NVTBits)) {
1459 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1460 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1461 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1462 DAG.getConstant(NVTBits - 1, DL, ShTy));
1463 } else if (Amt == NVTBits) {
1465 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1466 DAG.getConstant(NVTBits - 1, DL, ShTy));
1468 Lo = DAG.getNode(ISD::OR, DL, NVT,
1469 DAG.getNode(ISD::SRL, DL, NVT, InL,
1470 DAG.getConstant(Amt, DL, ShTy)),
1471 DAG.getNode(ISD::SHL, DL, NVT, InH,
1472 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1473 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1477 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1478 /// this shift based on knowledge of the high bit of the shift amount. If we
1479 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1481 bool DAGTypeLegalizer::
1482 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1483 SDValue Amt = N->getOperand(1);
1484 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1485 EVT ShTy = Amt.getValueType();
1486 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1487 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1488 assert(isPowerOf2_32(NVTBits) &&
1489 "Expanded integer type size not a power of two!");
1492 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1493 APInt KnownZero, KnownOne;
1494 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1496 // If we don't know anything about the high bits, exit.
1497 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1500 // Get the incoming operand to be shifted.
1502 GetExpandedInteger(N->getOperand(0), InL, InH);
1504 // If we know that any of the high bits of the shift amount are one, then we
1505 // can do this as a couple of simple shifts.
1506 if (KnownOne.intersects(HighBitMask)) {
1507 // Mask out the high bit, which we know is set.
1508 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1509 DAG.getConstant(~HighBitMask, dl, ShTy));
1511 switch (N->getOpcode()) {
1512 default: llvm_unreachable("Unknown shift");
1514 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1515 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1518 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1519 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1522 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1523 DAG.getConstant(NVTBits - 1, dl, ShTy));
1524 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1529 // If we know that all of the high bits of the shift amount are zero, then we
1530 // can do this as a couple of simple shifts.
1531 if ((KnownZero & HighBitMask) == HighBitMask) {
1532 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1533 // shift if x is zero. We can use XOR here because x is known to be smaller
1535 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1536 DAG.getConstant(NVTBits - 1, dl, ShTy));
1539 switch (N->getOpcode()) {
1540 default: llvm_unreachable("Unknown shift");
1541 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1543 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1546 // When shifting right the arithmetic for Lo and Hi is swapped.
1547 if (N->getOpcode() != ISD::SHL)
1548 std::swap(InL, InH);
1550 // Use a little trick to get the bits that move from Lo to Hi. First
1551 // shift by one bit.
1552 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1553 // Then compute the remaining shift with amount-1.
1554 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1556 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1557 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1559 if (N->getOpcode() != ISD::SHL)
1567 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1569 bool DAGTypeLegalizer::
1570 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1571 SDValue Amt = N->getOperand(1);
1572 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1573 EVT ShTy = Amt.getValueType();
1574 unsigned NVTBits = NVT.getSizeInBits();
1575 assert(isPowerOf2_32(NVTBits) &&
1576 "Expanded integer type size not a power of two!");
1579 // Get the incoming operand to be shifted.
1581 GetExpandedInteger(N->getOperand(0), InL, InH);
1583 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1584 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1585 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1586 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1587 Amt, NVBitsNode, ISD::SETULT);
1588 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1589 Amt, DAG.getConstant(0, dl, ShTy),
1592 SDValue LoS, HiS, LoL, HiL;
1593 switch (N->getOpcode()) {
1594 default: llvm_unreachable("Unknown shift");
1596 // Short: ShAmt < NVTBits
1597 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1598 HiS = DAG.getNode(ISD::OR, dl, NVT,
1599 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1600 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1602 // Long: ShAmt >= NVTBits
1603 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1604 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1606 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1607 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1608 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1611 // Short: ShAmt < NVTBits
1612 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1613 LoS = DAG.getNode(ISD::OR, dl, NVT,
1614 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1615 // FIXME: If Amt is zero, the following shift generates an undefined result
1616 // on some architectures.
1617 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1619 // Long: ShAmt >= NVTBits
1620 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1621 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1623 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1624 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1625 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1628 // Short: ShAmt < NVTBits
1629 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1630 LoS = DAG.getNode(ISD::OR, dl, NVT,
1631 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1632 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1634 // Long: ShAmt >= NVTBits
1635 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1636 DAG.getConstant(NVTBits - 1, dl, ShTy));
1637 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1639 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1640 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1641 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1646 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1647 SDValue &Lo, SDValue &Hi) {
1649 // Expand the subcomponents.
1650 SDValue LHSL, LHSH, RHSL, RHSH;
1651 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1652 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1654 EVT NVT = LHSL.getValueType();
1655 SDValue LoOps[2] = { LHSL, RHSL };
1656 SDValue HiOps[3] = { LHSH, RHSH };
1658 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1659 // them. TODO: Teach operation legalization how to expand unsupported
1660 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1661 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1662 // generate a value of this type in the expanded code sequence.
1664 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1665 ISD::ADDC : ISD::SUBC,
1666 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1669 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1670 if (N->getOpcode() == ISD::ADD) {
1671 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1672 HiOps[2] = Lo.getValue(1);
1673 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1675 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1676 HiOps[2] = Lo.getValue(1);
1677 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1683 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1684 ISD::UADDO : ISD::USUBO,
1685 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1687 SDVTList VTList = DAG.getVTList(NVT, NVT);
1688 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1690 if (N->getOpcode() == ISD::ADD) {
1692 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1693 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1696 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1697 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1699 SDValue OVF = Lo.getValue(1);
1702 case TargetLoweringBase::UndefinedBooleanContent:
1703 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1705 case TargetLoweringBase::ZeroOrOneBooleanContent:
1706 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1708 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1709 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1714 if (N->getOpcode() == ISD::ADD) {
1715 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1716 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1717 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1719 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1720 DAG.getConstant(1, dl, NVT),
1721 DAG.getConstant(0, dl, NVT));
1722 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1724 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1725 DAG.getConstant(1, dl, NVT), Carry1);
1726 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1728 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1729 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1731 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1732 LoOps[0], LoOps[1], ISD::SETULT);
1733 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1734 DAG.getConstant(1, dl, NVT),
1735 DAG.getConstant(0, dl, NVT));
1736 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1740 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1741 SDValue &Lo, SDValue &Hi) {
1742 // Expand the subcomponents.
1743 SDValue LHSL, LHSH, RHSL, RHSH;
1745 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1746 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1747 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1748 SDValue LoOps[2] = { LHSL, RHSL };
1749 SDValue HiOps[3] = { LHSH, RHSH };
1751 if (N->getOpcode() == ISD::ADDC) {
1752 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1753 HiOps[2] = Lo.getValue(1);
1754 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1756 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1757 HiOps[2] = Lo.getValue(1);
1758 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1761 // Legalized the flag result - switch anything that used the old flag to
1763 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1766 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1767 SDValue &Lo, SDValue &Hi) {
1768 // Expand the subcomponents.
1769 SDValue LHSL, LHSH, RHSL, RHSH;
1771 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1772 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1773 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1774 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1775 SDValue HiOps[3] = { LHSH, RHSH };
1777 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1778 HiOps[2] = Lo.getValue(1);
1779 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1781 // Legalized the flag result - switch anything that used the old flag to
1783 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1786 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1787 SDValue &Lo, SDValue &Hi) {
1788 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1790 SDValue Op = N->getOperand(0);
1791 if (Op.getValueType().bitsLE(NVT)) {
1792 // The low part is any extension of the input (which degenerates to a copy).
1793 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1794 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1796 // For example, extension of an i48 to an i64. The operand type necessarily
1797 // promotes to the result type, so will end up being expanded too.
1798 assert(getTypeAction(Op.getValueType()) ==
1799 TargetLowering::TypePromoteInteger &&
1800 "Only know how to promote this result!");
1801 SDValue Res = GetPromotedInteger(Op);
1802 assert(Res.getValueType() == N->getValueType(0) &&
1803 "Operand over promoted?");
1804 // Split the promoted operand. This will simplify when it is expanded.
1805 SplitInteger(Res, Lo, Hi);
1809 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1810 SDValue &Lo, SDValue &Hi) {
1812 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1813 EVT NVT = Lo.getValueType();
1814 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1815 unsigned NVTBits = NVT.getSizeInBits();
1816 unsigned EVTBits = EVT.getSizeInBits();
1818 if (NVTBits < EVTBits) {
1819 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1820 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1821 EVTBits - NVTBits)));
1823 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1824 // The high part replicates the sign bit of Lo, make it explicit.
1825 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1826 DAG.getConstant(NVTBits - 1, dl,
1827 TLI.getPointerTy(DAG.getDataLayout())));
1831 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1832 SDValue &Lo, SDValue &Hi) {
1834 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1835 EVT NVT = Lo.getValueType();
1836 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1837 unsigned NVTBits = NVT.getSizeInBits();
1838 unsigned EVTBits = EVT.getSizeInBits();
1840 if (NVTBits < EVTBits) {
1841 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1842 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1843 EVTBits - NVTBits)));
1845 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1846 // The high part must be zero, make it explicit.
1847 Hi = DAG.getConstant(0, dl, NVT);
1851 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
1852 SDValue &Lo, SDValue &Hi) {
1854 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1855 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
1856 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
1859 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1860 SDValue &Lo, SDValue &Hi) {
1862 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1863 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1864 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1867 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1868 SDValue &Lo, SDValue &Hi) {
1869 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1870 unsigned NBitWidth = NVT.getSizeInBits();
1871 auto Constant = cast<ConstantSDNode>(N);
1872 const APInt &Cst = Constant->getAPIntValue();
1873 bool IsTarget = Constant->isTargetOpcode();
1874 bool IsOpaque = Constant->isOpaque();
1876 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1877 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1881 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1882 SDValue &Lo, SDValue &Hi) {
1884 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1885 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1886 EVT NVT = Lo.getValueType();
1888 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1889 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1891 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1892 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1894 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1895 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1896 DAG.getConstant(NVT.getSizeInBits(), dl,
1898 Hi = DAG.getConstant(0, dl, NVT);
1901 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1902 SDValue &Lo, SDValue &Hi) {
1904 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1905 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1906 EVT NVT = Lo.getValueType();
1907 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1908 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1909 Hi = DAG.getConstant(0, dl, NVT);
1912 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1913 SDValue &Lo, SDValue &Hi) {
1915 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1916 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1917 EVT NVT = Lo.getValueType();
1919 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1920 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1922 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1923 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1925 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1926 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1927 DAG.getConstant(NVT.getSizeInBits(), dl,
1929 Hi = DAG.getConstant(0, dl, NVT);
1932 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1935 EVT VT = N->getValueType(0);
1937 SDValue Op = N->getOperand(0);
1938 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1939 Op = GetPromotedFloat(Op);
1941 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1942 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1943 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, true/*irrelevant*/, dl).first,
1947 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1950 EVT VT = N->getValueType(0);
1952 SDValue Op = N->getOperand(0);
1953 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1954 Op = GetPromotedFloat(Op);
1956 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1957 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1958 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, false/*irrelevant*/, dl).first,
1962 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1963 SDValue &Lo, SDValue &Hi) {
1964 if (ISD::isNormalLoad(N)) {
1965 ExpandRes_NormalLoad(N, Lo, Hi);
1969 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1971 EVT VT = N->getValueType(0);
1972 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1973 SDValue Ch = N->getChain();
1974 SDValue Ptr = N->getBasePtr();
1975 ISD::LoadExtType ExtType = N->getExtensionType();
1976 unsigned Alignment = N->getAlignment();
1977 bool isVolatile = N->isVolatile();
1978 bool isNonTemporal = N->isNonTemporal();
1979 bool isInvariant = N->isInvariant();
1980 AAMDNodes AAInfo = N->getAAInfo();
1983 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1985 if (N->getMemoryVT().bitsLE(NVT)) {
1986 EVT MemVT = N->getMemoryVT();
1988 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1989 MemVT, isVolatile, isNonTemporal, isInvariant,
1992 // Remember the chain.
1993 Ch = Lo.getValue(1);
1995 if (ExtType == ISD::SEXTLOAD) {
1996 // The high part is obtained by SRA'ing all but one of the bits of the
1998 unsigned LoSize = Lo.getValueType().getSizeInBits();
1999 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2000 DAG.getConstant(LoSize - 1, dl,
2001 TLI.getPointerTy(DAG.getDataLayout())));
2002 } else if (ExtType == ISD::ZEXTLOAD) {
2003 // The high part is just a zero.
2004 Hi = DAG.getConstant(0, dl, NVT);
2006 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
2007 // The high part is undefined.
2008 Hi = DAG.getUNDEF(NVT);
2010 } else if (DAG.getDataLayout().isLittleEndian()) {
2011 // Little-endian - low bits are at low addresses.
2012 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
2013 isVolatile, isNonTemporal, isInvariant, Alignment,
2016 unsigned ExcessBits =
2017 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2018 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2020 // Increment the pointer to the other half.
2021 unsigned IncrementSize = NVT.getSizeInBits()/8;
2022 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2023 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2024 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2025 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2026 isVolatile, isNonTemporal, isInvariant,
2027 MinAlign(Alignment, IncrementSize), AAInfo);
2029 // Build a factor node to remember that this load is independent of the
2031 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2034 // Big-endian - high bits are at low addresses. Favor aligned loads at
2035 // the cost of some bit-fiddling.
2036 EVT MemVT = N->getMemoryVT();
2037 unsigned EBytes = MemVT.getStoreSize();
2038 unsigned IncrementSize = NVT.getSizeInBits()/8;
2039 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2041 // Load both the high bits and maybe some of the low bits.
2042 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2043 EVT::getIntegerVT(*DAG.getContext(),
2044 MemVT.getSizeInBits() - ExcessBits),
2045 isVolatile, isNonTemporal, isInvariant, Alignment,
2048 // Increment the pointer to the other half.
2049 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2050 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2051 // Load the rest of the low bits.
2052 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2053 N->getPointerInfo().getWithOffset(IncrementSize),
2054 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2055 isVolatile, isNonTemporal, isInvariant,
2056 MinAlign(Alignment, IncrementSize), AAInfo);
2058 // Build a factor node to remember that this load is independent of the
2060 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2063 if (ExcessBits < NVT.getSizeInBits()) {
2064 // Transfer low bits from the bottom of Hi to the top of Lo.
2066 ISD::OR, dl, NVT, Lo,
2067 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2068 DAG.getConstant(ExcessBits, dl,
2069 TLI.getPointerTy(DAG.getDataLayout()))));
2070 // Move high bits to the right position in Hi.
2071 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2073 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2074 TLI.getPointerTy(DAG.getDataLayout())));
2078 // Legalized the chain result - switch anything that used the old chain to
2080 ReplaceValueWith(SDValue(N, 1), Ch);
2083 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2084 SDValue &Lo, SDValue &Hi) {
2086 SDValue LL, LH, RL, RH;
2087 GetExpandedInteger(N->getOperand(0), LL, LH);
2088 GetExpandedInteger(N->getOperand(1), RL, RH);
2089 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2090 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2093 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2094 SDValue &Lo, SDValue &Hi) {
2095 EVT VT = N->getValueType(0);
2096 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2099 SDValue LL, LH, RL, RH;
2100 GetExpandedInteger(N->getOperand(0), LL, LH);
2101 GetExpandedInteger(N->getOperand(1), RL, RH);
2103 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2106 // If nothing else, we can make a libcall.
2107 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2109 LC = RTLIB::MUL_I16;
2110 else if (VT == MVT::i32)
2111 LC = RTLIB::MUL_I32;
2112 else if (VT == MVT::i64)
2113 LC = RTLIB::MUL_I64;
2114 else if (VT == MVT::i128)
2115 LC = RTLIB::MUL_I128;
2116 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2118 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2119 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true/*irrelevant*/, dl).first,
2123 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2126 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2127 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2128 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2131 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2134 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2135 SDValue &Lo, SDValue &Hi) {
2136 SDValue LHS = Node->getOperand(0);
2137 SDValue RHS = Node->getOperand(1);
2140 // Expand the result by simply replacing it with the equivalent
2141 // non-overflow-checking operation.
2142 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2143 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2145 SplitInteger(Sum, Lo, Hi);
2147 // Compute the overflow.
2149 // LHSSign -> LHS >= 0
2150 // RHSSign -> RHS >= 0
2151 // SumSign -> Sum >= 0
2154 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2156 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2158 EVT OType = Node->getValueType(1);
2159 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2161 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2162 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2163 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2164 Node->getOpcode() == ISD::SADDO ?
2165 ISD::SETEQ : ISD::SETNE);
2167 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2168 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2170 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2172 // Use the calculated overflow everywhere.
2173 ReplaceValueWith(SDValue(Node, 1), Cmp);
2176 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2177 SDValue &Lo, SDValue &Hi) {
2178 EVT VT = N->getValueType(0);
2180 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2182 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2183 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2184 SplitInteger(Res.getValue(0), Lo, Hi);
2188 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2190 LC = RTLIB::SDIV_I16;
2191 else if (VT == MVT::i32)
2192 LC = RTLIB::SDIV_I32;
2193 else if (VT == MVT::i64)
2194 LC = RTLIB::SDIV_I64;
2195 else if (VT == MVT::i128)
2196 LC = RTLIB::SDIV_I128;
2197 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2199 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2202 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2203 SDValue &Lo, SDValue &Hi) {
2204 EVT VT = N->getValueType(0);
2207 // If we can emit an efficient shift operation, do so now. Check to see if
2208 // the RHS is a constant.
2209 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2210 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
2212 // If we can determine that the high bit of the shift is zero or one, even if
2213 // the low bits are variable, emit this shift in an optimized form.
2214 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2217 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2219 if (N->getOpcode() == ISD::SHL) {
2220 PartsOpc = ISD::SHL_PARTS;
2221 } else if (N->getOpcode() == ISD::SRL) {
2222 PartsOpc = ISD::SRL_PARTS;
2224 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2225 PartsOpc = ISD::SRA_PARTS;
2228 // Next check to see if the target supports this SHL_PARTS operation or if it
2229 // will custom expand it.
2230 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2231 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2232 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2233 Action == TargetLowering::Custom) {
2234 // Expand the subcomponents.
2236 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2237 EVT VT = LHSL.getValueType();
2239 // If the shift amount operand is coming from a vector legalization it may
2240 // have an illegal type. Fix that first by casting the operand, otherwise
2241 // the new SHL_PARTS operation would need further legalization.
2242 SDValue ShiftOp = N->getOperand(1);
2243 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2244 assert(ShiftTy.getScalarType().getSizeInBits() >=
2245 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2246 "ShiftAmountTy is too small to cover the range of this type!");
2247 if (ShiftOp.getValueType() != ShiftTy)
2248 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2250 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2251 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2252 Hi = Lo.getValue(1);
2256 // Otherwise, emit a libcall.
2257 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2259 if (N->getOpcode() == ISD::SHL) {
2260 isSigned = false; /*sign irrelevant*/
2262 LC = RTLIB::SHL_I16;
2263 else if (VT == MVT::i32)
2264 LC = RTLIB::SHL_I32;
2265 else if (VT == MVT::i64)
2266 LC = RTLIB::SHL_I64;
2267 else if (VT == MVT::i128)
2268 LC = RTLIB::SHL_I128;
2269 } else if (N->getOpcode() == ISD::SRL) {
2272 LC = RTLIB::SRL_I16;
2273 else if (VT == MVT::i32)
2274 LC = RTLIB::SRL_I32;
2275 else if (VT == MVT::i64)
2276 LC = RTLIB::SRL_I64;
2277 else if (VT == MVT::i128)
2278 LC = RTLIB::SRL_I128;
2280 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2283 LC = RTLIB::SRA_I16;
2284 else if (VT == MVT::i32)
2285 LC = RTLIB::SRA_I32;
2286 else if (VT == MVT::i64)
2287 LC = RTLIB::SRA_I64;
2288 else if (VT == MVT::i128)
2289 LC = RTLIB::SRA_I128;
2292 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2293 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2294 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, isSigned, dl).first, Lo, Hi);
2298 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2299 llvm_unreachable("Unsupported shift!");
2302 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2303 SDValue &Lo, SDValue &Hi) {
2304 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2306 SDValue Op = N->getOperand(0);
2307 if (Op.getValueType().bitsLE(NVT)) {
2308 // The low part is sign extension of the input (degenerates to a copy).
2309 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2310 // The high part is obtained by SRA'ing all but one of the bits of low part.
2311 unsigned LoSize = NVT.getSizeInBits();
2313 ISD::SRA, dl, NVT, Lo,
2314 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2316 // For example, extension of an i48 to an i64. The operand type necessarily
2317 // promotes to the result type, so will end up being expanded too.
2318 assert(getTypeAction(Op.getValueType()) ==
2319 TargetLowering::TypePromoteInteger &&
2320 "Only know how to promote this result!");
2321 SDValue Res = GetPromotedInteger(Op);
2322 assert(Res.getValueType() == N->getValueType(0) &&
2323 "Operand over promoted?");
2324 // Split the promoted operand. This will simplify when it is expanded.
2325 SplitInteger(Res, Lo, Hi);
2326 unsigned ExcessBits =
2327 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2328 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2329 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2334 void DAGTypeLegalizer::
2335 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2337 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2338 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2340 if (EVT.bitsLE(Lo.getValueType())) {
2341 // sext_inreg the low part if needed.
2342 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2345 // The high part gets the sign extension from the lo-part. This handles
2346 // things like sextinreg V:i64 from i8.
2347 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2348 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2349 TLI.getPointerTy(DAG.getDataLayout())));
2351 // For example, extension of an i48 to an i64. Leave the low part alone,
2352 // sext_inreg the high part.
2353 unsigned ExcessBits =
2354 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2355 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2356 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2361 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2362 SDValue &Lo, SDValue &Hi) {
2363 EVT VT = N->getValueType(0);
2365 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2367 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2368 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2369 SplitInteger(Res.getValue(1), Lo, Hi);
2373 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2375 LC = RTLIB::SREM_I16;
2376 else if (VT == MVT::i32)
2377 LC = RTLIB::SREM_I32;
2378 else if (VT == MVT::i64)
2379 LC = RTLIB::SREM_I64;
2380 else if (VT == MVT::i128)
2381 LC = RTLIB::SREM_I128;
2382 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2384 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2387 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2388 SDValue &Lo, SDValue &Hi) {
2389 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2391 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2392 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2394 DAG.getConstant(NVT.getSizeInBits(), dl,
2395 TLI.getPointerTy(DAG.getDataLayout())));
2396 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2399 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2400 SDValue &Lo, SDValue &Hi) {
2401 SDValue LHS = N->getOperand(0);
2402 SDValue RHS = N->getOperand(1);
2405 // Expand the result by simply replacing it with the equivalent
2406 // non-overflow-checking operation.
2407 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2408 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2410 SplitInteger(Sum, Lo, Hi);
2412 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2413 // overflows iff a - b > a.
2414 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2415 N->getOpcode () == ISD::UADDO ?
2416 ISD::SETULT : ISD::SETUGT);
2418 // Use the calculated overflow everywhere.
2419 ReplaceValueWith(SDValue(N, 1), Ofl);
2422 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2423 SDValue &Lo, SDValue &Hi) {
2424 EVT VT = N->getValueType(0);
2427 // A divide for UMULO should be faster than a function call.
2428 if (N->getOpcode() == ISD::UMULO) {
2429 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2431 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2432 SplitInteger(MUL, Lo, Hi);
2434 // A divide for UMULO will be faster than a function call. Select to
2435 // make sure we aren't using 0.
2436 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2437 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2438 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2439 DAG.getConstant(1, dl, VT), RHS);
2440 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2441 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2443 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2444 DAG.getConstant(0, dl, N->getValueType(1)),
2446 ReplaceValueWith(SDValue(N, 1), Overflow);
2450 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2451 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2452 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2454 // Replace this with a libcall that will check overflow.
2455 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2457 LC = RTLIB::MULO_I32;
2458 else if (VT == MVT::i64)
2459 LC = RTLIB::MULO_I64;
2460 else if (VT == MVT::i128)
2461 LC = RTLIB::MULO_I128;
2462 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2464 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2465 // Temporary for the overflow value, default it to zero.
2466 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2467 DAG.getConstant(0, dl, PtrVT), Temp,
2468 MachinePointerInfo(), false, false, 0);
2470 TargetLowering::ArgListTy Args;
2471 TargetLowering::ArgListEntry Entry;
2472 for (const SDValue &Op : N->op_values()) {
2473 EVT ArgVT = Op.getValueType();
2474 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2477 Entry.isSExt = true;
2478 Entry.isZExt = false;
2479 Args.push_back(Entry);
2482 // Also pass the address of the overflow check.
2484 Entry.Ty = PtrTy->getPointerTo();
2485 Entry.isSExt = true;
2486 Entry.isZExt = false;
2487 Args.push_back(Entry);
2489 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2491 TargetLowering::CallLoweringInfo CLI(DAG);
2492 CLI.setDebugLoc(dl).setChain(Chain)
2493 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2496 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2498 SplitInteger(CallInfo.first, Lo, Hi);
2499 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2500 MachinePointerInfo(), false, false, false, 0);
2501 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2502 DAG.getConstant(0, dl, PtrVT),
2504 // Use the overflow from the libcall everywhere.
2505 ReplaceValueWith(SDValue(N, 1), Ofl);
2508 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2509 SDValue &Lo, SDValue &Hi) {
2510 EVT VT = N->getValueType(0);
2512 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2514 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2515 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2516 SplitInteger(Res.getValue(0), Lo, Hi);
2520 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2522 LC = RTLIB::UDIV_I16;
2523 else if (VT == MVT::i32)
2524 LC = RTLIB::UDIV_I32;
2525 else if (VT == MVT::i64)
2526 LC = RTLIB::UDIV_I64;
2527 else if (VT == MVT::i128)
2528 LC = RTLIB::UDIV_I128;
2529 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2531 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2534 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2535 SDValue &Lo, SDValue &Hi) {
2536 EVT VT = N->getValueType(0);
2538 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2540 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2541 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2542 SplitInteger(Res.getValue(1), Lo, Hi);
2546 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2548 LC = RTLIB::UREM_I16;
2549 else if (VT == MVT::i32)
2550 LC = RTLIB::UREM_I32;
2551 else if (VT == MVT::i64)
2552 LC = RTLIB::UREM_I64;
2553 else if (VT == MVT::i128)
2554 LC = RTLIB::UREM_I128;
2555 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2557 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2560 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2561 SDValue &Lo, SDValue &Hi) {
2562 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2564 SDValue Op = N->getOperand(0);
2565 if (Op.getValueType().bitsLE(NVT)) {
2566 // The low part is zero extension of the input (degenerates to a copy).
2567 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2568 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2570 // For example, extension of an i48 to an i64. The operand type necessarily
2571 // promotes to the result type, so will end up being expanded too.
2572 assert(getTypeAction(Op.getValueType()) ==
2573 TargetLowering::TypePromoteInteger &&
2574 "Only know how to promote this result!");
2575 SDValue Res = GetPromotedInteger(Op);
2576 assert(Res.getValueType() == N->getValueType(0) &&
2577 "Operand over promoted?");
2578 // Split the promoted operand. This will simplify when it is expanded.
2579 SplitInteger(Res, Lo, Hi);
2580 unsigned ExcessBits =
2581 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2582 Hi = DAG.getZeroExtendInReg(Hi, dl,
2583 EVT::getIntegerVT(*DAG.getContext(),
2588 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2589 SDValue &Lo, SDValue &Hi) {
2591 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2592 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2593 SDValue Zero = DAG.getConstant(0, dl, VT);
2594 SDValue Swap = DAG.getAtomicCmpSwap(
2595 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2596 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2597 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2598 cast<AtomicSDNode>(N)->getOrdering(),
2599 cast<AtomicSDNode>(N)->getOrdering(),
2600 cast<AtomicSDNode>(N)->getSynchScope());
2602 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2603 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2606 //===----------------------------------------------------------------------===//
2607 // Integer Operand Expansion
2608 //===----------------------------------------------------------------------===//
2610 /// ExpandIntegerOperand - This method is called when the specified operand of
2611 /// the specified node is found to need expansion. At this point, all of the
2612 /// result types of the node are known to be legal, but other operands of the
2613 /// node may need promotion or expansion as well as the specified one.
2614 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2615 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2616 SDValue Res = SDValue();
2618 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2621 switch (N->getOpcode()) {
2624 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2625 N->dump(&DAG); dbgs() << "\n";
2627 llvm_unreachable("Do not know how to expand this operator's operand!");
2629 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2630 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2631 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2632 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2633 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2634 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2635 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2636 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2637 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2638 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2639 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2640 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2646 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2647 case ISD::RETURNADDR:
2648 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2650 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2653 // If the result is null, the sub-method took care of registering results etc.
2654 if (!Res.getNode()) return false;
2656 // If the result is N, the sub-method updated N in place. Tell the legalizer
2658 if (Res.getNode() == N)
2661 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2662 "Invalid operand expansion");
2664 ReplaceValueWith(SDValue(N, 0), Res);
2668 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2669 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2670 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2672 ISD::CondCode &CCCode,
2674 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2675 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2676 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2678 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2679 if (RHSLo == RHSHi) {
2680 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2681 if (RHSCST->isAllOnesValue()) {
2682 // Equality comparison to -1.
2683 NewLHS = DAG.getNode(ISD::AND, dl,
2684 LHSLo.getValueType(), LHSLo, LHSHi);
2691 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2692 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2693 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2694 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2698 // If this is a comparison of the sign bit, just look at the top part.
2700 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2701 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2702 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2708 // FIXME: This generated code sucks.
2709 ISD::CondCode LowCC;
2711 default: llvm_unreachable("Unknown integer setcc!");
2713 case ISD::SETULT: LowCC = ISD::SETULT; break;
2715 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2717 case ISD::SETULE: LowCC = ISD::SETULE; break;
2719 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2722 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2723 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2724 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2726 // NOTE: on targets without efficient SELECT of bools, we can always use
2727 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2728 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2731 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2732 TLI.isTypeLegal(RHSLo.getValueType()))
2733 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2734 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2735 if (!Tmp1.getNode())
2736 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2737 LHSLo, RHSLo, LowCC);
2738 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2739 TLI.isTypeLegal(RHSHi.getValueType()))
2740 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2741 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2742 if (!Tmp2.getNode())
2743 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2744 getSetCCResultType(LHSHi.getValueType()),
2745 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2747 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2748 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2749 if ((Tmp1C && Tmp1C->isNullValue()) ||
2750 (Tmp2C && Tmp2C->isNullValue() &&
2751 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2752 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2753 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2754 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2755 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2756 // low part is known false, returns high part.
2757 // For LE / GE, if high part is known false, ignore the low part.
2758 // For LT / GT, if high part is known true, ignore the low part.
2764 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2765 LHSHi, RHSHi, ISD::SETEQ, false,
2766 DagCombineInfo, dl);
2767 if (!NewLHS.getNode())
2768 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2769 LHSHi, RHSHi, ISD::SETEQ);
2770 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2771 NewLHS, Tmp1, Tmp2);
2775 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2776 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2777 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2778 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2780 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2781 // against zero to select between true and false values.
2782 if (!NewRHS.getNode()) {
2783 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2784 CCCode = ISD::SETNE;
2787 // Update N to have the operands specified.
2788 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2789 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2790 N->getOperand(4)), 0);
2793 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2794 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2795 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2796 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2798 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2799 // against zero to select between true and false values.
2800 if (!NewRHS.getNode()) {
2801 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2802 CCCode = ISD::SETNE;
2805 // Update N to have the operands specified.
2806 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2807 N->getOperand(2), N->getOperand(3),
2808 DAG.getCondCode(CCCode)), 0);
2811 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2812 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2813 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2814 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2816 // If ExpandSetCCOperands returned a scalar, use it.
2817 if (!NewRHS.getNode()) {
2818 assert(NewLHS.getValueType() == N->getValueType(0) &&
2819 "Unexpected setcc expansion!");
2823 // Otherwise, update N to have the operands specified.
2824 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2825 DAG.getCondCode(CCCode)), 0);
2828 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2829 // The value being shifted is legal, but the shift amount is too big.
2830 // It follows that either the result of the shift is undefined, or the
2831 // upper half of the shift amount is zero. Just use the lower half.
2833 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2834 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2837 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2838 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2839 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2840 // constant to valid type.
2842 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2843 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2846 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2847 SDValue Op = N->getOperand(0);
2848 EVT DstVT = N->getValueType(0);
2849 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2850 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2851 "Don't know how to expand this SINT_TO_FP!");
2852 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first;
2855 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2856 if (ISD::isNormalStore(N))
2857 return ExpandOp_NormalStore(N, OpNo);
2859 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2860 assert(OpNo == 1 && "Can only expand the stored value so far");
2862 EVT VT = N->getOperand(1).getValueType();
2863 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2864 SDValue Ch = N->getChain();
2865 SDValue Ptr = N->getBasePtr();
2866 unsigned Alignment = N->getAlignment();
2867 bool isVolatile = N->isVolatile();
2868 bool isNonTemporal = N->isNonTemporal();
2869 AAMDNodes AAInfo = N->getAAInfo();
2873 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2875 if (N->getMemoryVT().bitsLE(NVT)) {
2876 GetExpandedInteger(N->getValue(), Lo, Hi);
2877 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2878 N->getMemoryVT(), isVolatile, isNonTemporal,
2882 if (DAG.getDataLayout().isLittleEndian()) {
2883 // Little-endian - low bits are at low addresses.
2884 GetExpandedInteger(N->getValue(), Lo, Hi);
2886 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2887 isVolatile, isNonTemporal, Alignment, AAInfo);
2889 unsigned ExcessBits =
2890 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2891 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2893 // Increment the pointer to the other half.
2894 unsigned IncrementSize = NVT.getSizeInBits()/8;
2895 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2896 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2897 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2898 N->getPointerInfo().getWithOffset(IncrementSize),
2899 NEVT, isVolatile, isNonTemporal,
2900 MinAlign(Alignment, IncrementSize), AAInfo);
2901 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2904 // Big-endian - high bits are at low addresses. Favor aligned stores at
2905 // the cost of some bit-fiddling.
2906 GetExpandedInteger(N->getValue(), Lo, Hi);
2908 EVT ExtVT = N->getMemoryVT();
2909 unsigned EBytes = ExtVT.getStoreSize();
2910 unsigned IncrementSize = NVT.getSizeInBits()/8;
2911 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2912 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2913 ExtVT.getSizeInBits() - ExcessBits);
2915 if (ExcessBits < NVT.getSizeInBits()) {
2916 // Transfer high bits from the top of Lo to the bottom of Hi.
2917 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2918 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2919 TLI.getPointerTy(DAG.getDataLayout())));
2921 ISD::OR, dl, NVT, Hi,
2922 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2923 DAG.getConstant(ExcessBits, dl,
2924 TLI.getPointerTy(DAG.getDataLayout()))));
2927 // Store both the high bits and maybe some of the low bits.
2928 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2929 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2931 // Increment the pointer to the other half.
2932 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2933 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2934 // Store the lowest ExcessBits bits in the second half.
2935 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2936 N->getPointerInfo().getWithOffset(IncrementSize),
2937 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2938 isVolatile, isNonTemporal,
2939 MinAlign(Alignment, IncrementSize), AAInfo);
2940 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2943 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2945 GetExpandedInteger(N->getOperand(0), InL, InH);
2946 // Just truncate the low part of the source.
2947 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2950 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2951 SDValue Op = N->getOperand(0);
2952 EVT SrcVT = Op.getValueType();
2953 EVT DstVT = N->getValueType(0);
2956 // The following optimization is valid only if every value in SrcVT (when
2957 // treated as signed) is representable in DstVT. Check that the mantissa
2958 // size of DstVT is >= than the number of bits in SrcVT -1.
2959 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2960 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2961 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2962 // Do a signed conversion then adjust the result.
2963 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2964 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2966 // The result of the signed conversion needs adjusting if the 'sign bit' of
2967 // the incoming integer was set. To handle this, we dynamically test to see
2968 // if it is set, and, if so, add a fudge factor.
2970 const uint64_t F32TwoE32 = 0x4F800000ULL;
2971 const uint64_t F32TwoE64 = 0x5F800000ULL;
2972 const uint64_t F32TwoE128 = 0x7F800000ULL;
2975 if (SrcVT == MVT::i32)
2976 FF = APInt(32, F32TwoE32);
2977 else if (SrcVT == MVT::i64)
2978 FF = APInt(32, F32TwoE64);
2979 else if (SrcVT == MVT::i128)
2980 FF = APInt(32, F32TwoE128);
2982 llvm_unreachable("Unsupported UINT_TO_FP!");
2984 // Check whether the sign bit is set.
2986 GetExpandedInteger(Op, Lo, Hi);
2987 SDValue SignSet = DAG.getSetCC(dl,
2988 getSetCCResultType(Hi.getValueType()),
2990 DAG.getConstant(0, dl, Hi.getValueType()),
2993 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2995 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2996 TLI.getPointerTy(DAG.getDataLayout()));
2998 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2999 SDValue Zero = DAG.getIntPtrConstant(0, dl);
3000 SDValue Four = DAG.getIntPtrConstant(4, dl);
3001 if (DAG.getDataLayout().isBigEndian())
3002 std::swap(Zero, Four);
3003 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
3005 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
3006 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
3008 Alignment = std::min(Alignment, 4u);
3010 // Load the value out, extending it from f32 to the destination float type.
3011 // FIXME: Avoid the extend by constructing the right constant pool?
3012 SDValue Fudge = DAG.getExtLoad(
3013 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
3014 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
3015 false, false, false, Alignment);
3016 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
3019 // Otherwise, use a libcall.
3020 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
3021 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3022 "Don't know how to expand this UINT_TO_FP!");
3023 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first;
3026 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
3028 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3029 cast<AtomicSDNode>(N)->getMemoryVT(),
3031 N->getOperand(1), N->getOperand(2),
3032 cast<AtomicSDNode>(N)->getMemOperand(),
3033 cast<AtomicSDNode>(N)->getOrdering(),
3034 cast<AtomicSDNode>(N)->getSynchScope());
3035 return Swap.getValue(1);
3039 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3040 SDValue InOp0 = N->getOperand(0);
3041 EVT InVT = InOp0.getValueType();
3043 EVT OutVT = N->getValueType(0);
3044 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3045 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3046 unsigned OutNumElems = OutVT.getVectorNumElements();
3047 EVT NOutVTElem = NOutVT.getVectorElementType();
3050 SDValue BaseIdx = N->getOperand(1);
3052 SmallVector<SDValue, 8> Ops;
3053 Ops.reserve(OutNumElems);
3054 for (unsigned i = 0; i != OutNumElems; ++i) {
3056 // Extract the element from the original vector.
3057 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3058 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3059 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3060 InVT.getVectorElementType(), N->getOperand(0), Index);
3062 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3063 // Insert the converted element to the new vector.
3067 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3071 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3072 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3073 EVT VT = N->getValueType(0);
3076 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3078 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3079 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3080 EVT OutVT = V0.getValueType();
3082 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3086 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3087 EVT OutVT = N->getValueType(0);
3088 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3089 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3090 unsigned NumElems = N->getNumOperands();
3091 EVT NOutVTElem = NOutVT.getVectorElementType();
3095 SmallVector<SDValue, 8> Ops;
3096 Ops.reserve(NumElems);
3097 for (unsigned i = 0; i != NumElems; ++i) {
3099 // BUILD_VECTOR integer operand types are allowed to be larger than the
3100 // result's element type. This may still be true after the promotion. For
3101 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3102 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3103 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3104 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3106 Op = N->getOperand(i);
3110 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3113 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3117 assert(!N->getOperand(0).getValueType().isVector() &&
3118 "Input must be a scalar");
3120 EVT OutVT = N->getValueType(0);
3121 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3122 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3123 EVT NOutVTElem = NOutVT.getVectorElementType();
3125 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3127 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3130 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3133 EVT OutVT = N->getValueType(0);
3134 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3135 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3137 EVT InElemTy = OutVT.getVectorElementType();
3138 EVT OutElemTy = NOutVT.getVectorElementType();
3140 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3141 unsigned NumOutElem = NOutVT.getVectorNumElements();
3142 unsigned NumOperands = N->getNumOperands();
3143 assert(NumElem * NumOperands == NumOutElem &&
3144 "Unexpected number of elements");
3146 // Take the elements from the first vector.
3147 SmallVector<SDValue, 8> Ops(NumOutElem);
3148 for (unsigned i = 0; i < NumOperands; ++i) {
3149 SDValue Op = N->getOperand(i);
3150 for (unsigned j = 0; j < NumElem; ++j) {
3151 SDValue Ext = DAG.getNode(
3152 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op,
3153 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3154 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3158 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3161 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3162 EVT OutVT = N->getValueType(0);
3163 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3164 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3166 EVT NOutVTElem = NOutVT.getVectorElementType();
3169 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3171 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3172 NOutVTElem, N->getOperand(1));
3173 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3174 V0, ConvElem, N->getOperand(2));
3177 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3179 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3180 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3181 TLI.getVectorIdxTy(DAG.getDataLayout()));
3182 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3183 V0->getValueType(0).getScalarType(), V0, V1);
3185 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3186 // element types. If this is the case then we need to expand the outgoing
3187 // value and not truncate it.
3188 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3191 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3193 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3194 MVT InVT = V0.getValueType().getSimpleVT();
3195 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3196 N->getValueType(0).getVectorNumElements());
3197 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3198 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3201 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3203 unsigned NumElems = N->getNumOperands();
3205 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3207 SmallVector<SDValue, 8> NewOps;
3208 NewOps.reserve(NumElems);
3210 // For each incoming vector
3211 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3212 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3213 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3214 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3216 for (unsigned i=0; i<NumElem; ++i) {
3217 // Extract element from incoming vector
3218 SDValue Ex = DAG.getNode(
3219 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3220 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3221 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3222 NewOps.push_back(Tr);
3226 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);