1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
105 case ISD::ATOMIC_LOAD_ADD:
106 case ISD::ATOMIC_LOAD_SUB:
107 case ISD::ATOMIC_LOAD_AND:
108 case ISD::ATOMIC_LOAD_OR:
109 case ISD::ATOMIC_LOAD_XOR:
110 case ISD::ATOMIC_LOAD_NAND:
111 case ISD::ATOMIC_LOAD_MIN:
112 case ISD::ATOMIC_LOAD_MAX:
113 case ISD::ATOMIC_LOAD_UMIN:
114 case ISD::ATOMIC_LOAD_UMAX:
115 case ISD::ATOMIC_SWAP:
116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
118 case ISD::ATOMIC_CMP_SWAP:
119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
122 // If the result is null then the sub-method took care of registering it.
124 SetPromotedInteger(SDValue(N, ResNo), Res);
127 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
128 // Sign-extend the new bits, and continue the assertion.
129 SDValue Op = SExtPromotedInteger(N->getOperand(0));
130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
131 Op.getValueType(), Op, N->getOperand(1));
134 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
135 // Zero the new bits, and continue the assertion.
136 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
138 Op.getValueType(), Op, N->getOperand(1));
141 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
142 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
145 N->getChain(), N->getBasePtr(),
146 Op2, N->getMemOperand());
147 // Legalized the chain result - switch anything that used the old chain to
149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
158 Op2, Op3, N->getMemOperand());
159 // Legalized the chain result - switch anything that used the old chain to
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
166 SDValue InOp = N->getOperand(0);
167 EVT InVT = InOp.getValueType();
168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
169 EVT OutVT = N->getValueType(0);
170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
171 DebugLoc dl = N->getDebugLoc();
173 switch (getTypeAction(InVT)) {
175 assert(false && "Unknown type action!");
180 if (NOutVT.bitsEq(NInVT))
181 // The input promotes to the same size. Convert the promoted value.
182 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
185 // Promote the integer operand by hand.
186 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
190 case ScalarizeVector:
191 // Convert the element to an integer and promote it by hand.
192 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
193 BitConvertToInteger(GetScalarizedVector(InOp)));
195 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
196 // pieces of the input into integers and reassemble in the final type.
198 GetSplitVector(N->getOperand(0), Lo, Hi);
199 Lo = BitConvertToInteger(Lo);
200 Hi = BitConvertToInteger(Hi);
202 if (TLI.isBigEndian())
205 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
206 EVT::getIntegerVT(*DAG.getContext(),
207 NOutVT.getSizeInBits()),
208 JoinIntegers(Lo, Hi));
209 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
212 if (OutVT.bitsEq(NInVT))
213 // The input is widened to the same size. Convert to the widened value.
214 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
217 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
218 CreateStackStoreLoad(InOp, OutVT));
221 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
222 SDValue Op = GetPromotedInteger(N->getOperand(0));
223 EVT OVT = N->getValueType(0);
224 EVT NVT = Op.getValueType();
225 DebugLoc dl = N->getDebugLoc();
227 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
228 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
229 DAG.getConstant(DiffBits, TLI.getPointerTy()));
232 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
233 // The pair element type may be legal, or may not promote to the same type as
234 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
235 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
236 TLI.getTypeToTransformTo(*DAG.getContext(),
237 N->getValueType(0)), JoinIntegers(N->getOperand(0),
241 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
242 EVT VT = N->getValueType(0);
243 // FIXME there is no actual debug info here
244 DebugLoc dl = N->getDebugLoc();
245 // Zero extend things like i1, sign extend everything else. It shouldn't
246 // matter in theory which one we pick, but this tends to give better code?
247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
248 SDValue Result = DAG.getNode(Opc, dl,
249 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
251 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
255 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
256 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
257 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
258 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
259 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
260 "can only promote integers");
261 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
262 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
263 N->getOperand(1), N->getOperand(2),
264 N->getOperand(3), N->getOperand(4), CvtCode);
267 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
268 // Zero extend to the promoted type and do the count there.
269 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
270 DebugLoc dl = N->getDebugLoc();
271 EVT OVT = N->getValueType(0);
272 EVT NVT = Op.getValueType();
273 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
274 // Subtract off the extra leading bits in the bigger type.
275 return DAG.getNode(ISD::SUB, dl, NVT, Op,
276 DAG.getConstant(NVT.getSizeInBits() -
277 OVT.getSizeInBits(), NVT));
280 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
281 // Zero extend to the promoted type and do the count there.
282 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
283 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
286 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
287 SDValue Op = GetPromotedInteger(N->getOperand(0));
288 EVT OVT = N->getValueType(0);
289 EVT NVT = Op.getValueType();
290 DebugLoc dl = N->getDebugLoc();
291 // The count is the same in the promoted type except if the original
292 // value was zero. This can be handled by setting the bit just off
293 // the top of the original type.
294 APInt TopBit(NVT.getSizeInBits(), 0);
295 TopBit.setBit(OVT.getSizeInBits());
296 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
297 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
300 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
301 DebugLoc dl = N->getDebugLoc();
302 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
303 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
307 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
308 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
309 unsigned NewOpc = N->getOpcode();
310 DebugLoc dl = N->getDebugLoc();
312 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
313 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
314 // and SINT conversions are Custom, there is no way to tell which is
315 // preferable. We choose SINT because that's the right thing on PPC.)
316 if (N->getOpcode() == ISD::FP_TO_UINT &&
317 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
318 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
319 NewOpc = ISD::FP_TO_SINT;
321 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
323 // Assert that the converted value fits in the original type. If it doesn't
324 // (eg: because the value being converted is too big), then the result of the
325 // original operation was undefined anyway, so the assert is still correct.
326 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
327 ISD::AssertZext : ISD::AssertSext, dl,
328 NVT, Res, DAG.getValueType(N->getValueType(0)));
331 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
332 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
333 DebugLoc dl = N->getDebugLoc();
335 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
337 return DAG.getNode(ISD::AssertZext, dl,
338 NVT, Res, DAG.getValueType(N->getValueType(0)));
341 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
342 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
343 DebugLoc dl = N->getDebugLoc();
345 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
346 SDValue Res = GetPromotedInteger(N->getOperand(0));
347 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
349 // If the result and operand types are the same after promotion, simplify
350 // to an in-register extension.
351 if (NVT == Res.getValueType()) {
352 // The high bits are not guaranteed to be anything. Insert an extend.
353 if (N->getOpcode() == ISD::SIGN_EXTEND)
354 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
355 DAG.getValueType(N->getOperand(0).getValueType()));
356 if (N->getOpcode() == ISD::ZERO_EXTEND)
357 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
358 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
363 // Otherwise, just extend the original operand all the way to the larger type.
364 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
367 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
368 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
370 ISD::LoadExtType ExtType =
371 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
372 DebugLoc dl = N->getDebugLoc();
373 SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(),
375 N->getMemoryVT(), N->isVolatile(),
376 N->isNonTemporal(), N->getAlignment());
378 // Legalized the chain result - switch anything that used the old chain to
380 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
384 /// Promote the overflow flag of an overflowing arithmetic node.
385 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
386 // Simply change the return type of the boolean result.
387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
388 EVT ValueVTs[] = { N->getValueType(0), NVT };
389 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
390 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
391 DAG.getVTList(ValueVTs, 2), Ops, 2);
393 // Modified the sum result - switch anything that used the old sum to use
395 ReplaceValueWith(SDValue(N, 0), Res);
397 return SDValue(Res.getNode(), 1);
400 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
402 return PromoteIntRes_Overflow(N);
404 // The operation overflowed iff the result in the larger type is not the
405 // sign extension of its truncation to the original type.
406 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
407 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
408 EVT OVT = N->getOperand(0).getValueType();
409 EVT NVT = LHS.getValueType();
410 DebugLoc dl = N->getDebugLoc();
412 // Do the arithmetic in the larger type.
413 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
414 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
416 // Calculate the overflow flag: sign extend the arithmetic result from
417 // the original type.
418 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
419 DAG.getValueType(OVT));
420 // Overflowed if and only if this is not equal to Res.
421 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
423 // Use the calculated overflow everywhere.
424 ReplaceValueWith(SDValue(N, 1), Ofl);
429 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
430 // Sign extend the input.
431 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
432 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
433 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
434 LHS.getValueType(), LHS, RHS);
437 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
438 SDValue LHS = GetPromotedInteger(N->getOperand(1));
439 SDValue RHS = GetPromotedInteger(N->getOperand(2));
440 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
441 LHS.getValueType(), N->getOperand(0),LHS,RHS);
444 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
445 SDValue LHS = GetPromotedInteger(N->getOperand(2));
446 SDValue RHS = GetPromotedInteger(N->getOperand(3));
447 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
448 LHS.getValueType(), N->getOperand(0),
449 N->getOperand(1), LHS, RHS, N->getOperand(4));
452 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
453 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
454 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
455 DebugLoc dl = N->getDebugLoc();
457 // Get the SETCC result using the canonical SETCC type.
458 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
459 N->getOperand(1), N->getOperand(2));
461 // Convert to the expected type.
462 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
463 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
464 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
467 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
468 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
469 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
470 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
473 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
474 SDValue Op = GetPromotedInteger(N->getOperand(0));
475 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
476 Op.getValueType(), Op, N->getOperand(1));
479 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
480 // The input may have strange things in the top bits of the registers, but
481 // these operations don't care. They may have weird bits going out, but
482 // that too is okay if they are integer operations.
483 SDValue LHS = GetPromotedInteger(N->getOperand(0));
484 SDValue RHS = GetPromotedInteger(N->getOperand(1));
485 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
486 LHS.getValueType(), LHS, RHS);
489 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
490 // The input value must be properly sign extended.
491 SDValue Res = SExtPromotedInteger(N->getOperand(0));
492 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
493 Res.getValueType(), Res, N->getOperand(1));
496 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
497 // The input value must be properly zero extended.
498 EVT VT = N->getValueType(0);
499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
500 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
501 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
504 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
505 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
508 switch (getTypeAction(N->getOperand(0).getValueType())) {
509 default: llvm_unreachable("Unknown type action!");
512 Res = N->getOperand(0);
515 Res = GetPromotedInteger(N->getOperand(0));
519 // Truncate to NVT instead of VT
520 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
523 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
525 return PromoteIntRes_Overflow(N);
527 // The operation overflowed iff the result in the larger type is not the
528 // zero extension of its truncation to the original type.
529 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
530 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
531 EVT OVT = N->getOperand(0).getValueType();
532 EVT NVT = LHS.getValueType();
533 DebugLoc dl = N->getDebugLoc();
535 // Do the arithmetic in the larger type.
536 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
537 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
539 // Calculate the overflow flag: zero extend the arithmetic result from
540 // the original type.
541 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
542 // Overflowed if and only if this is not equal to Res.
543 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
545 // Use the calculated overflow everywhere.
546 ReplaceValueWith(SDValue(N, 1), Ofl);
552 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
553 // Promote the overflow bit trivially.
555 return PromoteIntRes_Overflow(N);
557 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
558 DebugLoc DL = N->getDebugLoc();
559 unsigned SmallSize = LHS.getValueType().getSizeInBits();
561 // To determine if the result overflowed in a larger type, we extend the input
562 // to the larger type, do the multiply, then check the high bits of the result
563 // to see if the overflow happened.
564 if (N->getOpcode() == ISD::SMULO) {
565 LHS = SExtPromotedInteger(LHS);
566 RHS = SExtPromotedInteger(RHS);
568 LHS = ZExtPromotedInteger(LHS);
569 RHS = ZExtPromotedInteger(RHS);
572 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
575 // For an unsigned overflow, we check to see if the high part is != 0;
577 if (N->getOpcode() == ISD::UMULO) {
578 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
579 DAG.getIntPtrConstant(SmallSize));
580 // Overflowed if and only if this is not equal to Res.
581 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
582 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
584 // Signed multiply overflowed if the high part is not 0 and not -1.
585 SDValue Hi = DAG.getNode(ISD::SRA, DL, Mul.getValueType(), Mul,
586 DAG.getIntPtrConstant(SmallSize));
587 Hi = DAG.getNode(ISD::ADD, DL, Hi.getValueType(), Hi,
588 DAG.getConstant(1, Hi.getValueType()));
589 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
590 DAG.getConstant(1, Hi.getValueType()), ISD::SETUGT);
593 // Use the calculated overflow everywhere.
594 ReplaceValueWith(SDValue(N, 1), Overflow);
599 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
600 // Zero extend the input.
601 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
602 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
603 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
604 LHS.getValueType(), LHS, RHS);
607 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
608 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
609 N->getValueType(0)));
612 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
613 SDValue Chain = N->getOperand(0); // Get the chain.
614 SDValue Ptr = N->getOperand(1); // Get the pointer.
615 EVT VT = N->getValueType(0);
616 DebugLoc dl = N->getDebugLoc();
618 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
619 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
620 // The argument is passed as NumRegs registers of type RegVT.
622 SmallVector<SDValue, 8> Parts(NumRegs);
623 for (unsigned i = 0; i < NumRegs; ++i) {
624 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
625 N->getConstantOperandVal(3));
626 Chain = Parts[i].getValue(1);
629 // Handle endianness of the load.
630 if (TLI.isBigEndian())
631 std::reverse(Parts.begin(), Parts.end());
633 // Assemble the parts in the promoted type.
634 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
635 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
636 for (unsigned i = 1; i < NumRegs; ++i) {
637 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
638 // Shift it to the right position and "or" it in.
639 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
640 DAG.getConstant(i * RegVT.getSizeInBits(),
641 TLI.getPointerTy()));
642 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
645 // Modified the chain result - switch anything that used the old chain to
647 ReplaceValueWith(SDValue(N, 1), Chain);
652 //===----------------------------------------------------------------------===//
653 // Integer Operand Promotion
654 //===----------------------------------------------------------------------===//
656 /// PromoteIntegerOperand - This method is called when the specified operand of
657 /// the specified node is found to need promotion. At this point, all of the
658 /// result types of the node are known to be legal, but other operands of the
659 /// node may need promotion or expansion as well as the specified one.
660 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
661 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
662 SDValue Res = SDValue();
664 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
667 switch (N->getOpcode()) {
670 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
671 N->dump(&DAG); dbgs() << "\n";
673 llvm_unreachable("Do not know how to promote this operator's operand!");
675 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
676 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
677 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
678 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
679 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
680 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
681 case ISD::CONVERT_RNDSAT:
682 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
683 case ISD::INSERT_VECTOR_ELT:
684 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
685 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
686 case ISD::SCALAR_TO_VECTOR:
687 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
688 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
689 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
690 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
691 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
692 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
693 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
695 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
696 case ISD::FP16_TO_FP32:
697 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
698 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
704 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
707 // If the result is null, the sub-method took care of registering results etc.
708 if (!Res.getNode()) return false;
710 // If the result is N, the sub-method updated N in place. Tell the legalizer
712 if (Res.getNode() == N)
715 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
716 "Invalid operand expansion");
718 ReplaceValueWith(SDValue(N, 0), Res);
722 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
723 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
724 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
725 ISD::CondCode CCCode) {
726 // We have to insert explicit sign or zero extends. Note that we could
727 // insert sign extends for ALL conditions, but zero extend is cheaper on
728 // many machines (an AND instead of two shifts), so prefer it.
730 default: llvm_unreachable("Unknown integer comparison!");
737 // ALL of these operations will work if we either sign or zero extend
738 // the operands (including the unsigned comparisons!). Zero extend is
739 // usually a simpler/cheaper operation, so prefer it.
740 NewLHS = ZExtPromotedInteger(NewLHS);
741 NewRHS = ZExtPromotedInteger(NewRHS);
747 NewLHS = SExtPromotedInteger(NewLHS);
748 NewRHS = SExtPromotedInteger(NewRHS);
753 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
754 SDValue Op = GetPromotedInteger(N->getOperand(0));
755 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
758 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
759 // This should only occur in unusual situations like bitcasting to an
760 // x86_fp80, so just turn it into a store+load
761 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
764 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
765 assert(OpNo == 2 && "Don't know how to promote this operand!");
767 SDValue LHS = N->getOperand(2);
768 SDValue RHS = N->getOperand(3);
769 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
771 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
773 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
774 N->getOperand(1), LHS, RHS, N->getOperand(4)),
778 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
779 assert(OpNo == 1 && "only know how to promote condition");
781 // Promote all the way up to the canonical SetCC type.
782 EVT SVT = TLI.getSetCCResultType(MVT::Other);
783 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
785 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
786 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
787 N->getOperand(2)), 0);
790 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
791 // Since the result type is legal, the operands must promote to it.
792 EVT OVT = N->getOperand(0).getValueType();
793 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
794 SDValue Hi = GetPromotedInteger(N->getOperand(1));
795 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
796 DebugLoc dl = N->getDebugLoc();
798 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
799 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
800 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
803 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
804 // The vector type is legal but the element type is not. This implies
805 // that the vector is a power-of-two in length and that the element
806 // type does not have a strange size (eg: it is not i1).
807 EVT VecVT = N->getValueType(0);
808 unsigned NumElts = VecVT.getVectorNumElements();
809 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
811 // Promote the inserted value. The type does not need to match the
812 // vector element type. Check that any extra bits introduced will be
814 assert(N->getOperand(0).getValueType().getSizeInBits() >=
815 N->getValueType(0).getVectorElementType().getSizeInBits() &&
816 "Type of inserted value narrower than vector element type!");
818 SmallVector<SDValue, 16> NewOps;
819 for (unsigned i = 0; i < NumElts; ++i)
820 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
822 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
825 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
826 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
827 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
828 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
829 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
830 "can only promote integer arguments");
831 SDValue InOp = GetPromotedInteger(N->getOperand(0));
832 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
833 N->getOperand(1), N->getOperand(2),
834 N->getOperand(3), N->getOperand(4), CvtCode);
837 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
840 // Promote the inserted value. This is valid because the type does not
841 // have to match the vector element type.
843 // Check that any extra bits introduced will be truncated away.
844 assert(N->getOperand(1).getValueType().getSizeInBits() >=
845 N->getValueType(0).getVectorElementType().getSizeInBits() &&
846 "Type of inserted value narrower than vector element type!");
847 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
848 GetPromotedInteger(N->getOperand(1)),
853 assert(OpNo == 2 && "Different operand and result vector types?");
855 // Promote the index.
856 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
857 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
858 N->getOperand(1), Idx), 0);
861 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
863 DebugLoc dl = N->getDebugLoc();
864 NewOps[0] = N->getOperand(0);
865 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
866 SDValue Flag = GetPromotedInteger(N->getOperand(i));
867 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
869 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
872 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
873 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
874 // the operand in place.
875 return SDValue(DAG.UpdateNodeOperands(N,
876 GetPromotedInteger(N->getOperand(0))), 0);
879 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
880 assert(OpNo == 0 && "Only know how to promote condition");
882 // Promote all the way up to the canonical SetCC type.
883 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
884 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
886 return SDValue(DAG.UpdateNodeOperands(N, Cond,
887 N->getOperand(1), N->getOperand(2)), 0);
890 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
891 assert(OpNo == 0 && "Don't know how to promote this operand!");
893 SDValue LHS = N->getOperand(0);
894 SDValue RHS = N->getOperand(1);
895 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
897 // The CC (#4) and the possible return values (#2 and #3) have legal types.
898 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
899 N->getOperand(3), N->getOperand(4)), 0);
902 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
903 assert(OpNo == 0 && "Don't know how to promote this operand!");
905 SDValue LHS = N->getOperand(0);
906 SDValue RHS = N->getOperand(1);
907 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
909 // The CC (#2) is always legal.
910 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
913 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
914 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
915 ZExtPromotedInteger(N->getOperand(1))), 0);
918 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
919 SDValue Op = GetPromotedInteger(N->getOperand(0));
920 DebugLoc dl = N->getDebugLoc();
921 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
922 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
923 Op, DAG.getValueType(N->getOperand(0).getValueType()));
926 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
927 return SDValue(DAG.UpdateNodeOperands(N,
928 SExtPromotedInteger(N->getOperand(0))), 0);
931 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
932 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
933 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
934 unsigned Alignment = N->getAlignment();
935 bool isVolatile = N->isVolatile();
936 bool isNonTemporal = N->isNonTemporal();
937 DebugLoc dl = N->getDebugLoc();
939 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
941 // Truncate the value and store the result.
942 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
944 isVolatile, isNonTemporal, Alignment);
947 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
948 SDValue Op = GetPromotedInteger(N->getOperand(0));
949 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
952 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
953 return SDValue(DAG.UpdateNodeOperands(N,
954 ZExtPromotedInteger(N->getOperand(0))), 0);
957 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
958 DebugLoc dl = N->getDebugLoc();
959 SDValue Op = GetPromotedInteger(N->getOperand(0));
960 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
961 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
965 //===----------------------------------------------------------------------===//
966 // Integer Result Expansion
967 //===----------------------------------------------------------------------===//
969 /// ExpandIntegerResult - This method is called when the specified result of the
970 /// specified node is found to need expansion. At this point, the node may also
971 /// have invalid operands or may have other results that need promotion, we just
972 /// know that (at least) one result needs expansion.
973 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
974 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
978 // See if the target wants to custom expand this node.
979 if (CustomLowerNode(N, N->getValueType(ResNo), true))
982 switch (N->getOpcode()) {
985 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
986 N->dump(&DAG); dbgs() << "\n";
988 llvm_unreachable("Do not know how to expand the result of this operator!");
990 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
991 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
992 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
993 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
995 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
996 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
997 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
998 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
999 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1001 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1002 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1003 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1004 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1005 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1006 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1007 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1008 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1009 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1010 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1011 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1012 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1013 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1014 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1015 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1016 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1017 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1018 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1019 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1020 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1022 case ISD::ATOMIC_LOAD_ADD:
1023 case ISD::ATOMIC_LOAD_SUB:
1024 case ISD::ATOMIC_LOAD_AND:
1025 case ISD::ATOMIC_LOAD_OR:
1026 case ISD::ATOMIC_LOAD_XOR:
1027 case ISD::ATOMIC_LOAD_NAND:
1028 case ISD::ATOMIC_LOAD_MIN:
1029 case ISD::ATOMIC_LOAD_MAX:
1030 case ISD::ATOMIC_LOAD_UMIN:
1031 case ISD::ATOMIC_LOAD_UMAX:
1032 case ISD::ATOMIC_SWAP: {
1033 SDValue Ch = N->getOperand(0);
1034 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1035 SplitInteger(Tmp.first, Lo, Hi);
1036 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1042 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1045 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1048 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1051 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1055 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1058 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1060 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1063 // If Lo/Hi is null, the sub-method took care of registering results etc.
1065 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1068 /// Lower an atomic node to the appropriate builtin call.
1069 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1070 unsigned Opc = Node->getOpcode();
1071 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1076 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1078 case ISD::ATOMIC_SWAP:
1079 switch (VT.SimpleTy) {
1080 default: llvm_unreachable("Unexpected value type for atomic!");
1081 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1082 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1083 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1084 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1087 case ISD::ATOMIC_CMP_SWAP:
1088 switch (VT.SimpleTy) {
1089 default: llvm_unreachable("Unexpected value type for atomic!");
1090 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1091 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1092 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1093 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1096 case ISD::ATOMIC_LOAD_ADD:
1097 switch (VT.SimpleTy) {
1098 default: llvm_unreachable("Unexpected value type for atomic!");
1099 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1100 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1101 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1102 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1105 case ISD::ATOMIC_LOAD_SUB:
1106 switch (VT.SimpleTy) {
1107 default: llvm_unreachable("Unexpected value type for atomic!");
1108 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1109 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1110 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1111 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1114 case ISD::ATOMIC_LOAD_AND:
1115 switch (VT.SimpleTy) {
1116 default: llvm_unreachable("Unexpected value type for atomic!");
1117 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1118 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1119 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1120 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1123 case ISD::ATOMIC_LOAD_OR:
1124 switch (VT.SimpleTy) {
1125 default: llvm_unreachable("Unexpected value type for atomic!");
1126 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1127 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1128 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1129 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1132 case ISD::ATOMIC_LOAD_XOR:
1133 switch (VT.SimpleTy) {
1134 default: llvm_unreachable("Unexpected value type for atomic!");
1135 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1136 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1137 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1138 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1141 case ISD::ATOMIC_LOAD_NAND:
1142 switch (VT.SimpleTy) {
1143 default: llvm_unreachable("Unexpected value type for atomic!");
1144 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1145 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1146 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1147 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1152 return ExpandChainLibCall(LC, Node, false);
1155 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1156 /// and the shift amount is a constant 'Amt'. Expand the operation.
1157 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1158 SDValue &Lo, SDValue &Hi) {
1159 DebugLoc dl = N->getDebugLoc();
1160 // Expand the incoming operand to be shifted, so that we have its parts
1162 GetExpandedInteger(N->getOperand(0), InL, InH);
1164 EVT NVT = InL.getValueType();
1165 unsigned VTBits = N->getValueType(0).getSizeInBits();
1166 unsigned NVTBits = NVT.getSizeInBits();
1167 EVT ShTy = N->getOperand(1).getValueType();
1169 if (N->getOpcode() == ISD::SHL) {
1171 Lo = Hi = DAG.getConstant(0, NVT);
1172 } else if (Amt > NVTBits) {
1173 Lo = DAG.getConstant(0, NVT);
1174 Hi = DAG.getNode(ISD::SHL, dl,
1175 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1176 } else if (Amt == NVTBits) {
1177 Lo = DAG.getConstant(0, NVT);
1179 } else if (Amt == 1 &&
1180 TLI.isOperationLegalOrCustom(ISD::ADDC,
1181 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1182 // Emit this X << 1 as X+X.
1183 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1184 SDValue LoOps[2] = { InL, InL };
1185 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1186 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1187 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1189 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1190 Hi = DAG.getNode(ISD::OR, dl, NVT,
1191 DAG.getNode(ISD::SHL, dl, NVT, InH,
1192 DAG.getConstant(Amt, ShTy)),
1193 DAG.getNode(ISD::SRL, dl, NVT, InL,
1194 DAG.getConstant(NVTBits-Amt, ShTy)));
1199 if (N->getOpcode() == ISD::SRL) {
1201 Lo = DAG.getConstant(0, NVT);
1202 Hi = DAG.getConstant(0, NVT);
1203 } else if (Amt > NVTBits) {
1204 Lo = DAG.getNode(ISD::SRL, dl,
1205 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1206 Hi = DAG.getConstant(0, NVT);
1207 } else if (Amt == NVTBits) {
1209 Hi = DAG.getConstant(0, NVT);
1211 Lo = DAG.getNode(ISD::OR, dl, NVT,
1212 DAG.getNode(ISD::SRL, dl, NVT, InL,
1213 DAG.getConstant(Amt, ShTy)),
1214 DAG.getNode(ISD::SHL, dl, NVT, InH,
1215 DAG.getConstant(NVTBits-Amt, ShTy)));
1216 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1221 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1223 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1224 DAG.getConstant(NVTBits-1, ShTy));
1225 } else if (Amt > NVTBits) {
1226 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1227 DAG.getConstant(Amt-NVTBits, ShTy));
1228 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1229 DAG.getConstant(NVTBits-1, ShTy));
1230 } else if (Amt == NVTBits) {
1232 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1233 DAG.getConstant(NVTBits-1, ShTy));
1235 Lo = DAG.getNode(ISD::OR, dl, NVT,
1236 DAG.getNode(ISD::SRL, dl, NVT, InL,
1237 DAG.getConstant(Amt, ShTy)),
1238 DAG.getNode(ISD::SHL, dl, NVT, InH,
1239 DAG.getConstant(NVTBits-Amt, ShTy)));
1240 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1244 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1245 /// this shift based on knowledge of the high bit of the shift amount. If we
1246 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1248 bool DAGTypeLegalizer::
1249 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1250 SDValue Amt = N->getOperand(1);
1251 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1252 EVT ShTy = Amt.getValueType();
1253 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1254 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1255 assert(isPowerOf2_32(NVTBits) &&
1256 "Expanded integer type size not a power of two!");
1257 DebugLoc dl = N->getDebugLoc();
1259 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1260 APInt KnownZero, KnownOne;
1261 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1263 // If we don't know anything about the high bits, exit.
1264 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1267 // Get the incoming operand to be shifted.
1269 GetExpandedInteger(N->getOperand(0), InL, InH);
1271 // If we know that any of the high bits of the shift amount are one, then we
1272 // can do this as a couple of simple shifts.
1273 if (KnownOne.intersects(HighBitMask)) {
1274 // Mask out the high bit, which we know is set.
1275 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1276 DAG.getConstant(~HighBitMask, ShTy));
1278 switch (N->getOpcode()) {
1279 default: llvm_unreachable("Unknown shift");
1281 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1282 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1285 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1286 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1289 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1290 DAG.getConstant(NVTBits-1, ShTy));
1291 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1297 // FIXME: This code is broken for shifts with a zero amount!
1298 // If we know that all of the high bits of the shift amount are zero, then we
1299 // can do this as a couple of simple shifts.
1300 if ((KnownZero & HighBitMask) == HighBitMask) {
1302 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1303 DAG.getConstant(NVTBits, ShTy),
1306 switch (N->getOpcode()) {
1307 default: llvm_unreachable("Unknown shift");
1308 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1310 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1313 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1314 Hi = DAG.getNode(ISD::OR, NVT,
1315 DAG.getNode(Op1, NVT, InH, Amt),
1316 DAG.getNode(Op2, NVT, InL, Amt2));
1324 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1326 bool DAGTypeLegalizer::
1327 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1328 SDValue Amt = N->getOperand(1);
1329 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1330 EVT ShTy = Amt.getValueType();
1331 unsigned NVTBits = NVT.getSizeInBits();
1332 assert(isPowerOf2_32(NVTBits) &&
1333 "Expanded integer type size not a power of two!");
1334 DebugLoc dl = N->getDebugLoc();
1336 // Get the incoming operand to be shifted.
1338 GetExpandedInteger(N->getOperand(0), InL, InH);
1340 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1341 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1342 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1343 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1344 Amt, NVBitsNode, ISD::SETULT);
1346 SDValue LoS, HiS, LoL, HiL;
1347 switch (N->getOpcode()) {
1348 default: llvm_unreachable("Unknown shift");
1350 // Short: ShAmt < NVTBits
1351 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1352 HiS = DAG.getNode(ISD::OR, dl, NVT,
1353 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1354 // FIXME: If Amt is zero, the following shift generates an undefined result
1355 // on some architectures.
1356 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1358 // Long: ShAmt >= NVTBits
1359 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1360 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1362 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1363 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1366 // Short: ShAmt < NVTBits
1367 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1368 LoS = DAG.getNode(ISD::OR, dl, NVT,
1369 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1370 // FIXME: If Amt is zero, the following shift generates an undefined result
1371 // on some architectures.
1372 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1374 // Long: ShAmt >= NVTBits
1375 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1376 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1378 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1379 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1382 // Short: ShAmt < NVTBits
1383 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1384 LoS = DAG.getNode(ISD::OR, dl, NVT,
1385 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1386 // FIXME: If Amt is zero, the following shift generates an undefined result
1387 // on some architectures.
1388 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1390 // Long: ShAmt >= NVTBits
1391 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1392 DAG.getConstant(NVTBits-1, ShTy));
1393 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1395 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1396 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1403 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1404 SDValue &Lo, SDValue &Hi) {
1405 DebugLoc dl = N->getDebugLoc();
1406 // Expand the subcomponents.
1407 SDValue LHSL, LHSH, RHSL, RHSH;
1408 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1409 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1411 EVT NVT = LHSL.getValueType();
1412 SDValue LoOps[2] = { LHSL, RHSL };
1413 SDValue HiOps[3] = { LHSH, RHSH };
1415 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1416 // them. TODO: Teach operation legalization how to expand unsupported
1417 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1418 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1419 // generate a value of this type in the expanded code sequence.
1421 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1422 ISD::ADDC : ISD::SUBC,
1423 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1426 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1427 if (N->getOpcode() == ISD::ADD) {
1428 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1429 HiOps[2] = Lo.getValue(1);
1430 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1432 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1433 HiOps[2] = Lo.getValue(1);
1434 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1439 if (N->getOpcode() == ISD::ADD) {
1440 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1441 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1442 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1444 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1445 DAG.getConstant(1, NVT),
1446 DAG.getConstant(0, NVT));
1447 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1449 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1450 DAG.getConstant(1, NVT), Carry1);
1451 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1453 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1454 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1456 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1457 LoOps[0], LoOps[1], ISD::SETULT);
1458 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1459 DAG.getConstant(1, NVT),
1460 DAG.getConstant(0, NVT));
1461 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1465 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1466 SDValue &Lo, SDValue &Hi) {
1467 // Expand the subcomponents.
1468 SDValue LHSL, LHSH, RHSL, RHSH;
1469 DebugLoc dl = N->getDebugLoc();
1470 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1471 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1472 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1473 SDValue LoOps[2] = { LHSL, RHSL };
1474 SDValue HiOps[3] = { LHSH, RHSH };
1476 if (N->getOpcode() == ISD::ADDC) {
1477 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1478 HiOps[2] = Lo.getValue(1);
1479 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1481 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1482 HiOps[2] = Lo.getValue(1);
1483 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1486 // Legalized the flag result - switch anything that used the old flag to
1488 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1491 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1492 SDValue &Lo, SDValue &Hi) {
1493 // Expand the subcomponents.
1494 SDValue LHSL, LHSH, RHSL, RHSH;
1495 DebugLoc dl = N->getDebugLoc();
1496 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1497 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1498 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1499 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1500 SDValue HiOps[3] = { LHSH, RHSH };
1502 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1503 HiOps[2] = Lo.getValue(1);
1504 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1506 // Legalized the flag result - switch anything that used the old flag to
1508 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1511 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1512 SDValue &Lo, SDValue &Hi) {
1513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1514 DebugLoc dl = N->getDebugLoc();
1515 SDValue Op = N->getOperand(0);
1516 if (Op.getValueType().bitsLE(NVT)) {
1517 // The low part is any extension of the input (which degenerates to a copy).
1518 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1519 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1521 // For example, extension of an i48 to an i64. The operand type necessarily
1522 // promotes to the result type, so will end up being expanded too.
1523 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1524 "Only know how to promote this result!");
1525 SDValue Res = GetPromotedInteger(Op);
1526 assert(Res.getValueType() == N->getValueType(0) &&
1527 "Operand over promoted?");
1528 // Split the promoted operand. This will simplify when it is expanded.
1529 SplitInteger(Res, Lo, Hi);
1533 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1534 SDValue &Lo, SDValue &Hi) {
1535 DebugLoc dl = N->getDebugLoc();
1536 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1537 EVT NVT = Lo.getValueType();
1538 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1539 unsigned NVTBits = NVT.getSizeInBits();
1540 unsigned EVTBits = EVT.getSizeInBits();
1542 if (NVTBits < EVTBits) {
1543 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1544 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1545 EVTBits - NVTBits)));
1547 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1548 // The high part replicates the sign bit of Lo, make it explicit.
1549 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1550 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1554 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1555 SDValue &Lo, SDValue &Hi) {
1556 DebugLoc dl = N->getDebugLoc();
1557 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1558 EVT NVT = Lo.getValueType();
1559 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1560 unsigned NVTBits = NVT.getSizeInBits();
1561 unsigned EVTBits = EVT.getSizeInBits();
1563 if (NVTBits < EVTBits) {
1564 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1565 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1566 EVTBits - NVTBits)));
1568 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1569 // The high part must be zero, make it explicit.
1570 Hi = DAG.getConstant(0, NVT);
1574 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1575 SDValue &Lo, SDValue &Hi) {
1576 DebugLoc dl = N->getDebugLoc();
1577 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1578 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1579 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1582 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1583 SDValue &Lo, SDValue &Hi) {
1584 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1585 unsigned NBitWidth = NVT.getSizeInBits();
1586 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1587 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1588 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1591 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1592 SDValue &Lo, SDValue &Hi) {
1593 DebugLoc dl = N->getDebugLoc();
1594 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1595 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1596 EVT NVT = Lo.getValueType();
1598 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1599 DAG.getConstant(0, NVT), ISD::SETNE);
1601 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1602 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1604 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1605 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1606 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1607 Hi = DAG.getConstant(0, NVT);
1610 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1611 SDValue &Lo, SDValue &Hi) {
1612 DebugLoc dl = N->getDebugLoc();
1613 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1614 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1615 EVT NVT = Lo.getValueType();
1616 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1617 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1618 Hi = DAG.getConstant(0, NVT);
1621 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1622 SDValue &Lo, SDValue &Hi) {
1623 DebugLoc dl = N->getDebugLoc();
1624 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1625 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1626 EVT NVT = Lo.getValueType();
1628 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1629 DAG.getConstant(0, NVT), ISD::SETNE);
1631 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1632 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1634 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1635 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1636 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1637 Hi = DAG.getConstant(0, NVT);
1640 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1642 DebugLoc dl = N->getDebugLoc();
1643 EVT VT = N->getValueType(0);
1644 SDValue Op = N->getOperand(0);
1645 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1646 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1647 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1650 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1652 DebugLoc dl = N->getDebugLoc();
1653 EVT VT = N->getValueType(0);
1654 SDValue Op = N->getOperand(0);
1655 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1656 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1657 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1660 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1661 SDValue &Lo, SDValue &Hi) {
1662 if (ISD::isNormalLoad(N)) {
1663 ExpandRes_NormalLoad(N, Lo, Hi);
1667 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1669 EVT VT = N->getValueType(0);
1670 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1671 SDValue Ch = N->getChain();
1672 SDValue Ptr = N->getBasePtr();
1673 ISD::LoadExtType ExtType = N->getExtensionType();
1674 unsigned Alignment = N->getAlignment();
1675 bool isVolatile = N->isVolatile();
1676 bool isNonTemporal = N->isNonTemporal();
1677 DebugLoc dl = N->getDebugLoc();
1679 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1681 if (N->getMemoryVT().bitsLE(NVT)) {
1682 EVT MemVT = N->getMemoryVT();
1684 Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1685 MemVT, isVolatile, isNonTemporal, Alignment);
1687 // Remember the chain.
1688 Ch = Lo.getValue(1);
1690 if (ExtType == ISD::SEXTLOAD) {
1691 // The high part is obtained by SRA'ing all but one of the bits of the
1693 unsigned LoSize = Lo.getValueType().getSizeInBits();
1694 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1695 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1696 } else if (ExtType == ISD::ZEXTLOAD) {
1697 // The high part is just a zero.
1698 Hi = DAG.getConstant(0, NVT);
1700 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1701 // The high part is undefined.
1702 Hi = DAG.getUNDEF(NVT);
1704 } else if (TLI.isLittleEndian()) {
1705 // Little-endian - low bits are at low addresses.
1706 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1707 isVolatile, isNonTemporal, Alignment);
1709 unsigned ExcessBits =
1710 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1711 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1713 // Increment the pointer to the other half.
1714 unsigned IncrementSize = NVT.getSizeInBits()/8;
1715 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1716 DAG.getIntPtrConstant(IncrementSize));
1717 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr,
1718 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1719 isVolatile, isNonTemporal,
1720 MinAlign(Alignment, IncrementSize));
1722 // Build a factor node to remember that this load is independent of the
1724 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1727 // Big-endian - high bits are at low addresses. Favor aligned loads at
1728 // the cost of some bit-fiddling.
1729 EVT MemVT = N->getMemoryVT();
1730 unsigned EBytes = MemVT.getStoreSize();
1731 unsigned IncrementSize = NVT.getSizeInBits()/8;
1732 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1734 // Load both the high bits and maybe some of the low bits.
1735 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1736 EVT::getIntegerVT(*DAG.getContext(),
1737 MemVT.getSizeInBits() - ExcessBits),
1738 isVolatile, isNonTemporal, Alignment);
1740 // Increment the pointer to the other half.
1741 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1742 DAG.getIntPtrConstant(IncrementSize));
1743 // Load the rest of the low bits.
1744 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr,
1745 N->getPointerInfo().getWithOffset(IncrementSize),
1746 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1747 isVolatile, isNonTemporal,
1748 MinAlign(Alignment, IncrementSize));
1750 // Build a factor node to remember that this load is independent of the
1752 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1755 if (ExcessBits < NVT.getSizeInBits()) {
1756 // Transfer low bits from the bottom of Hi to the top of Lo.
1757 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1758 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1759 DAG.getConstant(ExcessBits,
1760 TLI.getPointerTy())));
1761 // Move high bits to the right position in Hi.
1762 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1764 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1765 TLI.getPointerTy()));
1769 // Legalized the chain result - switch anything that used the old chain to
1771 ReplaceValueWith(SDValue(N, 1), Ch);
1774 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1775 SDValue &Lo, SDValue &Hi) {
1776 DebugLoc dl = N->getDebugLoc();
1777 SDValue LL, LH, RL, RH;
1778 GetExpandedInteger(N->getOperand(0), LL, LH);
1779 GetExpandedInteger(N->getOperand(1), RL, RH);
1780 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1781 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1784 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1785 SDValue &Lo, SDValue &Hi) {
1786 EVT VT = N->getValueType(0);
1787 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1788 DebugLoc dl = N->getDebugLoc();
1790 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1791 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1792 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1793 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1794 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1795 SDValue LL, LH, RL, RH;
1796 GetExpandedInteger(N->getOperand(0), LL, LH);
1797 GetExpandedInteger(N->getOperand(1), RL, RH);
1798 unsigned OuterBitSize = VT.getSizeInBits();
1799 unsigned InnerBitSize = NVT.getSizeInBits();
1800 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1801 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1803 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1804 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1805 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1806 // The inputs are both zero-extended.
1808 // We can emit a umul_lohi.
1809 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1810 Hi = SDValue(Lo.getNode(), 1);
1814 // We can emit a mulhu+mul.
1815 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1816 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1820 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1821 // The input values are both sign-extended.
1823 // We can emit a smul_lohi.
1824 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1825 Hi = SDValue(Lo.getNode(), 1);
1829 // We can emit a mulhs+mul.
1830 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1831 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1836 // Lo,Hi = umul LHS, RHS.
1837 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1838 DAG.getVTList(NVT, NVT), LL, RL);
1840 Hi = UMulLOHI.getValue(1);
1841 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1842 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1843 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1844 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1848 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1849 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1850 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1851 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1852 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1853 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1858 // If nothing else, we can make a libcall.
1859 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1861 LC = RTLIB::MUL_I16;
1862 else if (VT == MVT::i32)
1863 LC = RTLIB::MUL_I32;
1864 else if (VT == MVT::i64)
1865 LC = RTLIB::MUL_I64;
1866 else if (VT == MVT::i128)
1867 LC = RTLIB::MUL_I128;
1868 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1870 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1871 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1874 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1875 SDValue &Lo, SDValue &Hi) {
1876 SDValue LHS = Node->getOperand(0);
1877 SDValue RHS = Node->getOperand(1);
1878 DebugLoc dl = Node->getDebugLoc();
1880 // Expand the result by simply replacing it with the equivalent
1881 // non-overflow-checking operation.
1882 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1883 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1885 SplitInteger(Sum, Lo, Hi);
1887 // Compute the overflow.
1889 // LHSSign -> LHS >= 0
1890 // RHSSign -> RHS >= 0
1891 // SumSign -> Sum >= 0
1894 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1896 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1898 EVT OType = Node->getValueType(1);
1899 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1901 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1902 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1903 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1904 Node->getOpcode() == ISD::SADDO ?
1905 ISD::SETEQ : ISD::SETNE);
1907 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1908 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1910 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1912 // Use the calculated overflow everywhere.
1913 ReplaceValueWith(SDValue(Node, 1), Cmp);
1916 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1917 SDValue &Lo, SDValue &Hi) {
1918 EVT VT = N->getValueType(0);
1919 DebugLoc dl = N->getDebugLoc();
1921 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1923 LC = RTLIB::SDIV_I16;
1924 else if (VT == MVT::i32)
1925 LC = RTLIB::SDIV_I32;
1926 else if (VT == MVT::i64)
1927 LC = RTLIB::SDIV_I64;
1928 else if (VT == MVT::i128)
1929 LC = RTLIB::SDIV_I128;
1930 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1932 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1933 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1936 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1937 SDValue &Lo, SDValue &Hi) {
1938 EVT VT = N->getValueType(0);
1939 DebugLoc dl = N->getDebugLoc();
1941 // If we can emit an efficient shift operation, do so now. Check to see if
1942 // the RHS is a constant.
1943 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1944 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1946 // If we can determine that the high bit of the shift is zero or one, even if
1947 // the low bits are variable, emit this shift in an optimized form.
1948 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1951 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1953 if (N->getOpcode() == ISD::SHL) {
1954 PartsOpc = ISD::SHL_PARTS;
1955 } else if (N->getOpcode() == ISD::SRL) {
1956 PartsOpc = ISD::SRL_PARTS;
1958 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1959 PartsOpc = ISD::SRA_PARTS;
1962 // Next check to see if the target supports this SHL_PARTS operation or if it
1963 // will custom expand it.
1964 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1965 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1966 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1967 Action == TargetLowering::Custom) {
1968 // Expand the subcomponents.
1970 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1972 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1973 EVT VT = LHSL.getValueType();
1974 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1975 Hi = Lo.getValue(1);
1979 // Otherwise, emit a libcall.
1980 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1982 if (N->getOpcode() == ISD::SHL) {
1983 isSigned = false; /*sign irrelevant*/
1985 LC = RTLIB::SHL_I16;
1986 else if (VT == MVT::i32)
1987 LC = RTLIB::SHL_I32;
1988 else if (VT == MVT::i64)
1989 LC = RTLIB::SHL_I64;
1990 else if (VT == MVT::i128)
1991 LC = RTLIB::SHL_I128;
1992 } else if (N->getOpcode() == ISD::SRL) {
1995 LC = RTLIB::SRL_I16;
1996 else if (VT == MVT::i32)
1997 LC = RTLIB::SRL_I32;
1998 else if (VT == MVT::i64)
1999 LC = RTLIB::SRL_I64;
2000 else if (VT == MVT::i128)
2001 LC = RTLIB::SRL_I128;
2003 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2006 LC = RTLIB::SRA_I16;
2007 else if (VT == MVT::i32)
2008 LC = RTLIB::SRA_I32;
2009 else if (VT == MVT::i64)
2010 LC = RTLIB::SRA_I64;
2011 else if (VT == MVT::i128)
2012 LC = RTLIB::SRA_I128;
2015 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2016 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2017 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2021 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2022 llvm_unreachable("Unsupported shift!");
2025 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2026 SDValue &Lo, SDValue &Hi) {
2027 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2028 DebugLoc dl = N->getDebugLoc();
2029 SDValue Op = N->getOperand(0);
2030 if (Op.getValueType().bitsLE(NVT)) {
2031 // The low part is sign extension of the input (degenerates to a copy).
2032 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2033 // The high part is obtained by SRA'ing all but one of the bits of low part.
2034 unsigned LoSize = NVT.getSizeInBits();
2035 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2036 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2038 // For example, extension of an i48 to an i64. The operand type necessarily
2039 // promotes to the result type, so will end up being expanded too.
2040 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2041 "Only know how to promote this result!");
2042 SDValue Res = GetPromotedInteger(Op);
2043 assert(Res.getValueType() == N->getValueType(0) &&
2044 "Operand over promoted?");
2045 // Split the promoted operand. This will simplify when it is expanded.
2046 SplitInteger(Res, Lo, Hi);
2047 unsigned ExcessBits =
2048 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2049 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2050 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2055 void DAGTypeLegalizer::
2056 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2057 DebugLoc dl = N->getDebugLoc();
2058 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2059 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2061 if (EVT.bitsLE(Lo.getValueType())) {
2062 // sext_inreg the low part if needed.
2063 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2066 // The high part gets the sign extension from the lo-part. This handles
2067 // things like sextinreg V:i64 from i8.
2068 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2069 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2070 TLI.getPointerTy()));
2072 // For example, extension of an i48 to an i64. Leave the low part alone,
2073 // sext_inreg the high part.
2074 unsigned ExcessBits =
2075 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2076 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2077 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2082 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2083 SDValue &Lo, SDValue &Hi) {
2084 EVT VT = N->getValueType(0);
2085 DebugLoc dl = N->getDebugLoc();
2087 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2089 LC = RTLIB::SREM_I16;
2090 else if (VT == MVT::i32)
2091 LC = RTLIB::SREM_I32;
2092 else if (VT == MVT::i64)
2093 LC = RTLIB::SREM_I64;
2094 else if (VT == MVT::i128)
2095 LC = RTLIB::SREM_I128;
2096 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2098 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2099 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2102 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2103 SDValue &Lo, SDValue &Hi) {
2104 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2105 DebugLoc dl = N->getDebugLoc();
2106 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2107 Hi = DAG.getNode(ISD::SRL, dl,
2108 N->getOperand(0).getValueType(), N->getOperand(0),
2109 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2110 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2113 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2114 SDValue &Lo, SDValue &Hi) {
2115 SDValue LHS = N->getOperand(0);
2116 SDValue RHS = N->getOperand(1);
2117 DebugLoc dl = N->getDebugLoc();
2119 // Expand the result by simply replacing it with the equivalent
2120 // non-overflow-checking operation.
2121 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2122 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2124 SplitInteger(Sum, Lo, Hi);
2126 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2127 // overflows iff a - b > a.
2128 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2129 N->getOpcode () == ISD::UADDO ?
2130 ISD::SETULT : ISD::SETUGT);
2132 // Use the calculated overflow everywhere.
2133 ReplaceValueWith(SDValue(N, 1), Ofl);
2136 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2137 SDValue &Lo, SDValue &Hi) {
2138 EVT VT = N->getValueType(0);
2139 DebugLoc dl = N->getDebugLoc();
2141 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2143 LC = RTLIB::UDIV_I16;
2144 else if (VT == MVT::i32)
2145 LC = RTLIB::UDIV_I32;
2146 else if (VT == MVT::i64)
2147 LC = RTLIB::UDIV_I64;
2148 else if (VT == MVT::i128)
2149 LC = RTLIB::UDIV_I128;
2150 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2152 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2153 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2156 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2157 SDValue &Lo, SDValue &Hi) {
2158 EVT VT = N->getValueType(0);
2159 DebugLoc dl = N->getDebugLoc();
2161 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2163 LC = RTLIB::UREM_I16;
2164 else if (VT == MVT::i32)
2165 LC = RTLIB::UREM_I32;
2166 else if (VT == MVT::i64)
2167 LC = RTLIB::UREM_I64;
2168 else if (VT == MVT::i128)
2169 LC = RTLIB::UREM_I128;
2170 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2172 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2173 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2176 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2177 SDValue &Lo, SDValue &Hi) {
2178 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2179 DebugLoc dl = N->getDebugLoc();
2180 SDValue Op = N->getOperand(0);
2181 if (Op.getValueType().bitsLE(NVT)) {
2182 // The low part is zero extension of the input (degenerates to a copy).
2183 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2184 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2186 // For example, extension of an i48 to an i64. The operand type necessarily
2187 // promotes to the result type, so will end up being expanded too.
2188 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2189 "Only know how to promote this result!");
2190 SDValue Res = GetPromotedInteger(Op);
2191 assert(Res.getValueType() == N->getValueType(0) &&
2192 "Operand over promoted?");
2193 // Split the promoted operand. This will simplify when it is expanded.
2194 SplitInteger(Res, Lo, Hi);
2195 unsigned ExcessBits =
2196 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2197 Hi = DAG.getZeroExtendInReg(Hi, dl,
2198 EVT::getIntegerVT(*DAG.getContext(),
2204 //===----------------------------------------------------------------------===//
2205 // Integer Operand Expansion
2206 //===----------------------------------------------------------------------===//
2208 /// ExpandIntegerOperand - This method is called when the specified operand of
2209 /// the specified node is found to need expansion. At this point, all of the
2210 /// result types of the node are known to be legal, but other operands of the
2211 /// node may need promotion or expansion as well as the specified one.
2212 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2213 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2214 SDValue Res = SDValue();
2216 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2219 switch (N->getOpcode()) {
2222 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2223 N->dump(&DAG); dbgs() << "\n";
2225 llvm_unreachable("Do not know how to expand this operator's operand!");
2227 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2228 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2229 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2230 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2231 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2232 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2233 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2234 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2235 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2236 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2237 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2238 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2244 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2245 case ISD::RETURNADDR:
2246 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2249 // If the result is null, the sub-method took care of registering results etc.
2250 if (!Res.getNode()) return false;
2252 // If the result is N, the sub-method updated N in place. Tell the legalizer
2254 if (Res.getNode() == N)
2257 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2258 "Invalid operand expansion");
2260 ReplaceValueWith(SDValue(N, 0), Res);
2264 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2265 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2266 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2268 ISD::CondCode &CCCode,
2270 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2271 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2272 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2274 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2275 if (RHSLo == RHSHi) {
2276 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2277 if (RHSCST->isAllOnesValue()) {
2278 // Equality comparison to -1.
2279 NewLHS = DAG.getNode(ISD::AND, dl,
2280 LHSLo.getValueType(), LHSLo, LHSHi);
2287 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2288 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2289 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2290 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2294 // If this is a comparison of the sign bit, just look at the top part.
2296 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2297 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2298 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2304 // FIXME: This generated code sucks.
2305 ISD::CondCode LowCC;
2307 default: llvm_unreachable("Unknown integer setcc!");
2309 case ISD::SETULT: LowCC = ISD::SETULT; break;
2311 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2313 case ISD::SETULE: LowCC = ISD::SETULE; break;
2315 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2318 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2319 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2320 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2322 // NOTE: on targets without efficient SELECT of bools, we can always use
2323 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2324 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2326 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2327 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2328 if (!Tmp1.getNode())
2329 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2330 LHSLo, RHSLo, LowCC);
2331 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2332 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2333 if (!Tmp2.getNode())
2334 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2335 TLI.getSetCCResultType(LHSHi.getValueType()),
2336 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2338 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2339 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2340 if ((Tmp1C && Tmp1C->isNullValue()) ||
2341 (Tmp2C && Tmp2C->isNullValue() &&
2342 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2343 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2344 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2345 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2346 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2347 // low part is known false, returns high part.
2348 // For LE / GE, if high part is known false, ignore the low part.
2349 // For LT / GT, if high part is known true, ignore the low part.
2355 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2356 LHSHi, RHSHi, ISD::SETEQ, false,
2357 DagCombineInfo, dl);
2358 if (!NewLHS.getNode())
2359 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2360 LHSHi, RHSHi, ISD::SETEQ);
2361 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2362 NewLHS, Tmp1, Tmp2);
2366 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2367 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2368 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2369 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2371 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2372 // against zero to select between true and false values.
2373 if (NewRHS.getNode() == 0) {
2374 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2375 CCCode = ISD::SETNE;
2378 // Update N to have the operands specified.
2379 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2380 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2381 N->getOperand(4)), 0);
2384 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2385 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2386 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2387 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2389 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2390 // against zero to select between true and false values.
2391 if (NewRHS.getNode() == 0) {
2392 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2393 CCCode = ISD::SETNE;
2396 // Update N to have the operands specified.
2397 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2398 N->getOperand(2), N->getOperand(3),
2399 DAG.getCondCode(CCCode)), 0);
2402 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2403 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2404 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2405 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2407 // If ExpandSetCCOperands returned a scalar, use it.
2408 if (NewRHS.getNode() == 0) {
2409 assert(NewLHS.getValueType() == N->getValueType(0) &&
2410 "Unexpected setcc expansion!");
2414 // Otherwise, update N to have the operands specified.
2415 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2416 DAG.getCondCode(CCCode)), 0);
2419 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2420 // The value being shifted is legal, but the shift amount is too big.
2421 // It follows that either the result of the shift is undefined, or the
2422 // upper half of the shift amount is zero. Just use the lower half.
2424 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2425 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2428 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2429 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2430 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2431 // constant to valid type.
2433 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2434 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2437 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2438 SDValue Op = N->getOperand(0);
2439 EVT DstVT = N->getValueType(0);
2440 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2441 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2442 "Don't know how to expand this SINT_TO_FP!");
2443 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2446 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2447 if (ISD::isNormalStore(N))
2448 return ExpandOp_NormalStore(N, OpNo);
2450 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2451 assert(OpNo == 1 && "Can only expand the stored value so far");
2453 EVT VT = N->getOperand(1).getValueType();
2454 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2455 SDValue Ch = N->getChain();
2456 SDValue Ptr = N->getBasePtr();
2457 unsigned Alignment = N->getAlignment();
2458 bool isVolatile = N->isVolatile();
2459 bool isNonTemporal = N->isNonTemporal();
2460 DebugLoc dl = N->getDebugLoc();
2463 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2465 if (N->getMemoryVT().bitsLE(NVT)) {
2466 GetExpandedInteger(N->getValue(), Lo, Hi);
2467 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2468 N->getMemoryVT(), isVolatile, isNonTemporal,
2472 if (TLI.isLittleEndian()) {
2473 // Little-endian - low bits are at low addresses.
2474 GetExpandedInteger(N->getValue(), Lo, Hi);
2476 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2477 isVolatile, isNonTemporal, Alignment);
2479 unsigned ExcessBits =
2480 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2481 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2483 // Increment the pointer to the other half.
2484 unsigned IncrementSize = NVT.getSizeInBits()/8;
2485 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2486 DAG.getIntPtrConstant(IncrementSize));
2487 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2488 N->getPointerInfo().getWithOffset(IncrementSize),
2489 NEVT, isVolatile, isNonTemporal,
2490 MinAlign(Alignment, IncrementSize));
2491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2494 // Big-endian - high bits are at low addresses. Favor aligned stores at
2495 // the cost of some bit-fiddling.
2496 GetExpandedInteger(N->getValue(), Lo, Hi);
2498 EVT ExtVT = N->getMemoryVT();
2499 unsigned EBytes = ExtVT.getStoreSize();
2500 unsigned IncrementSize = NVT.getSizeInBits()/8;
2501 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2502 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2503 ExtVT.getSizeInBits() - ExcessBits);
2505 if (ExcessBits < NVT.getSizeInBits()) {
2506 // Transfer high bits from the top of Lo to the bottom of Hi.
2507 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2508 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2509 TLI.getPointerTy()));
2510 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2511 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2512 DAG.getConstant(ExcessBits,
2513 TLI.getPointerTy())));
2516 // Store both the high bits and maybe some of the low bits.
2517 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2518 HiVT, isVolatile, isNonTemporal, Alignment);
2520 // Increment the pointer to the other half.
2521 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2522 DAG.getIntPtrConstant(IncrementSize));
2523 // Store the lowest ExcessBits bits in the second half.
2524 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2525 N->getPointerInfo().getWithOffset(IncrementSize),
2526 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2527 isVolatile, isNonTemporal,
2528 MinAlign(Alignment, IncrementSize));
2529 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2532 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2534 GetExpandedInteger(N->getOperand(0), InL, InH);
2535 // Just truncate the low part of the source.
2536 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2539 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2540 switch (VT.getSimpleVT().SimpleTy) {
2541 default: llvm_unreachable("Unknown FP format");
2542 case MVT::f32: return &APFloat::IEEEsingle;
2543 case MVT::f64: return &APFloat::IEEEdouble;
2544 case MVT::f80: return &APFloat::x87DoubleExtended;
2545 case MVT::f128: return &APFloat::IEEEquad;
2546 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2550 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2551 SDValue Op = N->getOperand(0);
2552 EVT SrcVT = Op.getValueType();
2553 EVT DstVT = N->getValueType(0);
2554 DebugLoc dl = N->getDebugLoc();
2556 // The following optimization is valid only if every value in SrcVT (when
2557 // treated as signed) is representable in DstVT. Check that the mantissa
2558 // size of DstVT is >= than the number of bits in SrcVT -1.
2559 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2560 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2561 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2562 // Do a signed conversion then adjust the result.
2563 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2564 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2566 // The result of the signed conversion needs adjusting if the 'sign bit' of
2567 // the incoming integer was set. To handle this, we dynamically test to see
2568 // if it is set, and, if so, add a fudge factor.
2570 const uint64_t F32TwoE32 = 0x4F800000ULL;
2571 const uint64_t F32TwoE64 = 0x5F800000ULL;
2572 const uint64_t F32TwoE128 = 0x7F800000ULL;
2575 if (SrcVT == MVT::i32)
2576 FF = APInt(32, F32TwoE32);
2577 else if (SrcVT == MVT::i64)
2578 FF = APInt(32, F32TwoE64);
2579 else if (SrcVT == MVT::i128)
2580 FF = APInt(32, F32TwoE128);
2582 assert(false && "Unsupported UINT_TO_FP!");
2584 // Check whether the sign bit is set.
2586 GetExpandedInteger(Op, Lo, Hi);
2587 SDValue SignSet = DAG.getSetCC(dl,
2588 TLI.getSetCCResultType(Hi.getValueType()),
2589 Hi, DAG.getConstant(0, Hi.getValueType()),
2592 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2593 SDValue FudgePtr = DAG.getConstantPool(
2594 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2595 TLI.getPointerTy());
2597 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2598 SDValue Zero = DAG.getIntPtrConstant(0);
2599 SDValue Four = DAG.getIntPtrConstant(4);
2600 if (TLI.isBigEndian()) std::swap(Zero, Four);
2601 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2603 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2604 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2605 Alignment = std::min(Alignment, 4u);
2607 // Load the value out, extending it from f32 to the destination float type.
2608 // FIXME: Avoid the extend by constructing the right constant pool?
2609 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(),
2611 MachinePointerInfo::getConstantPool(),
2613 false, false, Alignment);
2614 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2617 // Otherwise, use a libcall.
2618 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2619 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2620 "Don't know how to expand this UINT_TO_FP!");
2621 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);