1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, PseudoSourceValue::getConstantPool(),
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
517 PseudoSourceValue::getConstantPool(), 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
575 MVT::ValueType intVT;
578 else if (VT==MVT::f32)
581 assert(0 && "Unaligned load of unsupported floating point type");
583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
585 SVOffset, ST->isVolatile(), Alignment);
587 assert(MVT::isInteger(ST->getMemoryVT()) &&
588 "Unaligned store of unknown type.");
589 // Get the half-size VT
590 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
591 int NumBits = MVT::getSizeInBits(NewStoredVT);
592 int IncrementSize = NumBits / 8;
594 // Divide the stored value in two parts.
595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
599 // Store the two parts
600 SDOperand Store1, Store2;
601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
602 ST->getSrcValue(), SVOffset, NewStoredVT,
603 ST->isVolatile(), Alignment);
604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
605 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
606 Alignment = MinAlign(Alignment, IncrementSize);
607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
608 ST->getSrcValue(), SVOffset + IncrementSize,
609 NewStoredVT, ST->isVolatile(), Alignment);
611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
614 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
616 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
617 TargetLowering &TLI) {
618 int SVOffset = LD->getSrcValueOffset();
619 SDOperand Chain = LD->getChain();
620 SDOperand Ptr = LD->getBasePtr();
621 MVT::ValueType VT = LD->getValueType(0);
622 MVT::ValueType LoadedVT = LD->getMemoryVT();
623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
624 // Expand to a (misaligned) integer load of the same size,
625 // then bitconvert to floating point.
626 MVT::ValueType intVT;
627 if (LoadedVT == MVT::f64)
629 else if (LoadedVT == MVT::f32)
632 assert(0 && "Unaligned load of unsupported floating point type");
634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, LD->isVolatile(),
637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
641 SDOperand Ops[] = { Result, Chain };
642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
646 "Unaligned load of unsupported type.");
648 // Compute the new VT that is half the size of the old one. We either have an
649 // integer MVT or we have a vector MVT.
650 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
651 MVT::ValueType NewLoadedVT;
652 if (!MVT::isVector(LoadedVT)) {
653 NewLoadedVT = MVT::getIntegerType(NumBits/2);
655 // FIXME: This is not right for <1 x anything> it is also not right for
656 // non-power-of-two vectors.
657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
658 MVT::getVectorNumElements(LoadedVT)/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
802 case ISD::MEMOPERAND:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1068 Result = Tmp1; // chain
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1075 SmallVector<SDOperand, 8> Ops;
1076 Ops.push_back(Tmp1);
1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1078 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1079 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1081 // Otherwise promote them.
1082 Ops.push_back(PromoteOp(Node->getOperand(1)));
1083 Ops.push_back(PromoteOp(Node->getOperand(2)));
1085 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Legal:
1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1106 case ISD::DEBUG_LOC:
1107 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1108 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1121 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1122 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1123 default: assert(0 && "This action is not supported yet!");
1124 case TargetLowering::Legal:
1125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1127 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case TargetLowering::Expand:
1131 Result = LegalizeOp(Node->getOperand(0));
1136 case ISD::MEMBARRIER: {
1137 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1138 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1139 default: assert(0 && "This action is not supported yet!");
1140 case TargetLowering::Legal: {
1142 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1143 for (int x = 1; x < 6; ++x)
1144 Ops[x] = PromoteOp(Node->getOperand(x));
1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1148 case TargetLowering::Expand:
1149 //There is no libgcc call for this op
1150 Result = Node->getOperand(0); // Noop
1156 case ISD::Constant: {
1157 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1159 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1161 // We know we don't need to expand constants here, constants only have one
1162 // value and we check that it is fine above.
1164 if (opAction == TargetLowering::Custom) {
1165 Tmp1 = TLI.LowerOperation(Result, DAG);
1171 case ISD::ConstantFP: {
1172 // Spill FP immediates to the constant pool if the target cannot directly
1173 // codegen them. Targets often have some immediate values that can be
1174 // efficiently generated into an FP register without a load. We explicitly
1175 // leave these constants as ConstantFP nodes for the target to deal with.
1176 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1178 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1179 default: assert(0 && "This action is not supported yet!");
1180 case TargetLowering::Legal:
1182 case TargetLowering::Custom:
1183 Tmp3 = TLI.LowerOperation(Result, DAG);
1189 case TargetLowering::Expand: {
1190 // Check to see if this FP immediate is already legal.
1191 bool isLegal = false;
1192 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1193 E = TLI.legal_fpimm_end(); I != E; ++I) {
1194 if (CFP->isExactlyValue(*I)) {
1199 // If this is a legal constant, turn it into a TargetConstantFP node.
1202 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1207 case ISD::TokenFactor:
1208 if (Node->getNumOperands() == 2) {
1209 Tmp1 = LegalizeOp(Node->getOperand(0));
1210 Tmp2 = LegalizeOp(Node->getOperand(1));
1211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1212 } else if (Node->getNumOperands() == 3) {
1213 Tmp1 = LegalizeOp(Node->getOperand(0));
1214 Tmp2 = LegalizeOp(Node->getOperand(1));
1215 Tmp3 = LegalizeOp(Node->getOperand(2));
1216 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1218 SmallVector<SDOperand, 8> Ops;
1219 // Legalize the operands.
1220 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1221 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1222 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1226 case ISD::FORMAL_ARGUMENTS:
1228 // The only option for this is to custom lower it.
1229 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1230 assert(Tmp3.Val && "Target didn't custom lower this node!");
1232 // The number of incoming and outgoing values should match; unless the final
1233 // outgoing value is a flag.
1234 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1235 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1236 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1238 "Lowering call/formal_arguments produced unexpected # results!");
1240 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1241 // remember that we legalized all of them, so it doesn't get relegalized.
1242 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1243 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1245 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1248 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1251 case ISD::EXTRACT_SUBREG: {
1252 Tmp1 = LegalizeOp(Node->getOperand(0));
1253 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1254 assert(idx && "Operand must be a constant");
1255 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1256 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1259 case ISD::INSERT_SUBREG: {
1260 Tmp1 = LegalizeOp(Node->getOperand(0));
1261 Tmp2 = LegalizeOp(Node->getOperand(1));
1262 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1263 assert(idx && "Operand must be a constant");
1264 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1265 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1268 case ISD::BUILD_VECTOR:
1269 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1270 default: assert(0 && "This action is not supported yet!");
1271 case TargetLowering::Custom:
1272 Tmp3 = TLI.LowerOperation(Result, DAG);
1278 case TargetLowering::Expand:
1279 Result = ExpandBUILD_VECTOR(Result.Val);
1283 case ISD::INSERT_VECTOR_ELT:
1284 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1285 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1287 // The type of the value to insert may not be legal, even though the vector
1288 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1290 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1291 default: assert(0 && "Cannot expand insert element operand");
1292 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1293 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1297 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1298 Node->getValueType(0))) {
1299 default: assert(0 && "This action is not supported yet!");
1300 case TargetLowering::Legal:
1302 case TargetLowering::Custom:
1303 Tmp4 = TLI.LowerOperation(Result, DAG);
1309 case TargetLowering::Expand: {
1310 // If the insert index is a constant, codegen this as a scalar_to_vector,
1311 // then a shuffle that inserts it into the right position in the vector.
1312 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1313 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1314 // match the element type of the vector being created.
1315 if (Tmp2.getValueType() ==
1316 MVT::getVectorElementType(Op.getValueType())) {
1317 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1318 Tmp1.getValueType(), Tmp2);
1320 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1321 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1322 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1324 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1325 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1326 // elt 0 of the RHS.
1327 SmallVector<SDOperand, 8> ShufOps;
1328 for (unsigned i = 0; i != NumElts; ++i) {
1329 if (i != InsertPos->getValue())
1330 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1332 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1334 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1335 &ShufOps[0], ShufOps.size());
1337 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1338 Tmp1, ScVec, ShufMask);
1339 Result = LegalizeOp(Result);
1344 // If the target doesn't support this, we have to spill the input vector
1345 // to a temporary stack slot, update the element, then reload it. This is
1346 // badness. We could also load the value into a vector register (either
1347 // with a "move to register" or "extload into register" instruction, then
1348 // permute it into place, if the idx is a constant and if the idx is
1349 // supported by the target.
1350 MVT::ValueType VT = Tmp1.getValueType();
1351 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1352 MVT::ValueType IdxVT = Tmp3.getValueType();
1353 MVT::ValueType PtrVT = TLI.getPointerTy();
1354 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1356 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1357 int SPFI = StackPtrFI->getIndex();
1359 // Store the vector.
1360 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1361 PseudoSourceValue::getFixedStack(),
1364 // Truncate or zero extend offset to target pointer type.
1365 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1366 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1367 // Add the offset to the index.
1368 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1369 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1370 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1371 // Store the scalar value.
1372 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1373 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1374 // Load the updated vector.
1375 Result = DAG.getLoad(VT, Ch, StackPtr,
1376 PseudoSourceValue::getFixedStack(), SPFI);
1381 case ISD::SCALAR_TO_VECTOR:
1382 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1383 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1387 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1388 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1389 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1390 Node->getValueType(0))) {
1391 default: assert(0 && "This action is not supported yet!");
1392 case TargetLowering::Legal:
1394 case TargetLowering::Custom:
1395 Tmp3 = TLI.LowerOperation(Result, DAG);
1401 case TargetLowering::Expand:
1402 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1406 case ISD::VECTOR_SHUFFLE:
1407 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1408 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1409 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1411 // Allow targets to custom lower the SHUFFLEs they support.
1412 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1413 default: assert(0 && "Unknown operation action!");
1414 case TargetLowering::Legal:
1415 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1416 "vector shuffle should not be created if not legal!");
1418 case TargetLowering::Custom:
1419 Tmp3 = TLI.LowerOperation(Result, DAG);
1425 case TargetLowering::Expand: {
1426 MVT::ValueType VT = Node->getValueType(0);
1427 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1428 MVT::ValueType PtrVT = TLI.getPointerTy();
1429 SDOperand Mask = Node->getOperand(2);
1430 unsigned NumElems = Mask.getNumOperands();
1431 SmallVector<SDOperand,8> Ops;
1432 for (unsigned i = 0; i != NumElems; ++i) {
1433 SDOperand Arg = Mask.getOperand(i);
1434 if (Arg.getOpcode() == ISD::UNDEF) {
1435 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1437 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1438 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1440 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1441 DAG.getConstant(Idx, PtrVT)));
1443 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1444 DAG.getConstant(Idx - NumElems, PtrVT)));
1447 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1450 case TargetLowering::Promote: {
1451 // Change base type to a different vector type.
1452 MVT::ValueType OVT = Node->getValueType(0);
1453 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1455 // Cast the two input vectors.
1456 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1457 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1459 // Convert the shuffle mask to the right # elements.
1460 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1461 assert(Tmp3.Val && "Shuffle not legal?");
1462 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1463 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1469 case ISD::EXTRACT_VECTOR_ELT:
1470 Tmp1 = Node->getOperand(0);
1471 Tmp2 = LegalizeOp(Node->getOperand(1));
1472 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1473 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1476 case ISD::EXTRACT_SUBVECTOR:
1477 Tmp1 = Node->getOperand(0);
1478 Tmp2 = LegalizeOp(Node->getOperand(1));
1479 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1480 Result = ExpandEXTRACT_SUBVECTOR(Result);
1483 case ISD::CALLSEQ_START: {
1484 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1486 // Recursively Legalize all of the inputs of the call end that do not lead
1487 // to this call start. This ensures that any libcalls that need be inserted
1488 // are inserted *before* the CALLSEQ_START.
1489 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1490 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1491 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1495 // Now that we legalized all of the inputs (which may have inserted
1496 // libcalls) create the new CALLSEQ_START node.
1497 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1499 // Merge in the last call, to ensure that this call start after the last
1501 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1502 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1503 Tmp1 = LegalizeOp(Tmp1);
1506 // Do not try to legalize the target-specific arguments (#1+).
1507 if (Tmp1 != Node->getOperand(0)) {
1508 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1510 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1513 // Remember that the CALLSEQ_START is legalized.
1514 AddLegalizedOperand(Op.getValue(0), Result);
1515 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1516 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1518 // Now that the callseq_start and all of the non-call nodes above this call
1519 // sequence have been legalized, legalize the call itself. During this
1520 // process, no libcalls can/will be inserted, guaranteeing that no calls
1522 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1523 SDOperand InCallSEQ = LastCALLSEQ_END;
1524 // Note that we are selecting this call!
1525 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1526 IsLegalizingCall = true;
1528 // Legalize the call, starting from the CALLSEQ_END.
1529 LegalizeOp(LastCALLSEQ_END);
1530 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1533 case ISD::CALLSEQ_END:
1534 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1535 // will cause this node to be legalized as well as handling libcalls right.
1536 if (LastCALLSEQ_END.Val != Node) {
1537 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1538 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1539 assert(I != LegalizedNodes.end() &&
1540 "Legalizing the call start should have legalized this node!");
1544 // Otherwise, the call start has been legalized and everything is going
1545 // according to plan. Just legalize ourselves normally here.
1546 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1547 // Do not try to legalize the target-specific arguments (#1+), except for
1548 // an optional flag input.
1549 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1550 if (Tmp1 != Node->getOperand(0)) {
1551 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1553 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1556 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1557 if (Tmp1 != Node->getOperand(0) ||
1558 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1559 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1562 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1565 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1566 // This finishes up call legalization.
1567 IsLegalizingCall = false;
1569 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1570 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1571 if (Node->getNumValues() == 2)
1572 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1573 return Result.getValue(Op.ResNo);
1574 case ISD::DYNAMIC_STACKALLOC: {
1575 MVT::ValueType VT = Node->getValueType(0);
1576 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1577 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1578 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1581 Tmp1 = Result.getValue(0);
1582 Tmp2 = Result.getValue(1);
1583 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1584 default: assert(0 && "This action is not supported yet!");
1585 case TargetLowering::Expand: {
1586 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1587 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1588 " not tell us which reg is the stack pointer!");
1589 SDOperand Chain = Tmp1.getOperand(0);
1591 // Chain the dynamic stack allocation so that it doesn't modify the stack
1592 // pointer when other instructions are using the stack.
1593 Chain = DAG.getCALLSEQ_START(Chain,
1594 DAG.getConstant(0, TLI.getPointerTy()));
1596 SDOperand Size = Tmp2.getOperand(1);
1597 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1598 Chain = SP.getValue(1);
1599 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1600 unsigned StackAlign =
1601 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1602 if (Align > StackAlign)
1603 SP = DAG.getNode(ISD::AND, VT, SP,
1604 DAG.getConstant(-(uint64_t)Align, VT));
1605 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1606 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1609 DAG.getCALLSEQ_END(Chain,
1610 DAG.getConstant(0, TLI.getPointerTy()),
1611 DAG.getConstant(0, TLI.getPointerTy()),
1614 Tmp1 = LegalizeOp(Tmp1);
1615 Tmp2 = LegalizeOp(Tmp2);
1618 case TargetLowering::Custom:
1619 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1621 Tmp1 = LegalizeOp(Tmp3);
1622 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1625 case TargetLowering::Legal:
1628 // Since this op produce two values, make sure to remember that we
1629 // legalized both of them.
1630 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1631 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1632 return Op.ResNo ? Tmp2 : Tmp1;
1634 case ISD::INLINEASM: {
1635 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1636 bool Changed = false;
1637 // Legalize all of the operands of the inline asm, in case they are nodes
1638 // that need to be expanded or something. Note we skip the asm string and
1639 // all of the TargetConstant flags.
1640 SDOperand Op = LegalizeOp(Ops[0]);
1641 Changed = Op != Ops[0];
1644 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1645 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1646 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1647 for (++i; NumVals; ++i, --NumVals) {
1648 SDOperand Op = LegalizeOp(Ops[i]);
1657 Op = LegalizeOp(Ops.back());
1658 Changed |= Op != Ops.back();
1663 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1665 // INLINE asm returns a chain and flag, make sure to add both to the map.
1666 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1667 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1668 return Result.getValue(Op.ResNo);
1671 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1672 // Ensure that libcalls are emitted before a branch.
1673 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1674 Tmp1 = LegalizeOp(Tmp1);
1675 LastCALLSEQ_END = DAG.getEntryNode();
1677 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1680 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1681 // Ensure that libcalls are emitted before a branch.
1682 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1683 Tmp1 = LegalizeOp(Tmp1);
1684 LastCALLSEQ_END = DAG.getEntryNode();
1686 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1687 default: assert(0 && "Indirect target must be legal type (pointer)!");
1689 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1695 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1696 // Ensure that libcalls are emitted before a branch.
1697 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1698 Tmp1 = LegalizeOp(Tmp1);
1699 LastCALLSEQ_END = DAG.getEntryNode();
1701 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1702 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1704 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1705 default: assert(0 && "This action is not supported yet!");
1706 case TargetLowering::Legal: break;
1707 case TargetLowering::Custom:
1708 Tmp1 = TLI.LowerOperation(Result, DAG);
1709 if (Tmp1.Val) Result = Tmp1;
1711 case TargetLowering::Expand: {
1712 SDOperand Chain = Result.getOperand(0);
1713 SDOperand Table = Result.getOperand(1);
1714 SDOperand Index = Result.getOperand(2);
1716 MVT::ValueType PTy = TLI.getPointerTy();
1717 MachineFunction &MF = DAG.getMachineFunction();
1718 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1719 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1720 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1723 switch (EntrySize) {
1724 default: assert(0 && "Size of jump table not supported yet."); break;
1725 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1726 PseudoSourceValue::getJumpTable(), 0); break;
1727 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1728 PseudoSourceValue::getJumpTable(), 0); break;
1732 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1733 // For PIC, the sequence is:
1734 // BRIND(load(Jumptable + index) + RelocBase)
1735 // RelocBase can be JumpTable, GOT or some sort of global base.
1736 if (PTy != MVT::i32)
1737 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1738 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1739 TLI.getPICJumpTableRelocBase(Table, DAG));
1741 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1746 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1747 // Ensure that libcalls are emitted before a return.
1748 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1749 Tmp1 = LegalizeOp(Tmp1);
1750 LastCALLSEQ_END = DAG.getEntryNode();
1752 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1753 case Expand: assert(0 && "It's impossible to expand bools");
1755 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1758 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1760 // The top bits of the promoted condition are not necessarily zero, ensure
1761 // that the value is properly zero extended.
1762 if (!DAG.MaskedValueIsZero(Tmp2,
1763 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1764 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1768 // Basic block destination (Op#2) is always legal.
1769 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1771 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1772 default: assert(0 && "This action is not supported yet!");
1773 case TargetLowering::Legal: break;
1774 case TargetLowering::Custom:
1775 Tmp1 = TLI.LowerOperation(Result, DAG);
1776 if (Tmp1.Val) Result = Tmp1;
1778 case TargetLowering::Expand:
1779 // Expand brcond's setcc into its constituent parts and create a BR_CC
1781 if (Tmp2.getOpcode() == ISD::SETCC) {
1782 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1783 Tmp2.getOperand(0), Tmp2.getOperand(1),
1784 Node->getOperand(2));
1786 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1787 DAG.getCondCode(ISD::SETNE), Tmp2,
1788 DAG.getConstant(0, Tmp2.getValueType()),
1789 Node->getOperand(2));
1795 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1796 // Ensure that libcalls are emitted before a branch.
1797 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1798 Tmp1 = LegalizeOp(Tmp1);
1799 Tmp2 = Node->getOperand(2); // LHS
1800 Tmp3 = Node->getOperand(3); // RHS
1801 Tmp4 = Node->getOperand(1); // CC
1803 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1804 LastCALLSEQ_END = DAG.getEntryNode();
1806 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1807 // the LHS is a legal SETCC itself. In this case, we need to compare
1808 // the result against zero to select between true and false values.
1809 if (Tmp3.Val == 0) {
1810 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1811 Tmp4 = DAG.getCondCode(ISD::SETNE);
1814 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1815 Node->getOperand(4));
1817 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1818 default: assert(0 && "Unexpected action for BR_CC!");
1819 case TargetLowering::Legal: break;
1820 case TargetLowering::Custom:
1821 Tmp4 = TLI.LowerOperation(Result, DAG);
1822 if (Tmp4.Val) Result = Tmp4;
1827 LoadSDNode *LD = cast<LoadSDNode>(Node);
1828 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1829 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1831 ISD::LoadExtType ExtType = LD->getExtensionType();
1832 if (ExtType == ISD::NON_EXTLOAD) {
1833 MVT::ValueType VT = Node->getValueType(0);
1834 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1835 Tmp3 = Result.getValue(0);
1836 Tmp4 = Result.getValue(1);
1838 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1839 default: assert(0 && "This action is not supported yet!");
1840 case TargetLowering::Legal:
1841 // If this is an unaligned load and the target doesn't support it,
1843 if (!TLI.allowsUnalignedMemoryAccesses()) {
1844 unsigned ABIAlignment = TLI.getTargetData()->
1845 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1846 if (LD->getAlignment() < ABIAlignment){
1847 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1849 Tmp3 = Result.getOperand(0);
1850 Tmp4 = Result.getOperand(1);
1851 Tmp3 = LegalizeOp(Tmp3);
1852 Tmp4 = LegalizeOp(Tmp4);
1856 case TargetLowering::Custom:
1857 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1859 Tmp3 = LegalizeOp(Tmp1);
1860 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1863 case TargetLowering::Promote: {
1864 // Only promote a load of vector type to another.
1865 assert(MVT::isVector(VT) && "Cannot promote this load!");
1866 // Change base type to a different vector type.
1867 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1869 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1870 LD->getSrcValueOffset(),
1871 LD->isVolatile(), LD->getAlignment());
1872 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1873 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1877 // Since loads produce two values, make sure to remember that we
1878 // legalized both of them.
1879 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1880 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1881 return Op.ResNo ? Tmp4 : Tmp3;
1883 MVT::ValueType SrcVT = LD->getMemoryVT();
1884 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1885 int SVOffset = LD->getSrcValueOffset();
1886 unsigned Alignment = LD->getAlignment();
1887 bool isVolatile = LD->isVolatile();
1889 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1890 // Some targets pretend to have an i1 loading operation, and actually
1891 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1892 // bits are guaranteed to be zero; it helps the optimizers understand
1893 // that these bits are zero. It is also useful for EXTLOAD, since it
1894 // tells the optimizers that those bits are undefined. It would be
1895 // nice to have an effective generic way of getting these benefits...
1896 // Until such a way is found, don't insist on promoting i1 here.
1897 (SrcVT != MVT::i1 ||
1898 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1899 // Promote to a byte-sized load if not loading an integral number of
1900 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1901 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1902 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1905 // The extra bits are guaranteed to be zero, since we stored them that
1906 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1908 ISD::LoadExtType NewExtType =
1909 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1911 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1912 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1913 NVT, isVolatile, Alignment);
1915 Ch = Result.getValue(1); // The chain.
1917 if (ExtType == ISD::SEXTLOAD)
1918 // Having the top bits zero doesn't help when sign extending.
1919 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1920 Result, DAG.getValueType(SrcVT));
1921 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1922 // All the top bits are guaranteed to be zero - inform the optimizers.
1923 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1924 DAG.getValueType(SrcVT));
1926 Tmp1 = LegalizeOp(Result);
1927 Tmp2 = LegalizeOp(Ch);
1928 } else if (SrcWidth & (SrcWidth - 1)) {
1929 // If not loading a power-of-2 number of bits, expand as two loads.
1930 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1931 "Unsupported extload!");
1932 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1933 assert(RoundWidth < SrcWidth);
1934 unsigned ExtraWidth = SrcWidth - RoundWidth;
1935 assert(ExtraWidth < RoundWidth);
1936 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1937 "Load size not an integral number of bytes!");
1938 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1939 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1940 SDOperand Lo, Hi, Ch;
1941 unsigned IncrementSize;
1943 if (TLI.isLittleEndian()) {
1944 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1945 // Load the bottom RoundWidth bits.
1946 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1947 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1950 // Load the remaining ExtraWidth bits.
1951 IncrementSize = RoundWidth / 8;
1952 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1953 DAG.getIntPtrConstant(IncrementSize));
1954 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1955 LD->getSrcValue(), SVOffset + IncrementSize,
1956 ExtraVT, isVolatile,
1957 MinAlign(Alignment, IncrementSize));
1959 // Build a factor node to remember that this load is independent of the
1961 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1964 // Move the top bits to the right place.
1965 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1966 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1968 // Join the hi and lo parts.
1969 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1971 // Big endian - avoid unaligned loads.
1972 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1973 // Load the top RoundWidth bits.
1974 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1975 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1978 // Load the remaining ExtraWidth bits.
1979 IncrementSize = RoundWidth / 8;
1980 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1981 DAG.getIntPtrConstant(IncrementSize));
1982 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1983 LD->getSrcValue(), SVOffset + IncrementSize,
1984 ExtraVT, isVolatile,
1985 MinAlign(Alignment, IncrementSize));
1987 // Build a factor node to remember that this load is independent of the
1989 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1992 // Move the top bits to the right place.
1993 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1994 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1996 // Join the hi and lo parts.
1997 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2000 Tmp1 = LegalizeOp(Result);
2001 Tmp2 = LegalizeOp(Ch);
2003 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2004 default: assert(0 && "This action is not supported yet!");
2005 case TargetLowering::Custom:
2008 case TargetLowering::Legal:
2009 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2010 Tmp1 = Result.getValue(0);
2011 Tmp2 = Result.getValue(1);
2014 Tmp3 = TLI.LowerOperation(Result, DAG);
2016 Tmp1 = LegalizeOp(Tmp3);
2017 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2020 // If this is an unaligned load and the target doesn't support it,
2022 if (!TLI.allowsUnalignedMemoryAccesses()) {
2023 unsigned ABIAlignment = TLI.getTargetData()->
2024 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2025 if (LD->getAlignment() < ABIAlignment){
2026 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2028 Tmp1 = Result.getOperand(0);
2029 Tmp2 = Result.getOperand(1);
2030 Tmp1 = LegalizeOp(Tmp1);
2031 Tmp2 = LegalizeOp(Tmp2);
2036 case TargetLowering::Expand:
2037 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2038 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2039 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2040 LD->getSrcValueOffset(),
2041 LD->isVolatile(), LD->getAlignment());
2042 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2043 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2044 Tmp2 = LegalizeOp(Load.getValue(1));
2047 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2048 // Turn the unsupported load into an EXTLOAD followed by an explicit
2049 // zero/sign extend inreg.
2050 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2051 Tmp1, Tmp2, LD->getSrcValue(),
2052 LD->getSrcValueOffset(), SrcVT,
2053 LD->isVolatile(), LD->getAlignment());
2055 if (ExtType == ISD::SEXTLOAD)
2056 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2057 Result, DAG.getValueType(SrcVT));
2059 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2060 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2061 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2066 // Since loads produce two values, make sure to remember that we legalized
2068 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2069 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2070 return Op.ResNo ? Tmp2 : Tmp1;
2073 case ISD::EXTRACT_ELEMENT: {
2074 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2075 switch (getTypeAction(OpTy)) {
2076 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2078 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2080 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2081 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2082 TLI.getShiftAmountTy()));
2083 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2086 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2087 Node->getOperand(0));
2091 // Get both the low and high parts.
2092 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2093 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2094 Result = Tmp2; // 1 -> Hi
2096 Result = Tmp1; // 0 -> Lo
2102 case ISD::CopyToReg:
2103 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2105 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2106 "Register type must be legal!");
2107 // Legalize the incoming value (must be a legal type).
2108 Tmp2 = LegalizeOp(Node->getOperand(2));
2109 if (Node->getNumValues() == 1) {
2110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2112 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2113 if (Node->getNumOperands() == 4) {
2114 Tmp3 = LegalizeOp(Node->getOperand(3));
2115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2118 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2121 // Since this produces two values, make sure to remember that we legalized
2123 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2124 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2130 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2132 // Ensure that libcalls are emitted before a return.
2133 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2134 Tmp1 = LegalizeOp(Tmp1);
2135 LastCALLSEQ_END = DAG.getEntryNode();
2137 switch (Node->getNumOperands()) {
2139 Tmp2 = Node->getOperand(1);
2140 Tmp3 = Node->getOperand(2); // Signness
2141 switch (getTypeAction(Tmp2.getValueType())) {
2143 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2146 if (!MVT::isVector(Tmp2.getValueType())) {
2148 ExpandOp(Tmp2, Lo, Hi);
2150 // Big endian systems want the hi reg first.
2151 if (TLI.isBigEndian())
2155 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2157 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2158 Result = LegalizeOp(Result);
2160 SDNode *InVal = Tmp2.Val;
2161 int InIx = Tmp2.ResNo;
2162 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2163 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2165 // Figure out if there is a simple type corresponding to this Vector
2166 // type. If so, convert to the vector type.
2167 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2168 if (TLI.isTypeLegal(TVT)) {
2169 // Turn this into a return of the vector type.
2170 Tmp2 = LegalizeOp(Tmp2);
2171 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2172 } else if (NumElems == 1) {
2173 // Turn this into a return of the scalar type.
2174 Tmp2 = ScalarizeVectorOp(Tmp2);
2175 Tmp2 = LegalizeOp(Tmp2);
2176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2178 // FIXME: Returns of gcc generic vectors smaller than a legal type
2179 // should be returned in integer registers!
2181 // The scalarized value type may not be legal, e.g. it might require
2182 // promotion or expansion. Relegalize the return.
2183 Result = LegalizeOp(Result);
2185 // FIXME: Returns of gcc generic vectors larger than a legal vector
2186 // type should be returned by reference!
2188 SplitVectorOp(Tmp2, Lo, Hi);
2189 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2190 Result = LegalizeOp(Result);
2195 Tmp2 = PromoteOp(Node->getOperand(1));
2196 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2197 Result = LegalizeOp(Result);
2202 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2204 default: { // ret <values>
2205 SmallVector<SDOperand, 8> NewValues;
2206 NewValues.push_back(Tmp1);
2207 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2208 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2210 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2211 NewValues.push_back(Node->getOperand(i+1));
2215 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2216 "FIXME: TODO: implement returning non-legal vector types!");
2217 ExpandOp(Node->getOperand(i), Lo, Hi);
2218 NewValues.push_back(Lo);
2219 NewValues.push_back(Node->getOperand(i+1));
2221 NewValues.push_back(Hi);
2222 NewValues.push_back(Node->getOperand(i+1));
2227 assert(0 && "Can't promote multiple return value yet!");
2230 if (NewValues.size() == Node->getNumOperands())
2231 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2233 Result = DAG.getNode(ISD::RET, MVT::Other,
2234 &NewValues[0], NewValues.size());
2239 if (Result.getOpcode() == ISD::RET) {
2240 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2241 default: assert(0 && "This action is not supported yet!");
2242 case TargetLowering::Legal: break;
2243 case TargetLowering::Custom:
2244 Tmp1 = TLI.LowerOperation(Result, DAG);
2245 if (Tmp1.Val) Result = Tmp1;
2251 StoreSDNode *ST = cast<StoreSDNode>(Node);
2252 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2253 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2254 int SVOffset = ST->getSrcValueOffset();
2255 unsigned Alignment = ST->getAlignment();
2256 bool isVolatile = ST->isVolatile();
2258 if (!ST->isTruncatingStore()) {
2259 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2260 // FIXME: We shouldn't do this for TargetConstantFP's.
2261 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2262 // to phase ordering between legalized code and the dag combiner. This
2263 // probably means that we need to integrate dag combiner and legalizer
2265 // We generally can't do this one for long doubles.
2266 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2267 if (CFP->getValueType(0) == MVT::f32 &&
2268 getTypeAction(MVT::i32) == Legal) {
2269 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2270 convertToAPInt().getZExtValue(),
2272 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2273 SVOffset, isVolatile, Alignment);
2275 } else if (CFP->getValueType(0) == MVT::f64) {
2276 // If this target supports 64-bit registers, do a single 64-bit store.
2277 if (getTypeAction(MVT::i64) == Legal) {
2278 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2279 getZExtValue(), MVT::i64);
2280 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2281 SVOffset, isVolatile, Alignment);
2283 } else if (getTypeAction(MVT::i32) == Legal) {
2284 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2285 // stores. If the target supports neither 32- nor 64-bits, this
2286 // xform is certainly not worth it.
2287 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2288 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2289 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2290 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2292 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2293 SVOffset, isVolatile, Alignment);
2294 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2295 DAG.getIntPtrConstant(4));
2296 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2297 isVolatile, MinAlign(Alignment, 4U));
2299 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2305 switch (getTypeAction(ST->getMemoryVT())) {
2307 Tmp3 = LegalizeOp(ST->getValue());
2308 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2311 MVT::ValueType VT = Tmp3.getValueType();
2312 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2313 default: assert(0 && "This action is not supported yet!");
2314 case TargetLowering::Legal:
2315 // If this is an unaligned store and the target doesn't support it,
2317 if (!TLI.allowsUnalignedMemoryAccesses()) {
2318 unsigned ABIAlignment = TLI.getTargetData()->
2319 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2320 if (ST->getAlignment() < ABIAlignment)
2321 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2325 case TargetLowering::Custom:
2326 Tmp1 = TLI.LowerOperation(Result, DAG);
2327 if (Tmp1.Val) Result = Tmp1;
2329 case TargetLowering::Promote:
2330 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2331 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2332 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2333 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2334 ST->getSrcValue(), SVOffset, isVolatile,
2341 // Truncate the value and store the result.
2342 Tmp3 = PromoteOp(ST->getValue());
2343 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2344 SVOffset, ST->getMemoryVT(),
2345 isVolatile, Alignment);
2349 unsigned IncrementSize = 0;
2352 // If this is a vector type, then we have to calculate the increment as
2353 // the product of the element size in bytes, and the number of elements
2354 // in the high half of the vector.
2355 if (MVT::isVector(ST->getValue().getValueType())) {
2356 SDNode *InVal = ST->getValue().Val;
2357 int InIx = ST->getValue().ResNo;
2358 MVT::ValueType InVT = InVal->getValueType(InIx);
2359 unsigned NumElems = MVT::getVectorNumElements(InVT);
2360 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2362 // Figure out if there is a simple type corresponding to this Vector
2363 // type. If so, convert to the vector type.
2364 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2365 if (TLI.isTypeLegal(TVT)) {
2366 // Turn this into a normal store of the vector type.
2367 Tmp3 = LegalizeOp(ST->getValue());
2368 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2369 SVOffset, isVolatile, Alignment);
2370 Result = LegalizeOp(Result);
2372 } else if (NumElems == 1) {
2373 // Turn this into a normal store of the scalar type.
2374 Tmp3 = ScalarizeVectorOp(ST->getValue());
2375 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2376 SVOffset, isVolatile, Alignment);
2377 // The scalarized value type may not be legal, e.g. it might require
2378 // promotion or expansion. Relegalize the scalar store.
2379 Result = LegalizeOp(Result);
2382 SplitVectorOp(ST->getValue(), Lo, Hi);
2383 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2384 MVT::getSizeInBits(EVT)/8;
2387 ExpandOp(ST->getValue(), Lo, Hi);
2388 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2390 if (TLI.isBigEndian())
2394 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2395 SVOffset, isVolatile, Alignment);
2397 if (Hi.Val == NULL) {
2398 // Must be int <-> float one-to-one expansion.
2403 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2404 DAG.getIntPtrConstant(IncrementSize));
2405 assert(isTypeLegal(Tmp2.getValueType()) &&
2406 "Pointers must be legal!");
2407 SVOffset += IncrementSize;
2408 Alignment = MinAlign(Alignment, IncrementSize);
2409 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2410 SVOffset, isVolatile, Alignment);
2411 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2415 switch (getTypeAction(ST->getValue().getValueType())) {
2417 Tmp3 = LegalizeOp(ST->getValue());
2420 // We can promote the value, the truncstore will still take care of it.
2421 Tmp3 = PromoteOp(ST->getValue());
2424 // Just store the low part. This may become a non-trunc store, so make
2425 // sure to use getTruncStore, not UpdateNodeOperands below.
2426 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2427 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2428 SVOffset, MVT::i8, isVolatile, Alignment);
2431 MVT::ValueType StVT = ST->getMemoryVT();
2432 unsigned StWidth = MVT::getSizeInBits(StVT);
2434 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2435 // Promote to a byte-sized store with upper bits zero if not
2436 // storing an integral number of bytes. For example, promote
2437 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2438 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2439 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2440 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2441 SVOffset, NVT, isVolatile, Alignment);
2442 } else if (StWidth & (StWidth - 1)) {
2443 // If not storing a power-of-2 number of bits, expand as two stores.
2444 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2445 "Unsupported truncstore!");
2446 unsigned RoundWidth = 1 << Log2_32(StWidth);
2447 assert(RoundWidth < StWidth);
2448 unsigned ExtraWidth = StWidth - RoundWidth;
2449 assert(ExtraWidth < RoundWidth);
2450 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2451 "Store size not an integral number of bytes!");
2452 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2453 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2455 unsigned IncrementSize;
2457 if (TLI.isLittleEndian()) {
2458 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2459 // Store the bottom RoundWidth bits.
2460 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2462 isVolatile, Alignment);
2464 // Store the remaining ExtraWidth bits.
2465 IncrementSize = RoundWidth / 8;
2466 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2467 DAG.getIntPtrConstant(IncrementSize));
2468 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2469 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2470 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2471 SVOffset + IncrementSize, ExtraVT, isVolatile,
2472 MinAlign(Alignment, IncrementSize));
2474 // Big endian - avoid unaligned stores.
2475 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2476 // Store the top RoundWidth bits.
2477 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2478 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2479 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2480 RoundVT, isVolatile, Alignment);
2482 // Store the remaining ExtraWidth bits.
2483 IncrementSize = RoundWidth / 8;
2484 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2485 DAG.getIntPtrConstant(IncrementSize));
2486 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2487 SVOffset + IncrementSize, ExtraVT, isVolatile,
2488 MinAlign(Alignment, IncrementSize));
2491 // The order of the stores doesn't matter.
2492 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2494 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2495 Tmp2 != ST->getBasePtr())
2496 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2499 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2500 default: assert(0 && "This action is not supported yet!");
2501 case TargetLowering::Legal:
2502 // If this is an unaligned store and the target doesn't support it,
2504 if (!TLI.allowsUnalignedMemoryAccesses()) {
2505 unsigned ABIAlignment = TLI.getTargetData()->
2506 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2507 if (ST->getAlignment() < ABIAlignment)
2508 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2512 case TargetLowering::Custom:
2513 Result = TLI.LowerOperation(Result, DAG);
2516 // TRUNCSTORE:i16 i32 -> STORE i16
2517 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2518 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2519 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2520 isVolatile, Alignment);
2528 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2531 case ISD::STACKSAVE:
2532 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2533 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2534 Tmp1 = Result.getValue(0);
2535 Tmp2 = Result.getValue(1);
2537 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2538 default: assert(0 && "This action is not supported yet!");
2539 case TargetLowering::Legal: break;
2540 case TargetLowering::Custom:
2541 Tmp3 = TLI.LowerOperation(Result, DAG);
2543 Tmp1 = LegalizeOp(Tmp3);
2544 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2547 case TargetLowering::Expand:
2548 // Expand to CopyFromReg if the target set
2549 // StackPointerRegisterToSaveRestore.
2550 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2551 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2552 Node->getValueType(0));
2553 Tmp2 = Tmp1.getValue(1);
2555 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2556 Tmp2 = Node->getOperand(0);
2561 // Since stacksave produce two values, make sure to remember that we
2562 // legalized both of them.
2563 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2564 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2565 return Op.ResNo ? Tmp2 : Tmp1;
2567 case ISD::STACKRESTORE:
2568 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2569 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2570 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2572 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2573 default: assert(0 && "This action is not supported yet!");
2574 case TargetLowering::Legal: break;
2575 case TargetLowering::Custom:
2576 Tmp1 = TLI.LowerOperation(Result, DAG);
2577 if (Tmp1.Val) Result = Tmp1;
2579 case TargetLowering::Expand:
2580 // Expand to CopyToReg if the target set
2581 // StackPointerRegisterToSaveRestore.
2582 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2583 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2591 case ISD::READCYCLECOUNTER:
2592 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2593 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2594 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2595 Node->getValueType(0))) {
2596 default: assert(0 && "This action is not supported yet!");
2597 case TargetLowering::Legal:
2598 Tmp1 = Result.getValue(0);
2599 Tmp2 = Result.getValue(1);
2601 case TargetLowering::Custom:
2602 Result = TLI.LowerOperation(Result, DAG);
2603 Tmp1 = LegalizeOp(Result.getValue(0));
2604 Tmp2 = LegalizeOp(Result.getValue(1));
2608 // Since rdcc produce two values, make sure to remember that we legalized
2610 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2611 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2615 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2616 case Expand: assert(0 && "It's impossible to expand bools");
2618 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2621 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2622 // Make sure the condition is either zero or one.
2623 if (!DAG.MaskedValueIsZero(Tmp1,
2624 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2625 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2628 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2629 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2631 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2633 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2634 default: assert(0 && "This action is not supported yet!");
2635 case TargetLowering::Legal: break;
2636 case TargetLowering::Custom: {
2637 Tmp1 = TLI.LowerOperation(Result, DAG);
2638 if (Tmp1.Val) Result = Tmp1;
2641 case TargetLowering::Expand:
2642 if (Tmp1.getOpcode() == ISD::SETCC) {
2643 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2645 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2647 Result = DAG.getSelectCC(Tmp1,
2648 DAG.getConstant(0, Tmp1.getValueType()),
2649 Tmp2, Tmp3, ISD::SETNE);
2652 case TargetLowering::Promote: {
2653 MVT::ValueType NVT =
2654 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2655 unsigned ExtOp, TruncOp;
2656 if (MVT::isVector(Tmp2.getValueType())) {
2657 ExtOp = ISD::BIT_CONVERT;
2658 TruncOp = ISD::BIT_CONVERT;
2659 } else if (MVT::isInteger(Tmp2.getValueType())) {
2660 ExtOp = ISD::ANY_EXTEND;
2661 TruncOp = ISD::TRUNCATE;
2663 ExtOp = ISD::FP_EXTEND;
2664 TruncOp = ISD::FP_ROUND;
2666 // Promote each of the values to the new type.
2667 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2668 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2669 // Perform the larger operation, then round down.
2670 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2671 if (TruncOp != ISD::FP_ROUND)
2672 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2674 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2675 DAG.getIntPtrConstant(0));
2680 case ISD::SELECT_CC: {
2681 Tmp1 = Node->getOperand(0); // LHS
2682 Tmp2 = Node->getOperand(1); // RHS
2683 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2684 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2685 SDOperand CC = Node->getOperand(4);
2687 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2689 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2690 // the LHS is a legal SETCC itself. In this case, we need to compare
2691 // the result against zero to select between true and false values.
2692 if (Tmp2.Val == 0) {
2693 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2694 CC = DAG.getCondCode(ISD::SETNE);
2696 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2698 // Everything is legal, see if we should expand this op or something.
2699 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2700 default: assert(0 && "This action is not supported yet!");
2701 case TargetLowering::Legal: break;
2702 case TargetLowering::Custom:
2703 Tmp1 = TLI.LowerOperation(Result, DAG);
2704 if (Tmp1.Val) Result = Tmp1;
2710 Tmp1 = Node->getOperand(0);
2711 Tmp2 = Node->getOperand(1);
2712 Tmp3 = Node->getOperand(2);
2713 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2715 // If we had to Expand the SetCC operands into a SELECT node, then it may
2716 // not always be possible to return a true LHS & RHS. In this case, just
2717 // return the value we legalized, returned in the LHS
2718 if (Tmp2.Val == 0) {
2723 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2724 default: assert(0 && "Cannot handle this action for SETCC yet!");
2725 case TargetLowering::Custom:
2728 case TargetLowering::Legal:
2729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2731 Tmp4 = TLI.LowerOperation(Result, DAG);
2732 if (Tmp4.Val) Result = Tmp4;
2735 case TargetLowering::Promote: {
2736 // First step, figure out the appropriate operation to use.
2737 // Allow SETCC to not be supported for all legal data types
2738 // Mostly this targets FP
2739 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2740 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2742 // Scan for the appropriate larger type to use.
2744 NewInTy = (MVT::ValueType)(NewInTy+1);
2746 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2747 "Fell off of the edge of the integer world");
2748 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2749 "Fell off of the edge of the floating point world");
2751 // If the target supports SETCC of this type, use it.
2752 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2755 if (MVT::isInteger(NewInTy))
2756 assert(0 && "Cannot promote Legal Integer SETCC yet");
2758 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2759 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2761 Tmp1 = LegalizeOp(Tmp1);
2762 Tmp2 = LegalizeOp(Tmp2);
2763 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2764 Result = LegalizeOp(Result);
2767 case TargetLowering::Expand:
2768 // Expand a setcc node into a select_cc of the same condition, lhs, and
2769 // rhs that selects between const 1 (true) and const 0 (false).
2770 MVT::ValueType VT = Node->getValueType(0);
2771 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2772 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2779 case ISD::MEMMOVE: {
2780 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2781 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2783 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2784 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2785 case Expand: assert(0 && "Cannot expand a byte!");
2787 Tmp3 = LegalizeOp(Node->getOperand(2));
2790 Tmp3 = PromoteOp(Node->getOperand(2));
2794 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2798 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2800 // Length is too big, just take the lo-part of the length.
2802 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2806 Tmp4 = LegalizeOp(Node->getOperand(3));
2809 Tmp4 = PromoteOp(Node->getOperand(3));
2814 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2815 case Expand: assert(0 && "Cannot expand this yet!");
2817 Tmp5 = LegalizeOp(Node->getOperand(4));
2820 Tmp5 = PromoteOp(Node->getOperand(4));
2825 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2826 case Expand: assert(0 && "Cannot expand this yet!");
2828 Tmp6 = LegalizeOp(Node->getOperand(5));
2831 Tmp6 = PromoteOp(Node->getOperand(5));
2835 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2836 default: assert(0 && "This action not implemented for this operation!");
2837 case TargetLowering::Custom:
2840 case TargetLowering::Legal: {
2841 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2842 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2844 Tmp1 = TLI.LowerOperation(Result, DAG);
2845 if (Tmp1.Val) Result = Tmp1;
2849 case TargetLowering::Expand: {
2850 // Otherwise, the target does not support this operation. Lower the
2851 // operation to an explicit libcall as appropriate.
2852 MVT::ValueType IntPtr = TLI.getPointerTy();
2853 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2854 TargetLowering::ArgListTy Args;
2855 TargetLowering::ArgListEntry Entry;
2857 const char *FnName = 0;
2858 if (Node->getOpcode() == ISD::MEMSET) {
2859 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2860 Args.push_back(Entry);
2861 // Extend the (previously legalized) ubyte argument to be an int value
2863 if (Tmp3.getValueType() > MVT::i32)
2864 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2866 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2867 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2868 Args.push_back(Entry);
2869 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2870 Args.push_back(Entry);
2873 } else if (Node->getOpcode() == ISD::MEMCPY ||
2874 Node->getOpcode() == ISD::MEMMOVE) {
2875 Entry.Ty = IntPtrTy;
2876 Entry.Node = Tmp2; Args.push_back(Entry);
2877 Entry.Node = Tmp3; Args.push_back(Entry);
2878 Entry.Node = Tmp4; Args.push_back(Entry);
2879 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2881 assert(0 && "Unknown op!");
2884 std::pair<SDOperand,SDOperand> CallResult =
2885 TLI.LowerCallTo(Tmp1, Type::VoidTy,
2886 false, false, false, CallingConv::C, false,
2887 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2888 Result = CallResult.second;
2895 case ISD::SHL_PARTS:
2896 case ISD::SRA_PARTS:
2897 case ISD::SRL_PARTS: {
2898 SmallVector<SDOperand, 8> Ops;
2899 bool Changed = false;
2900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2901 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2902 Changed |= Ops.back() != Node->getOperand(i);
2905 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2907 switch (TLI.getOperationAction(Node->getOpcode(),
2908 Node->getValueType(0))) {
2909 default: assert(0 && "This action is not supported yet!");
2910 case TargetLowering::Legal: break;
2911 case TargetLowering::Custom:
2912 Tmp1 = TLI.LowerOperation(Result, DAG);
2914 SDOperand Tmp2, RetVal(0, 0);
2915 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2916 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2917 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2921 assert(RetVal.Val && "Illegal result number");
2927 // Since these produce multiple values, make sure to remember that we
2928 // legalized all of them.
2929 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2930 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2931 return Result.getValue(Op.ResNo);
2953 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2954 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2955 case Expand: assert(0 && "Not possible");
2957 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2960 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2964 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2966 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2967 default: assert(0 && "BinOp legalize operation not supported");
2968 case TargetLowering::Legal: break;
2969 case TargetLowering::Custom:
2970 Tmp1 = TLI.LowerOperation(Result, DAG);
2971 if (Tmp1.Val) Result = Tmp1;
2973 case TargetLowering::Expand: {
2974 MVT::ValueType VT = Op.getValueType();
2976 // See if multiply or divide can be lowered using two-result operations.
2977 SDVTList VTs = DAG.getVTList(VT, VT);
2978 if (Node->getOpcode() == ISD::MUL) {
2979 // We just need the low half of the multiply; try both the signed
2980 // and unsigned forms. If the target supports both SMUL_LOHI and
2981 // UMUL_LOHI, form a preference by checking which forms of plain
2982 // MULH it supports.
2983 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2984 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2985 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2986 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2987 unsigned OpToUse = 0;
2988 if (HasSMUL_LOHI && !HasMULHS) {
2989 OpToUse = ISD::SMUL_LOHI;
2990 } else if (HasUMUL_LOHI && !HasMULHU) {
2991 OpToUse = ISD::UMUL_LOHI;
2992 } else if (HasSMUL_LOHI) {
2993 OpToUse = ISD::SMUL_LOHI;
2994 } else if (HasUMUL_LOHI) {
2995 OpToUse = ISD::UMUL_LOHI;
2998 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3002 if (Node->getOpcode() == ISD::MULHS &&
3003 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3004 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3007 if (Node->getOpcode() == ISD::MULHU &&
3008 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3009 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3012 if (Node->getOpcode() == ISD::SDIV &&
3013 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3014 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3017 if (Node->getOpcode() == ISD::UDIV &&
3018 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3019 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3023 // Check to see if we have a libcall for this operator.
3024 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3025 bool isSigned = false;
3026 switch (Node->getOpcode()) {
3029 if (VT == MVT::i32) {
3030 LC = Node->getOpcode() == ISD::UDIV
3031 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3032 isSigned = Node->getOpcode() == ISD::SDIV;
3036 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3037 RTLIB::POW_PPCF128);
3041 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3043 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3047 assert(MVT::isVector(Node->getValueType(0)) &&
3048 "Cannot expand this binary operator!");
3049 // Expand the operation into a bunch of nasty scalar code.
3050 Result = LegalizeOp(UnrollVectorOp(Op));
3053 case TargetLowering::Promote: {
3054 switch (Node->getOpcode()) {
3055 default: assert(0 && "Do not know how to promote this BinOp!");
3059 MVT::ValueType OVT = Node->getValueType(0);
3060 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3061 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3062 // Bit convert each of the values to the new type.
3063 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3064 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3065 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3066 // Bit convert the result back the original type.
3067 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3075 case ISD::SMUL_LOHI:
3076 case ISD::UMUL_LOHI:
3079 // These nodes will only be produced by target-specific lowering, so
3080 // they shouldn't be here if they aren't legal.
3081 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3082 "This must be legal!");
3084 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3085 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3086 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3089 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3090 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3091 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3092 case Expand: assert(0 && "Not possible");
3094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3097 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3103 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3104 default: assert(0 && "Operation not supported");
3105 case TargetLowering::Custom:
3106 Tmp1 = TLI.LowerOperation(Result, DAG);
3107 if (Tmp1.Val) Result = Tmp1;
3109 case TargetLowering::Legal: break;
3110 case TargetLowering::Expand: {
3111 // If this target supports fabs/fneg natively and select is cheap,
3112 // do this efficiently.
3113 if (!TLI.isSelectExpensive() &&
3114 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3115 TargetLowering::Legal &&
3116 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3117 TargetLowering::Legal) {
3118 // Get the sign bit of the RHS.
3119 MVT::ValueType IVT =
3120 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3121 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3122 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3123 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3124 // Get the absolute value of the result.
3125 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3126 // Select between the nabs and abs value based on the sign bit of
3128 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3129 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3132 Result = LegalizeOp(Result);
3136 // Otherwise, do bitwise ops!
3137 MVT::ValueType NVT =
3138 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3139 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3140 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3141 Result = LegalizeOp(Result);
3149 Tmp1 = LegalizeOp(Node->getOperand(0));
3150 Tmp2 = LegalizeOp(Node->getOperand(1));
3151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3152 // Since this produces two values, make sure to remember that we legalized
3154 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3155 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3160 Tmp1 = LegalizeOp(Node->getOperand(0));
3161 Tmp2 = LegalizeOp(Node->getOperand(1));
3162 Tmp3 = LegalizeOp(Node->getOperand(2));
3163 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3164 // Since this produces two values, make sure to remember that we legalized
3166 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3167 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3170 case ISD::BUILD_PAIR: {
3171 MVT::ValueType PairTy = Node->getValueType(0);
3172 // TODO: handle the case where the Lo and Hi operands are not of legal type
3173 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3174 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3175 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3176 case TargetLowering::Promote:
3177 case TargetLowering::Custom:
3178 assert(0 && "Cannot promote/custom this yet!");
3179 case TargetLowering::Legal:
3180 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3181 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3183 case TargetLowering::Expand:
3184 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3185 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3186 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3187 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3188 TLI.getShiftAmountTy()));
3189 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3198 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3199 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3201 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3202 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3203 case TargetLowering::Custom:
3206 case TargetLowering::Legal:
3207 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3209 Tmp1 = TLI.LowerOperation(Result, DAG);
3210 if (Tmp1.Val) Result = Tmp1;
3213 case TargetLowering::Expand: {
3214 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3215 bool isSigned = DivOpc == ISD::SDIV;
3216 MVT::ValueType VT = Node->getValueType(0);
3218 // See if remainder can be lowered using two-result operations.
3219 SDVTList VTs = DAG.getVTList(VT, VT);
3220 if (Node->getOpcode() == ISD::SREM &&
3221 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3222 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3225 if (Node->getOpcode() == ISD::UREM &&
3226 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3227 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3231 if (MVT::isInteger(VT)) {
3232 if (TLI.getOperationAction(DivOpc, VT) ==
3233 TargetLowering::Legal) {
3235 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3236 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3237 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3238 } else if (MVT::isVector(VT)) {
3239 Result = LegalizeOp(UnrollVectorOp(Op));
3241 assert(VT == MVT::i32 &&
3242 "Cannot expand this binary operator!");
3243 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3244 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3246 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3249 assert(MVT::isFloatingPoint(VT) &&
3250 "remainder op must have integer or floating-point type");
3251 if (MVT::isVector(VT)) {
3252 Result = LegalizeOp(UnrollVectorOp(Op));
3254 // Floating point mod -> fmod libcall.
3255 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3256 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3258 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3259 false/*sign irrelevant*/, Dummy);
3267 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3268 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3270 MVT::ValueType VT = Node->getValueType(0);
3271 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3272 default: assert(0 && "This action is not supported yet!");
3273 case TargetLowering::Custom:
3276 case TargetLowering::Legal:
3277 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3278 Result = Result.getValue(0);
3279 Tmp1 = Result.getValue(1);
3282 Tmp2 = TLI.LowerOperation(Result, DAG);
3284 Result = LegalizeOp(Tmp2);
3285 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3289 case TargetLowering::Expand: {
3290 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3291 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3292 // Increment the pointer, VAList, to the next vaarg
3293 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3294 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3295 TLI.getPointerTy()));
3296 // Store the incremented VAList to the legalized pointer
3297 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3298 // Load the actual argument out of the pointer VAList
3299 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3300 Tmp1 = LegalizeOp(Result.getValue(1));
3301 Result = LegalizeOp(Result);
3305 // Since VAARG produces two values, make sure to remember that we
3306 // legalized both of them.
3307 AddLegalizedOperand(SDOperand(Node, 0), Result);
3308 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3309 return Op.ResNo ? Tmp1 : Result;
3313 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3314 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3315 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3317 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3318 default: assert(0 && "This action is not supported yet!");
3319 case TargetLowering::Custom:
3322 case TargetLowering::Legal:
3323 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3324 Node->getOperand(3), Node->getOperand(4));
3326 Tmp1 = TLI.LowerOperation(Result, DAG);
3327 if (Tmp1.Val) Result = Tmp1;
3330 case TargetLowering::Expand:
3331 // This defaults to loading a pointer from the input and storing it to the
3332 // output, returning the chain.
3333 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3334 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3335 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3336 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3342 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3343 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3345 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3346 default: assert(0 && "This action is not supported yet!");
3347 case TargetLowering::Custom:
3350 case TargetLowering::Legal:
3351 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3353 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3354 if (Tmp1.Val) Result = Tmp1;
3357 case TargetLowering::Expand:
3358 Result = Tmp1; // Default to a no-op, return the chain
3364 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3365 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3367 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3369 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3370 default: assert(0 && "This action is not supported yet!");
3371 case TargetLowering::Legal: break;
3372 case TargetLowering::Custom:
3373 Tmp1 = TLI.LowerOperation(Result, DAG);
3374 if (Tmp1.Val) Result = Tmp1;
3381 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3382 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3384 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3386 assert(0 && "ROTL/ROTR legalize operation not supported");
3388 case TargetLowering::Legal:
3390 case TargetLowering::Custom:
3391 Tmp1 = TLI.LowerOperation(Result, DAG);
3392 if (Tmp1.Val) Result = Tmp1;
3394 case TargetLowering::Promote:
3395 assert(0 && "Do not know how to promote ROTL/ROTR");
3397 case TargetLowering::Expand:
3398 assert(0 && "Do not know how to expand ROTL/ROTR");
3404 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3405 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3406 case TargetLowering::Custom:
3407 assert(0 && "Cannot custom legalize this yet!");
3408 case TargetLowering::Legal:
3409 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3411 case TargetLowering::Promote: {
3412 MVT::ValueType OVT = Tmp1.getValueType();
3413 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3414 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3416 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3417 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3418 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3419 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3422 case TargetLowering::Expand:
3423 Result = ExpandBSWAP(Tmp1);
3431 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3432 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3433 case TargetLowering::Custom:
3434 case TargetLowering::Legal:
3435 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3436 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3437 TargetLowering::Custom) {
3438 Tmp1 = TLI.LowerOperation(Result, DAG);
3444 case TargetLowering::Promote: {
3445 MVT::ValueType OVT = Tmp1.getValueType();
3446 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3448 // Zero extend the argument.
3449 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3450 // Perform the larger operation, then subtract if needed.
3451 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3452 switch (Node->getOpcode()) {
3457 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3458 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3459 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3461 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3462 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3465 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3466 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3467 DAG.getConstant(MVT::getSizeInBits(NVT) -
3468 MVT::getSizeInBits(OVT), NVT));
3473 case TargetLowering::Expand:
3474 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3485 Tmp1 = LegalizeOp(Node->getOperand(0));
3486 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3487 case TargetLowering::Promote:
3488 case TargetLowering::Custom:
3491 case TargetLowering::Legal:
3492 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3494 Tmp1 = TLI.LowerOperation(Result, DAG);
3495 if (Tmp1.Val) Result = Tmp1;
3498 case TargetLowering::Expand:
3499 switch (Node->getOpcode()) {
3500 default: assert(0 && "Unreachable!");
3502 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3503 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3504 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3507 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3508 MVT::ValueType VT = Node->getValueType(0);
3509 Tmp2 = DAG.getConstantFP(0.0, VT);
3510 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3511 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3512 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3518 MVT::ValueType VT = Node->getValueType(0);
3520 // Expand unsupported unary vector operators by unrolling them.
3521 if (MVT::isVector(VT)) {
3522 Result = LegalizeOp(UnrollVectorOp(Op));
3526 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3527 switch(Node->getOpcode()) {
3529 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3530 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3533 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3534 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3537 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3538 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3540 default: assert(0 && "Unreachable!");
3543 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3544 false/*sign irrelevant*/, Dummy);
3552 MVT::ValueType VT = Node->getValueType(0);
3554 // Expand unsupported unary vector operators by unrolling them.
3555 if (MVT::isVector(VT)) {
3556 Result = LegalizeOp(UnrollVectorOp(Op));
3560 // We always lower FPOWI into a libcall. No target support for it yet.
3561 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3562 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3564 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3565 false/*sign irrelevant*/, Dummy);
3568 case ISD::BIT_CONVERT:
3569 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3570 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3571 Node->getValueType(0));
3572 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3573 // The input has to be a vector type, we have to either scalarize it, pack
3574 // it, or convert it based on whether the input vector type is legal.
3575 SDNode *InVal = Node->getOperand(0).Val;
3576 int InIx = Node->getOperand(0).ResNo;
3577 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3578 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3580 // Figure out if there is a simple type corresponding to this Vector
3581 // type. If so, convert to the vector type.
3582 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3583 if (TLI.isTypeLegal(TVT)) {
3584 // Turn this into a bit convert of the vector input.
3585 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3586 LegalizeOp(Node->getOperand(0)));
3588 } else if (NumElems == 1) {
3589 // Turn this into a bit convert of the scalar input.
3590 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3591 ScalarizeVectorOp(Node->getOperand(0)));
3594 // FIXME: UNIMP! Store then reload
3595 assert(0 && "Cast from unsupported vector type not implemented yet!");
3598 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3599 Node->getOperand(0).getValueType())) {
3600 default: assert(0 && "Unknown operation action!");
3601 case TargetLowering::Expand:
3602 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3603 Node->getValueType(0));
3605 case TargetLowering::Legal:
3606 Tmp1 = LegalizeOp(Node->getOperand(0));
3607 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3613 // Conversion operators. The source and destination have different types.
3614 case ISD::SINT_TO_FP:
3615 case ISD::UINT_TO_FP: {
3616 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3617 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3619 switch (TLI.getOperationAction(Node->getOpcode(),
3620 Node->getOperand(0).getValueType())) {
3621 default: assert(0 && "Unknown operation action!");
3622 case TargetLowering::Custom:
3625 case TargetLowering::Legal:
3626 Tmp1 = LegalizeOp(Node->getOperand(0));
3627 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3629 Tmp1 = TLI.LowerOperation(Result, DAG);
3630 if (Tmp1.Val) Result = Tmp1;
3633 case TargetLowering::Expand:
3634 Result = ExpandLegalINT_TO_FP(isSigned,
3635 LegalizeOp(Node->getOperand(0)),
3636 Node->getValueType(0));
3638 case TargetLowering::Promote:
3639 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3640 Node->getValueType(0),
3646 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3647 Node->getValueType(0), Node->getOperand(0));
3650 Tmp1 = PromoteOp(Node->getOperand(0));
3652 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3653 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3655 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3656 Node->getOperand(0).getValueType());
3658 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3659 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3665 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3667 Tmp1 = LegalizeOp(Node->getOperand(0));
3668 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3671 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3673 // Since the result is legal, we should just be able to truncate the low
3674 // part of the source.
3675 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3678 Result = PromoteOp(Node->getOperand(0));
3679 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3684 case ISD::FP_TO_SINT:
3685 case ISD::FP_TO_UINT:
3686 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3688 Tmp1 = LegalizeOp(Node->getOperand(0));
3690 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3691 default: assert(0 && "Unknown operation action!");
3692 case TargetLowering::Custom:
3695 case TargetLowering::Legal:
3696 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3698 Tmp1 = TLI.LowerOperation(Result, DAG);
3699 if (Tmp1.Val) Result = Tmp1;
3702 case TargetLowering::Promote:
3703 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3704 Node->getOpcode() == ISD::FP_TO_SINT);
3706 case TargetLowering::Expand:
3707 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3708 SDOperand True, False;
3709 MVT::ValueType VT = Node->getOperand(0).getValueType();
3710 MVT::ValueType NVT = Node->getValueType(0);
3711 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3712 const uint64_t zero[] = {0, 0};
3713 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3714 uint64_t x = 1ULL << ShiftAmt;
3715 (void)apf.convertFromZeroExtendedInteger
3716 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3717 Tmp2 = DAG.getConstantFP(apf, VT);
3718 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3719 Node->getOperand(0), Tmp2, ISD::SETLT);
3720 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3721 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3722 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3724 False = DAG.getNode(ISD::XOR, NVT, False,
3725 DAG.getConstant(1ULL << ShiftAmt, NVT));
3726 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3729 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3735 MVT::ValueType VT = Op.getValueType();
3736 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3737 // Convert ppcf128 to i32
3738 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3739 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3740 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3741 Node->getOperand(0), DAG.getValueType(MVT::f64));
3742 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3743 DAG.getIntPtrConstant(1));
3744 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3746 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3747 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3748 Tmp2 = DAG.getConstantFP(apf, OVT);
3749 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3750 // FIXME: generated code sucks.
3751 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3752 DAG.getNode(ISD::ADD, MVT::i32,
3753 DAG.getNode(ISD::FP_TO_SINT, VT,
3754 DAG.getNode(ISD::FSUB, OVT,
3755 Node->getOperand(0), Tmp2)),
3756 DAG.getConstant(0x80000000, MVT::i32)),
3757 DAG.getNode(ISD::FP_TO_SINT, VT,
3758 Node->getOperand(0)),
3759 DAG.getCondCode(ISD::SETGE));
3763 // Convert f32 / f64 to i32 / i64.
3764 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3765 switch (Node->getOpcode()) {
3766 case ISD::FP_TO_SINT: {
3767 if (OVT == MVT::f32)
3768 LC = (VT == MVT::i32)
3769 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3770 else if (OVT == MVT::f64)
3771 LC = (VT == MVT::i32)
3772 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3773 else if (OVT == MVT::f80) {
3774 assert(VT == MVT::i64);
3775 LC = RTLIB::FPTOSINT_F80_I64;
3777 else if (OVT == MVT::ppcf128) {
3778 assert(VT == MVT::i64);
3779 LC = RTLIB::FPTOSINT_PPCF128_I64;
3783 case ISD::FP_TO_UINT: {
3784 if (OVT == MVT::f32)
3785 LC = (VT == MVT::i32)
3786 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3787 else if (OVT == MVT::f64)
3788 LC = (VT == MVT::i32)
3789 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3790 else if (OVT == MVT::f80) {
3791 LC = (VT == MVT::i32)
3792 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3794 else if (OVT == MVT::ppcf128) {
3795 assert(VT == MVT::i64);
3796 LC = RTLIB::FPTOUINT_PPCF128_I64;
3800 default: assert(0 && "Unreachable!");
3803 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3804 false/*sign irrelevant*/, Dummy);
3808 Tmp1 = PromoteOp(Node->getOperand(0));
3809 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3810 Result = LegalizeOp(Result);
3815 case ISD::FP_EXTEND: {
3816 MVT::ValueType DstVT = Op.getValueType();
3817 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3818 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3819 // The only other way we can lower this is to turn it into a STORE,
3820 // LOAD pair, targetting a temporary location (a stack slot).
3821 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3824 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3825 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3827 Tmp1 = LegalizeOp(Node->getOperand(0));
3828 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3831 Tmp1 = PromoteOp(Node->getOperand(0));
3832 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3837 case ISD::FP_ROUND: {
3838 MVT::ValueType DstVT = Op.getValueType();
3839 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3840 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3841 if (SrcVT == MVT::ppcf128) {
3843 ExpandOp(Node->getOperand(0), Lo, Result);
3844 // Round it the rest of the way (e.g. to f32) if needed.
3845 if (DstVT!=MVT::f64)
3846 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3849 // The only other way we can lower this is to turn it into a STORE,
3850 // LOAD pair, targetting a temporary location (a stack slot).
3851 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3854 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3855 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3857 Tmp1 = LegalizeOp(Node->getOperand(0));
3858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3861 Tmp1 = PromoteOp(Node->getOperand(0));
3862 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3863 Node->getOperand(1));
3868 case ISD::ANY_EXTEND:
3869 case ISD::ZERO_EXTEND:
3870 case ISD::SIGN_EXTEND:
3871 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3872 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3874 Tmp1 = LegalizeOp(Node->getOperand(0));
3875 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3876 TargetLowering::Custom) {
3877 Tmp2 = TLI.LowerOperation(Result, DAG);
3882 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3885 switch (Node->getOpcode()) {
3886 case ISD::ANY_EXTEND:
3887 Tmp1 = PromoteOp(Node->getOperand(0));
3888 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3890 case ISD::ZERO_EXTEND:
3891 Result = PromoteOp(Node->getOperand(0));
3892 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3893 Result = DAG.getZeroExtendInReg(Result,
3894 Node->getOperand(0).getValueType());
3896 case ISD::SIGN_EXTEND:
3897 Result = PromoteOp(Node->getOperand(0));
3898 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3899 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3901 DAG.getValueType(Node->getOperand(0).getValueType()));
3906 case ISD::FP_ROUND_INREG:
3907 case ISD::SIGN_EXTEND_INREG: {
3908 Tmp1 = LegalizeOp(Node->getOperand(0));
3909 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3911 // If this operation is not supported, convert it to a shl/shr or load/store
3913 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3914 default: assert(0 && "This action not supported for this op yet!");
3915 case TargetLowering::Legal:
3916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3918 case TargetLowering::Expand:
3919 // If this is an integer extend and shifts are supported, do that.
3920 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3921 // NOTE: we could fall back on load/store here too for targets without
3922 // SAR. However, it is doubtful that any exist.
3923 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3924 MVT::getSizeInBits(ExtraVT);
3925 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3926 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3927 Node->getOperand(0), ShiftCst);
3928 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3930 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3931 // The only way we can lower this is to turn it into a TRUNCSTORE,
3932 // EXTLOAD pair, targetting a temporary location (a stack slot).
3934 // NOTE: there is a choice here between constantly creating new stack
3935 // slots and always reusing the same one. We currently always create
3936 // new ones, as reuse may inhibit scheduling.
3937 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3938 Node->getValueType(0));
3940 assert(0 && "Unknown op");
3946 case ISD::TRAMPOLINE: {
3948 for (unsigned i = 0; i != 6; ++i)
3949 Ops[i] = LegalizeOp(Node->getOperand(i));
3950 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3951 // The only option for this node is to custom lower it.
3952 Result = TLI.LowerOperation(Result, DAG);
3953 assert(Result.Val && "Should always custom lower!");
3955 // Since trampoline produces two values, make sure to remember that we
3956 // legalized both of them.
3957 Tmp1 = LegalizeOp(Result.getValue(1));
3958 Result = LegalizeOp(Result);
3959 AddLegalizedOperand(SDOperand(Node, 0), Result);
3960 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3961 return Op.ResNo ? Tmp1 : Result;
3963 case ISD::FLT_ROUNDS_: {
3964 MVT::ValueType VT = Node->getValueType(0);
3965 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3966 default: assert(0 && "This action not supported for this op yet!");
3967 case TargetLowering::Custom:
3968 Result = TLI.LowerOperation(Op, DAG);
3969 if (Result.Val) break;
3971 case TargetLowering::Legal:
3972 // If this operation is not supported, lower it to constant 1
3973 Result = DAG.getConstant(1, VT);
3978 MVT::ValueType VT = Node->getValueType(0);
3979 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3980 default: assert(0 && "This action not supported for this op yet!");
3981 case TargetLowering::Legal:
3982 Tmp1 = LegalizeOp(Node->getOperand(0));
3983 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3985 case TargetLowering::Custom:
3986 Result = TLI.LowerOperation(Op, DAG);
3987 if (Result.Val) break;
3989 case TargetLowering::Expand:
3990 // If this operation is not supported, lower it to 'abort()' call
3991 Tmp1 = LegalizeOp(Node->getOperand(0));
3992 TargetLowering::ArgListTy Args;
3993 std::pair<SDOperand,SDOperand> CallResult =
3994 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3995 false, false, false, CallingConv::C, false,
3996 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3998 Result = CallResult.second;
4005 assert(Result.getValueType() == Op.getValueType() &&
4006 "Bad legalization!");
4008 // Make sure that the generated code is itself legal.
4010 Result = LegalizeOp(Result);
4012 // Note that LegalizeOp may be reentered even from single-use nodes, which
4013 // means that we always must cache transformed nodes.
4014 AddLegalizedOperand(Op, Result);
4018 /// PromoteOp - Given an operation that produces a value in an invalid type,
4019 /// promote it to compute the value into a larger type. The produced value will
4020 /// have the correct bits for the low portion of the register, but no guarantee
4021 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4022 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4023 MVT::ValueType VT = Op.getValueType();
4024 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4025 assert(getTypeAction(VT) == Promote &&
4026 "Caller should expand or legalize operands that are not promotable!");
4027 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4028 "Cannot promote to smaller type!");
4030 SDOperand Tmp1, Tmp2, Tmp3;
4032 SDNode *Node = Op.Val;
4034 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4035 if (I != PromotedNodes.end()) return I->second;
4037 switch (Node->getOpcode()) {
4038 case ISD::CopyFromReg:
4039 assert(0 && "CopyFromReg must be legal!");
4042 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4044 assert(0 && "Do not know how to promote this operator!");
4047 Result = DAG.getNode(ISD::UNDEF, NVT);
4051 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4053 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4054 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4056 case ISD::ConstantFP:
4057 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4058 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4062 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4063 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4064 Node->getOperand(1), Node->getOperand(2));
4068 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4070 Result = LegalizeOp(Node->getOperand(0));
4071 assert(Result.getValueType() >= NVT &&
4072 "This truncation doesn't make sense!");
4073 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4074 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4077 // The truncation is not required, because we don't guarantee anything
4078 // about high bits anyway.
4079 Result = PromoteOp(Node->getOperand(0));
4082 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4083 // Truncate the low part of the expanded value to the result type
4084 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4087 case ISD::SIGN_EXTEND:
4088 case ISD::ZERO_EXTEND:
4089 case ISD::ANY_EXTEND:
4090 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4091 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4093 // Input is legal? Just do extend all the way to the larger type.
4094 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4097 // Promote the reg if it's smaller.
4098 Result = PromoteOp(Node->getOperand(0));
4099 // The high bits are not guaranteed to be anything. Insert an extend.
4100 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4101 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4102 DAG.getValueType(Node->getOperand(0).getValueType()));
4103 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4104 Result = DAG.getZeroExtendInReg(Result,
4105 Node->getOperand(0).getValueType());
4109 case ISD::BIT_CONVERT:
4110 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4111 Node->getValueType(0));
4112 Result = PromoteOp(Result);
4115 case ISD::FP_EXTEND:
4116 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4118 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4119 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4120 case Promote: assert(0 && "Unreachable with 2 FP types!");
4122 if (Node->getConstantOperandVal(1) == 0) {
4123 // Input is legal? Do an FP_ROUND_INREG.
4124 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4125 DAG.getValueType(VT));
4127 // Just remove the truncate, it isn't affecting the value.
4128 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4129 Node->getOperand(1));
4134 case ISD::SINT_TO_FP:
4135 case ISD::UINT_TO_FP:
4136 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4138 // No extra round required here.
4139 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4143 Result = PromoteOp(Node->getOperand(0));
4144 if (Node->getOpcode() == ISD::SINT_TO_FP)
4145 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4147 DAG.getValueType(Node->getOperand(0).getValueType()));
4149 Result = DAG.getZeroExtendInReg(Result,
4150 Node->getOperand(0).getValueType());
4151 // No extra round required here.
4152 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4155 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4156 Node->getOperand(0));
4157 // Round if we cannot tolerate excess precision.
4158 if (NoExcessFPPrecision)
4159 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4160 DAG.getValueType(VT));
4165 case ISD::SIGN_EXTEND_INREG:
4166 Result = PromoteOp(Node->getOperand(0));
4167 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4168 Node->getOperand(1));
4170 case ISD::FP_TO_SINT:
4171 case ISD::FP_TO_UINT:
4172 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4175 Tmp1 = Node->getOperand(0);
4178 // The input result is prerounded, so we don't have to do anything
4180 Tmp1 = PromoteOp(Node->getOperand(0));
4183 // If we're promoting a UINT to a larger size, check to see if the new node
4184 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4185 // we can use that instead. This allows us to generate better code for
4186 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4187 // legal, such as PowerPC.
4188 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4189 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4190 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4191 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4192 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4194 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4200 Tmp1 = PromoteOp(Node->getOperand(0));
4201 assert(Tmp1.getValueType() == NVT);
4202 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4203 // NOTE: we do not have to do any extra rounding here for
4204 // NoExcessFPPrecision, because we know the input will have the appropriate
4205 // precision, and these operations don't modify precision at all.
4211 Tmp1 = PromoteOp(Node->getOperand(0));
4212 assert(Tmp1.getValueType() == NVT);
4213 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4214 if (NoExcessFPPrecision)
4215 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4216 DAG.getValueType(VT));
4220 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4221 // directly as well, which may be better.
4222 Tmp1 = PromoteOp(Node->getOperand(0));
4223 assert(Tmp1.getValueType() == NVT);
4224 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4225 if (NoExcessFPPrecision)
4226 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4227 DAG.getValueType(VT));
4237 // The input may have strange things in the top bits of the registers, but
4238 // these operations don't care. They may have weird bits going out, but
4239 // that too is okay if they are integer operations.
4240 Tmp1 = PromoteOp(Node->getOperand(0));
4241 Tmp2 = PromoteOp(Node->getOperand(1));
4242 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4243 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4248 Tmp1 = PromoteOp(Node->getOperand(0));
4249 Tmp2 = PromoteOp(Node->getOperand(1));
4250 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4251 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4253 // Floating point operations will give excess precision that we may not be
4254 // able to tolerate. If we DO allow excess precision, just leave it,
4255 // otherwise excise it.
4256 // FIXME: Why would we need to round FP ops more than integer ones?
4257 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4258 if (NoExcessFPPrecision)
4259 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4260 DAG.getValueType(VT));
4265 // These operators require that their input be sign extended.
4266 Tmp1 = PromoteOp(Node->getOperand(0));
4267 Tmp2 = PromoteOp(Node->getOperand(1));
4268 if (MVT::isInteger(NVT)) {
4269 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4270 DAG.getValueType(VT));
4271 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4272 DAG.getValueType(VT));
4274 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4276 // Perform FP_ROUND: this is probably overly pessimistic.
4277 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4278 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4279 DAG.getValueType(VT));
4283 case ISD::FCOPYSIGN:
4284 // These operators require that their input be fp extended.
4285 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4286 case Expand: assert(0 && "not implemented");
4287 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4288 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4290 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4291 case Expand: assert(0 && "not implemented");
4292 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4293 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4295 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4297 // Perform FP_ROUND: this is probably overly pessimistic.
4298 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4299 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4300 DAG.getValueType(VT));
4305 // These operators require that their input be zero extended.
4306 Tmp1 = PromoteOp(Node->getOperand(0));
4307 Tmp2 = PromoteOp(Node->getOperand(1));
4308 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4309 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4310 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4311 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4315 Tmp1 = PromoteOp(Node->getOperand(0));
4316 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4319 // The input value must be properly sign extended.
4320 Tmp1 = PromoteOp(Node->getOperand(0));
4321 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4322 DAG.getValueType(VT));
4323 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4326 // The input value must be properly zero extended.
4327 Tmp1 = PromoteOp(Node->getOperand(0));
4328 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4329 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4333 Tmp1 = Node->getOperand(0); // Get the chain.
4334 Tmp2 = Node->getOperand(1); // Get the pointer.
4335 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4336 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4337 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4339 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4340 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4341 // Increment the pointer, VAList, to the next vaarg
4342 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4343 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4344 TLI.getPointerTy()));
4345 // Store the incremented VAList to the legalized pointer
4346 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4347 // Load the actual argument out of the pointer VAList
4348 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4350 // Remember that we legalized the chain.
4351 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4355 LoadSDNode *LD = cast<LoadSDNode>(Node);
4356 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4357 ? ISD::EXTLOAD : LD->getExtensionType();
4358 Result = DAG.getExtLoad(ExtType, NVT,
4359 LD->getChain(), LD->getBasePtr(),
4360 LD->getSrcValue(), LD->getSrcValueOffset(),
4363 LD->getAlignment());
4364 // Remember that we legalized the chain.
4365 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4369 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4370 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4371 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4373 case ISD::SELECT_CC:
4374 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4375 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4376 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4377 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4380 Tmp1 = Node->getOperand(0);
4381 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4382 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4383 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4384 DAG.getConstant(MVT::getSizeInBits(NVT) -
4385 MVT::getSizeInBits(VT),
4386 TLI.getShiftAmountTy()));
4391 // Zero extend the argument
4392 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4393 // Perform the larger operation, then subtract if needed.
4394 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4395 switch(Node->getOpcode()) {
4400 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4401 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4402 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4404 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4405 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4408 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4409 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4410 DAG.getConstant(MVT::getSizeInBits(NVT) -
4411 MVT::getSizeInBits(VT), NVT));
4415 case ISD::EXTRACT_SUBVECTOR:
4416 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4418 case ISD::EXTRACT_VECTOR_ELT:
4419 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4423 assert(Result.Val && "Didn't set a result!");
4425 // Make sure the result is itself legal.
4426 Result = LegalizeOp(Result);
4428 // Remember that we promoted this!
4429 AddPromotedOperand(Op, Result);
4433 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4434 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4435 /// based on the vector type. The return type of this matches the element type
4436 /// of the vector, which may not be legal for the target.
4437 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4438 // We know that operand #0 is the Vec vector. If the index is a constant
4439 // or if the invec is a supported hardware type, we can use it. Otherwise,
4440 // lower to a store then an indexed load.
4441 SDOperand Vec = Op.getOperand(0);
4442 SDOperand Idx = Op.getOperand(1);
4444 MVT::ValueType TVT = Vec.getValueType();
4445 unsigned NumElems = MVT::getVectorNumElements(TVT);
4447 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4448 default: assert(0 && "This action is not supported yet!");
4449 case TargetLowering::Custom: {
4450 Vec = LegalizeOp(Vec);
4451 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4452 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4457 case TargetLowering::Legal:
4458 if (isTypeLegal(TVT)) {
4459 Vec = LegalizeOp(Vec);
4460 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4464 case TargetLowering::Expand:
4468 if (NumElems == 1) {
4469 // This must be an access of the only element. Return it.
4470 Op = ScalarizeVectorOp(Vec);
4471 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4472 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4473 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4475 SplitVectorOp(Vec, Lo, Hi);
4476 if (CIdx->getValue() < NumLoElts) {
4480 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4481 Idx.getValueType());
4484 // It's now an extract from the appropriate high or low part. Recurse.
4485 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4486 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4488 // Store the value to a temporary stack slot, then LOAD the scalar
4489 // element back out.
4490 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4491 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4493 // Add the offset to the index.
4494 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4495 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4496 DAG.getConstant(EltSize, Idx.getValueType()));
4498 if (MVT::getSizeInBits(Idx.getValueType()) >
4499 MVT::getSizeInBits(TLI.getPointerTy()))
4500 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4502 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4504 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4506 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4511 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4512 /// we assume the operation can be split if it is not already legal.
4513 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4514 // We know that operand #0 is the Vec vector. For now we assume the index
4515 // is a constant and that the extracted result is a supported hardware type.
4516 SDOperand Vec = Op.getOperand(0);
4517 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4519 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4521 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4522 // This must be an access of the desired vector length. Return it.
4526 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4528 SplitVectorOp(Vec, Lo, Hi);
4529 if (CIdx->getValue() < NumElems/2) {
4533 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4536 // It's now an extract from the appropriate high or low part. Recurse.
4537 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4538 return ExpandEXTRACT_SUBVECTOR(Op);
4541 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4542 /// with condition CC on the current target. This usually involves legalizing
4543 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4544 /// there may be no choice but to create a new SetCC node to represent the
4545 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4546 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4547 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4550 SDOperand Tmp1, Tmp2, Tmp3, Result;
4552 switch (getTypeAction(LHS.getValueType())) {
4554 Tmp1 = LegalizeOp(LHS); // LHS
4555 Tmp2 = LegalizeOp(RHS); // RHS
4558 Tmp1 = PromoteOp(LHS); // LHS
4559 Tmp2 = PromoteOp(RHS); // RHS
4561 // If this is an FP compare, the operands have already been extended.
4562 if (MVT::isInteger(LHS.getValueType())) {
4563 MVT::ValueType VT = LHS.getValueType();
4564 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4566 // Otherwise, we have to insert explicit sign or zero extends. Note
4567 // that we could insert sign extends for ALL conditions, but zero extend
4568 // is cheaper on many machines (an AND instead of two shifts), so prefer
4570 switch (cast<CondCodeSDNode>(CC)->get()) {
4571 default: assert(0 && "Unknown integer comparison!");
4578 // ALL of these operations will work if we either sign or zero extend
4579 // the operands (including the unsigned comparisons!). Zero extend is
4580 // usually a simpler/cheaper operation, so prefer it.
4581 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4582 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4588 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4589 DAG.getValueType(VT));
4590 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4591 DAG.getValueType(VT));
4597 MVT::ValueType VT = LHS.getValueType();
4598 if (VT == MVT::f32 || VT == MVT::f64) {
4599 // Expand into one or more soft-fp libcall(s).
4600 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4601 switch (cast<CondCodeSDNode>(CC)->get()) {
4604 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4608 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4612 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4616 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4620 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4624 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4627 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4630 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4633 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4634 switch (cast<CondCodeSDNode>(CC)->get()) {
4636 // SETONE = SETOLT | SETOGT
4637 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4640 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4643 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4646 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4649 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4652 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4654 default: assert(0 && "Unsupported FP setcc!");
4659 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4660 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4661 false /*sign irrelevant*/, Dummy);
4662 Tmp2 = DAG.getConstant(0, MVT::i32);
4663 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4664 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4665 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4666 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4667 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4668 false /*sign irrelevant*/, Dummy);
4669 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4670 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4671 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4679 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4680 ExpandOp(LHS, LHSLo, LHSHi);
4681 ExpandOp(RHS, RHSLo, RHSHi);
4682 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4684 if (VT==MVT::ppcf128) {
4685 // FIXME: This generated code sucks. We want to generate
4686 // FCMP crN, hi1, hi2
4688 // FCMP crN, lo1, lo2
4689 // The following can be improved, but not that much.
4690 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4691 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4692 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4693 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4694 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4695 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4696 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4705 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4706 if (RHSCST->isAllOnesValue()) {
4707 // Comparison to -1.
4708 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4713 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4714 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4715 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4716 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4719 // If this is a comparison of the sign bit, just look at the top part.
4721 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4722 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4723 CST->getValue() == 0) || // X < 0
4724 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4725 CST->isAllOnesValue())) { // X > -1
4731 // FIXME: This generated code sucks.
4732 ISD::CondCode LowCC;
4734 default: assert(0 && "Unknown integer setcc!");
4736 case ISD::SETULT: LowCC = ISD::SETULT; break;
4738 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4740 case ISD::SETULE: LowCC = ISD::SETULE; break;
4742 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4745 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4746 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4747 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4749 // NOTE: on targets without efficient SELECT of bools, we can always use
4750 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4751 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4752 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4753 false, DagCombineInfo);
4755 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4756 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4757 CCCode, false, DagCombineInfo);
4759 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4761 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4762 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4763 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4764 (Tmp2C && Tmp2C->getValue() == 0 &&
4765 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4766 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4767 (Tmp2C && Tmp2C->getValue() == 1 &&
4768 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4769 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4770 // low part is known false, returns high part.
4771 // For LE / GE, if high part is known false, ignore the low part.
4772 // For LT / GT, if high part is known true, ignore the low part.
4776 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4777 ISD::SETEQ, false, DagCombineInfo);
4779 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4780 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4781 Result, Tmp1, Tmp2));
4792 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4793 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4794 /// a load from the stack slot to DestVT, extending it if needed.
4795 /// The resultant code need not be legal.
4796 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4797 MVT::ValueType SlotVT,
4798 MVT::ValueType DestVT) {
4799 // Create the stack frame object.
4800 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4802 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4803 int SPFI = StackPtrFI->getIndex();
4805 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4806 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4807 unsigned DestSize = MVT::getSizeInBits(DestVT);
4809 // Emit a store to the stack slot. Use a truncstore if the input value is
4810 // later than DestVT.
4812 if (SrcSize > SlotSize)
4813 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4814 PseudoSourceValue::getFixedStack(),
4817 assert(SrcSize == SlotSize && "Invalid store");
4818 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4819 PseudoSourceValue::getFixedStack(),
4823 // Result is a load from the stack slot.
4824 if (SlotSize == DestSize)
4825 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4827 assert(SlotSize < DestSize && "Unknown extension!");
4828 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4831 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4832 // Create a vector sized/aligned stack slot, store the value to element #0,
4833 // then load the whole vector back out.
4834 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4836 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4837 int SPFI = StackPtrFI->getIndex();
4839 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4840 PseudoSourceValue::getFixedStack(), SPFI);
4841 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4842 PseudoSourceValue::getFixedStack(), SPFI);
4846 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4847 /// support the operation, but do support the resultant vector type.
4848 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4850 // If the only non-undef value is the low element, turn this into a
4851 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4852 unsigned NumElems = Node->getNumOperands();
4853 bool isOnlyLowElement = true;
4854 SDOperand SplatValue = Node->getOperand(0);
4855 std::map<SDOperand, std::vector<unsigned> > Values;
4856 Values[SplatValue].push_back(0);
4857 bool isConstant = true;
4858 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4859 SplatValue.getOpcode() != ISD::UNDEF)
4862 for (unsigned i = 1; i < NumElems; ++i) {
4863 SDOperand V = Node->getOperand(i);
4864 Values[V].push_back(i);
4865 if (V.getOpcode() != ISD::UNDEF)
4866 isOnlyLowElement = false;
4867 if (SplatValue != V)
4868 SplatValue = SDOperand(0,0);
4870 // If this isn't a constant element or an undef, we can't use a constant
4872 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4873 V.getOpcode() != ISD::UNDEF)
4877 if (isOnlyLowElement) {
4878 // If the low element is an undef too, then this whole things is an undef.
4879 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4880 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4881 // Otherwise, turn this into a scalar_to_vector node.
4882 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4883 Node->getOperand(0));
4886 // If all elements are constants, create a load from the constant pool.
4888 MVT::ValueType VT = Node->getValueType(0);
4890 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4891 std::vector<Constant*> CV;
4892 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4893 if (ConstantFPSDNode *V =
4894 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4895 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4896 } else if (ConstantSDNode *V =
4897 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4898 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4900 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4901 CV.push_back(UndefValue::get(OpNTy));
4904 Constant *CP = ConstantVector::get(CV);
4905 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4906 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4907 PseudoSourceValue::getConstantPool(), 0);
4910 if (SplatValue.Val) { // Splat of one value?
4911 // Build the shuffle constant vector: <0, 0, 0, 0>
4912 MVT::ValueType MaskVT =
4913 MVT::getIntVectorWithNumElements(NumElems);
4914 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4915 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4916 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4917 &ZeroVec[0], ZeroVec.size());
4919 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4920 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4921 // Get the splatted value into the low element of a vector register.
4922 SDOperand LowValVec =
4923 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4925 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4926 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4927 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4932 // If there are only two unique elements, we may be able to turn this into a
4934 if (Values.size() == 2) {
4935 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4936 MVT::ValueType MaskVT =
4937 MVT::getIntVectorWithNumElements(NumElems);
4938 std::vector<SDOperand> MaskVec(NumElems);
4940 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4941 E = Values.end(); I != E; ++I) {
4942 for (std::vector<unsigned>::iterator II = I->second.begin(),
4943 EE = I->second.end(); II != EE; ++II)
4944 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4947 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4948 &MaskVec[0], MaskVec.size());
4950 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4951 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4952 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4953 SmallVector<SDOperand, 8> Ops;
4954 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4955 E = Values.end(); I != E; ++I) {
4956 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4960 Ops.push_back(ShuffleMask);
4962 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4963 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4964 &Ops[0], Ops.size());
4968 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4969 // aligned object on the stack, store each element into it, then load
4970 // the result as a vector.
4971 MVT::ValueType VT = Node->getValueType(0);
4972 // Create the stack frame object.
4973 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4975 // Emit a store of each element to the stack slot.
4976 SmallVector<SDOperand, 8> Stores;
4977 unsigned TypeByteSize =
4978 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4979 // Store (in the right endianness) the elements to memory.
4980 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4981 // Ignore undef elements.
4982 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4984 unsigned Offset = TypeByteSize*i;
4986 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4987 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4989 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4993 SDOperand StoreChain;
4994 if (!Stores.empty()) // Not all undef elements?
4995 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4996 &Stores[0], Stores.size());
4998 StoreChain = DAG.getEntryNode();
5000 // Result is a load from the stack slot.
5001 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5004 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5005 SDOperand Op, SDOperand Amt,
5006 SDOperand &Lo, SDOperand &Hi) {
5007 // Expand the subcomponents.
5008 SDOperand LHSL, LHSH;
5009 ExpandOp(Op, LHSL, LHSH);
5011 SDOperand Ops[] = { LHSL, LHSH, Amt };
5012 MVT::ValueType VT = LHSL.getValueType();
5013 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5014 Hi = Lo.getValue(1);
5018 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5019 /// smaller elements. If we can't find a way that is more efficient than a
5020 /// libcall on this target, return false. Otherwise, return true with the
5021 /// low-parts expanded into Lo and Hi.
5022 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5023 SDOperand &Lo, SDOperand &Hi) {
5024 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5025 "This is not a shift!");
5027 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5028 SDOperand ShAmt = LegalizeOp(Amt);
5029 MVT::ValueType ShTy = ShAmt.getValueType();
5030 unsigned ShBits = MVT::getSizeInBits(ShTy);
5031 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5032 unsigned NVTBits = MVT::getSizeInBits(NVT);
5034 // Handle the case when Amt is an immediate.
5035 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5036 unsigned Cst = CN->getValue();
5037 // Expand the incoming operand to be shifted, so that we have its parts
5039 ExpandOp(Op, InL, InH);
5043 Lo = DAG.getConstant(0, NVT);
5044 Hi = DAG.getConstant(0, NVT);
5045 } else if (Cst > NVTBits) {
5046 Lo = DAG.getConstant(0, NVT);
5047 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5048 } else if (Cst == NVTBits) {
5049 Lo = DAG.getConstant(0, NVT);
5052 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5053 Hi = DAG.getNode(ISD::OR, NVT,
5054 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5055 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5060 Lo = DAG.getConstant(0, NVT);
5061 Hi = DAG.getConstant(0, NVT);
5062 } else if (Cst > NVTBits) {
5063 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5064 Hi = DAG.getConstant(0, NVT);
5065 } else if (Cst == NVTBits) {
5067 Hi = DAG.getConstant(0, NVT);
5069 Lo = DAG.getNode(ISD::OR, NVT,
5070 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5071 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5072 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5077 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5078 DAG.getConstant(NVTBits-1, ShTy));
5079 } else if (Cst > NVTBits) {
5080 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5081 DAG.getConstant(Cst-NVTBits, ShTy));
5082 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5083 DAG.getConstant(NVTBits-1, ShTy));
5084 } else if (Cst == NVTBits) {
5086 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5087 DAG.getConstant(NVTBits-1, ShTy));
5089 Lo = DAG.getNode(ISD::OR, NVT,
5090 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5091 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5092 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5098 // Okay, the shift amount isn't constant. However, if we can tell that it is
5099 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5100 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5101 APInt KnownZero, KnownOne;
5102 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5104 // If we know that the high bit of the shift amount is one, then we can do
5105 // this as a couple of simple shifts.
5106 if (KnownOne.intersects(Mask)) {
5107 // Mask out the high bit, which we know is set.
5108 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5109 DAG.getConstant(~Mask, Amt.getValueType()));
5111 // Expand the incoming operand to be shifted, so that we have its parts
5113 ExpandOp(Op, InL, InH);
5116 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5117 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5120 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5121 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5124 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5125 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5126 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5131 // If we know that the high bit of the shift amount is zero, then we can do
5132 // this as a couple of simple shifts.
5133 if (KnownZero.intersects(Mask)) {
5135 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5136 DAG.getConstant(NVTBits, Amt.getValueType()),
5139 // Expand the incoming operand to be shifted, so that we have its parts
5141 ExpandOp(Op, InL, InH);
5144 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5145 Hi = DAG.getNode(ISD::OR, NVT,
5146 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5147 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5150 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5151 Lo = DAG.getNode(ISD::OR, NVT,
5152 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5153 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5156 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5157 Lo = DAG.getNode(ISD::OR, NVT,
5158 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5159 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5168 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5169 // does not fit into a register, return the lo part and set the hi part to the
5170 // by-reg argument. If it does fit into a single register, return the result
5171 // and leave the Hi part unset.
5172 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5173 bool isSigned, SDOperand &Hi) {
5174 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5175 // The input chain to this libcall is the entry node of the function.
5176 // Legalizing the call will automatically add the previous call to the
5178 SDOperand InChain = DAG.getEntryNode();
5180 TargetLowering::ArgListTy Args;
5181 TargetLowering::ArgListEntry Entry;
5182 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5183 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5184 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5185 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5186 Entry.isSExt = isSigned;
5187 Entry.isZExt = !isSigned;
5188 Args.push_back(Entry);
5190 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5192 // Splice the libcall in wherever FindInputOutputChains tells us to.
5193 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5194 std::pair<SDOperand,SDOperand> CallInfo =
5195 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5196 false, Callee, Args, DAG);
5198 // Legalize the call sequence, starting with the chain. This will advance
5199 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5200 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5201 LegalizeOp(CallInfo.second);
5203 switch (getTypeAction(CallInfo.first.getValueType())) {
5204 default: assert(0 && "Unknown thing");
5206 Result = CallInfo.first;
5209 ExpandOp(CallInfo.first, Result, Hi);
5216 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5218 SDOperand SelectionDAGLegalize::
5219 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5220 assert(getTypeAction(Source.getValueType()) == Expand &&
5221 "This is not an expansion!");
5222 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5225 assert(Source.getValueType() == MVT::i64 &&
5226 "This only works for 64-bit -> FP");
5227 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5228 // incoming integer is set. To handle this, we dynamically test to see if
5229 // it is set, and, if so, add a fudge factor.
5231 ExpandOp(Source, Lo, Hi);
5233 // If this is unsigned, and not supported, first perform the conversion to
5234 // signed, then adjust the result if the sign bit is set.
5235 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5236 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5238 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5239 DAG.getConstant(0, Hi.getValueType()),
5241 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5242 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5243 SignSet, Four, Zero);
5244 uint64_t FF = 0x5f800000ULL;
5245 if (TLI.isLittleEndian()) FF <<= 32;
5246 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5248 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5249 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5250 SDOperand FudgeInReg;
5251 if (DestTy == MVT::f32)
5252 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5253 PseudoSourceValue::getConstantPool(), 0);
5254 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5255 // FIXME: Avoid the extend by construction the right constantpool?
5256 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5258 PseudoSourceValue::getConstantPool(), 0,
5261 assert(0 && "Unexpected conversion");
5263 MVT::ValueType SCVT = SignedConv.getValueType();
5264 if (SCVT != DestTy) {
5265 // Destination type needs to be expanded as well. The FADD now we are
5266 // constructing will be expanded into a libcall.
5267 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5268 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5269 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5270 SignedConv, SignedConv.getValue(1));
5272 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5274 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5277 // Check to see if the target has a custom way to lower this. If so, use it.
5278 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5279 default: assert(0 && "This action not implemented for this operation!");
5280 case TargetLowering::Legal:
5281 case TargetLowering::Expand:
5282 break; // This case is handled below.
5283 case TargetLowering::Custom: {
5284 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5287 return LegalizeOp(NV);
5288 break; // The target decided this was legal after all
5292 // Expand the source, then glue it back together for the call. We must expand
5293 // the source in case it is shared (this pass of legalize must traverse it).
5294 SDOperand SrcLo, SrcHi;
5295 ExpandOp(Source, SrcLo, SrcHi);
5296 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5299 if (DestTy == MVT::f32)
5300 LC = RTLIB::SINTTOFP_I64_F32;
5302 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5303 LC = RTLIB::SINTTOFP_I64_F64;
5306 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5307 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5308 SDOperand UnusedHiPart;
5309 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5313 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5314 /// INT_TO_FP operation of the specified operand when the target requests that
5315 /// we expand it. At this point, we know that the result and operand types are
5316 /// legal for the target.
5317 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5319 MVT::ValueType DestVT) {
5320 if (Op0.getValueType() == MVT::i32) {
5321 // simple 32-bit [signed|unsigned] integer to float/double expansion
5323 // Get the stack frame index of a 8 byte buffer.
5324 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5326 // word offset constant for Hi/Lo address computation
5327 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5328 // set up Hi and Lo (into buffer) address based on endian
5329 SDOperand Hi = StackSlot;
5330 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5331 if (TLI.isLittleEndian())
5334 // if signed map to unsigned space
5335 SDOperand Op0Mapped;
5337 // constant used to invert sign bit (signed to unsigned mapping)
5338 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5339 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5343 // store the lo of the constructed double - based on integer input
5344 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5345 Op0Mapped, Lo, NULL, 0);
5346 // initial hi portion of constructed double
5347 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5348 // store the hi of the constructed double - biased exponent
5349 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5350 // load the constructed double
5351 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5352 // FP constant to bias correct the final result
5353 SDOperand Bias = DAG.getConstantFP(isSigned ?
5354 BitsToDouble(0x4330000080000000ULL)
5355 : BitsToDouble(0x4330000000000000ULL),
5357 // subtract the bias
5358 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5361 // handle final rounding
5362 if (DestVT == MVT::f64) {
5365 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5366 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5367 DAG.getIntPtrConstant(0));
5368 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5369 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5373 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5374 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5376 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5377 DAG.getConstant(0, Op0.getValueType()),
5379 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5380 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5381 SignSet, Four, Zero);
5383 // If the sign bit of the integer is set, the large number will be treated
5384 // as a negative number. To counteract this, the dynamic code adds an
5385 // offset depending on the data type.
5387 switch (Op0.getValueType()) {
5388 default: assert(0 && "Unsupported integer type!");
5389 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5390 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5391 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5392 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5394 if (TLI.isLittleEndian()) FF <<= 32;
5395 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5397 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5398 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5399 SDOperand FudgeInReg;
5400 if (DestVT == MVT::f32)
5401 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5402 PseudoSourceValue::getConstantPool(), 0);
5405 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5406 DAG.getEntryNode(), CPIdx,
5407 PseudoSourceValue::getConstantPool(), 0,
5411 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5414 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5415 /// *INT_TO_FP operation of the specified operand when the target requests that
5416 /// we promote it. At this point, we know that the result and operand types are
5417 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5418 /// operation that takes a larger input.
5419 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5420 MVT::ValueType DestVT,
5422 // First step, figure out the appropriate *INT_TO_FP operation to use.
5423 MVT::ValueType NewInTy = LegalOp.getValueType();
5425 unsigned OpToUse = 0;
5427 // Scan for the appropriate larger type to use.
5429 NewInTy = (MVT::ValueType)(NewInTy+1);
5430 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5432 // If the target supports SINT_TO_FP of this type, use it.
5433 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5435 case TargetLowering::Legal:
5436 if (!TLI.isTypeLegal(NewInTy))
5437 break; // Can't use this datatype.
5439 case TargetLowering::Custom:
5440 OpToUse = ISD::SINT_TO_FP;
5444 if (isSigned) continue;
5446 // If the target supports UINT_TO_FP of this type, use it.
5447 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5449 case TargetLowering::Legal:
5450 if (!TLI.isTypeLegal(NewInTy))
5451 break; // Can't use this datatype.
5453 case TargetLowering::Custom:
5454 OpToUse = ISD::UINT_TO_FP;
5459 // Otherwise, try a larger type.
5462 // Okay, we found the operation and type to use. Zero extend our input to the
5463 // desired type then run the operation on it.
5464 return DAG.getNode(OpToUse, DestVT,
5465 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5469 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5470 /// FP_TO_*INT operation of the specified operand when the target requests that
5471 /// we promote it. At this point, we know that the result and operand types are
5472 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5473 /// operation that returns a larger result.
5474 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5475 MVT::ValueType DestVT,
5477 // First step, figure out the appropriate FP_TO*INT operation to use.
5478 MVT::ValueType NewOutTy = DestVT;
5480 unsigned OpToUse = 0;
5482 // Scan for the appropriate larger type to use.
5484 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5485 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5487 // If the target supports FP_TO_SINT returning this type, use it.
5488 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5490 case TargetLowering::Legal:
5491 if (!TLI.isTypeLegal(NewOutTy))
5492 break; // Can't use this datatype.
5494 case TargetLowering::Custom:
5495 OpToUse = ISD::FP_TO_SINT;
5500 // If the target supports FP_TO_UINT of this type, use it.
5501 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5503 case TargetLowering::Legal:
5504 if (!TLI.isTypeLegal(NewOutTy))
5505 break; // Can't use this datatype.
5507 case TargetLowering::Custom:
5508 OpToUse = ISD::FP_TO_UINT;
5513 // Otherwise, try a larger type.
5517 // Okay, we found the operation and type to use.
5518 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5520 // If the operation produces an invalid type, it must be custom lowered. Use
5521 // the target lowering hooks to expand it. Just keep the low part of the
5522 // expanded operation, we know that we're truncating anyway.
5523 if (getTypeAction(NewOutTy) == Expand) {
5524 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5525 assert(Operation.Val && "Didn't return anything");
5528 // Truncate the result of the extended FP_TO_*INT operation to the desired
5530 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5533 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5535 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5536 MVT::ValueType VT = Op.getValueType();
5537 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5538 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5540 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5542 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5543 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5544 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5546 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5547 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5548 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5549 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5550 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5551 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5552 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5553 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5554 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5556 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5557 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5558 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5559 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5560 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5561 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5562 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5563 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5564 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5565 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5566 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5567 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5568 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5569 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5570 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5571 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5572 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5573 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5574 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5575 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5576 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5580 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5582 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5584 default: assert(0 && "Cannot expand this yet!");
5586 static const uint64_t mask[6] = {
5587 0x5555555555555555ULL, 0x3333333333333333ULL,
5588 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5589 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5591 MVT::ValueType VT = Op.getValueType();
5592 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5593 unsigned len = MVT::getSizeInBits(VT);
5594 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5595 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5596 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5597 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5598 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5599 DAG.getNode(ISD::AND, VT,
5600 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5605 // for now, we do this:
5606 // x = x | (x >> 1);
5607 // x = x | (x >> 2);
5609 // x = x | (x >>16);
5610 // x = x | (x >>32); // for 64-bit input
5611 // return popcount(~x);
5613 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5614 MVT::ValueType VT = Op.getValueType();
5615 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5616 unsigned len = MVT::getSizeInBits(VT);
5617 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5618 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5619 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5621 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5622 return DAG.getNode(ISD::CTPOP, VT, Op);
5625 // for now, we use: { return popcount(~x & (x - 1)); }
5626 // unless the target has ctlz but not ctpop, in which case we use:
5627 // { return 32 - nlz(~x & (x-1)); }
5628 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5629 MVT::ValueType VT = Op.getValueType();
5630 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5631 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5632 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5633 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5634 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5635 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5636 TLI.isOperationLegal(ISD::CTLZ, VT))
5637 return DAG.getNode(ISD::SUB, VT,
5638 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5639 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5640 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5645 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5646 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5647 /// LegalizeNodes map is filled in for any results that are not expanded, the
5648 /// ExpandedNodes map is filled in for any results that are expanded, and the
5649 /// Lo/Hi values are returned.
5650 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5651 MVT::ValueType VT = Op.getValueType();
5652 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5653 SDNode *Node = Op.Val;
5654 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5655 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5656 MVT::isVector(VT)) &&
5657 "Cannot expand to FP value or to larger int value!");
5659 // See if we already expanded it.
5660 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5661 = ExpandedNodes.find(Op);
5662 if (I != ExpandedNodes.end()) {
5663 Lo = I->second.first;
5664 Hi = I->second.second;
5668 switch (Node->getOpcode()) {
5669 case ISD::CopyFromReg:
5670 assert(0 && "CopyFromReg must be legal!");
5671 case ISD::FP_ROUND_INREG:
5672 if (VT == MVT::ppcf128 &&
5673 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5674 TargetLowering::Custom) {
5675 SDOperand SrcLo, SrcHi, Src;
5676 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5677 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5678 SDOperand Result = TLI.LowerOperation(
5679 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5680 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5681 Lo = Result.Val->getOperand(0);
5682 Hi = Result.Val->getOperand(1);
5688 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5690 assert(0 && "Do not know how to expand this operator!");
5692 case ISD::EXTRACT_VECTOR_ELT:
5693 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5694 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5695 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5696 return ExpandOp(Lo, Lo, Hi);
5698 NVT = TLI.getTypeToExpandTo(VT);
5699 Lo = DAG.getNode(ISD::UNDEF, NVT);
5700 Hi = DAG.getNode(ISD::UNDEF, NVT);
5702 case ISD::Constant: {
5703 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5704 Lo = DAG.getConstant(Cst, NVT);
5705 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5708 case ISD::ConstantFP: {
5709 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5710 if (CFP->getValueType(0) == MVT::ppcf128) {
5711 APInt api = CFP->getValueAPF().convertToAPInt();
5712 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5714 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5718 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5719 if (getTypeAction(Lo.getValueType()) == Expand)
5720 ExpandOp(Lo, Lo, Hi);
5723 case ISD::BUILD_PAIR:
5724 // Return the operands.
5725 Lo = Node->getOperand(0);
5726 Hi = Node->getOperand(1);
5729 case ISD::MERGE_VALUES:
5730 if (Node->getNumValues() == 1) {
5731 ExpandOp(Op.getOperand(0), Lo, Hi);
5734 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5735 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5736 Op.getValue(1).getValueType() == MVT::Other &&
5737 "unhandled MERGE_VALUES");
5738 ExpandOp(Op.getOperand(0), Lo, Hi);
5739 // Remember that we legalized the chain.
5740 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5743 case ISD::SIGN_EXTEND_INREG:
5744 ExpandOp(Node->getOperand(0), Lo, Hi);
5745 // sext_inreg the low part if needed.
5746 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5748 // The high part gets the sign extension from the lo-part. This handles
5749 // things like sextinreg V:i64 from i8.
5750 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5751 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5752 TLI.getShiftAmountTy()));
5756 ExpandOp(Node->getOperand(0), Lo, Hi);
5757 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5758 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5764 ExpandOp(Node->getOperand(0), Lo, Hi);
5765 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5766 DAG.getNode(ISD::CTPOP, NVT, Lo),
5767 DAG.getNode(ISD::CTPOP, NVT, Hi));
5768 Hi = DAG.getConstant(0, NVT);
5772 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5773 ExpandOp(Node->getOperand(0), Lo, Hi);
5774 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5775 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5776 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5778 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5779 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5781 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5782 Hi = DAG.getConstant(0, NVT);
5787 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5788 ExpandOp(Node->getOperand(0), Lo, Hi);
5789 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5790 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5791 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5793 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5794 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5796 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5797 Hi = DAG.getConstant(0, NVT);
5802 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5803 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5804 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5805 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5807 // Remember that we legalized the chain.
5808 Hi = LegalizeOp(Hi);
5809 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5810 if (TLI.isBigEndian())
5816 LoadSDNode *LD = cast<LoadSDNode>(Node);
5817 SDOperand Ch = LD->getChain(); // Legalize the chain.
5818 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5819 ISD::LoadExtType ExtType = LD->getExtensionType();
5820 int SVOffset = LD->getSrcValueOffset();
5821 unsigned Alignment = LD->getAlignment();
5822 bool isVolatile = LD->isVolatile();
5824 if (ExtType == ISD::NON_EXTLOAD) {
5825 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5826 isVolatile, Alignment);
5827 if (VT == MVT::f32 || VT == MVT::f64) {
5828 // f32->i32 or f64->i64 one to one expansion.
5829 // Remember that we legalized the chain.
5830 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5831 // Recursively expand the new load.
5832 if (getTypeAction(NVT) == Expand)
5833 ExpandOp(Lo, Lo, Hi);
5837 // Increment the pointer to the other half.
5838 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5839 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5840 DAG.getIntPtrConstant(IncrementSize));
5841 SVOffset += IncrementSize;
5842 Alignment = MinAlign(Alignment, IncrementSize);
5843 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5844 isVolatile, Alignment);
5846 // Build a factor node to remember that this load is independent of the
5848 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5851 // Remember that we legalized the chain.
5852 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5853 if (TLI.isBigEndian())
5856 MVT::ValueType EVT = LD->getMemoryVT();
5858 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5859 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5860 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5861 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5862 SVOffset, isVolatile, Alignment);
5863 // Remember that we legalized the chain.
5864 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5865 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5870 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5871 SVOffset, isVolatile, Alignment);
5873 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5874 SVOffset, EVT, isVolatile,
5877 // Remember that we legalized the chain.
5878 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5880 if (ExtType == ISD::SEXTLOAD) {
5881 // The high part is obtained by SRA'ing all but one of the bits of the
5883 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5884 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5885 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5886 } else if (ExtType == ISD::ZEXTLOAD) {
5887 // The high part is just a zero.
5888 Hi = DAG.getConstant(0, NVT);
5889 } else /* if (ExtType == ISD::EXTLOAD) */ {
5890 // The high part is undefined.
5891 Hi = DAG.getNode(ISD::UNDEF, NVT);
5898 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5899 SDOperand LL, LH, RL, RH;
5900 ExpandOp(Node->getOperand(0), LL, LH);
5901 ExpandOp(Node->getOperand(1), RL, RH);
5902 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5903 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5907 SDOperand LL, LH, RL, RH;
5908 ExpandOp(Node->getOperand(1), LL, LH);
5909 ExpandOp(Node->getOperand(2), RL, RH);
5910 if (getTypeAction(NVT) == Expand)
5911 NVT = TLI.getTypeToExpandTo(NVT);
5912 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5914 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5917 case ISD::SELECT_CC: {
5918 SDOperand TL, TH, FL, FH;
5919 ExpandOp(Node->getOperand(2), TL, TH);
5920 ExpandOp(Node->getOperand(3), FL, FH);
5921 if (getTypeAction(NVT) == Expand)
5922 NVT = TLI.getTypeToExpandTo(NVT);
5923 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5924 Node->getOperand(1), TL, FL, Node->getOperand(4));
5926 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5927 Node->getOperand(1), TH, FH, Node->getOperand(4));
5930 case ISD::ANY_EXTEND:
5931 // The low part is any extension of the input (which degenerates to a copy).
5932 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5933 // The high part is undefined.
5934 Hi = DAG.getNode(ISD::UNDEF, NVT);
5936 case ISD::SIGN_EXTEND: {
5937 // The low part is just a sign extension of the input (which degenerates to
5939 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5941 // The high part is obtained by SRA'ing all but one of the bits of the lo
5943 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5944 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5945 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5948 case ISD::ZERO_EXTEND:
5949 // The low part is just a zero extension of the input (which degenerates to
5951 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5953 // The high part is just a zero.
5954 Hi = DAG.getConstant(0, NVT);
5957 case ISD::TRUNCATE: {
5958 // The input value must be larger than this value. Expand *it*.
5960 ExpandOp(Node->getOperand(0), NewLo, Hi);
5962 // The low part is now either the right size, or it is closer. If not the
5963 // right size, make an illegal truncate so we recursively expand it.
5964 if (NewLo.getValueType() != Node->getValueType(0))
5965 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5966 ExpandOp(NewLo, Lo, Hi);
5970 case ISD::BIT_CONVERT: {
5972 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5973 // If the target wants to, allow it to lower this itself.
5974 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5975 case Expand: assert(0 && "cannot expand FP!");
5976 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5977 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5979 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5982 // f32 / f64 must be expanded to i32 / i64.
5983 if (VT == MVT::f32 || VT == MVT::f64) {
5984 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5985 if (getTypeAction(NVT) == Expand)
5986 ExpandOp(Lo, Lo, Hi);
5990 // If source operand will be expanded to the same type as VT, i.e.
5991 // i64 <- f64, i32 <- f32, expand the source operand instead.
5992 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5993 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5994 ExpandOp(Node->getOperand(0), Lo, Hi);
5998 // Turn this into a load/store pair by default.
6000 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6002 ExpandOp(Tmp, Lo, Hi);
6006 case ISD::READCYCLECOUNTER: {
6007 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6008 TargetLowering::Custom &&
6009 "Must custom expand ReadCycleCounter");
6010 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6011 assert(Tmp.Val && "Node must be custom expanded!");
6012 ExpandOp(Tmp.getValue(0), Lo, Hi);
6013 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6014 LegalizeOp(Tmp.getValue(1)));
6018 // These operators cannot be expanded directly, emit them as calls to
6019 // library functions.
6020 case ISD::FP_TO_SINT: {
6021 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6023 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6024 case Expand: assert(0 && "cannot expand FP!");
6025 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6026 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6029 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6031 // Now that the custom expander is done, expand the result, which is still
6034 ExpandOp(Op, Lo, Hi);
6039 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6040 if (Node->getOperand(0).getValueType() == MVT::f32)
6041 LC = RTLIB::FPTOSINT_F32_I64;
6042 else if (Node->getOperand(0).getValueType() == MVT::f64)
6043 LC = RTLIB::FPTOSINT_F64_I64;
6044 else if (Node->getOperand(0).getValueType() == MVT::f80)
6045 LC = RTLIB::FPTOSINT_F80_I64;
6046 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6047 LC = RTLIB::FPTOSINT_PPCF128_I64;
6048 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6049 false/*sign irrelevant*/, Hi);
6053 case ISD::FP_TO_UINT: {
6054 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6056 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6057 case Expand: assert(0 && "cannot expand FP!");
6058 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6059 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6062 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6064 // Now that the custom expander is done, expand the result.
6066 ExpandOp(Op, Lo, Hi);
6071 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6072 if (Node->getOperand(0).getValueType() == MVT::f32)
6073 LC = RTLIB::FPTOUINT_F32_I64;
6074 else if (Node->getOperand(0).getValueType() == MVT::f64)
6075 LC = RTLIB::FPTOUINT_F64_I64;
6076 else if (Node->getOperand(0).getValueType() == MVT::f80)
6077 LC = RTLIB::FPTOUINT_F80_I64;
6078 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6079 LC = RTLIB::FPTOUINT_PPCF128_I64;
6080 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6081 false/*sign irrelevant*/, Hi);
6086 // If the target wants custom lowering, do so.
6087 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6088 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6089 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6090 Op = TLI.LowerOperation(Op, DAG);
6092 // Now that the custom expander is done, expand the result, which is
6094 ExpandOp(Op, Lo, Hi);
6099 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6100 // this X << 1 as X+X.
6101 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6102 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6103 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6104 SDOperand LoOps[2], HiOps[3];
6105 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6106 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6107 LoOps[1] = LoOps[0];
6108 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6110 HiOps[1] = HiOps[0];
6111 HiOps[2] = Lo.getValue(1);
6112 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6117 // If we can emit an efficient shift operation, do so now.
6118 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6121 // If this target supports SHL_PARTS, use it.
6122 TargetLowering::LegalizeAction Action =
6123 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6124 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6125 Action == TargetLowering::Custom) {
6126 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6130 // Otherwise, emit a libcall.
6131 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6132 false/*left shift=unsigned*/, Hi);
6137 // If the target wants custom lowering, do so.
6138 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6139 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6140 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6141 Op = TLI.LowerOperation(Op, DAG);
6143 // Now that the custom expander is done, expand the result, which is
6145 ExpandOp(Op, Lo, Hi);
6150 // If we can emit an efficient shift operation, do so now.
6151 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6154 // If this target supports SRA_PARTS, use it.
6155 TargetLowering::LegalizeAction Action =
6156 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6157 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6158 Action == TargetLowering::Custom) {
6159 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6163 // Otherwise, emit a libcall.
6164 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6165 true/*ashr is signed*/, Hi);
6170 // If the target wants custom lowering, do so.
6171 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6172 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6173 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6174 Op = TLI.LowerOperation(Op, DAG);
6176 // Now that the custom expander is done, expand the result, which is
6178 ExpandOp(Op, Lo, Hi);
6183 // If we can emit an efficient shift operation, do so now.
6184 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6187 // If this target supports SRL_PARTS, use it.
6188 TargetLowering::LegalizeAction Action =
6189 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6190 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6191 Action == TargetLowering::Custom) {
6192 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6196 // Otherwise, emit a libcall.
6197 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6198 false/*lshr is unsigned*/, Hi);
6204 // If the target wants to custom expand this, let them.
6205 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6206 TargetLowering::Custom) {
6207 Op = TLI.LowerOperation(Op, DAG);
6209 ExpandOp(Op, Lo, Hi);
6214 // Expand the subcomponents.
6215 SDOperand LHSL, LHSH, RHSL, RHSH;
6216 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6217 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6218 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6219 SDOperand LoOps[2], HiOps[3];
6224 if (Node->getOpcode() == ISD::ADD) {
6225 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6226 HiOps[2] = Lo.getValue(1);
6227 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6229 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6230 HiOps[2] = Lo.getValue(1);
6231 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6238 // Expand the subcomponents.
6239 SDOperand LHSL, LHSH, RHSL, RHSH;
6240 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6241 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6242 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6243 SDOperand LoOps[2] = { LHSL, RHSL };
6244 SDOperand HiOps[3] = { LHSH, RHSH };
6246 if (Node->getOpcode() == ISD::ADDC) {
6247 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6248 HiOps[2] = Lo.getValue(1);
6249 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6251 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6252 HiOps[2] = Lo.getValue(1);
6253 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6255 // Remember that we legalized the flag.
6256 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6261 // Expand the subcomponents.
6262 SDOperand LHSL, LHSH, RHSL, RHSH;
6263 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6264 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6265 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6266 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6267 SDOperand HiOps[3] = { LHSH, RHSH };
6269 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6270 HiOps[2] = Lo.getValue(1);
6271 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6273 // Remember that we legalized the flag.
6274 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6278 // If the target wants to custom expand this, let them.
6279 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6280 SDOperand New = TLI.LowerOperation(Op, DAG);
6282 ExpandOp(New, Lo, Hi);
6287 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6288 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6289 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6290 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6291 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6292 SDOperand LL, LH, RL, RH;
6293 ExpandOp(Node->getOperand(0), LL, LH);
6294 ExpandOp(Node->getOperand(1), RL, RH);
6295 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6296 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6297 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6298 // FIXME: generalize this to handle other bit sizes
6299 if (LHSSB == 32 && RHSSB == 32 &&
6300 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6301 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6302 // The inputs are both zero-extended.
6304 // We can emit a umul_lohi.
6305 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6306 Hi = SDOperand(Lo.Val, 1);
6310 // We can emit a mulhu+mul.
6311 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6312 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6316 if (LHSSB > BitSize && RHSSB > BitSize) {
6317 // The input values are both sign-extended.
6319 // We can emit a smul_lohi.
6320 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6321 Hi = SDOperand(Lo.Val, 1);
6325 // We can emit a mulhs+mul.
6326 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6327 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6332 // Lo,Hi = umul LHS, RHS.
6333 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6334 DAG.getVTList(NVT, NVT), LL, RL);
6336 Hi = UMulLOHI.getValue(1);
6337 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6338 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6339 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6340 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6344 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6345 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6346 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6347 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6348 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6349 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6354 // If nothing else, we can make a libcall.
6355 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6356 false/*sign irrelevant*/, Hi);
6360 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6363 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6366 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6369 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6373 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6376 RTLIB::ADD_PPCF128)),
6380 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6383 RTLIB::SUB_PPCF128)),
6387 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6390 RTLIB::MUL_PPCF128)),
6394 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6397 RTLIB::DIV_PPCF128)),
6400 case ISD::FP_EXTEND:
6401 if (VT == MVT::ppcf128) {
6402 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6403 Node->getOperand(0).getValueType()==MVT::f64);
6404 const uint64_t zero = 0;
6405 if (Node->getOperand(0).getValueType()==MVT::f32)
6406 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6408 Hi = Node->getOperand(0);
6409 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6412 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6415 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6418 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6421 RTLIB::POWI_PPCF128)),
6427 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6428 switch(Node->getOpcode()) {
6430 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6431 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6434 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6435 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6438 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6439 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6441 default: assert(0 && "Unreachable!");
6443 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6447 if (VT == MVT::ppcf128) {
6449 ExpandOp(Node->getOperand(0), Lo, Tmp);
6450 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6451 // lo = hi==fabs(hi) ? lo : -lo;
6452 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6453 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6454 DAG.getCondCode(ISD::SETEQ));
6457 SDOperand Mask = (VT == MVT::f64)
6458 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6459 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6460 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6461 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6462 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6463 if (getTypeAction(NVT) == Expand)
6464 ExpandOp(Lo, Lo, Hi);
6468 if (VT == MVT::ppcf128) {
6469 ExpandOp(Node->getOperand(0), Lo, Hi);
6470 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6471 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6474 SDOperand Mask = (VT == MVT::f64)
6475 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6476 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6477 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6478 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6479 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6480 if (getTypeAction(NVT) == Expand)
6481 ExpandOp(Lo, Lo, Hi);
6484 case ISD::FCOPYSIGN: {
6485 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6486 if (getTypeAction(NVT) == Expand)
6487 ExpandOp(Lo, Lo, Hi);
6490 case ISD::SINT_TO_FP:
6491 case ISD::UINT_TO_FP: {
6492 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6493 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6494 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6495 static uint64_t zero = 0;
6497 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6498 Node->getOperand(0)));
6499 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6501 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6502 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6503 Node->getOperand(0)));
6504 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6505 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6506 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6507 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6508 DAG.getConstant(0, MVT::i32),
6509 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6511 APFloat(APInt(128, 2, TwoE32)),
6514 DAG.getCondCode(ISD::SETLT)),
6519 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6520 // si64->ppcf128 done by libcall, below
6521 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6522 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6524 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6525 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6526 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6527 DAG.getConstant(0, MVT::i64),
6528 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6530 APFloat(APInt(128, 2, TwoE64)),
6533 DAG.getCondCode(ISD::SETLT)),
6537 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6538 if (Node->getOperand(0).getValueType() == MVT::i64) {
6540 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6541 else if (VT == MVT::f64)
6542 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6543 else if (VT == MVT::f80) {
6545 LC = RTLIB::SINTTOFP_I64_F80;
6547 else if (VT == MVT::ppcf128) {
6549 LC = RTLIB::SINTTOFP_I64_PPCF128;
6553 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6555 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6558 // Promote the operand if needed.
6559 if (getTypeAction(SrcVT) == Promote) {
6560 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6562 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6563 DAG.getValueType(SrcVT))
6564 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6565 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6568 const char *LibCall = TLI.getLibcallName(LC);
6570 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6572 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6573 Node->getOperand(0));
6574 if (getTypeAction(Lo.getValueType()) == Expand)
6575 ExpandOp(Lo, Lo, Hi);
6581 // Make sure the resultant values have been legalized themselves, unless this
6582 // is a type that requires multi-step expansion.
6583 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6584 Lo = LegalizeOp(Lo);
6586 // Don't legalize the high part if it is expanded to a single node.
6587 Hi = LegalizeOp(Hi);
6590 // Remember in a map if the values will be reused later.
6591 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6592 assert(isNew && "Value already expanded?!?");
6595 /// SplitVectorOp - Given an operand of vector type, break it down into
6596 /// two smaller values, still of vector type.
6597 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6599 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6600 SDNode *Node = Op.Val;
6601 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6602 assert(NumElements > 1 && "Cannot split a single element vector!");
6604 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6606 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6607 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6609 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6610 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6612 // See if we already split it.
6613 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6614 = SplitNodes.find(Op);
6615 if (I != SplitNodes.end()) {
6616 Lo = I->second.first;
6617 Hi = I->second.second;
6621 switch (Node->getOpcode()) {
6626 assert(0 && "Unhandled operation in SplitVectorOp!");
6628 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6629 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6631 case ISD::BUILD_PAIR:
6632 Lo = Node->getOperand(0);
6633 Hi = Node->getOperand(1);
6635 case ISD::INSERT_VECTOR_ELT: {
6636 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6637 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6638 SDOperand ScalarOp = Node->getOperand(1);
6639 if (Index < NewNumElts_Lo)
6640 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6641 DAG.getConstant(Index, TLI.getPointerTy()));
6643 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6644 DAG.getConstant(Index - NewNumElts_Lo,
6645 TLI.getPointerTy()));
6648 case ISD::VECTOR_SHUFFLE: {
6649 // Build the low part.
6650 SDOperand Mask = Node->getOperand(2);
6651 SmallVector<SDOperand, 8> Ops;
6652 MVT::ValueType PtrVT = TLI.getPointerTy();
6654 // Insert all of the elements from the input that are needed. We use
6655 // buildvector of extractelement here because the input vectors will have
6656 // to be legalized, so this makes the code simpler.
6657 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6658 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6659 SDOperand InVec = Node->getOperand(0);
6660 if (Idx >= NumElements) {
6661 InVec = Node->getOperand(1);
6664 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6665 DAG.getConstant(Idx, PtrVT)));
6667 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6670 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6671 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6672 SDOperand InVec = Node->getOperand(0);
6673 if (Idx >= NumElements) {
6674 InVec = Node->getOperand(1);
6677 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6678 DAG.getConstant(Idx, PtrVT)));
6680 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6683 case ISD::BUILD_VECTOR: {
6684 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6685 Node->op_begin()+NewNumElts_Lo);
6686 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6688 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6690 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6693 case ISD::CONCAT_VECTORS: {
6694 // FIXME: Handle non-power-of-two vectors?
6695 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6696 if (NewNumSubvectors == 1) {
6697 Lo = Node->getOperand(0);
6698 Hi = Node->getOperand(1);
6700 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6701 Node->op_begin()+NewNumSubvectors);
6702 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6704 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6706 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6711 SDOperand Cond = Node->getOperand(0);
6713 SDOperand LL, LH, RL, RH;
6714 SplitVectorOp(Node->getOperand(1), LL, LH);
6715 SplitVectorOp(Node->getOperand(2), RL, RH);
6717 if (MVT::isVector(Cond.getValueType())) {
6718 // Handle a vector merge.
6720 SplitVectorOp(Cond, CL, CH);
6721 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6722 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6724 // Handle a simple select with vector operands.
6725 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6726 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6746 SDOperand LL, LH, RL, RH;
6747 SplitVectorOp(Node->getOperand(0), LL, LH);
6748 SplitVectorOp(Node->getOperand(1), RL, RH);
6750 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6751 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6756 SplitVectorOp(Node->getOperand(0), L, H);
6758 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6759 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6770 case ISD::FP_TO_SINT:
6771 case ISD::FP_TO_UINT:
6772 case ISD::SINT_TO_FP:
6773 case ISD::UINT_TO_FP: {
6775 SplitVectorOp(Node->getOperand(0), L, H);
6777 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6778 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6782 LoadSDNode *LD = cast<LoadSDNode>(Node);
6783 SDOperand Ch = LD->getChain();
6784 SDOperand Ptr = LD->getBasePtr();
6785 const Value *SV = LD->getSrcValue();
6786 int SVOffset = LD->getSrcValueOffset();
6787 unsigned Alignment = LD->getAlignment();
6788 bool isVolatile = LD->isVolatile();
6790 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6791 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6792 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6793 DAG.getIntPtrConstant(IncrementSize));
6794 SVOffset += IncrementSize;
6795 Alignment = MinAlign(Alignment, IncrementSize);
6796 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6798 // Build a factor node to remember that this load is independent of the
6800 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6803 // Remember that we legalized the chain.
6804 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6807 case ISD::BIT_CONVERT: {
6808 // We know the result is a vector. The input may be either a vector or a
6810 SDOperand InOp = Node->getOperand(0);
6811 if (!MVT::isVector(InOp.getValueType()) ||
6812 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6813 // The input is a scalar or single-element vector.
6814 // Lower to a store/load so that it can be split.
6815 // FIXME: this could be improved probably.
6816 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6817 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6819 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6821 PseudoSourceValue::getFixedStack(),
6823 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6824 PseudoSourceValue::getFixedStack(),
6827 // Split the vector and convert each of the pieces now.
6828 SplitVectorOp(InOp, Lo, Hi);
6829 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6830 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6835 // Remember in a map if the values will be reused later.
6837 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6838 assert(isNew && "Value already split?!?");
6842 /// ScalarizeVectorOp - Given an operand of single-element vector type
6843 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6844 /// scalar (e.g. f32) value.
6845 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6846 assert(MVT::isVector(Op.getValueType()) &&
6847 "Bad ScalarizeVectorOp invocation!");
6848 SDNode *Node = Op.Val;
6849 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6850 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6852 // See if we already scalarized it.
6853 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6854 if (I != ScalarizedNodes.end()) return I->second;
6857 switch (Node->getOpcode()) {
6860 Node->dump(&DAG); cerr << "\n";
6862 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6879 Result = DAG.getNode(Node->getOpcode(),
6881 ScalarizeVectorOp(Node->getOperand(0)),
6882 ScalarizeVectorOp(Node->getOperand(1)));
6889 Result = DAG.getNode(Node->getOpcode(),
6891 ScalarizeVectorOp(Node->getOperand(0)));
6894 Result = DAG.getNode(Node->getOpcode(),
6896 ScalarizeVectorOp(Node->getOperand(0)),
6897 Node->getOperand(1));
6900 LoadSDNode *LD = cast<LoadSDNode>(Node);
6901 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6902 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6904 const Value *SV = LD->getSrcValue();
6905 int SVOffset = LD->getSrcValueOffset();
6906 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6907 LD->isVolatile(), LD->getAlignment());
6909 // Remember that we legalized the chain.
6910 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6913 case ISD::BUILD_VECTOR:
6914 Result = Node->getOperand(0);
6916 case ISD::INSERT_VECTOR_ELT:
6917 // Returning the inserted scalar element.
6918 Result = Node->getOperand(1);
6920 case ISD::CONCAT_VECTORS:
6921 assert(Node->getOperand(0).getValueType() == NewVT &&
6922 "Concat of non-legal vectors not yet supported!");
6923 Result = Node->getOperand(0);
6925 case ISD::VECTOR_SHUFFLE: {
6926 // Figure out if the scalar is the LHS or RHS and return it.
6927 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6928 if (cast<ConstantSDNode>(EltNum)->getValue())
6929 Result = ScalarizeVectorOp(Node->getOperand(1));
6931 Result = ScalarizeVectorOp(Node->getOperand(0));
6934 case ISD::EXTRACT_SUBVECTOR:
6935 Result = Node->getOperand(0);
6936 assert(Result.getValueType() == NewVT);
6938 case ISD::BIT_CONVERT:
6939 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6942 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6943 ScalarizeVectorOp(Op.getOperand(1)),
6944 ScalarizeVectorOp(Op.getOperand(2)));
6948 if (TLI.isTypeLegal(NewVT))
6949 Result = LegalizeOp(Result);
6950 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6951 assert(isNew && "Value already scalarized?");
6956 // SelectionDAG::Legalize - This is the entry point for the file.
6958 void SelectionDAG::Legalize() {
6959 if (ViewLegalizeDAGs) viewGraph();
6961 /// run - This is the main entry point to this class.
6963 SelectionDAGLegalize(*this).LegalizeDAG();