1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// UnrollVectorOp - We know that the given vector has a legal type, however
151 /// the operation it performs is not legal and is an operation that we have
152 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
153 /// operating on each element individually.
154 SDOperand UnrollVectorOp(SDOperand O);
156 /// PromoteOp - Given an operation that produces a value in an invalid type,
157 /// promote it to compute the value into a larger type. The produced value
158 /// will have the correct bits for the low portion of the register, but no
159 /// guarantee is made about the top bits: it may be zero, sign-extended, or
161 SDOperand PromoteOp(SDOperand O);
163 /// ExpandOp - Expand the specified SDOperand into its two component pieces
164 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
165 /// the LegalizeNodes map is filled in for any results that are not expanded,
166 /// the ExpandedNodes map is filled in for any results that are expanded, and
167 /// the Lo/Hi values are returned. This applies to integer types and Vector
169 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
171 /// SplitVectorOp - Given an operand of vector type, break it down into
172 /// two smaller values.
173 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
175 /// ScalarizeVectorOp - Given an operand of single-element vector type
176 /// (e.g. v1f32), convert it into the equivalent operation that returns a
177 /// scalar (e.g. f32) value.
178 SDOperand ScalarizeVectorOp(SDOperand O);
180 /// isShuffleLegal - Return true if a vector shuffle is legal with the
181 /// specified mask and type. Targets can specify exactly which masks they
182 /// support and the code generator is tasked with not creating illegal masks.
184 /// Note that this will also return true for shuffles that are promoted to a
187 /// If this is a legal shuffle, this method returns the (possibly promoted)
188 /// build_vector Mask. If it's not a legal shuffle, it returns null.
189 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
191 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
192 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
194 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
196 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
198 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
201 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
202 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
203 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
206 MVT::ValueType DestVT);
207 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
209 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand ExpandBSWAP(SDOperand Op);
213 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
214 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
215 SDOperand &Lo, SDOperand &Hi);
216 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
217 SDOperand &Lo, SDOperand &Hi);
219 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
220 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
222 SDOperand getIntPtrConstant(uint64_t Val) {
223 return DAG.getConstant(Val, TLI.getPointerTy());
228 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
229 /// specified mask and type. Targets can specify exactly which masks they
230 /// support and the code generator is tasked with not creating illegal masks.
232 /// Note that this will also return true for shuffles that are promoted to a
234 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
235 SDOperand Mask) const {
236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
238 case TargetLowering::Legal:
239 case TargetLowering::Custom:
241 case TargetLowering::Promote: {
242 // If this is promoted to a different type, convert the shuffle mask and
243 // ask if it is legal in the promoted type!
244 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
246 // If we changed # elements, change the shuffle mask.
247 unsigned NumEltsGrowth =
248 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
250 if (NumEltsGrowth > 1) {
251 // Renumber the elements.
252 SmallVector<SDOperand, 8> Ops;
253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
254 SDOperand InOp = Mask.getOperand(i);
255 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
256 if (InOp.getOpcode() == ISD::UNDEF)
257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
273 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
274 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
275 ValueTypeActions(TLI.getValueTypeActions()) {
276 assert(MVT::LAST_VALUETYPE <= 32 &&
277 "Too many value types for ValueTypeActions to hold!");
280 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
281 /// contains all of a nodes operands before it contains the node.
282 static void ComputeTopDownOrdering(SelectionDAG &DAG,
283 SmallVector<SDNode*, 64> &Order) {
285 DenseMap<SDNode*, unsigned> Visited;
286 std::vector<SDNode*> Worklist;
287 Worklist.reserve(128);
289 // Compute ordering from all of the leaves in the graphs, those (like the
290 // entry node) that have no operands.
291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
292 E = DAG.allnodes_end(); I != E; ++I) {
293 if (I->getNumOperands() == 0) {
295 Worklist.push_back(I);
299 while (!Worklist.empty()) {
300 SDNode *N = Worklist.back();
303 if (++Visited[N] != N->getNumOperands())
304 continue; // Haven't visited all operands yet
308 // Now that we have N in, add anything that uses it if all of their operands
310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
312 Worklist.push_back(*UI);
315 assert(Order.size() == Visited.size() &&
317 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
318 "Error: DAG is cyclic!");
322 void SelectionDAGLegalize::LegalizeDAG() {
323 LastCALLSEQ_END = DAG.getEntryNode();
324 IsLegalizingCall = false;
326 // The legalize process is inherently a bottom-up recursive process (users
327 // legalize their uses before themselves). Given infinite stack space, we
328 // could just start legalizing on the root and traverse the whole graph. In
329 // practice however, this causes us to run out of stack space on large basic
330 // blocks. To avoid this problem, compute an ordering of the nodes where each
331 // node is only legalized after all of its operands are legalized.
332 SmallVector<SDNode*, 64> Order;
333 ComputeTopDownOrdering(DAG, Order);
335 for (unsigned i = 0, e = Order.size(); i != e; ++i)
336 HandleOp(SDOperand(Order[i], 0));
338 // Finally, it's possible the root changed. Get the new root.
339 SDOperand OldRoot = DAG.getRoot();
340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
341 DAG.setRoot(LegalizedNodes[OldRoot]);
343 ExpandedNodes.clear();
344 LegalizedNodes.clear();
345 PromotedNodes.clear();
347 ScalarizedNodes.clear();
349 // Remove dead nodes now.
350 DAG.RemoveDeadNodes();
354 /// FindCallEndFromCallStart - Given a chained node that is part of a call
355 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
356 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
357 if (Node->getOpcode() == ISD::CALLSEQ_END)
359 if (Node->use_empty())
360 return 0; // No CallSeqEnd
362 // The chain is usually at the end.
363 SDOperand TheChain(Node, Node->getNumValues()-1);
364 if (TheChain.getValueType() != MVT::Other) {
365 // Sometimes it's at the beginning.
366 TheChain = SDOperand(Node, 0);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Otherwise, hunt for it.
369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
370 if (Node->getValueType(i) == MVT::Other) {
371 TheChain = SDOperand(Node, i);
375 // Otherwise, we walked into a node without a chain.
376 if (TheChain.getValueType() != MVT::Other)
381 for (SDNode::use_iterator UI = Node->use_begin(),
382 E = Node->use_end(); UI != E; ++UI) {
384 // Make sure to only follow users of our token chain.
386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
387 if (User->getOperand(i) == TheChain)
388 if (SDNode *Result = FindCallEndFromCallStart(User))
394 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
395 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
396 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
397 assert(Node && "Didn't find callseq_start for a call??");
398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
400 assert(Node->getOperand(0).getValueType() == MVT::Other &&
401 "Node doesn't have a token chain argument!");
402 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
405 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
406 /// see if any uses can reach Dest. If no dest operands can get to dest,
407 /// legalize them, legalize ourself, and return false, otherwise, return true.
409 /// Keep track of the nodes we fine that actually do lead to Dest in
410 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
412 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
413 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
414 if (N == Dest) return true; // N certainly leads to Dest :)
416 // If we've already processed this node and it does lead to Dest, there is no
417 // need to reprocess it.
418 if (NodesLeadingTo.count(N)) return true;
420 // If the first result of this node has been already legalized, then it cannot
422 switch (getTypeAction(N->getValueType(0))) {
424 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
427 if (PromotedNodes.count(SDOperand(N, 0))) return false;
430 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
434 // Okay, this node has not already been legalized. Check and legalize all
435 // operands. If none lead to Dest, then we can legalize this node.
436 bool OperandsLeadToDest = false;
437 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
438 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
439 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
441 if (OperandsLeadToDest) {
442 NodesLeadingTo.insert(N);
446 // Okay, this node looks safe, legalize it and return false.
447 HandleOp(SDOperand(N, 0));
451 /// HandleOp - Legalize, Promote, or Expand the specified operand as
452 /// appropriate for its type.
453 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
454 MVT::ValueType VT = Op.getValueType();
455 switch (getTypeAction(VT)) {
456 default: assert(0 && "Bad type action!");
457 case Legal: (void)LegalizeOp(Op); break;
458 case Promote: (void)PromoteOp(Op); break;
460 if (!MVT::isVector(VT)) {
461 // If this is an illegal scalar, expand it into its two component
464 if (Op.getOpcode() == ISD::TargetConstant)
465 break; // Allow illegal target nodes.
467 } else if (MVT::getVectorNumElements(VT) == 1) {
468 // If this is an illegal single element vector, convert it to a
470 (void)ScalarizeVectorOp(Op);
472 // Otherwise, this is an illegal multiple element vector.
473 // Split it in half and legalize both parts.
475 SplitVectorOp(Op, X, Y);
481 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
482 /// a load from the constant pool.
483 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
484 SelectionDAG &DAG, TargetLowering &TLI) {
487 // If a FP immediate is precise when represented as a float and if the
488 // target can do an extending load from float to double, we put it into
489 // the constant pool as a float, even if it's is statically typed as a
491 MVT::ValueType VT = CFP->getValueType(0);
492 bool isDouble = VT == MVT::f64;
493 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
496 if (VT!=MVT::f64 && VT!=MVT::f32)
497 assert(0 && "Invalid type expansion");
498 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
499 isDouble ? MVT::i64 : MVT::i32);
502 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
503 // Only do this if the target has a native EXTLOAD instruction from f32.
504 // Do not try to be clever about long doubles (so far)
505 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
506 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
511 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
513 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
514 CPIdx, NULL, 0, MVT::f32);
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
521 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
524 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
525 SelectionDAG &DAG, TargetLowering &TLI) {
526 MVT::ValueType VT = Node->getValueType(0);
527 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
528 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
529 "fcopysign expansion only supported for f32 and f64");
530 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
532 // First get the sign bit of second operand.
533 SDOperand Mask1 = (SrcVT == MVT::f64)
534 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
535 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
536 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
537 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
538 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
539 // Shift right or sign-extend it if the two operands have different types.
540 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
542 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
543 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
544 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
545 } else if (SizeDiff < 0)
546 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
548 // Clear the sign bit of first operand.
549 SDOperand Mask2 = (VT == MVT::f64)
550 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
551 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
552 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
553 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
554 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
556 // Or the value with the sign bit.
557 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
561 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
563 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
564 TargetLowering &TLI) {
565 SDOperand Chain = ST->getChain();
566 SDOperand Ptr = ST->getBasePtr();
567 SDOperand Val = ST->getValue();
568 MVT::ValueType VT = Val.getValueType();
569 int Alignment = ST->getAlignment();
570 int SVOffset = ST->getSrcValueOffset();
571 if (MVT::isFloatingPoint(ST->getStoredVT())) {
572 // Expand to a bitconvert of the value to the integer type of the
573 // same size, then a (misaligned) int store.
574 MVT::ValueType intVT;
577 else if (VT==MVT::f32)
580 assert(0 && "Unaligned load of unsupported floating point type");
582 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
583 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
584 SVOffset, ST->isVolatile(), Alignment);
586 assert(MVT::isInteger(ST->getStoredVT()) &&
587 "Unaligned store of unknown type.");
588 // Get the half-size VT
589 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
590 int NumBits = MVT::getSizeInBits(NewStoredVT);
591 int IncrementSize = NumBits / 8;
593 // Divide the stored value in two parts.
594 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
596 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
598 // Store the two parts
599 SDOperand Store1, Store2;
600 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
601 ST->getSrcValue(), SVOffset, NewStoredVT,
602 ST->isVolatile(), Alignment);
603 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
604 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
605 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
606 ST->getSrcValue(), SVOffset + IncrementSize,
607 NewStoredVT, ST->isVolatile(), Alignment);
609 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
612 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
614 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
615 TargetLowering &TLI) {
616 int SVOffset = LD->getSrcValueOffset();
617 SDOperand Chain = LD->getChain();
618 SDOperand Ptr = LD->getBasePtr();
619 MVT::ValueType VT = LD->getValueType(0);
620 MVT::ValueType LoadedVT = LD->getLoadedVT();
621 if (MVT::isFloatingPoint(VT)) {
622 // Expand to a (misaligned) integer load of the same size,
623 // then bitconvert to floating point.
624 MVT::ValueType intVT;
625 if (LoadedVT==MVT::f64)
627 else if (LoadedVT==MVT::f32)
630 assert(0 && "Unaligned load of unsupported floating point type");
632 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
633 SVOffset, LD->isVolatile(),
635 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
637 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
639 SDOperand Ops[] = { Result, Chain };
640 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
643 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type.");
644 MVT::ValueType NewLoadedVT = LoadedVT - 1;
645 int NumBits = MVT::getSizeInBits(NewLoadedVT);
646 int Alignment = LD->getAlignment();
647 int IncrementSize = NumBits / 8;
648 ISD::LoadExtType HiExtType = LD->getExtensionType();
650 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
651 if (HiExtType == ISD::NON_EXTLOAD)
652 HiExtType = ISD::ZEXTLOAD;
654 // Load the value in two parts
656 if (TLI.isLittleEndian()) {
657 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
658 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
659 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
660 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
661 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
662 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
665 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
666 NewLoadedVT,LD->isVolatile(), Alignment);
667 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
668 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
669 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
670 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
674 // aggregate the two parts
675 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
676 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
677 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
679 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
682 SDOperand Ops[] = { Result, TF };
683 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
686 /// UnrollVectorOp - We know that the given vector has a legal type, however
687 /// the operation it performs is not legal and is an operation that we have
688 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
689 /// operating on each element individually.
690 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
691 MVT::ValueType VT = Op.getValueType();
692 assert(isTypeLegal(VT) &&
693 "Caller should expand or promote operands that are not legal!");
694 assert(Op.Val->getNumValues() == 1 &&
695 "Can't unroll a vector with multiple results!");
696 unsigned NE = MVT::getVectorNumElements(VT);
697 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
699 SmallVector<SDOperand, 8> Scalars;
700 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
701 for (unsigned i = 0; i != NE; ++i) {
702 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
703 SDOperand Operand = Op.getOperand(j);
704 MVT::ValueType OperandVT = Operand.getValueType();
705 if (MVT::isVector(OperandVT)) {
706 // A vector operand; extract a single element.
707 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
708 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
711 DAG.getConstant(i, MVT::i32));
713 // A scalar operand; just use it as is.
714 Operands[j] = Operand;
717 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
718 &Operands[0], Operands.size()));
721 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
724 /// LegalizeOp - We know that the specified value has a legal type, and
725 /// that its operands are legal. Now ensure that the operation itself
726 /// is legal, recursively ensuring that the operands' operations remain
728 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
729 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
732 assert(isTypeLegal(Op.getValueType()) &&
733 "Caller should expand or promote operands that are not legal!");
734 SDNode *Node = Op.Val;
736 // If this operation defines any values that cannot be represented in a
737 // register on this target, make sure to expand or promote them.
738 if (Node->getNumValues() > 1) {
739 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
740 if (getTypeAction(Node->getValueType(i)) != Legal) {
741 HandleOp(Op.getValue(i));
742 assert(LegalizedNodes.count(Op) &&
743 "Handling didn't add legal operands!");
744 return LegalizedNodes[Op];
748 // Note that LegalizeOp may be reentered even from single-use nodes, which
749 // means that we always must cache transformed nodes.
750 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
751 if (I != LegalizedNodes.end()) return I->second;
753 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
754 SDOperand Result = Op;
755 bool isCustom = false;
757 switch (Node->getOpcode()) {
758 case ISD::FrameIndex:
759 case ISD::EntryToken:
761 case ISD::BasicBlock:
762 case ISD::TargetFrameIndex:
763 case ISD::TargetJumpTable:
764 case ISD::TargetConstant:
765 case ISD::TargetConstantFP:
766 case ISD::TargetConstantPool:
767 case ISD::TargetGlobalAddress:
768 case ISD::TargetGlobalTLSAddress:
769 case ISD::TargetExternalSymbol:
774 // Primitives must all be legal.
775 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
776 "This must be legal!");
779 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
780 // If this is a target node, legalize it by legalizing the operands then
781 // passing it through.
782 SmallVector<SDOperand, 8> Ops;
783 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
784 Ops.push_back(LegalizeOp(Node->getOperand(i)));
786 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
788 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
789 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
790 return Result.getValue(Op.ResNo);
792 // Otherwise this is an unhandled builtin node. splat.
794 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
796 assert(0 && "Do not know how to legalize this operator!");
798 case ISD::GLOBAL_OFFSET_TABLE:
799 case ISD::GlobalAddress:
800 case ISD::GlobalTLSAddress:
801 case ISD::ExternalSymbol:
802 case ISD::ConstantPool:
803 case ISD::JumpTable: // Nothing to do.
804 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
805 default: assert(0 && "This action is not supported yet!");
806 case TargetLowering::Custom:
807 Tmp1 = TLI.LowerOperation(Op, DAG);
808 if (Tmp1.Val) Result = Tmp1;
809 // FALLTHROUGH if the target doesn't want to lower this op after all.
810 case TargetLowering::Legal:
815 case ISD::RETURNADDR:
816 // The only option for these nodes is to custom lower them. If the target
817 // does not custom lower them, then return zero.
818 Tmp1 = TLI.LowerOperation(Op, DAG);
822 Result = DAG.getConstant(0, TLI.getPointerTy());
824 case ISD::FRAME_TO_ARGS_OFFSET: {
825 MVT::ValueType VT = Node->getValueType(0);
826 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
827 default: assert(0 && "This action is not supported yet!");
828 case TargetLowering::Custom:
829 Result = TLI.LowerOperation(Op, DAG);
830 if (Result.Val) break;
832 case TargetLowering::Legal:
833 Result = DAG.getConstant(0, VT);
838 case ISD::EXCEPTIONADDR: {
839 Tmp1 = LegalizeOp(Node->getOperand(0));
840 MVT::ValueType VT = Node->getValueType(0);
841 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
842 default: assert(0 && "This action is not supported yet!");
843 case TargetLowering::Expand: {
844 unsigned Reg = TLI.getExceptionAddressRegister();
845 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
848 case TargetLowering::Custom:
849 Result = TLI.LowerOperation(Op, DAG);
850 if (Result.Val) break;
852 case TargetLowering::Legal: {
853 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
854 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
855 Ops, 2).getValue(Op.ResNo);
861 case ISD::EHSELECTION: {
862 Tmp1 = LegalizeOp(Node->getOperand(0));
863 Tmp2 = LegalizeOp(Node->getOperand(1));
864 MVT::ValueType VT = Node->getValueType(0);
865 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
866 default: assert(0 && "This action is not supported yet!");
867 case TargetLowering::Expand: {
868 unsigned Reg = TLI.getExceptionSelectorRegister();
869 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
872 case TargetLowering::Custom:
873 Result = TLI.LowerOperation(Op, DAG);
874 if (Result.Val) break;
876 case TargetLowering::Legal: {
877 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
878 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
879 Ops, 2).getValue(Op.ResNo);
885 case ISD::EH_RETURN: {
886 MVT::ValueType VT = Node->getValueType(0);
887 // The only "good" option for this node is to custom lower it.
888 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
889 default: assert(0 && "This action is not supported at all!");
890 case TargetLowering::Custom:
891 Result = TLI.LowerOperation(Op, DAG);
892 if (Result.Val) break;
894 case TargetLowering::Legal:
895 // Target does not know, how to lower this, lower to noop
896 Result = LegalizeOp(Node->getOperand(0));
901 case ISD::AssertSext:
902 case ISD::AssertZext:
903 Tmp1 = LegalizeOp(Node->getOperand(0));
904 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
906 case ISD::MERGE_VALUES:
907 // Legalize eliminates MERGE_VALUES nodes.
908 Result = Node->getOperand(Op.ResNo);
910 case ISD::CopyFromReg:
911 Tmp1 = LegalizeOp(Node->getOperand(0));
912 Result = Op.getValue(0);
913 if (Node->getNumValues() == 2) {
914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
916 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
917 if (Node->getNumOperands() == 3) {
918 Tmp2 = LegalizeOp(Node->getOperand(2));
919 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
921 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
923 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
925 // Since CopyFromReg produces two values, make sure to remember that we
926 // legalized both of them.
927 AddLegalizedOperand(Op.getValue(0), Result);
928 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
929 return Result.getValue(Op.ResNo);
931 MVT::ValueType VT = Op.getValueType();
932 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
933 default: assert(0 && "This action is not supported yet!");
934 case TargetLowering::Expand:
935 if (MVT::isInteger(VT))
936 Result = DAG.getConstant(0, VT);
937 else if (MVT::isFloatingPoint(VT))
938 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
941 assert(0 && "Unknown value type!");
943 case TargetLowering::Legal:
949 case ISD::INTRINSIC_W_CHAIN:
950 case ISD::INTRINSIC_WO_CHAIN:
951 case ISD::INTRINSIC_VOID: {
952 SmallVector<SDOperand, 8> Ops;
953 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
954 Ops.push_back(LegalizeOp(Node->getOperand(i)));
955 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
957 // Allow the target to custom lower its intrinsics if it wants to.
958 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
959 TargetLowering::Custom) {
960 Tmp3 = TLI.LowerOperation(Result, DAG);
961 if (Tmp3.Val) Result = Tmp3;
964 if (Result.Val->getNumValues() == 1) break;
966 // Must have return value and chain result.
967 assert(Result.Val->getNumValues() == 2 &&
968 "Cannot return more than two values!");
970 // Since loads produce two values, make sure to remember that we
971 // legalized both of them.
972 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
973 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
974 return Result.getValue(Op.ResNo);
978 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
979 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
981 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
982 case TargetLowering::Promote:
983 default: assert(0 && "This action is not supported yet!");
984 case TargetLowering::Expand: {
985 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
986 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
987 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
989 if (MMI && (useDEBUG_LOC || useLABEL)) {
990 const std::string &FName =
991 cast<StringSDNode>(Node->getOperand(3))->getValue();
992 const std::string &DirName =
993 cast<StringSDNode>(Node->getOperand(4))->getValue();
994 unsigned SrcFile = MMI->RecordSource(DirName, FName);
996 SmallVector<SDOperand, 8> Ops;
997 Ops.push_back(Tmp1); // chain
998 SDOperand LineOp = Node->getOperand(1);
999 SDOperand ColOp = Node->getOperand(2);
1002 Ops.push_back(LineOp); // line #
1003 Ops.push_back(ColOp); // col #
1004 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1005 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1007 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1008 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1009 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
1010 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1011 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
1014 Result = Tmp1; // chain
1018 case TargetLowering::Legal:
1019 if (Tmp1 != Node->getOperand(0) ||
1020 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1021 SmallVector<SDOperand, 8> Ops;
1022 Ops.push_back(Tmp1);
1023 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1024 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1025 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1027 // Otherwise promote them.
1028 Ops.push_back(PromoteOp(Node->getOperand(1)));
1029 Ops.push_back(PromoteOp(Node->getOperand(2)));
1031 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1032 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1033 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1039 case ISD::DEBUG_LOC:
1040 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1041 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1042 default: assert(0 && "This action is not supported yet!");
1043 case TargetLowering::Legal:
1044 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1046 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1047 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1048 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1054 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1055 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1056 default: assert(0 && "This action is not supported yet!");
1057 case TargetLowering::Legal:
1058 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1059 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1060 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1062 case TargetLowering::Expand:
1063 Result = LegalizeOp(Node->getOperand(0));
1068 case ISD::Constant: {
1069 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1071 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1073 // We know we don't need to expand constants here, constants only have one
1074 // value and we check that it is fine above.
1076 if (opAction == TargetLowering::Custom) {
1077 Tmp1 = TLI.LowerOperation(Result, DAG);
1083 case ISD::ConstantFP: {
1084 // Spill FP immediates to the constant pool if the target cannot directly
1085 // codegen them. Targets often have some immediate values that can be
1086 // efficiently generated into an FP register without a load. We explicitly
1087 // leave these constants as ConstantFP nodes for the target to deal with.
1088 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1090 // Check to see if this FP immediate is already legal.
1091 bool isLegal = false;
1092 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1093 E = TLI.legal_fpimm_end(); I != E; ++I)
1094 if (CFP->isExactlyValue(*I)) {
1099 // If this is a legal constant, turn it into a TargetConstantFP node.
1101 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1102 CFP->getValueType(0));
1106 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1107 default: assert(0 && "This action is not supported yet!");
1108 case TargetLowering::Custom:
1109 Tmp3 = TLI.LowerOperation(Result, DAG);
1115 case TargetLowering::Expand:
1116 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1120 case ISD::TokenFactor:
1121 if (Node->getNumOperands() == 2) {
1122 Tmp1 = LegalizeOp(Node->getOperand(0));
1123 Tmp2 = LegalizeOp(Node->getOperand(1));
1124 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1125 } else if (Node->getNumOperands() == 3) {
1126 Tmp1 = LegalizeOp(Node->getOperand(0));
1127 Tmp2 = LegalizeOp(Node->getOperand(1));
1128 Tmp3 = LegalizeOp(Node->getOperand(2));
1129 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1131 SmallVector<SDOperand, 8> Ops;
1132 // Legalize the operands.
1133 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1134 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1135 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1139 case ISD::FORMAL_ARGUMENTS:
1141 // The only option for this is to custom lower it.
1142 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1143 assert(Tmp3.Val && "Target didn't custom lower this node!");
1144 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1145 "Lowering call/formal_arguments produced unexpected # results!");
1147 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1148 // remember that we legalized all of them, so it doesn't get relegalized.
1149 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1150 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1153 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1156 case ISD::EXTRACT_SUBREG: {
1157 Tmp1 = LegalizeOp(Node->getOperand(0));
1158 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1159 assert(idx && "Operand must be a constant");
1160 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1161 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1164 case ISD::INSERT_SUBREG: {
1165 Tmp1 = LegalizeOp(Node->getOperand(0));
1166 Tmp2 = LegalizeOp(Node->getOperand(1));
1167 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1168 assert(idx && "Operand must be a constant");
1169 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1173 case ISD::BUILD_VECTOR:
1174 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1175 default: assert(0 && "This action is not supported yet!");
1176 case TargetLowering::Custom:
1177 Tmp3 = TLI.LowerOperation(Result, DAG);
1183 case TargetLowering::Expand:
1184 Result = ExpandBUILD_VECTOR(Result.Val);
1188 case ISD::INSERT_VECTOR_ELT:
1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1190 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1191 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1194 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1195 Node->getValueType(0))) {
1196 default: assert(0 && "This action is not supported yet!");
1197 case TargetLowering::Legal:
1199 case TargetLowering::Custom:
1200 Tmp3 = TLI.LowerOperation(Result, DAG);
1206 case TargetLowering::Expand: {
1207 // If the insert index is a constant, codegen this as a scalar_to_vector,
1208 // then a shuffle that inserts it into the right position in the vector.
1209 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1210 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1211 Tmp1.getValueType(), Tmp2);
1213 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1214 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1215 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1217 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1218 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1220 SmallVector<SDOperand, 8> ShufOps;
1221 for (unsigned i = 0; i != NumElts; ++i) {
1222 if (i != InsertPos->getValue())
1223 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1225 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1227 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1228 &ShufOps[0], ShufOps.size());
1230 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1231 Tmp1, ScVec, ShufMask);
1232 Result = LegalizeOp(Result);
1236 // If the target doesn't support this, we have to spill the input vector
1237 // to a temporary stack slot, update the element, then reload it. This is
1238 // badness. We could also load the value into a vector register (either
1239 // with a "move to register" or "extload into register" instruction, then
1240 // permute it into place, if the idx is a constant and if the idx is
1241 // supported by the target.
1242 MVT::ValueType VT = Tmp1.getValueType();
1243 MVT::ValueType EltVT = Tmp2.getValueType();
1244 MVT::ValueType IdxVT = Tmp3.getValueType();
1245 MVT::ValueType PtrVT = TLI.getPointerTy();
1246 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1247 // Store the vector.
1248 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1250 // Truncate or zero extend offset to target pointer type.
1251 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1252 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1253 // Add the offset to the index.
1254 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1255 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1256 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1257 // Store the scalar value.
1258 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1259 // Load the updated vector.
1260 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1265 case ISD::SCALAR_TO_VECTOR:
1266 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1267 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1271 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1272 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1273 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1274 Node->getValueType(0))) {
1275 default: assert(0 && "This action is not supported yet!");
1276 case TargetLowering::Legal:
1278 case TargetLowering::Custom:
1279 Tmp3 = TLI.LowerOperation(Result, DAG);
1285 case TargetLowering::Expand:
1286 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1290 case ISD::VECTOR_SHUFFLE:
1291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1292 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1293 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1295 // Allow targets to custom lower the SHUFFLEs they support.
1296 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1297 default: assert(0 && "Unknown operation action!");
1298 case TargetLowering::Legal:
1299 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1300 "vector shuffle should not be created if not legal!");
1302 case TargetLowering::Custom:
1303 Tmp3 = TLI.LowerOperation(Result, DAG);
1309 case TargetLowering::Expand: {
1310 MVT::ValueType VT = Node->getValueType(0);
1311 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1312 MVT::ValueType PtrVT = TLI.getPointerTy();
1313 SDOperand Mask = Node->getOperand(2);
1314 unsigned NumElems = Mask.getNumOperands();
1315 SmallVector<SDOperand,8> Ops;
1316 for (unsigned i = 0; i != NumElems; ++i) {
1317 SDOperand Arg = Mask.getOperand(i);
1318 if (Arg.getOpcode() == ISD::UNDEF) {
1319 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1321 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1322 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1324 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1325 DAG.getConstant(Idx, PtrVT)));
1327 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1328 DAG.getConstant(Idx - NumElems, PtrVT)));
1331 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1334 case TargetLowering::Promote: {
1335 // Change base type to a different vector type.
1336 MVT::ValueType OVT = Node->getValueType(0);
1337 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1339 // Cast the two input vectors.
1340 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1341 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1343 // Convert the shuffle mask to the right # elements.
1344 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1345 assert(Tmp3.Val && "Shuffle not legal?");
1346 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1347 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1353 case ISD::EXTRACT_VECTOR_ELT:
1354 Tmp1 = Node->getOperand(0);
1355 Tmp2 = LegalizeOp(Node->getOperand(1));
1356 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1357 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1360 case ISD::EXTRACT_SUBVECTOR:
1361 Tmp1 = Node->getOperand(0);
1362 Tmp2 = LegalizeOp(Node->getOperand(1));
1363 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1364 Result = ExpandEXTRACT_SUBVECTOR(Result);
1367 case ISD::CALLSEQ_START: {
1368 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1370 // Recursively Legalize all of the inputs of the call end that do not lead
1371 // to this call start. This ensures that any libcalls that need be inserted
1372 // are inserted *before* the CALLSEQ_START.
1373 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1374 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1375 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1379 // Now that we legalized all of the inputs (which may have inserted
1380 // libcalls) create the new CALLSEQ_START node.
1381 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1383 // Merge in the last call, to ensure that this call start after the last
1385 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1386 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1387 Tmp1 = LegalizeOp(Tmp1);
1390 // Do not try to legalize the target-specific arguments (#1+).
1391 if (Tmp1 != Node->getOperand(0)) {
1392 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1394 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1397 // Remember that the CALLSEQ_START is legalized.
1398 AddLegalizedOperand(Op.getValue(0), Result);
1399 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1400 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1402 // Now that the callseq_start and all of the non-call nodes above this call
1403 // sequence have been legalized, legalize the call itself. During this
1404 // process, no libcalls can/will be inserted, guaranteeing that no calls
1406 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1407 SDOperand InCallSEQ = LastCALLSEQ_END;
1408 // Note that we are selecting this call!
1409 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1410 IsLegalizingCall = true;
1412 // Legalize the call, starting from the CALLSEQ_END.
1413 LegalizeOp(LastCALLSEQ_END);
1414 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1417 case ISD::CALLSEQ_END:
1418 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1419 // will cause this node to be legalized as well as handling libcalls right.
1420 if (LastCALLSEQ_END.Val != Node) {
1421 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1422 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1423 assert(I != LegalizedNodes.end() &&
1424 "Legalizing the call start should have legalized this node!");
1428 // Otherwise, the call start has been legalized and everything is going
1429 // according to plan. Just legalize ourselves normally here.
1430 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1431 // Do not try to legalize the target-specific arguments (#1+), except for
1432 // an optional flag input.
1433 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1434 if (Tmp1 != Node->getOperand(0)) {
1435 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1437 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1440 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1441 if (Tmp1 != Node->getOperand(0) ||
1442 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1443 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1446 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1449 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1450 // This finishes up call legalization.
1451 IsLegalizingCall = false;
1453 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1454 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1455 if (Node->getNumValues() == 2)
1456 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1457 return Result.getValue(Op.ResNo);
1458 case ISD::DYNAMIC_STACKALLOC: {
1459 MVT::ValueType VT = Node->getValueType(0);
1460 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1461 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1462 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1465 Tmp1 = Result.getValue(0);
1466 Tmp2 = Result.getValue(1);
1467 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1468 default: assert(0 && "This action is not supported yet!");
1469 case TargetLowering::Expand: {
1470 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1471 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1472 " not tell us which reg is the stack pointer!");
1473 SDOperand Chain = Tmp1.getOperand(0);
1474 SDOperand Size = Tmp2.getOperand(1);
1475 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1476 Chain = SP.getValue(1);
1477 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1478 unsigned StackAlign =
1479 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1480 if (Align > StackAlign)
1481 SP = DAG.getNode(ISD::AND, VT, SP,
1482 DAG.getConstant(-(uint64_t)Align, VT));
1483 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1484 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1485 Tmp1 = LegalizeOp(Tmp1);
1486 Tmp2 = LegalizeOp(Tmp2);
1489 case TargetLowering::Custom:
1490 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1492 Tmp1 = LegalizeOp(Tmp3);
1493 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1496 case TargetLowering::Legal:
1499 // Since this op produce two values, make sure to remember that we
1500 // legalized both of them.
1501 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1502 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1503 return Op.ResNo ? Tmp2 : Tmp1;
1505 case ISD::INLINEASM: {
1506 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1507 bool Changed = false;
1508 // Legalize all of the operands of the inline asm, in case they are nodes
1509 // that need to be expanded or something. Note we skip the asm string and
1510 // all of the TargetConstant flags.
1511 SDOperand Op = LegalizeOp(Ops[0]);
1512 Changed = Op != Ops[0];
1515 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1516 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1517 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1518 for (++i; NumVals; ++i, --NumVals) {
1519 SDOperand Op = LegalizeOp(Ops[i]);
1528 Op = LegalizeOp(Ops.back());
1529 Changed |= Op != Ops.back();
1534 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1536 // INLINE asm returns a chain and flag, make sure to add both to the map.
1537 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1538 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1539 return Result.getValue(Op.ResNo);
1542 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1543 // Ensure that libcalls are emitted before a branch.
1544 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1545 Tmp1 = LegalizeOp(Tmp1);
1546 LastCALLSEQ_END = DAG.getEntryNode();
1548 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1551 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1552 // Ensure that libcalls are emitted before a branch.
1553 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1554 Tmp1 = LegalizeOp(Tmp1);
1555 LastCALLSEQ_END = DAG.getEntryNode();
1557 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1558 default: assert(0 && "Indirect target must be legal type (pointer)!");
1560 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1566 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1567 // Ensure that libcalls are emitted before a branch.
1568 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1569 Tmp1 = LegalizeOp(Tmp1);
1570 LastCALLSEQ_END = DAG.getEntryNode();
1572 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1573 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1575 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1576 default: assert(0 && "This action is not supported yet!");
1577 case TargetLowering::Legal: break;
1578 case TargetLowering::Custom:
1579 Tmp1 = TLI.LowerOperation(Result, DAG);
1580 if (Tmp1.Val) Result = Tmp1;
1582 case TargetLowering::Expand: {
1583 SDOperand Chain = Result.getOperand(0);
1584 SDOperand Table = Result.getOperand(1);
1585 SDOperand Index = Result.getOperand(2);
1587 MVT::ValueType PTy = TLI.getPointerTy();
1588 MachineFunction &MF = DAG.getMachineFunction();
1589 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1590 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1591 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1594 switch (EntrySize) {
1595 default: assert(0 && "Size of jump table not supported yet."); break;
1596 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1597 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1600 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1601 // For PIC, the sequence is:
1602 // BRIND(load(Jumptable + index) + RelocBase)
1603 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1605 if (TLI.usesGlobalOffsetTable())
1606 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1609 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1610 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1611 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1613 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1619 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1620 // Ensure that libcalls are emitted before a return.
1621 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1622 Tmp1 = LegalizeOp(Tmp1);
1623 LastCALLSEQ_END = DAG.getEntryNode();
1625 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1626 case Expand: assert(0 && "It's impossible to expand bools");
1628 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1631 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1633 // The top bits of the promoted condition are not necessarily zero, ensure
1634 // that the value is properly zero extended.
1635 if (!DAG.MaskedValueIsZero(Tmp2,
1636 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1637 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1641 // Basic block destination (Op#2) is always legal.
1642 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1644 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1645 default: assert(0 && "This action is not supported yet!");
1646 case TargetLowering::Legal: break;
1647 case TargetLowering::Custom:
1648 Tmp1 = TLI.LowerOperation(Result, DAG);
1649 if (Tmp1.Val) Result = Tmp1;
1651 case TargetLowering::Expand:
1652 // Expand brcond's setcc into its constituent parts and create a BR_CC
1654 if (Tmp2.getOpcode() == ISD::SETCC) {
1655 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1656 Tmp2.getOperand(0), Tmp2.getOperand(1),
1657 Node->getOperand(2));
1659 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1660 DAG.getCondCode(ISD::SETNE), Tmp2,
1661 DAG.getConstant(0, Tmp2.getValueType()),
1662 Node->getOperand(2));
1668 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1669 // Ensure that libcalls are emitted before a branch.
1670 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1671 Tmp1 = LegalizeOp(Tmp1);
1672 Tmp2 = Node->getOperand(2); // LHS
1673 Tmp3 = Node->getOperand(3); // RHS
1674 Tmp4 = Node->getOperand(1); // CC
1676 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1677 LastCALLSEQ_END = DAG.getEntryNode();
1679 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1680 // the LHS is a legal SETCC itself. In this case, we need to compare
1681 // the result against zero to select between true and false values.
1682 if (Tmp3.Val == 0) {
1683 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1684 Tmp4 = DAG.getCondCode(ISD::SETNE);
1687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1688 Node->getOperand(4));
1690 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1691 default: assert(0 && "Unexpected action for BR_CC!");
1692 case TargetLowering::Legal: break;
1693 case TargetLowering::Custom:
1694 Tmp4 = TLI.LowerOperation(Result, DAG);
1695 if (Tmp4.Val) Result = Tmp4;
1700 LoadSDNode *LD = cast<LoadSDNode>(Node);
1701 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1702 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1704 ISD::LoadExtType ExtType = LD->getExtensionType();
1705 if (ExtType == ISD::NON_EXTLOAD) {
1706 MVT::ValueType VT = Node->getValueType(0);
1707 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1708 Tmp3 = Result.getValue(0);
1709 Tmp4 = Result.getValue(1);
1711 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1712 default: assert(0 && "This action is not supported yet!");
1713 case TargetLowering::Legal:
1714 // If this is an unaligned load and the target doesn't support it,
1716 if (!TLI.allowsUnalignedMemoryAccesses()) {
1717 unsigned ABIAlignment = TLI.getTargetData()->
1718 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1719 if (LD->getAlignment() < ABIAlignment){
1720 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1722 Tmp3 = Result.getOperand(0);
1723 Tmp4 = Result.getOperand(1);
1724 Tmp3 = LegalizeOp(Tmp3);
1725 Tmp4 = LegalizeOp(Tmp4);
1729 case TargetLowering::Custom:
1730 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1732 Tmp3 = LegalizeOp(Tmp1);
1733 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1736 case TargetLowering::Promote: {
1737 // Only promote a load of vector type to another.
1738 assert(MVT::isVector(VT) && "Cannot promote this load!");
1739 // Change base type to a different vector type.
1740 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1742 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1743 LD->getSrcValueOffset(),
1744 LD->isVolatile(), LD->getAlignment());
1745 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1746 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1750 // Since loads produce two values, make sure to remember that we
1751 // legalized both of them.
1752 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1753 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1754 return Op.ResNo ? Tmp4 : Tmp3;
1756 MVT::ValueType SrcVT = LD->getLoadedVT();
1757 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1758 default: assert(0 && "This action is not supported yet!");
1759 case TargetLowering::Promote:
1760 assert(SrcVT == MVT::i1 &&
1761 "Can only promote extending LOAD from i1 -> i8!");
1762 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1763 LD->getSrcValue(), LD->getSrcValueOffset(),
1764 MVT::i8, LD->isVolatile(), LD->getAlignment());
1765 Tmp1 = Result.getValue(0);
1766 Tmp2 = Result.getValue(1);
1768 case TargetLowering::Custom:
1771 case TargetLowering::Legal:
1772 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1773 Tmp1 = Result.getValue(0);
1774 Tmp2 = Result.getValue(1);
1777 Tmp3 = TLI.LowerOperation(Result, DAG);
1779 Tmp1 = LegalizeOp(Tmp3);
1780 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1783 // If this is an unaligned load and the target doesn't support it,
1785 if (!TLI.allowsUnalignedMemoryAccesses()) {
1786 unsigned ABIAlignment = TLI.getTargetData()->
1787 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1788 if (LD->getAlignment() < ABIAlignment){
1789 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1791 Tmp1 = Result.getOperand(0);
1792 Tmp2 = Result.getOperand(1);
1793 Tmp1 = LegalizeOp(Tmp1);
1794 Tmp2 = LegalizeOp(Tmp2);
1799 case TargetLowering::Expand:
1800 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1801 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1802 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1803 LD->getSrcValueOffset(),
1804 LD->isVolatile(), LD->getAlignment());
1805 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1806 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1807 Tmp2 = LegalizeOp(Load.getValue(1));
1810 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1811 // Turn the unsupported load into an EXTLOAD followed by an explicit
1812 // zero/sign extend inreg.
1813 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1814 Tmp1, Tmp2, LD->getSrcValue(),
1815 LD->getSrcValueOffset(), SrcVT,
1816 LD->isVolatile(), LD->getAlignment());
1818 if (ExtType == ISD::SEXTLOAD)
1819 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1820 Result, DAG.getValueType(SrcVT));
1822 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1823 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1824 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1827 // Since loads produce two values, make sure to remember that we legalized
1829 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1830 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1831 return Op.ResNo ? Tmp2 : Tmp1;
1834 case ISD::EXTRACT_ELEMENT: {
1835 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1836 switch (getTypeAction(OpTy)) {
1837 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1839 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1841 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1842 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1843 TLI.getShiftAmountTy()));
1844 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1847 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1848 Node->getOperand(0));
1852 // Get both the low and high parts.
1853 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1854 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1855 Result = Tmp2; // 1 -> Hi
1857 Result = Tmp1; // 0 -> Lo
1863 case ISD::CopyToReg:
1864 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1866 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1867 "Register type must be legal!");
1868 // Legalize the incoming value (must be a legal type).
1869 Tmp2 = LegalizeOp(Node->getOperand(2));
1870 if (Node->getNumValues() == 1) {
1871 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1873 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1874 if (Node->getNumOperands() == 4) {
1875 Tmp3 = LegalizeOp(Node->getOperand(3));
1876 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1882 // Since this produces two values, make sure to remember that we legalized
1884 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1885 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1891 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1893 // Ensure that libcalls are emitted before a return.
1894 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1895 Tmp1 = LegalizeOp(Tmp1);
1896 LastCALLSEQ_END = DAG.getEntryNode();
1898 switch (Node->getNumOperands()) {
1900 Tmp2 = Node->getOperand(1);
1901 Tmp3 = Node->getOperand(2); // Signness
1902 switch (getTypeAction(Tmp2.getValueType())) {
1904 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1907 if (!MVT::isVector(Tmp2.getValueType())) {
1909 ExpandOp(Tmp2, Lo, Hi);
1911 // Big endian systems want the hi reg first.
1912 if (!TLI.isLittleEndian())
1916 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1918 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1919 Result = LegalizeOp(Result);
1921 SDNode *InVal = Tmp2.Val;
1922 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1923 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1925 // Figure out if there is a simple type corresponding to this Vector
1926 // type. If so, convert to the vector type.
1927 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1928 if (TLI.isTypeLegal(TVT)) {
1929 // Turn this into a return of the vector type.
1930 Tmp2 = LegalizeOp(Tmp2);
1931 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1932 } else if (NumElems == 1) {
1933 // Turn this into a return of the scalar type.
1934 Tmp2 = ScalarizeVectorOp(Tmp2);
1935 Tmp2 = LegalizeOp(Tmp2);
1936 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1938 // FIXME: Returns of gcc generic vectors smaller than a legal type
1939 // should be returned in integer registers!
1941 // The scalarized value type may not be legal, e.g. it might require
1942 // promotion or expansion. Relegalize the return.
1943 Result = LegalizeOp(Result);
1945 // FIXME: Returns of gcc generic vectors larger than a legal vector
1946 // type should be returned by reference!
1948 SplitVectorOp(Tmp2, Lo, Hi);
1949 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1950 Result = LegalizeOp(Result);
1955 Tmp2 = PromoteOp(Node->getOperand(1));
1956 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1957 Result = LegalizeOp(Result);
1962 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1964 default: { // ret <values>
1965 SmallVector<SDOperand, 8> NewValues;
1966 NewValues.push_back(Tmp1);
1967 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1968 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1970 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1971 NewValues.push_back(Node->getOperand(i+1));
1975 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1976 "FIXME: TODO: implement returning non-legal vector types!");
1977 ExpandOp(Node->getOperand(i), Lo, Hi);
1978 NewValues.push_back(Lo);
1979 NewValues.push_back(Node->getOperand(i+1));
1981 NewValues.push_back(Hi);
1982 NewValues.push_back(Node->getOperand(i+1));
1987 assert(0 && "Can't promote multiple return value yet!");
1990 if (NewValues.size() == Node->getNumOperands())
1991 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1993 Result = DAG.getNode(ISD::RET, MVT::Other,
1994 &NewValues[0], NewValues.size());
1999 if (Result.getOpcode() == ISD::RET) {
2000 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2001 default: assert(0 && "This action is not supported yet!");
2002 case TargetLowering::Legal: break;
2003 case TargetLowering::Custom:
2004 Tmp1 = TLI.LowerOperation(Result, DAG);
2005 if (Tmp1.Val) Result = Tmp1;
2011 StoreSDNode *ST = cast<StoreSDNode>(Node);
2012 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2013 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2014 int SVOffset = ST->getSrcValueOffset();
2015 unsigned Alignment = ST->getAlignment();
2016 bool isVolatile = ST->isVolatile();
2018 if (!ST->isTruncatingStore()) {
2019 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2020 // FIXME: We shouldn't do this for TargetConstantFP's.
2021 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2022 // to phase ordering between legalized code and the dag combiner. This
2023 // probably means that we need to integrate dag combiner and legalizer
2025 // We generally can't do this one for long doubles.
2026 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2027 if (CFP->getValueType(0) == MVT::f32 &&
2028 getTypeAction(MVT::i32) == Legal) {
2029 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2030 convertToAPInt().getZExtValue(),
2032 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2033 SVOffset, isVolatile, Alignment);
2035 } else if (CFP->getValueType(0) == MVT::f64) {
2036 // If this target supports 64-bit registers, do a single 64-bit store.
2037 if (getTypeAction(MVT::i64) == Legal) {
2038 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2039 getZExtValue(), MVT::i64);
2040 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2041 SVOffset, isVolatile, Alignment);
2043 } else if (getTypeAction(MVT::i32) == Legal) {
2044 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2045 // stores. If the target supports neither 32- nor 64-bits, this
2046 // xform is certainly not worth it.
2047 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2048 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2049 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2050 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2052 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2053 SVOffset, isVolatile, Alignment);
2054 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2055 getIntPtrConstant(4));
2056 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2057 isVolatile, std::max(Alignment, 4U));
2059 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2065 switch (getTypeAction(ST->getStoredVT())) {
2067 Tmp3 = LegalizeOp(ST->getValue());
2068 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2071 MVT::ValueType VT = Tmp3.getValueType();
2072 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2073 default: assert(0 && "This action is not supported yet!");
2074 case TargetLowering::Legal:
2075 // If this is an unaligned store and the target doesn't support it,
2077 if (!TLI.allowsUnalignedMemoryAccesses()) {
2078 unsigned ABIAlignment = TLI.getTargetData()->
2079 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2080 if (ST->getAlignment() < ABIAlignment)
2081 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2085 case TargetLowering::Custom:
2086 Tmp1 = TLI.LowerOperation(Result, DAG);
2087 if (Tmp1.Val) Result = Tmp1;
2089 case TargetLowering::Promote:
2090 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2091 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2092 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2093 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2094 ST->getSrcValue(), SVOffset, isVolatile,
2101 // Truncate the value and store the result.
2102 Tmp3 = PromoteOp(ST->getValue());
2103 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2104 SVOffset, ST->getStoredVT(),
2105 isVolatile, Alignment);
2109 unsigned IncrementSize = 0;
2112 // If this is a vector type, then we have to calculate the increment as
2113 // the product of the element size in bytes, and the number of elements
2114 // in the high half of the vector.
2115 if (MVT::isVector(ST->getValue().getValueType())) {
2116 SDNode *InVal = ST->getValue().Val;
2117 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2118 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2120 // Figure out if there is a simple type corresponding to this Vector
2121 // type. If so, convert to the vector type.
2122 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2123 if (TLI.isTypeLegal(TVT)) {
2124 // Turn this into a normal store of the vector type.
2125 Tmp3 = LegalizeOp(Node->getOperand(1));
2126 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2127 SVOffset, isVolatile, Alignment);
2128 Result = LegalizeOp(Result);
2130 } else if (NumElems == 1) {
2131 // Turn this into a normal store of the scalar type.
2132 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2133 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2134 SVOffset, isVolatile, Alignment);
2135 // The scalarized value type may not be legal, e.g. it might require
2136 // promotion or expansion. Relegalize the scalar store.
2137 Result = LegalizeOp(Result);
2140 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2141 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2144 ExpandOp(Node->getOperand(1), Lo, Hi);
2145 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2147 if (!TLI.isLittleEndian())
2151 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2152 SVOffset, isVolatile, Alignment);
2154 if (Hi.Val == NULL) {
2155 // Must be int <-> float one-to-one expansion.
2160 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2161 getIntPtrConstant(IncrementSize));
2162 assert(isTypeLegal(Tmp2.getValueType()) &&
2163 "Pointers must be legal!");
2164 SVOffset += IncrementSize;
2165 if (Alignment > IncrementSize)
2166 Alignment = IncrementSize;
2167 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2168 SVOffset, isVolatile, Alignment);
2169 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2174 assert(isTypeLegal(ST->getValue().getValueType()) &&
2175 "Cannot handle illegal TRUNCSTORE yet!");
2176 Tmp3 = LegalizeOp(ST->getValue());
2178 // The only promote case we handle is TRUNCSTORE:i1 X into
2179 // -> TRUNCSTORE:i8 (and X, 1)
2180 if (ST->getStoredVT() == MVT::i1 &&
2181 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2182 // Promote the bool to a mask then store.
2183 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2184 DAG.getConstant(1, Tmp3.getValueType()));
2185 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2187 isVolatile, Alignment);
2188 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2189 Tmp2 != ST->getBasePtr()) {
2190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2194 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2195 switch (TLI.getStoreXAction(StVT)) {
2196 default: assert(0 && "This action is not supported yet!");
2197 case TargetLowering::Legal:
2198 // If this is an unaligned store and the target doesn't support it,
2200 if (!TLI.allowsUnalignedMemoryAccesses()) {
2201 unsigned ABIAlignment = TLI.getTargetData()->
2202 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2203 if (ST->getAlignment() < ABIAlignment)
2204 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2208 case TargetLowering::Custom:
2209 Tmp1 = TLI.LowerOperation(Result, DAG);
2210 if (Tmp1.Val) Result = Tmp1;
2217 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2220 case ISD::STACKSAVE:
2221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2222 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2223 Tmp1 = Result.getValue(0);
2224 Tmp2 = Result.getValue(1);
2226 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2227 default: assert(0 && "This action is not supported yet!");
2228 case TargetLowering::Legal: break;
2229 case TargetLowering::Custom:
2230 Tmp3 = TLI.LowerOperation(Result, DAG);
2232 Tmp1 = LegalizeOp(Tmp3);
2233 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2236 case TargetLowering::Expand:
2237 // Expand to CopyFromReg if the target set
2238 // StackPointerRegisterToSaveRestore.
2239 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2240 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2241 Node->getValueType(0));
2242 Tmp2 = Tmp1.getValue(1);
2244 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2245 Tmp2 = Node->getOperand(0);
2250 // Since stacksave produce two values, make sure to remember that we
2251 // legalized both of them.
2252 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2253 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2254 return Op.ResNo ? Tmp2 : Tmp1;
2256 case ISD::STACKRESTORE:
2257 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2258 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2259 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2261 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2262 default: assert(0 && "This action is not supported yet!");
2263 case TargetLowering::Legal: break;
2264 case TargetLowering::Custom:
2265 Tmp1 = TLI.LowerOperation(Result, DAG);
2266 if (Tmp1.Val) Result = Tmp1;
2268 case TargetLowering::Expand:
2269 // Expand to CopyToReg if the target set
2270 // StackPointerRegisterToSaveRestore.
2271 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2272 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2280 case ISD::READCYCLECOUNTER:
2281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2282 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2283 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2284 Node->getValueType(0))) {
2285 default: assert(0 && "This action is not supported yet!");
2286 case TargetLowering::Legal:
2287 Tmp1 = Result.getValue(0);
2288 Tmp2 = Result.getValue(1);
2290 case TargetLowering::Custom:
2291 Result = TLI.LowerOperation(Result, DAG);
2292 Tmp1 = LegalizeOp(Result.getValue(0));
2293 Tmp2 = LegalizeOp(Result.getValue(1));
2297 // Since rdcc produce two values, make sure to remember that we legalized
2299 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2300 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2304 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2305 case Expand: assert(0 && "It's impossible to expand bools");
2307 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2310 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2311 // Make sure the condition is either zero or one.
2312 if (!DAG.MaskedValueIsZero(Tmp1,
2313 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2314 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2317 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2318 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2322 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2323 default: assert(0 && "This action is not supported yet!");
2324 case TargetLowering::Legal: break;
2325 case TargetLowering::Custom: {
2326 Tmp1 = TLI.LowerOperation(Result, DAG);
2327 if (Tmp1.Val) Result = Tmp1;
2330 case TargetLowering::Expand:
2331 if (Tmp1.getOpcode() == ISD::SETCC) {
2332 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2334 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2336 Result = DAG.getSelectCC(Tmp1,
2337 DAG.getConstant(0, Tmp1.getValueType()),
2338 Tmp2, Tmp3, ISD::SETNE);
2341 case TargetLowering::Promote: {
2342 MVT::ValueType NVT =
2343 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2344 unsigned ExtOp, TruncOp;
2345 if (MVT::isVector(Tmp2.getValueType())) {
2346 ExtOp = ISD::BIT_CONVERT;
2347 TruncOp = ISD::BIT_CONVERT;
2348 } else if (MVT::isInteger(Tmp2.getValueType())) {
2349 ExtOp = ISD::ANY_EXTEND;
2350 TruncOp = ISD::TRUNCATE;
2352 ExtOp = ISD::FP_EXTEND;
2353 TruncOp = ISD::FP_ROUND;
2355 // Promote each of the values to the new type.
2356 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2357 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2358 // Perform the larger operation, then round down.
2359 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2360 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2365 case ISD::SELECT_CC: {
2366 Tmp1 = Node->getOperand(0); // LHS
2367 Tmp2 = Node->getOperand(1); // RHS
2368 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2369 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2370 SDOperand CC = Node->getOperand(4);
2372 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2374 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2375 // the LHS is a legal SETCC itself. In this case, we need to compare
2376 // the result against zero to select between true and false values.
2377 if (Tmp2.Val == 0) {
2378 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2379 CC = DAG.getCondCode(ISD::SETNE);
2381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2383 // Everything is legal, see if we should expand this op or something.
2384 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2385 default: assert(0 && "This action is not supported yet!");
2386 case TargetLowering::Legal: break;
2387 case TargetLowering::Custom:
2388 Tmp1 = TLI.LowerOperation(Result, DAG);
2389 if (Tmp1.Val) Result = Tmp1;
2395 Tmp1 = Node->getOperand(0);
2396 Tmp2 = Node->getOperand(1);
2397 Tmp3 = Node->getOperand(2);
2398 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2400 // If we had to Expand the SetCC operands into a SELECT node, then it may
2401 // not always be possible to return a true LHS & RHS. In this case, just
2402 // return the value we legalized, returned in the LHS
2403 if (Tmp2.Val == 0) {
2408 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2409 default: assert(0 && "Cannot handle this action for SETCC yet!");
2410 case TargetLowering::Custom:
2413 case TargetLowering::Legal:
2414 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2416 Tmp4 = TLI.LowerOperation(Result, DAG);
2417 if (Tmp4.Val) Result = Tmp4;
2420 case TargetLowering::Promote: {
2421 // First step, figure out the appropriate operation to use.
2422 // Allow SETCC to not be supported for all legal data types
2423 // Mostly this targets FP
2424 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2425 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2427 // Scan for the appropriate larger type to use.
2429 NewInTy = (MVT::ValueType)(NewInTy+1);
2431 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2432 "Fell off of the edge of the integer world");
2433 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2434 "Fell off of the edge of the floating point world");
2436 // If the target supports SETCC of this type, use it.
2437 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2440 if (MVT::isInteger(NewInTy))
2441 assert(0 && "Cannot promote Legal Integer SETCC yet");
2443 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2444 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2446 Tmp1 = LegalizeOp(Tmp1);
2447 Tmp2 = LegalizeOp(Tmp2);
2448 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2449 Result = LegalizeOp(Result);
2452 case TargetLowering::Expand:
2453 // Expand a setcc node into a select_cc of the same condition, lhs, and
2454 // rhs that selects between const 1 (true) and const 0 (false).
2455 MVT::ValueType VT = Node->getValueType(0);
2456 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2457 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2464 case ISD::MEMMOVE: {
2465 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2466 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2468 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2469 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2470 case Expand: assert(0 && "Cannot expand a byte!");
2472 Tmp3 = LegalizeOp(Node->getOperand(2));
2475 Tmp3 = PromoteOp(Node->getOperand(2));
2479 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2483 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2485 // Length is too big, just take the lo-part of the length.
2487 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2491 Tmp4 = LegalizeOp(Node->getOperand(3));
2494 Tmp4 = PromoteOp(Node->getOperand(3));
2499 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2500 case Expand: assert(0 && "Cannot expand this yet!");
2502 Tmp5 = LegalizeOp(Node->getOperand(4));
2505 Tmp5 = PromoteOp(Node->getOperand(4));
2510 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2511 case Expand: assert(0 && "Cannot expand this yet!");
2513 Tmp6 = LegalizeOp(Node->getOperand(5));
2516 Tmp6 = PromoteOp(Node->getOperand(5));
2520 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2521 default: assert(0 && "This action not implemented for this operation!");
2522 case TargetLowering::Custom:
2525 case TargetLowering::Legal: {
2526 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2527 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2529 Tmp1 = TLI.LowerOperation(Result, DAG);
2530 if (Tmp1.Val) Result = Tmp1;
2534 case TargetLowering::Expand: {
2535 // Otherwise, the target does not support this operation. Lower the
2536 // operation to an explicit libcall as appropriate.
2537 MVT::ValueType IntPtr = TLI.getPointerTy();
2538 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2539 TargetLowering::ArgListTy Args;
2540 TargetLowering::ArgListEntry Entry;
2542 const char *FnName = 0;
2543 if (Node->getOpcode() == ISD::MEMSET) {
2544 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2545 Args.push_back(Entry);
2546 // Extend the (previously legalized) ubyte argument to be an int value
2548 if (Tmp3.getValueType() > MVT::i32)
2549 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2551 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2552 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2553 Args.push_back(Entry);
2554 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2555 Args.push_back(Entry);
2558 } else if (Node->getOpcode() == ISD::MEMCPY ||
2559 Node->getOpcode() == ISD::MEMMOVE) {
2560 Entry.Ty = IntPtrTy;
2561 Entry.Node = Tmp2; Args.push_back(Entry);
2562 Entry.Node = Tmp3; Args.push_back(Entry);
2563 Entry.Node = Tmp4; Args.push_back(Entry);
2564 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2566 assert(0 && "Unknown op!");
2569 std::pair<SDOperand,SDOperand> CallResult =
2570 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2571 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2572 Result = CallResult.second;
2579 case ISD::SHL_PARTS:
2580 case ISD::SRA_PARTS:
2581 case ISD::SRL_PARTS: {
2582 SmallVector<SDOperand, 8> Ops;
2583 bool Changed = false;
2584 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2585 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2586 Changed |= Ops.back() != Node->getOperand(i);
2589 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2591 switch (TLI.getOperationAction(Node->getOpcode(),
2592 Node->getValueType(0))) {
2593 default: assert(0 && "This action is not supported yet!");
2594 case TargetLowering::Legal: break;
2595 case TargetLowering::Custom:
2596 Tmp1 = TLI.LowerOperation(Result, DAG);
2598 SDOperand Tmp2, RetVal(0, 0);
2599 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2600 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2601 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2605 assert(RetVal.Val && "Illegal result number");
2611 // Since these produce multiple values, make sure to remember that we
2612 // legalized all of them.
2613 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2614 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2615 return Result.getValue(Op.ResNo);
2637 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2638 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2639 case Expand: assert(0 && "Not possible");
2641 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2644 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2648 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2650 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2651 default: assert(0 && "BinOp legalize operation not supported");
2652 case TargetLowering::Legal: break;
2653 case TargetLowering::Custom:
2654 Tmp1 = TLI.LowerOperation(Result, DAG);
2655 if (Tmp1.Val) Result = Tmp1;
2657 case TargetLowering::Expand: {
2658 MVT::ValueType VT = Op.getValueType();
2660 // See if multiply or divide can be lowered using two-result operations.
2661 SDVTList VTs = DAG.getVTList(VT, VT);
2662 if (Node->getOpcode() == ISD::MUL) {
2663 // We just need the low half of the multiply; try both the signed
2664 // and unsigned forms. If the target supports both SMUL_LOHI and
2665 // UMUL_LOHI, form a preference by checking which forms of plain
2666 // MULH it supports.
2667 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2668 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2669 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2670 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2671 unsigned OpToUse = 0;
2672 if (HasSMUL_LOHI && !HasMULHS) {
2673 OpToUse = ISD::SMUL_LOHI;
2674 } else if (HasUMUL_LOHI && !HasMULHU) {
2675 OpToUse = ISD::UMUL_LOHI;
2676 } else if (HasSMUL_LOHI) {
2677 OpToUse = ISD::SMUL_LOHI;
2678 } else if (HasUMUL_LOHI) {
2679 OpToUse = ISD::UMUL_LOHI;
2682 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2686 if (Node->getOpcode() == ISD::MULHS &&
2687 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2688 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2691 if (Node->getOpcode() == ISD::MULHU &&
2692 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2693 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2696 if (Node->getOpcode() == ISD::SDIV &&
2697 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2698 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2701 if (Node->getOpcode() == ISD::UDIV &&
2702 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2703 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2707 // Check to see if we have a libcall for this operator.
2708 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2709 bool isSigned = false;
2710 switch (Node->getOpcode()) {
2713 if (VT == MVT::i32) {
2714 LC = Node->getOpcode() == ISD::UDIV
2715 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2716 isSigned = Node->getOpcode() == ISD::SDIV;
2720 LC = VT == MVT::f32 ? RTLIB::POW_F32 :
2721 VT == MVT::f64 ? RTLIB::POW_F64 :
2722 VT == MVT::f80 ? RTLIB::POW_F80 :
2723 VT == MVT::ppcf128 ? RTLIB::POW_PPCF128 :
2724 RTLIB::UNKNOWN_LIBCALL;
2728 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2730 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2734 assert(MVT::isVector(Node->getValueType(0)) &&
2735 "Cannot expand this binary operator!");
2736 // Expand the operation into a bunch of nasty scalar code.
2737 Result = LegalizeOp(UnrollVectorOp(Op));
2740 case TargetLowering::Promote: {
2741 switch (Node->getOpcode()) {
2742 default: assert(0 && "Do not know how to promote this BinOp!");
2746 MVT::ValueType OVT = Node->getValueType(0);
2747 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2748 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2749 // Bit convert each of the values to the new type.
2750 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2751 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2752 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2753 // Bit convert the result back the original type.
2754 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2762 case ISD::SMUL_LOHI:
2763 case ISD::UMUL_LOHI:
2766 // These nodes will only be produced by target-specific lowering, so
2767 // they shouldn't be here if they aren't legal.
2768 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2769 "This must be legal!");
2771 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2772 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2773 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2776 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2777 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2778 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2779 case Expand: assert(0 && "Not possible");
2781 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2784 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2790 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2791 default: assert(0 && "Operation not supported");
2792 case TargetLowering::Custom:
2793 Tmp1 = TLI.LowerOperation(Result, DAG);
2794 if (Tmp1.Val) Result = Tmp1;
2796 case TargetLowering::Legal: break;
2797 case TargetLowering::Expand: {
2798 // If this target supports fabs/fneg natively and select is cheap,
2799 // do this efficiently.
2800 if (!TLI.isSelectExpensive() &&
2801 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2802 TargetLowering::Legal &&
2803 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2804 TargetLowering::Legal) {
2805 // Get the sign bit of the RHS.
2806 MVT::ValueType IVT =
2807 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2808 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2809 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2810 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2811 // Get the absolute value of the result.
2812 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2813 // Select between the nabs and abs value based on the sign bit of
2815 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2816 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2819 Result = LegalizeOp(Result);
2823 // Otherwise, do bitwise ops!
2824 MVT::ValueType NVT =
2825 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2826 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2827 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2828 Result = LegalizeOp(Result);
2836 Tmp1 = LegalizeOp(Node->getOperand(0));
2837 Tmp2 = LegalizeOp(Node->getOperand(1));
2838 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2839 // Since this produces two values, make sure to remember that we legalized
2841 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2842 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2847 Tmp1 = LegalizeOp(Node->getOperand(0));
2848 Tmp2 = LegalizeOp(Node->getOperand(1));
2849 Tmp3 = LegalizeOp(Node->getOperand(2));
2850 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2851 // Since this produces two values, make sure to remember that we legalized
2853 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2854 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2857 case ISD::BUILD_PAIR: {
2858 MVT::ValueType PairTy = Node->getValueType(0);
2859 // TODO: handle the case where the Lo and Hi operands are not of legal type
2860 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2861 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2862 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2863 case TargetLowering::Promote:
2864 case TargetLowering::Custom:
2865 assert(0 && "Cannot promote/custom this yet!");
2866 case TargetLowering::Legal:
2867 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2868 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2870 case TargetLowering::Expand:
2871 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2872 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2873 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2874 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2875 TLI.getShiftAmountTy()));
2876 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2885 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2886 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2888 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2889 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2890 case TargetLowering::Custom:
2893 case TargetLowering::Legal:
2894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2896 Tmp1 = TLI.LowerOperation(Result, DAG);
2897 if (Tmp1.Val) Result = Tmp1;
2900 case TargetLowering::Expand: {
2901 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2902 bool isSigned = DivOpc == ISD::SDIV;
2903 MVT::ValueType VT = Node->getValueType(0);
2905 // See if remainder can be lowered using two-result operations.
2906 SDVTList VTs = DAG.getVTList(VT, VT);
2907 if (Node->getOpcode() == ISD::SREM &&
2908 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2909 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2912 if (Node->getOpcode() == ISD::UREM &&
2913 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2914 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2918 if (MVT::isInteger(VT)) {
2919 if (TLI.getOperationAction(DivOpc, VT) ==
2920 TargetLowering::Legal) {
2922 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2923 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2924 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2926 assert(VT == MVT::i32 &&
2927 "Cannot expand this binary operator!");
2928 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2929 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2931 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2934 // Floating point mod -> fmod libcall.
2935 RTLIB::Libcall LC = VT == MVT::f32
2936 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2938 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2939 false/*sign irrelevant*/, Dummy);
2946 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2947 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2949 MVT::ValueType VT = Node->getValueType(0);
2950 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2951 default: assert(0 && "This action is not supported yet!");
2952 case TargetLowering::Custom:
2955 case TargetLowering::Legal:
2956 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2957 Result = Result.getValue(0);
2958 Tmp1 = Result.getValue(1);
2961 Tmp2 = TLI.LowerOperation(Result, DAG);
2963 Result = LegalizeOp(Tmp2);
2964 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2968 case TargetLowering::Expand: {
2969 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2970 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2971 SV->getValue(), SV->getOffset());
2972 // Increment the pointer, VAList, to the next vaarg
2973 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2974 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2975 TLI.getPointerTy()));
2976 // Store the incremented VAList to the legalized pointer
2977 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2979 // Load the actual argument out of the pointer VAList
2980 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2981 Tmp1 = LegalizeOp(Result.getValue(1));
2982 Result = LegalizeOp(Result);
2986 // Since VAARG produces two values, make sure to remember that we
2987 // legalized both of them.
2988 AddLegalizedOperand(SDOperand(Node, 0), Result);
2989 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2990 return Op.ResNo ? Tmp1 : Result;
2994 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2995 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2996 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2998 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2999 default: assert(0 && "This action is not supported yet!");
3000 case TargetLowering::Custom:
3003 case TargetLowering::Legal:
3004 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3005 Node->getOperand(3), Node->getOperand(4));
3007 Tmp1 = TLI.LowerOperation(Result, DAG);
3008 if (Tmp1.Val) Result = Tmp1;
3011 case TargetLowering::Expand:
3012 // This defaults to loading a pointer from the input and storing it to the
3013 // output, returning the chain.
3014 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
3015 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
3016 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
3018 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
3025 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3026 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3028 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3029 default: assert(0 && "This action is not supported yet!");
3030 case TargetLowering::Custom:
3033 case TargetLowering::Legal:
3034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3036 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3037 if (Tmp1.Val) Result = Tmp1;
3040 case TargetLowering::Expand:
3041 Result = Tmp1; // Default to a no-op, return the chain
3047 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3048 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3050 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3052 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3053 default: assert(0 && "This action is not supported yet!");
3054 case TargetLowering::Legal: break;
3055 case TargetLowering::Custom:
3056 Tmp1 = TLI.LowerOperation(Result, DAG);
3057 if (Tmp1.Val) Result = Tmp1;
3064 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3065 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3066 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3067 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3069 assert(0 && "ROTL/ROTR legalize operation not supported");
3071 case TargetLowering::Legal:
3073 case TargetLowering::Custom:
3074 Tmp1 = TLI.LowerOperation(Result, DAG);
3075 if (Tmp1.Val) Result = Tmp1;
3077 case TargetLowering::Promote:
3078 assert(0 && "Do not know how to promote ROTL/ROTR");
3080 case TargetLowering::Expand:
3081 assert(0 && "Do not know how to expand ROTL/ROTR");
3087 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3088 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3089 case TargetLowering::Custom:
3090 assert(0 && "Cannot custom legalize this yet!");
3091 case TargetLowering::Legal:
3092 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3094 case TargetLowering::Promote: {
3095 MVT::ValueType OVT = Tmp1.getValueType();
3096 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3097 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3099 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3100 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3101 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3102 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3105 case TargetLowering::Expand:
3106 Result = ExpandBSWAP(Tmp1);
3114 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3115 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3116 case TargetLowering::Custom:
3117 case TargetLowering::Legal:
3118 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3119 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3120 TargetLowering::Custom) {
3121 Tmp1 = TLI.LowerOperation(Result, DAG);
3127 case TargetLowering::Promote: {
3128 MVT::ValueType OVT = Tmp1.getValueType();
3129 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3131 // Zero extend the argument.
3132 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3133 // Perform the larger operation, then subtract if needed.
3134 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3135 switch (Node->getOpcode()) {
3140 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3141 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3142 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3144 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3145 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3148 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3149 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3150 DAG.getConstant(MVT::getSizeInBits(NVT) -
3151 MVT::getSizeInBits(OVT), NVT));
3156 case TargetLowering::Expand:
3157 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3168 Tmp1 = LegalizeOp(Node->getOperand(0));
3169 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3170 case TargetLowering::Promote:
3171 case TargetLowering::Custom:
3174 case TargetLowering::Legal:
3175 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3177 Tmp1 = TLI.LowerOperation(Result, DAG);
3178 if (Tmp1.Val) Result = Tmp1;
3181 case TargetLowering::Expand:
3182 switch (Node->getOpcode()) {
3183 default: assert(0 && "Unreachable!");
3185 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3186 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3187 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3190 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3191 MVT::ValueType VT = Node->getValueType(0);
3192 Tmp2 = DAG.getConstantFP(0.0, VT);
3193 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3194 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3195 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3201 MVT::ValueType VT = Node->getValueType(0);
3203 // Expand unsupported unary vector operators by unrolling them.
3204 if (MVT::isVector(VT)) {
3205 Result = LegalizeOp(UnrollVectorOp(Op));
3209 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3210 switch(Node->getOpcode()) {
3212 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 :
3213 VT == MVT::f64 ? RTLIB::SQRT_F64 :
3214 VT == MVT::f80 ? RTLIB::SQRT_F80 :
3215 VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 :
3216 RTLIB::UNKNOWN_LIBCALL;
3219 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
3222 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
3224 default: assert(0 && "Unreachable!");
3227 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3228 false/*sign irrelevant*/, Dummy);
3236 MVT::ValueType VT = Node->getValueType(0);
3238 // Expand unsupported unary vector operators by unrolling them.
3239 if (MVT::isVector(VT)) {
3240 Result = LegalizeOp(UnrollVectorOp(Op));
3244 // We always lower FPOWI into a libcall. No target support for it yet.
3246 VT == MVT::f32 ? RTLIB::POWI_F32 :
3247 VT == MVT::f64 ? RTLIB::POWI_F64 :
3248 VT == MVT::f80 ? RTLIB::POWI_F80 :
3249 VT == MVT::ppcf128 ? RTLIB::POWI_PPCF128 :
3250 RTLIB::UNKNOWN_LIBCALL;
3252 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3253 false/*sign irrelevant*/, Dummy);
3256 case ISD::BIT_CONVERT:
3257 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3258 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3259 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3260 // The input has to be a vector type, we have to either scalarize it, pack
3261 // it, or convert it based on whether the input vector type is legal.
3262 SDNode *InVal = Node->getOperand(0).Val;
3263 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3264 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3266 // Figure out if there is a simple type corresponding to this Vector
3267 // type. If so, convert to the vector type.
3268 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3269 if (TLI.isTypeLegal(TVT)) {
3270 // Turn this into a bit convert of the vector input.
3271 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3272 LegalizeOp(Node->getOperand(0)));
3274 } else if (NumElems == 1) {
3275 // Turn this into a bit convert of the scalar input.
3276 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3277 ScalarizeVectorOp(Node->getOperand(0)));
3280 // FIXME: UNIMP! Store then reload
3281 assert(0 && "Cast from unsupported vector type not implemented yet!");
3284 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3285 Node->getOperand(0).getValueType())) {
3286 default: assert(0 && "Unknown operation action!");
3287 case TargetLowering::Expand:
3288 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3290 case TargetLowering::Legal:
3291 Tmp1 = LegalizeOp(Node->getOperand(0));
3292 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3298 // Conversion operators. The source and destination have different types.
3299 case ISD::SINT_TO_FP:
3300 case ISD::UINT_TO_FP: {
3301 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3302 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3304 switch (TLI.getOperationAction(Node->getOpcode(),
3305 Node->getOperand(0).getValueType())) {
3306 default: assert(0 && "Unknown operation action!");
3307 case TargetLowering::Custom:
3310 case TargetLowering::Legal:
3311 Tmp1 = LegalizeOp(Node->getOperand(0));
3312 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3314 Tmp1 = TLI.LowerOperation(Result, DAG);
3315 if (Tmp1.Val) Result = Tmp1;
3318 case TargetLowering::Expand:
3319 Result = ExpandLegalINT_TO_FP(isSigned,
3320 LegalizeOp(Node->getOperand(0)),
3321 Node->getValueType(0));
3323 case TargetLowering::Promote:
3324 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3325 Node->getValueType(0),
3331 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3332 Node->getValueType(0), Node->getOperand(0));
3335 Tmp1 = PromoteOp(Node->getOperand(0));
3337 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3338 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3340 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3341 Node->getOperand(0).getValueType());
3343 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3344 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3350 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3352 Tmp1 = LegalizeOp(Node->getOperand(0));
3353 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3356 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3358 // Since the result is legal, we should just be able to truncate the low
3359 // part of the source.
3360 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3363 Result = PromoteOp(Node->getOperand(0));
3364 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3369 case ISD::FP_TO_SINT:
3370 case ISD::FP_TO_UINT:
3371 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3373 Tmp1 = LegalizeOp(Node->getOperand(0));
3375 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3376 default: assert(0 && "Unknown operation action!");
3377 case TargetLowering::Custom:
3380 case TargetLowering::Legal:
3381 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3383 Tmp1 = TLI.LowerOperation(Result, DAG);
3384 if (Tmp1.Val) Result = Tmp1;
3387 case TargetLowering::Promote:
3388 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3389 Node->getOpcode() == ISD::FP_TO_SINT);
3391 case TargetLowering::Expand:
3392 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3393 SDOperand True, False;
3394 MVT::ValueType VT = Node->getOperand(0).getValueType();
3395 MVT::ValueType NVT = Node->getValueType(0);
3396 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3397 const uint64_t zero[] = {0, 0};
3398 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3399 uint64_t x = 1ULL << ShiftAmt;
3400 (void)apf.convertFromZeroExtendedInteger
3401 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3402 Tmp2 = DAG.getConstantFP(apf, VT);
3403 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3404 Node->getOperand(0), Tmp2, ISD::SETLT);
3405 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3406 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3407 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3409 False = DAG.getNode(ISD::XOR, NVT, False,
3410 DAG.getConstant(1ULL << ShiftAmt, NVT));
3411 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3414 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3420 MVT::ValueType VT = Op.getValueType();
3421 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3422 // Convert ppcf128 to i32
3423 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3424 if (Node->getOpcode()==ISD::FP_TO_SINT)
3425 Result = DAG.getNode(ISD::FP_TO_SINT, VT,
3426 DAG.getNode(ISD::FP_ROUND, MVT::f64,
3427 (DAG.getNode(ISD::FP_ROUND_INREG,
3428 MVT::ppcf128, Node->getOperand(0),
3429 DAG.getValueType(MVT::f64)))));
3431 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3432 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3433 Tmp2 = DAG.getConstantFP(apf, OVT);
3434 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3435 // FIXME: generated code sucks.
3436 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3437 DAG.getNode(ISD::ADD, MVT::i32,
3438 DAG.getNode(ISD::FP_TO_SINT, VT,
3439 DAG.getNode(ISD::FSUB, OVT,
3440 Node->getOperand(0), Tmp2)),
3441 DAG.getConstant(0x80000000, MVT::i32)),
3442 DAG.getNode(ISD::FP_TO_SINT, VT,
3443 Node->getOperand(0)),
3444 DAG.getCondCode(ISD::SETGE));
3448 // Convert f32 / f64 to i32 / i64.
3449 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3450 switch (Node->getOpcode()) {
3451 case ISD::FP_TO_SINT: {
3452 if (OVT == MVT::f32)
3453 LC = (VT == MVT::i32)
3454 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3455 else if (OVT == MVT::f64)
3456 LC = (VT == MVT::i32)
3457 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3458 else if (OVT == MVT::f80) {
3459 assert(VT == MVT::i64);
3460 LC = RTLIB::FPTOSINT_F80_I64;
3462 else if (OVT == MVT::ppcf128) {
3463 assert(VT == MVT::i64);
3464 LC = RTLIB::FPTOSINT_PPCF128_I64;
3468 case ISD::FP_TO_UINT: {
3469 if (OVT == MVT::f32)
3470 LC = (VT == MVT::i32)
3471 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3472 else if (OVT == MVT::f64)
3473 LC = (VT == MVT::i32)
3474 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3475 else if (OVT == MVT::f80) {
3476 LC = (VT == MVT::i32)
3477 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3479 else if (OVT == MVT::ppcf128) {
3480 assert(VT == MVT::i64);
3481 LC = RTLIB::FPTOUINT_PPCF128_I64;
3485 default: assert(0 && "Unreachable!");
3488 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3489 false/*sign irrelevant*/, Dummy);
3493 Tmp1 = PromoteOp(Node->getOperand(0));
3494 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3495 Result = LegalizeOp(Result);
3500 case ISD::FP_EXTEND:
3501 case ISD::FP_ROUND: {
3502 MVT::ValueType newVT = Op.getValueType();
3503 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3504 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3505 if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) {
3507 ExpandOp(Node->getOperand(0), Lo, Hi);
3508 if (newVT == MVT::f64)
3511 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi);
3514 // The only other way we can lower this is to turn it into a STORE,
3515 // LOAD pair, targetting a temporary location (a stack slot).
3517 // NOTE: there is a choice here between constantly creating new stack
3518 // slots and always reusing the same one. We currently always create
3519 // new ones, as reuse may inhibit scheduling.
3520 MVT::ValueType slotVT =
3521 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3522 const Type *Ty = MVT::getTypeForValueType(slotVT);
3523 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3524 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3525 MachineFunction &MF = DAG.getMachineFunction();
3527 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3528 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3529 if (Node->getOpcode() == ISD::FP_EXTEND) {
3530 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3531 StackSlot, NULL, 0);
3532 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3533 Result, StackSlot, NULL, 0, oldVT);
3535 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3536 StackSlot, NULL, 0, newVT);
3537 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0);
3544 case ISD::ANY_EXTEND:
3545 case ISD::ZERO_EXTEND:
3546 case ISD::SIGN_EXTEND:
3547 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3548 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3550 Tmp1 = LegalizeOp(Node->getOperand(0));
3551 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3554 switch (Node->getOpcode()) {
3555 case ISD::ANY_EXTEND:
3556 Tmp1 = PromoteOp(Node->getOperand(0));
3557 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3559 case ISD::ZERO_EXTEND:
3560 Result = PromoteOp(Node->getOperand(0));
3561 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3562 Result = DAG.getZeroExtendInReg(Result,
3563 Node->getOperand(0).getValueType());
3565 case ISD::SIGN_EXTEND:
3566 Result = PromoteOp(Node->getOperand(0));
3567 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3568 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3570 DAG.getValueType(Node->getOperand(0).getValueType()));
3572 case ISD::FP_EXTEND:
3573 Result = PromoteOp(Node->getOperand(0));
3574 if (Result.getValueType() != Op.getValueType())
3575 // Dynamically dead while we have only 2 FP types.
3576 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3579 Result = PromoteOp(Node->getOperand(0));
3580 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3585 case ISD::FP_ROUND_INREG:
3586 case ISD::SIGN_EXTEND_INREG: {
3587 Tmp1 = LegalizeOp(Node->getOperand(0));
3588 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3590 // If this operation is not supported, convert it to a shl/shr or load/store
3592 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3593 default: assert(0 && "This action not supported for this op yet!");
3594 case TargetLowering::Legal:
3595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3597 case TargetLowering::Expand:
3598 // If this is an integer extend and shifts are supported, do that.
3599 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3600 // NOTE: we could fall back on load/store here too for targets without
3601 // SAR. However, it is doubtful that any exist.
3602 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3603 MVT::getSizeInBits(ExtraVT);
3604 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3605 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3606 Node->getOperand(0), ShiftCst);
3607 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3609 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3610 // The only way we can lower this is to turn it into a TRUNCSTORE,
3611 // EXTLOAD pair, targetting a temporary location (a stack slot).
3613 // NOTE: there is a choice here between constantly creating new stack
3614 // slots and always reusing the same one. We currently always create
3615 // new ones, as reuse may inhibit scheduling.
3616 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3617 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3618 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3619 MachineFunction &MF = DAG.getMachineFunction();
3621 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3622 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3623 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3624 StackSlot, NULL, 0, ExtraVT);
3625 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3626 Result, StackSlot, NULL, 0, ExtraVT);
3628 assert(0 && "Unknown op");
3634 case ISD::TRAMPOLINE: {
3636 for (unsigned i = 0; i != 6; ++i)
3637 Ops[i] = LegalizeOp(Node->getOperand(i));
3638 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3639 // The only option for this node is to custom lower it.
3640 Result = TLI.LowerOperation(Result, DAG);
3641 assert(Result.Val && "Should always custom lower!");
3643 // Since trampoline produces two values, make sure to remember that we
3644 // legalized both of them.
3645 Tmp1 = LegalizeOp(Result.getValue(1));
3646 Result = LegalizeOp(Result);
3647 AddLegalizedOperand(SDOperand(Node, 0), Result);
3648 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3649 return Op.ResNo ? Tmp1 : Result;
3653 assert(Result.getValueType() == Op.getValueType() &&
3654 "Bad legalization!");
3656 // Make sure that the generated code is itself legal.
3658 Result = LegalizeOp(Result);
3660 // Note that LegalizeOp may be reentered even from single-use nodes, which
3661 // means that we always must cache transformed nodes.
3662 AddLegalizedOperand(Op, Result);
3666 /// PromoteOp - Given an operation that produces a value in an invalid type,
3667 /// promote it to compute the value into a larger type. The produced value will
3668 /// have the correct bits for the low portion of the register, but no guarantee
3669 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3670 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3671 MVT::ValueType VT = Op.getValueType();
3672 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3673 assert(getTypeAction(VT) == Promote &&
3674 "Caller should expand or legalize operands that are not promotable!");
3675 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3676 "Cannot promote to smaller type!");
3678 SDOperand Tmp1, Tmp2, Tmp3;
3680 SDNode *Node = Op.Val;
3682 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3683 if (I != PromotedNodes.end()) return I->second;
3685 switch (Node->getOpcode()) {
3686 case ISD::CopyFromReg:
3687 assert(0 && "CopyFromReg must be legal!");
3690 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3692 assert(0 && "Do not know how to promote this operator!");
3695 Result = DAG.getNode(ISD::UNDEF, NVT);
3699 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3701 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3702 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3704 case ISD::ConstantFP:
3705 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3706 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3710 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3711 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3712 Node->getOperand(1), Node->getOperand(2));
3716 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3718 Result = LegalizeOp(Node->getOperand(0));
3719 assert(Result.getValueType() >= NVT &&
3720 "This truncation doesn't make sense!");
3721 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3722 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3725 // The truncation is not required, because we don't guarantee anything
3726 // about high bits anyway.
3727 Result = PromoteOp(Node->getOperand(0));
3730 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3731 // Truncate the low part of the expanded value to the result type
3732 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3735 case ISD::SIGN_EXTEND:
3736 case ISD::ZERO_EXTEND:
3737 case ISD::ANY_EXTEND:
3738 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3739 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3741 // Input is legal? Just do extend all the way to the larger type.
3742 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3745 // Promote the reg if it's smaller.
3746 Result = PromoteOp(Node->getOperand(0));
3747 // The high bits are not guaranteed to be anything. Insert an extend.
3748 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3749 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3750 DAG.getValueType(Node->getOperand(0).getValueType()));
3751 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3752 Result = DAG.getZeroExtendInReg(Result,
3753 Node->getOperand(0).getValueType());
3757 case ISD::BIT_CONVERT:
3758 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3759 Result = PromoteOp(Result);
3762 case ISD::FP_EXTEND:
3763 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3765 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3766 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3767 case Promote: assert(0 && "Unreachable with 2 FP types!");
3769 // Input is legal? Do an FP_ROUND_INREG.
3770 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3771 DAG.getValueType(VT));
3776 case ISD::SINT_TO_FP:
3777 case ISD::UINT_TO_FP:
3778 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3780 // No extra round required here.
3781 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3785 Result = PromoteOp(Node->getOperand(0));
3786 if (Node->getOpcode() == ISD::SINT_TO_FP)
3787 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3789 DAG.getValueType(Node->getOperand(0).getValueType()));
3791 Result = DAG.getZeroExtendInReg(Result,
3792 Node->getOperand(0).getValueType());
3793 // No extra round required here.
3794 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3797 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3798 Node->getOperand(0));
3799 // Round if we cannot tolerate excess precision.
3800 if (NoExcessFPPrecision)
3801 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3802 DAG.getValueType(VT));
3807 case ISD::SIGN_EXTEND_INREG:
3808 Result = PromoteOp(Node->getOperand(0));
3809 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3810 Node->getOperand(1));
3812 case ISD::FP_TO_SINT:
3813 case ISD::FP_TO_UINT:
3814 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3817 Tmp1 = Node->getOperand(0);
3820 // The input result is prerounded, so we don't have to do anything
3822 Tmp1 = PromoteOp(Node->getOperand(0));
3825 // If we're promoting a UINT to a larger size, check to see if the new node
3826 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3827 // we can use that instead. This allows us to generate better code for
3828 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3829 // legal, such as PowerPC.
3830 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3831 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3832 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3833 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3834 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3836 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3842 Tmp1 = PromoteOp(Node->getOperand(0));
3843 assert(Tmp1.getValueType() == NVT);
3844 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3845 // NOTE: we do not have to do any extra rounding here for
3846 // NoExcessFPPrecision, because we know the input will have the appropriate
3847 // precision, and these operations don't modify precision at all.
3853 Tmp1 = PromoteOp(Node->getOperand(0));
3854 assert(Tmp1.getValueType() == NVT);
3855 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3856 if (NoExcessFPPrecision)
3857 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3858 DAG.getValueType(VT));
3862 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3863 // directly as well, which may be better.
3864 Tmp1 = PromoteOp(Node->getOperand(0));
3865 assert(Tmp1.getValueType() == NVT);
3866 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3867 if (NoExcessFPPrecision)
3868 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3869 DAG.getValueType(VT));
3879 // The input may have strange things in the top bits of the registers, but
3880 // these operations don't care. They may have weird bits going out, but
3881 // that too is okay if they are integer operations.
3882 Tmp1 = PromoteOp(Node->getOperand(0));
3883 Tmp2 = PromoteOp(Node->getOperand(1));
3884 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3885 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3890 Tmp1 = PromoteOp(Node->getOperand(0));
3891 Tmp2 = PromoteOp(Node->getOperand(1));
3892 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3893 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3895 // Floating point operations will give excess precision that we may not be
3896 // able to tolerate. If we DO allow excess precision, just leave it,
3897 // otherwise excise it.
3898 // FIXME: Why would we need to round FP ops more than integer ones?
3899 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3900 if (NoExcessFPPrecision)
3901 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3902 DAG.getValueType(VT));
3907 // These operators require that their input be sign extended.
3908 Tmp1 = PromoteOp(Node->getOperand(0));
3909 Tmp2 = PromoteOp(Node->getOperand(1));
3910 if (MVT::isInteger(NVT)) {
3911 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3912 DAG.getValueType(VT));
3913 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3914 DAG.getValueType(VT));
3916 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3918 // Perform FP_ROUND: this is probably overly pessimistic.
3919 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3920 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3921 DAG.getValueType(VT));
3925 case ISD::FCOPYSIGN:
3926 // These operators require that their input be fp extended.
3927 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3929 Tmp1 = LegalizeOp(Node->getOperand(0));
3932 Tmp1 = PromoteOp(Node->getOperand(0));
3935 assert(0 && "not implemented");
3937 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3939 Tmp2 = LegalizeOp(Node->getOperand(1));
3942 Tmp2 = PromoteOp(Node->getOperand(1));
3945 assert(0 && "not implemented");
3947 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3949 // Perform FP_ROUND: this is probably overly pessimistic.
3950 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3951 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3952 DAG.getValueType(VT));
3957 // These operators require that their input be zero extended.
3958 Tmp1 = PromoteOp(Node->getOperand(0));
3959 Tmp2 = PromoteOp(Node->getOperand(1));
3960 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3961 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3962 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3963 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3967 Tmp1 = PromoteOp(Node->getOperand(0));
3968 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3971 // The input value must be properly sign extended.
3972 Tmp1 = PromoteOp(Node->getOperand(0));
3973 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3974 DAG.getValueType(VT));
3975 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3978 // The input value must be properly zero extended.
3979 Tmp1 = PromoteOp(Node->getOperand(0));
3980 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3981 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3985 Tmp1 = Node->getOperand(0); // Get the chain.
3986 Tmp2 = Node->getOperand(1); // Get the pointer.
3987 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3988 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3989 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3991 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3992 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3993 SV->getValue(), SV->getOffset());
3994 // Increment the pointer, VAList, to the next vaarg
3995 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3996 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3997 TLI.getPointerTy()));
3998 // Store the incremented VAList to the legalized pointer
3999 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
4001 // Load the actual argument out of the pointer VAList
4002 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4004 // Remember that we legalized the chain.
4005 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4009 LoadSDNode *LD = cast<LoadSDNode>(Node);
4010 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4011 ? ISD::EXTLOAD : LD->getExtensionType();
4012 Result = DAG.getExtLoad(ExtType, NVT,
4013 LD->getChain(), LD->getBasePtr(),
4014 LD->getSrcValue(), LD->getSrcValueOffset(),
4017 LD->getAlignment());
4018 // Remember that we legalized the chain.
4019 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4023 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4024 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4025 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4027 case ISD::SELECT_CC:
4028 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4029 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4030 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4031 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4034 Tmp1 = Node->getOperand(0);
4035 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4036 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4037 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4038 DAG.getConstant(MVT::getSizeInBits(NVT) -
4039 MVT::getSizeInBits(VT),
4040 TLI.getShiftAmountTy()));
4045 // Zero extend the argument
4046 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4047 // Perform the larger operation, then subtract if needed.
4048 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4049 switch(Node->getOpcode()) {
4054 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4055 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4056 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4058 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4059 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4062 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4063 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4064 DAG.getConstant(MVT::getSizeInBits(NVT) -
4065 MVT::getSizeInBits(VT), NVT));
4069 case ISD::EXTRACT_SUBVECTOR:
4070 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4072 case ISD::EXTRACT_VECTOR_ELT:
4073 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4077 assert(Result.Val && "Didn't set a result!");
4079 // Make sure the result is itself legal.
4080 Result = LegalizeOp(Result);
4082 // Remember that we promoted this!
4083 AddPromotedOperand(Op, Result);
4087 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4088 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4089 /// based on the vector type. The return type of this matches the element type
4090 /// of the vector, which may not be legal for the target.
4091 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4092 // We know that operand #0 is the Vec vector. If the index is a constant
4093 // or if the invec is a supported hardware type, we can use it. Otherwise,
4094 // lower to a store then an indexed load.
4095 SDOperand Vec = Op.getOperand(0);
4096 SDOperand Idx = Op.getOperand(1);
4098 MVT::ValueType TVT = Vec.getValueType();
4099 unsigned NumElems = MVT::getVectorNumElements(TVT);
4101 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4102 default: assert(0 && "This action is not supported yet!");
4103 case TargetLowering::Custom: {
4104 Vec = LegalizeOp(Vec);
4105 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4106 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4111 case TargetLowering::Legal:
4112 if (isTypeLegal(TVT)) {
4113 Vec = LegalizeOp(Vec);
4114 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4118 case TargetLowering::Expand:
4122 if (NumElems == 1) {
4123 // This must be an access of the only element. Return it.
4124 Op = ScalarizeVectorOp(Vec);
4125 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4126 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4128 SplitVectorOp(Vec, Lo, Hi);
4129 if (CIdx->getValue() < NumElems/2) {
4133 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
4134 Idx.getValueType());
4137 // It's now an extract from the appropriate high or low part. Recurse.
4138 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4139 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4141 // Store the value to a temporary stack slot, then LOAD the scalar
4142 // element back out.
4143 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4144 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4146 // Add the offset to the index.
4147 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4148 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4149 DAG.getConstant(EltSize, Idx.getValueType()));
4151 if (MVT::getSizeInBits(Idx.getValueType()) >
4152 MVT::getSizeInBits(TLI.getPointerTy()))
4153 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), StackPtr);
4155 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), StackPtr);
4157 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4159 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4164 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4165 /// we assume the operation can be split if it is not already legal.
4166 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4167 // We know that operand #0 is the Vec vector. For now we assume the index
4168 // is a constant and that the extracted result is a supported hardware type.
4169 SDOperand Vec = Op.getOperand(0);
4170 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4172 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4174 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4175 // This must be an access of the desired vector length. Return it.
4179 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4181 SplitVectorOp(Vec, Lo, Hi);
4182 if (CIdx->getValue() < NumElems/2) {
4186 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4189 // It's now an extract from the appropriate high or low part. Recurse.
4190 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4191 return ExpandEXTRACT_SUBVECTOR(Op);
4194 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4195 /// with condition CC on the current target. This usually involves legalizing
4196 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4197 /// there may be no choice but to create a new SetCC node to represent the
4198 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4199 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4200 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4203 SDOperand Tmp1, Tmp2, Tmp3, Result;
4205 switch (getTypeAction(LHS.getValueType())) {
4207 Tmp1 = LegalizeOp(LHS); // LHS
4208 Tmp2 = LegalizeOp(RHS); // RHS
4211 Tmp1 = PromoteOp(LHS); // LHS
4212 Tmp2 = PromoteOp(RHS); // RHS
4214 // If this is an FP compare, the operands have already been extended.
4215 if (MVT::isInteger(LHS.getValueType())) {
4216 MVT::ValueType VT = LHS.getValueType();
4217 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4219 // Otherwise, we have to insert explicit sign or zero extends. Note
4220 // that we could insert sign extends for ALL conditions, but zero extend
4221 // is cheaper on many machines (an AND instead of two shifts), so prefer
4223 switch (cast<CondCodeSDNode>(CC)->get()) {
4224 default: assert(0 && "Unknown integer comparison!");
4231 // ALL of these operations will work if we either sign or zero extend
4232 // the operands (including the unsigned comparisons!). Zero extend is
4233 // usually a simpler/cheaper operation, so prefer it.
4234 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4235 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4241 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4242 DAG.getValueType(VT));
4243 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4244 DAG.getValueType(VT));
4250 MVT::ValueType VT = LHS.getValueType();
4251 if (VT == MVT::f32 || VT == MVT::f64) {
4252 // Expand into one or more soft-fp libcall(s).
4253 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4254 switch (cast<CondCodeSDNode>(CC)->get()) {
4257 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4261 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4265 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4269 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4273 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4277 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4280 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4283 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4286 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4287 switch (cast<CondCodeSDNode>(CC)->get()) {
4289 // SETONE = SETOLT | SETOGT
4290 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4293 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4296 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4299 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4302 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4305 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4307 default: assert(0 && "Unsupported FP setcc!");
4312 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4313 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4314 false /*sign irrelevant*/, Dummy);
4315 Tmp2 = DAG.getConstant(0, MVT::i32);
4316 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4317 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4318 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4319 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4320 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4321 false /*sign irrelevant*/, Dummy);
4322 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4323 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4324 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4332 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4333 ExpandOp(LHS, LHSLo, LHSHi);
4334 ExpandOp(RHS, RHSLo, RHSHi);
4335 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4337 if (VT==MVT::ppcf128) {
4338 // FIXME: This generated code sucks. We want to generate
4339 // FCMP crN, hi1, hi2
4341 // FCMP crN, lo1, lo2
4342 // The following can be improved, but not that much.
4343 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4344 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4345 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4346 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4347 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4348 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4349 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4358 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4359 if (RHSCST->isAllOnesValue()) {
4360 // Comparison to -1.
4361 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4366 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4367 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4368 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4369 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4372 // If this is a comparison of the sign bit, just look at the top part.
4374 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4375 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4376 CST->getValue() == 0) || // X < 0
4377 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4378 CST->isAllOnesValue())) { // X > -1
4384 // FIXME: This generated code sucks.
4385 ISD::CondCode LowCC;
4387 default: assert(0 && "Unknown integer setcc!");
4389 case ISD::SETULT: LowCC = ISD::SETULT; break;
4391 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4393 case ISD::SETULE: LowCC = ISD::SETULE; break;
4395 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4398 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4399 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4400 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4402 // NOTE: on targets without efficient SELECT of bools, we can always use
4403 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4404 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4405 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4406 false, DagCombineInfo);
4408 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4409 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4410 CCCode, false, DagCombineInfo);
4412 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4414 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4415 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4416 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4417 (Tmp2C && Tmp2C->getValue() == 0 &&
4418 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4419 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4420 (Tmp2C && Tmp2C->getValue() == 1 &&
4421 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4422 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4423 // low part is known false, returns high part.
4424 // For LE / GE, if high part is known false, ignore the low part.
4425 // For LT / GT, if high part is known true, ignore the low part.
4429 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4430 ISD::SETEQ, false, DagCombineInfo);
4432 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4433 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4434 Result, Tmp1, Tmp2));
4445 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4446 /// The resultant code need not be legal. Note that SrcOp is the input operand
4447 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4448 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4450 // Create the stack frame object.
4451 SDOperand FIPtr = DAG.CreateStackTemporary(DestVT);
4453 // Emit a store to the stack slot.
4454 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4455 // Result is a load from the stack slot.
4456 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4459 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4460 // Create a vector sized/aligned stack slot, store the value to element #0,
4461 // then load the whole vector back out.
4462 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4463 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4465 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4469 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4470 /// support the operation, but do support the resultant vector type.
4471 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4473 // If the only non-undef value is the low element, turn this into a
4474 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4475 unsigned NumElems = Node->getNumOperands();
4476 bool isOnlyLowElement = true;
4477 SDOperand SplatValue = Node->getOperand(0);
4478 std::map<SDOperand, std::vector<unsigned> > Values;
4479 Values[SplatValue].push_back(0);
4480 bool isConstant = true;
4481 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4482 SplatValue.getOpcode() != ISD::UNDEF)
4485 for (unsigned i = 1; i < NumElems; ++i) {
4486 SDOperand V = Node->getOperand(i);
4487 Values[V].push_back(i);
4488 if (V.getOpcode() != ISD::UNDEF)
4489 isOnlyLowElement = false;
4490 if (SplatValue != V)
4491 SplatValue = SDOperand(0,0);
4493 // If this isn't a constant element or an undef, we can't use a constant
4495 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4496 V.getOpcode() != ISD::UNDEF)
4500 if (isOnlyLowElement) {
4501 // If the low element is an undef too, then this whole things is an undef.
4502 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4503 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4504 // Otherwise, turn this into a scalar_to_vector node.
4505 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4506 Node->getOperand(0));
4509 // If all elements are constants, create a load from the constant pool.
4511 MVT::ValueType VT = Node->getValueType(0);
4513 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4514 std::vector<Constant*> CV;
4515 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4516 if (ConstantFPSDNode *V =
4517 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4518 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4519 } else if (ConstantSDNode *V =
4520 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4521 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4523 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4524 CV.push_back(UndefValue::get(OpNTy));
4527 Constant *CP = ConstantVector::get(CV);
4528 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4529 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4532 if (SplatValue.Val) { // Splat of one value?
4533 // Build the shuffle constant vector: <0, 0, 0, 0>
4534 MVT::ValueType MaskVT =
4535 MVT::getIntVectorWithNumElements(NumElems);
4536 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4537 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4538 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4539 &ZeroVec[0], ZeroVec.size());
4541 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4542 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4543 // Get the splatted value into the low element of a vector register.
4544 SDOperand LowValVec =
4545 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4547 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4548 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4549 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4554 // If there are only two unique elements, we may be able to turn this into a
4556 if (Values.size() == 2) {
4557 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4558 MVT::ValueType MaskVT =
4559 MVT::getIntVectorWithNumElements(NumElems);
4560 std::vector<SDOperand> MaskVec(NumElems);
4562 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4563 E = Values.end(); I != E; ++I) {
4564 for (std::vector<unsigned>::iterator II = I->second.begin(),
4565 EE = I->second.end(); II != EE; ++II)
4566 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4569 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4570 &MaskVec[0], MaskVec.size());
4572 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4573 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4574 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4575 SmallVector<SDOperand, 8> Ops;
4576 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4577 E = Values.end(); I != E; ++I) {
4578 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4582 Ops.push_back(ShuffleMask);
4584 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4585 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4586 &Ops[0], Ops.size());
4590 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4591 // aligned object on the stack, store each element into it, then load
4592 // the result as a vector.
4593 MVT::ValueType VT = Node->getValueType(0);
4594 // Create the stack frame object.
4595 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4597 // Emit a store of each element to the stack slot.
4598 SmallVector<SDOperand, 8> Stores;
4599 unsigned TypeByteSize =
4600 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4601 // Store (in the right endianness) the elements to memory.
4602 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4603 // Ignore undef elements.
4604 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4606 unsigned Offset = TypeByteSize*i;
4608 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4609 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4611 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4615 SDOperand StoreChain;
4616 if (!Stores.empty()) // Not all undef elements?
4617 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4618 &Stores[0], Stores.size());
4620 StoreChain = DAG.getEntryNode();
4622 // Result is a load from the stack slot.
4623 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4626 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4627 SDOperand Op, SDOperand Amt,
4628 SDOperand &Lo, SDOperand &Hi) {
4629 // Expand the subcomponents.
4630 SDOperand LHSL, LHSH;
4631 ExpandOp(Op, LHSL, LHSH);
4633 SDOperand Ops[] = { LHSL, LHSH, Amt };
4634 MVT::ValueType VT = LHSL.getValueType();
4635 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4636 Hi = Lo.getValue(1);
4640 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4641 /// smaller elements. If we can't find a way that is more efficient than a
4642 /// libcall on this target, return false. Otherwise, return true with the
4643 /// low-parts expanded into Lo and Hi.
4644 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4645 SDOperand &Lo, SDOperand &Hi) {
4646 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4647 "This is not a shift!");
4649 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4650 SDOperand ShAmt = LegalizeOp(Amt);
4651 MVT::ValueType ShTy = ShAmt.getValueType();
4652 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4653 unsigned NVTBits = MVT::getSizeInBits(NVT);
4655 // Handle the case when Amt is an immediate.
4656 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4657 unsigned Cst = CN->getValue();
4658 // Expand the incoming operand to be shifted, so that we have its parts
4660 ExpandOp(Op, InL, InH);
4664 Lo = DAG.getConstant(0, NVT);
4665 Hi = DAG.getConstant(0, NVT);
4666 } else if (Cst > NVTBits) {
4667 Lo = DAG.getConstant(0, NVT);
4668 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4669 } else if (Cst == NVTBits) {
4670 Lo = DAG.getConstant(0, NVT);
4673 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4674 Hi = DAG.getNode(ISD::OR, NVT,
4675 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4676 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4681 Lo = DAG.getConstant(0, NVT);
4682 Hi = DAG.getConstant(0, NVT);
4683 } else if (Cst > NVTBits) {
4684 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4685 Hi = DAG.getConstant(0, NVT);
4686 } else if (Cst == NVTBits) {
4688 Hi = DAG.getConstant(0, NVT);
4690 Lo = DAG.getNode(ISD::OR, NVT,
4691 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4692 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4693 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4698 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4699 DAG.getConstant(NVTBits-1, ShTy));
4700 } else if (Cst > NVTBits) {
4701 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4702 DAG.getConstant(Cst-NVTBits, ShTy));
4703 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4704 DAG.getConstant(NVTBits-1, ShTy));
4705 } else if (Cst == NVTBits) {
4707 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4708 DAG.getConstant(NVTBits-1, ShTy));
4710 Lo = DAG.getNode(ISD::OR, NVT,
4711 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4712 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4713 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4719 // Okay, the shift amount isn't constant. However, if we can tell that it is
4720 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4721 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4722 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4724 // If we know that the high bit of the shift amount is one, then we can do
4725 // this as a couple of simple shifts.
4726 if (KnownOne & Mask) {
4727 // Mask out the high bit, which we know is set.
4728 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4729 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4731 // Expand the incoming operand to be shifted, so that we have its parts
4733 ExpandOp(Op, InL, InH);
4736 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4737 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4740 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4741 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4744 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4745 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4746 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4751 // If we know that the high bit of the shift amount is zero, then we can do
4752 // this as a couple of simple shifts.
4753 if (KnownZero & Mask) {
4755 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4756 DAG.getConstant(NVTBits, Amt.getValueType()),
4759 // Expand the incoming operand to be shifted, so that we have its parts
4761 ExpandOp(Op, InL, InH);
4764 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4765 Hi = DAG.getNode(ISD::OR, NVT,
4766 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4767 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4770 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4771 Lo = DAG.getNode(ISD::OR, NVT,
4772 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4773 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4776 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4777 Lo = DAG.getNode(ISD::OR, NVT,
4778 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4779 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4788 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4789 // does not fit into a register, return the lo part and set the hi part to the
4790 // by-reg argument. If it does fit into a single register, return the result
4791 // and leave the Hi part unset.
4792 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4793 bool isSigned, SDOperand &Hi) {
4794 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4795 // The input chain to this libcall is the entry node of the function.
4796 // Legalizing the call will automatically add the previous call to the
4798 SDOperand InChain = DAG.getEntryNode();
4800 TargetLowering::ArgListTy Args;
4801 TargetLowering::ArgListEntry Entry;
4802 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4803 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4804 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4805 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4806 Entry.isSExt = isSigned;
4807 Args.push_back(Entry);
4809 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4811 // Splice the libcall in wherever FindInputOutputChains tells us to.
4812 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4813 std::pair<SDOperand,SDOperand> CallInfo =
4814 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4817 // Legalize the call sequence, starting with the chain. This will advance
4818 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4819 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4820 LegalizeOp(CallInfo.second);
4822 switch (getTypeAction(CallInfo.first.getValueType())) {
4823 default: assert(0 && "Unknown thing");
4825 Result = CallInfo.first;
4828 ExpandOp(CallInfo.first, Result, Hi);
4835 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4837 SDOperand SelectionDAGLegalize::
4838 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4839 assert(getTypeAction(Source.getValueType()) == Expand &&
4840 "This is not an expansion!");
4841 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4844 assert(Source.getValueType() == MVT::i64 &&
4845 "This only works for 64-bit -> FP");
4846 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4847 // incoming integer is set. To handle this, we dynamically test to see if
4848 // it is set, and, if so, add a fudge factor.
4850 ExpandOp(Source, Lo, Hi);
4852 // If this is unsigned, and not supported, first perform the conversion to
4853 // signed, then adjust the result if the sign bit is set.
4854 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4855 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4857 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4858 DAG.getConstant(0, Hi.getValueType()),
4860 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4861 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4862 SignSet, Four, Zero);
4863 uint64_t FF = 0x5f800000ULL;
4864 if (TLI.isLittleEndian()) FF <<= 32;
4865 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4867 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4868 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4869 SDOperand FudgeInReg;
4870 if (DestTy == MVT::f32)
4871 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4872 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4873 // FIXME: Avoid the extend by construction the right constantpool?
4874 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
4875 CPIdx, NULL, 0, MVT::f32);
4877 assert(0 && "Unexpected conversion");
4879 MVT::ValueType SCVT = SignedConv.getValueType();
4880 if (SCVT != DestTy) {
4881 // Destination type needs to be expanded as well. The FADD now we are
4882 // constructing will be expanded into a libcall.
4883 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4884 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4885 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4886 SignedConv, SignedConv.getValue(1));
4888 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4890 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4893 // Check to see if the target has a custom way to lower this. If so, use it.
4894 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4895 default: assert(0 && "This action not implemented for this operation!");
4896 case TargetLowering::Legal:
4897 case TargetLowering::Expand:
4898 break; // This case is handled below.
4899 case TargetLowering::Custom: {
4900 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4903 return LegalizeOp(NV);
4904 break; // The target decided this was legal after all
4908 // Expand the source, then glue it back together for the call. We must expand
4909 // the source in case it is shared (this pass of legalize must traverse it).
4910 SDOperand SrcLo, SrcHi;
4911 ExpandOp(Source, SrcLo, SrcHi);
4912 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4915 if (DestTy == MVT::f32)
4916 LC = RTLIB::SINTTOFP_I64_F32;
4918 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4919 LC = RTLIB::SINTTOFP_I64_F64;
4922 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4923 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4924 SDOperand UnusedHiPart;
4925 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4929 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4930 /// INT_TO_FP operation of the specified operand when the target requests that
4931 /// we expand it. At this point, we know that the result and operand types are
4932 /// legal for the target.
4933 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4935 MVT::ValueType DestVT) {
4936 if (Op0.getValueType() == MVT::i32) {
4937 // simple 32-bit [signed|unsigned] integer to float/double expansion
4939 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4940 MachineFunction &MF = DAG.getMachineFunction();
4941 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4942 unsigned StackAlign =
4943 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4944 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4945 // get address of 8 byte buffer
4946 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4947 // word offset constant for Hi/Lo address computation
4948 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4949 // set up Hi and Lo (into buffer) address based on endian
4950 SDOperand Hi = StackSlot;
4951 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4952 if (TLI.isLittleEndian())
4955 // if signed map to unsigned space
4956 SDOperand Op0Mapped;
4958 // constant used to invert sign bit (signed to unsigned mapping)
4959 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4960 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4964 // store the lo of the constructed double - based on integer input
4965 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4966 Op0Mapped, Lo, NULL, 0);
4967 // initial hi portion of constructed double
4968 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4969 // store the hi of the constructed double - biased exponent
4970 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4971 // load the constructed double
4972 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4973 // FP constant to bias correct the final result
4974 SDOperand Bias = DAG.getConstantFP(isSigned ?
4975 BitsToDouble(0x4330000080000000ULL)
4976 : BitsToDouble(0x4330000000000000ULL),
4978 // subtract the bias
4979 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4982 // handle final rounding
4983 if (DestVT == MVT::f64) {
4986 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
4987 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
4988 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
4989 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
4993 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4994 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4996 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4997 DAG.getConstant(0, Op0.getValueType()),
4999 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
5000 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5001 SignSet, Four, Zero);
5003 // If the sign bit of the integer is set, the large number will be treated
5004 // as a negative number. To counteract this, the dynamic code adds an
5005 // offset depending on the data type.
5007 switch (Op0.getValueType()) {
5008 default: assert(0 && "Unsupported integer type!");
5009 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5010 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5011 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5012 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5014 if (TLI.isLittleEndian()) FF <<= 32;
5015 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5017 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5018 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5019 SDOperand FudgeInReg;
5020 if (DestVT == MVT::f32)
5021 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5023 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5024 DAG.getEntryNode(), CPIdx,
5025 NULL, 0, MVT::f32));
5028 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5031 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5032 /// *INT_TO_FP operation of the specified operand when the target requests that
5033 /// we promote it. At this point, we know that the result and operand types are
5034 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5035 /// operation that takes a larger input.
5036 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5037 MVT::ValueType DestVT,
5039 // First step, figure out the appropriate *INT_TO_FP operation to use.
5040 MVT::ValueType NewInTy = LegalOp.getValueType();
5042 unsigned OpToUse = 0;
5044 // Scan for the appropriate larger type to use.
5046 NewInTy = (MVT::ValueType)(NewInTy+1);
5047 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5049 // If the target supports SINT_TO_FP of this type, use it.
5050 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5052 case TargetLowering::Legal:
5053 if (!TLI.isTypeLegal(NewInTy))
5054 break; // Can't use this datatype.
5056 case TargetLowering::Custom:
5057 OpToUse = ISD::SINT_TO_FP;
5061 if (isSigned) continue;
5063 // If the target supports UINT_TO_FP of this type, use it.
5064 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5066 case TargetLowering::Legal:
5067 if (!TLI.isTypeLegal(NewInTy))
5068 break; // Can't use this datatype.
5070 case TargetLowering::Custom:
5071 OpToUse = ISD::UINT_TO_FP;
5076 // Otherwise, try a larger type.
5079 // Okay, we found the operation and type to use. Zero extend our input to the
5080 // desired type then run the operation on it.
5081 return DAG.getNode(OpToUse, DestVT,
5082 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5086 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5087 /// FP_TO_*INT operation of the specified operand when the target requests that
5088 /// we promote it. At this point, we know that the result and operand types are
5089 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5090 /// operation that returns a larger result.
5091 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5092 MVT::ValueType DestVT,
5094 // First step, figure out the appropriate FP_TO*INT operation to use.
5095 MVT::ValueType NewOutTy = DestVT;
5097 unsigned OpToUse = 0;
5099 // Scan for the appropriate larger type to use.
5101 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5102 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5104 // If the target supports FP_TO_SINT returning this type, use it.
5105 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5107 case TargetLowering::Legal:
5108 if (!TLI.isTypeLegal(NewOutTy))
5109 break; // Can't use this datatype.
5111 case TargetLowering::Custom:
5112 OpToUse = ISD::FP_TO_SINT;
5117 // If the target supports FP_TO_UINT of this type, use it.
5118 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5120 case TargetLowering::Legal:
5121 if (!TLI.isTypeLegal(NewOutTy))
5122 break; // Can't use this datatype.
5124 case TargetLowering::Custom:
5125 OpToUse = ISD::FP_TO_UINT;
5130 // Otherwise, try a larger type.
5133 // Okay, we found the operation and type to use. Truncate the result of the
5134 // extended FP_TO_*INT operation to the desired size.
5135 return DAG.getNode(ISD::TRUNCATE, DestVT,
5136 DAG.getNode(OpToUse, NewOutTy, LegalOp));
5139 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5141 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5142 MVT::ValueType VT = Op.getValueType();
5143 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5144 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5146 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5148 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5149 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5150 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5152 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5153 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5154 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5155 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5156 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5157 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5158 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5159 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5160 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5162 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5163 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5164 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5165 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5166 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5167 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5168 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5169 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5170 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5171 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5172 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5173 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5174 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5175 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5176 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5177 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5178 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5179 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5180 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5181 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5182 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5186 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5188 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5190 default: assert(0 && "Cannot expand this yet!");
5192 static const uint64_t mask[6] = {
5193 0x5555555555555555ULL, 0x3333333333333333ULL,
5194 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5195 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5197 MVT::ValueType VT = Op.getValueType();
5198 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5199 unsigned len = MVT::getSizeInBits(VT);
5200 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5201 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5202 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5203 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5204 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5205 DAG.getNode(ISD::AND, VT,
5206 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5211 // for now, we do this:
5212 // x = x | (x >> 1);
5213 // x = x | (x >> 2);
5215 // x = x | (x >>16);
5216 // x = x | (x >>32); // for 64-bit input
5217 // return popcount(~x);
5219 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5220 MVT::ValueType VT = Op.getValueType();
5221 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5222 unsigned len = MVT::getSizeInBits(VT);
5223 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5224 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5225 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5227 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5228 return DAG.getNode(ISD::CTPOP, VT, Op);
5231 // for now, we use: { return popcount(~x & (x - 1)); }
5232 // unless the target has ctlz but not ctpop, in which case we use:
5233 // { return 32 - nlz(~x & (x-1)); }
5234 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5235 MVT::ValueType VT = Op.getValueType();
5236 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5237 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5238 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5239 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5240 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5241 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5242 TLI.isOperationLegal(ISD::CTLZ, VT))
5243 return DAG.getNode(ISD::SUB, VT,
5244 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5245 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5246 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5251 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5252 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5253 /// LegalizeNodes map is filled in for any results that are not expanded, the
5254 /// ExpandedNodes map is filled in for any results that are expanded, and the
5255 /// Lo/Hi values are returned.
5256 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5257 MVT::ValueType VT = Op.getValueType();
5258 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5259 SDNode *Node = Op.Val;
5260 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5261 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5262 MVT::isVector(VT)) &&
5263 "Cannot expand to FP value or to larger int value!");
5265 // See if we already expanded it.
5266 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5267 = ExpandedNodes.find(Op);
5268 if (I != ExpandedNodes.end()) {
5269 Lo = I->second.first;
5270 Hi = I->second.second;
5274 switch (Node->getOpcode()) {
5275 case ISD::CopyFromReg:
5276 assert(0 && "CopyFromReg must be legal!");
5277 case ISD::FP_ROUND_INREG:
5278 if (VT == MVT::ppcf128 &&
5279 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5280 TargetLowering::Custom) {
5281 SDOperand SrcLo, SrcHi, Src;
5282 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5283 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5284 SDOperand Result = TLI.LowerOperation(
5285 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5286 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5287 Lo = Result.Val->getOperand(0);
5288 Hi = Result.Val->getOperand(1);
5294 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5296 assert(0 && "Do not know how to expand this operator!");
5299 NVT = TLI.getTypeToExpandTo(VT);
5300 Lo = DAG.getNode(ISD::UNDEF, NVT);
5301 Hi = DAG.getNode(ISD::UNDEF, NVT);
5303 case ISD::Constant: {
5304 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5305 Lo = DAG.getConstant(Cst, NVT);
5306 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5309 case ISD::ConstantFP: {
5310 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5311 if (CFP->getValueType(0) == MVT::ppcf128) {
5312 APInt api = CFP->getValueAPF().convertToAPInt();
5313 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5315 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5319 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5320 if (getTypeAction(Lo.getValueType()) == Expand)
5321 ExpandOp(Lo, Lo, Hi);
5324 case ISD::BUILD_PAIR:
5325 // Return the operands.
5326 Lo = Node->getOperand(0);
5327 Hi = Node->getOperand(1);
5330 case ISD::SIGN_EXTEND_INREG:
5331 ExpandOp(Node->getOperand(0), Lo, Hi);
5332 // sext_inreg the low part if needed.
5333 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5335 // The high part gets the sign extension from the lo-part. This handles
5336 // things like sextinreg V:i64 from i8.
5337 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5338 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5339 TLI.getShiftAmountTy()));
5343 ExpandOp(Node->getOperand(0), Lo, Hi);
5344 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5345 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5351 ExpandOp(Node->getOperand(0), Lo, Hi);
5352 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5353 DAG.getNode(ISD::CTPOP, NVT, Lo),
5354 DAG.getNode(ISD::CTPOP, NVT, Hi));
5355 Hi = DAG.getConstant(0, NVT);
5359 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5360 ExpandOp(Node->getOperand(0), Lo, Hi);
5361 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5362 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5363 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5365 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5366 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5368 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5369 Hi = DAG.getConstant(0, NVT);
5374 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5375 ExpandOp(Node->getOperand(0), Lo, Hi);
5376 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5377 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5378 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5380 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5381 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5383 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5384 Hi = DAG.getConstant(0, NVT);
5389 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5390 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5391 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5392 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5394 // Remember that we legalized the chain.
5395 Hi = LegalizeOp(Hi);
5396 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5397 if (!TLI.isLittleEndian())
5403 LoadSDNode *LD = cast<LoadSDNode>(Node);
5404 SDOperand Ch = LD->getChain(); // Legalize the chain.
5405 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5406 ISD::LoadExtType ExtType = LD->getExtensionType();
5407 int SVOffset = LD->getSrcValueOffset();
5408 unsigned Alignment = LD->getAlignment();
5409 bool isVolatile = LD->isVolatile();
5411 if (ExtType == ISD::NON_EXTLOAD) {
5412 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5413 isVolatile, Alignment);
5414 if (VT == MVT::f32 || VT == MVT::f64) {
5415 // f32->i32 or f64->i64 one to one expansion.
5416 // Remember that we legalized the chain.
5417 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5418 // Recursively expand the new load.
5419 if (getTypeAction(NVT) == Expand)
5420 ExpandOp(Lo, Lo, Hi);
5424 // Increment the pointer to the other half.
5425 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5426 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5427 getIntPtrConstant(IncrementSize));
5428 SVOffset += IncrementSize;
5429 if (Alignment > IncrementSize)
5430 Alignment = IncrementSize;
5431 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5432 isVolatile, Alignment);
5434 // Build a factor node to remember that this load is independent of the
5436 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5439 // Remember that we legalized the chain.
5440 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5441 if (!TLI.isLittleEndian())
5444 MVT::ValueType EVT = LD->getLoadedVT();
5446 if (VT == MVT::f64 && EVT == MVT::f32) {
5447 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5448 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5449 SVOffset, isVolatile, Alignment);
5450 // Remember that we legalized the chain.
5451 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5452 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5457 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5458 SVOffset, isVolatile, Alignment);
5460 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5461 SVOffset, EVT, isVolatile,
5464 // Remember that we legalized the chain.
5465 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5467 if (ExtType == ISD::SEXTLOAD) {
5468 // The high part is obtained by SRA'ing all but one of the bits of the
5470 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5471 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5472 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5473 } else if (ExtType == ISD::ZEXTLOAD) {
5474 // The high part is just a zero.
5475 Hi = DAG.getConstant(0, NVT);
5476 } else /* if (ExtType == ISD::EXTLOAD) */ {
5477 // The high part is undefined.
5478 Hi = DAG.getNode(ISD::UNDEF, NVT);
5485 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5486 SDOperand LL, LH, RL, RH;
5487 ExpandOp(Node->getOperand(0), LL, LH);
5488 ExpandOp(Node->getOperand(1), RL, RH);
5489 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5490 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5494 SDOperand LL, LH, RL, RH;
5495 ExpandOp(Node->getOperand(1), LL, LH);
5496 ExpandOp(Node->getOperand(2), RL, RH);
5497 if (getTypeAction(NVT) == Expand)
5498 NVT = TLI.getTypeToExpandTo(NVT);
5499 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5501 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5504 case ISD::SELECT_CC: {
5505 SDOperand TL, TH, FL, FH;
5506 ExpandOp(Node->getOperand(2), TL, TH);
5507 ExpandOp(Node->getOperand(3), FL, FH);
5508 if (getTypeAction(NVT) == Expand)
5509 NVT = TLI.getTypeToExpandTo(NVT);
5510 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5511 Node->getOperand(1), TL, FL, Node->getOperand(4));
5513 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5514 Node->getOperand(1), TH, FH, Node->getOperand(4));
5517 case ISD::ANY_EXTEND:
5518 // The low part is any extension of the input (which degenerates to a copy).
5519 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5520 // The high part is undefined.
5521 Hi = DAG.getNode(ISD::UNDEF, NVT);
5523 case ISD::SIGN_EXTEND: {
5524 // The low part is just a sign extension of the input (which degenerates to
5526 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5528 // The high part is obtained by SRA'ing all but one of the bits of the lo
5530 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5531 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5532 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5535 case ISD::ZERO_EXTEND:
5536 // The low part is just a zero extension of the input (which degenerates to
5538 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5540 // The high part is just a zero.
5541 Hi = DAG.getConstant(0, NVT);
5544 case ISD::TRUNCATE: {
5545 // The input value must be larger than this value. Expand *it*.
5547 ExpandOp(Node->getOperand(0), NewLo, Hi);
5549 // The low part is now either the right size, or it is closer. If not the
5550 // right size, make an illegal truncate so we recursively expand it.
5551 if (NewLo.getValueType() != Node->getValueType(0))
5552 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5553 ExpandOp(NewLo, Lo, Hi);
5557 case ISD::BIT_CONVERT: {
5559 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5560 // If the target wants to, allow it to lower this itself.
5561 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5562 case Expand: assert(0 && "cannot expand FP!");
5563 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5564 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5566 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5569 // f32 / f64 must be expanded to i32 / i64.
5570 if (VT == MVT::f32 || VT == MVT::f64) {
5571 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5572 if (getTypeAction(NVT) == Expand)
5573 ExpandOp(Lo, Lo, Hi);
5577 // If source operand will be expanded to the same type as VT, i.e.
5578 // i64 <- f64, i32 <- f32, expand the source operand instead.
5579 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5580 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5581 ExpandOp(Node->getOperand(0), Lo, Hi);
5585 // Turn this into a load/store pair by default.
5587 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5589 ExpandOp(Tmp, Lo, Hi);
5593 case ISD::READCYCLECOUNTER:
5594 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5595 TargetLowering::Custom &&
5596 "Must custom expand ReadCycleCounter");
5597 Lo = TLI.LowerOperation(Op, DAG);
5598 assert(Lo.Val && "Node must be custom expanded!");
5599 Hi = Lo.getValue(1);
5600 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5601 LegalizeOp(Lo.getValue(2)));
5604 // These operators cannot be expanded directly, emit them as calls to
5605 // library functions.
5606 case ISD::FP_TO_SINT: {
5607 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5609 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5610 case Expand: assert(0 && "cannot expand FP!");
5611 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5612 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5615 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5617 // Now that the custom expander is done, expand the result, which is still
5620 ExpandOp(Op, Lo, Hi);
5625 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5626 if (Node->getOperand(0).getValueType() == MVT::f32)
5627 LC = RTLIB::FPTOSINT_F32_I64;
5628 else if (Node->getOperand(0).getValueType() == MVT::f64)
5629 LC = RTLIB::FPTOSINT_F64_I64;
5630 else if (Node->getOperand(0).getValueType() == MVT::f80)
5631 LC = RTLIB::FPTOSINT_F80_I64;
5632 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5633 LC = RTLIB::FPTOSINT_PPCF128_I64;
5634 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5635 false/*sign irrelevant*/, Hi);
5639 case ISD::FP_TO_UINT: {
5640 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5642 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5643 case Expand: assert(0 && "cannot expand FP!");
5644 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5645 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5648 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5650 // Now that the custom expander is done, expand the result.
5652 ExpandOp(Op, Lo, Hi);
5657 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5658 if (Node->getOperand(0).getValueType() == MVT::f32)
5659 LC = RTLIB::FPTOUINT_F32_I64;
5660 else if (Node->getOperand(0).getValueType() == MVT::f64)
5661 LC = RTLIB::FPTOUINT_F64_I64;
5662 else if (Node->getOperand(0).getValueType() == MVT::f80)
5663 LC = RTLIB::FPTOUINT_F80_I64;
5664 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5665 LC = RTLIB::FPTOUINT_PPCF128_I64;
5666 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5667 false/*sign irrelevant*/, Hi);
5672 // If the target wants custom lowering, do so.
5673 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5674 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5675 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5676 Op = TLI.LowerOperation(Op, DAG);
5678 // Now that the custom expander is done, expand the result, which is
5680 ExpandOp(Op, Lo, Hi);
5685 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5686 // this X << 1 as X+X.
5687 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5688 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5689 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5690 SDOperand LoOps[2], HiOps[3];
5691 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5692 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5693 LoOps[1] = LoOps[0];
5694 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5696 HiOps[1] = HiOps[0];
5697 HiOps[2] = Lo.getValue(1);
5698 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5703 // If we can emit an efficient shift operation, do so now.
5704 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5707 // If this target supports SHL_PARTS, use it.
5708 TargetLowering::LegalizeAction Action =
5709 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5710 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5711 Action == TargetLowering::Custom) {
5712 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5716 // Otherwise, emit a libcall.
5717 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5718 false/*left shift=unsigned*/, Hi);
5723 // If the target wants custom lowering, do so.
5724 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5725 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5726 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5727 Op = TLI.LowerOperation(Op, DAG);
5729 // Now that the custom expander is done, expand the result, which is
5731 ExpandOp(Op, Lo, Hi);
5736 // If we can emit an efficient shift operation, do so now.
5737 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5740 // If this target supports SRA_PARTS, use it.
5741 TargetLowering::LegalizeAction Action =
5742 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5743 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5744 Action == TargetLowering::Custom) {
5745 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5749 // Otherwise, emit a libcall.
5750 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5751 true/*ashr is signed*/, Hi);
5756 // If the target wants custom lowering, do so.
5757 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5758 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5759 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5760 Op = TLI.LowerOperation(Op, DAG);
5762 // Now that the custom expander is done, expand the result, which is
5764 ExpandOp(Op, Lo, Hi);
5769 // If we can emit an efficient shift operation, do so now.
5770 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5773 // If this target supports SRL_PARTS, use it.
5774 TargetLowering::LegalizeAction Action =
5775 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5776 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5777 Action == TargetLowering::Custom) {
5778 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5782 // Otherwise, emit a libcall.
5783 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5784 false/*lshr is unsigned*/, Hi);
5790 // If the target wants to custom expand this, let them.
5791 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5792 TargetLowering::Custom) {
5793 Op = TLI.LowerOperation(Op, DAG);
5795 ExpandOp(Op, Lo, Hi);
5800 // Expand the subcomponents.
5801 SDOperand LHSL, LHSH, RHSL, RHSH;
5802 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5803 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5804 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5805 SDOperand LoOps[2], HiOps[3];
5810 if (Node->getOpcode() == ISD::ADD) {
5811 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5812 HiOps[2] = Lo.getValue(1);
5813 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5815 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5816 HiOps[2] = Lo.getValue(1);
5817 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5824 // Expand the subcomponents.
5825 SDOperand LHSL, LHSH, RHSL, RHSH;
5826 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5827 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5828 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5829 SDOperand LoOps[2] = { LHSL, RHSL };
5830 SDOperand HiOps[3] = { LHSH, RHSH };
5832 if (Node->getOpcode() == ISD::ADDC) {
5833 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5834 HiOps[2] = Lo.getValue(1);
5835 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5837 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5838 HiOps[2] = Lo.getValue(1);
5839 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5841 // Remember that we legalized the flag.
5842 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5847 // Expand the subcomponents.
5848 SDOperand LHSL, LHSH, RHSL, RHSH;
5849 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5850 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5851 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5852 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5853 SDOperand HiOps[3] = { LHSH, RHSH };
5855 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5856 HiOps[2] = Lo.getValue(1);
5857 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5859 // Remember that we legalized the flag.
5860 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5864 // If the target wants to custom expand this, let them.
5865 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5866 SDOperand New = TLI.LowerOperation(Op, DAG);
5868 ExpandOp(New, Lo, Hi);
5873 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5874 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5875 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
5876 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
5877 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
5878 SDOperand LL, LH, RL, RH;
5879 ExpandOp(Node->getOperand(0), LL, LH);
5880 ExpandOp(Node->getOperand(1), RL, RH);
5881 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
5882 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
5883 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
5884 // FIXME: generalize this to handle other bit sizes
5885 if (LHSSB == 32 && RHSSB == 32 &&
5886 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
5887 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
5888 // The inputs are both zero-extended.
5890 // We can emit a umul_lohi.
5891 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
5892 Hi = SDOperand(Lo.Val, 1);
5896 // We can emit a mulhu+mul.
5897 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5898 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5902 if (LHSSB > BitSize && RHSSB > BitSize) {
5903 // The input values are both sign-extended.
5905 // We can emit a smul_lohi.
5906 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
5907 Hi = SDOperand(Lo.Val, 1);
5911 // We can emit a mulhs+mul.
5912 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5913 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5918 // Lo,Hi = umul LHS, RHS.
5919 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
5920 DAG.getVTList(NVT, NVT), LL, RL);
5922 Hi = UMulLOHI.getValue(1);
5923 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5924 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5925 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5926 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5931 // If nothing else, we can make a libcall.
5932 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5933 false/*sign irrelevant*/, Hi);
5937 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5940 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5943 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5946 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5950 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 :
5951 VT == MVT::f64 ? RTLIB::ADD_F64 :
5952 VT == MVT::ppcf128 ?
5953 RTLIB::ADD_PPCF128 :
5954 RTLIB::UNKNOWN_LIBCALL),
5958 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 :
5959 VT == MVT::f64 ? RTLIB::SUB_F64 :
5960 VT == MVT::ppcf128 ?
5961 RTLIB::SUB_PPCF128 :
5962 RTLIB::UNKNOWN_LIBCALL),
5966 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 :
5967 VT == MVT::f64 ? RTLIB::MUL_F64 :
5968 VT == MVT::ppcf128 ?
5969 RTLIB::MUL_PPCF128 :
5970 RTLIB::UNKNOWN_LIBCALL),
5974 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 :
5975 VT == MVT::f64 ? RTLIB::DIV_F64 :
5976 VT == MVT::ppcf128 ?
5977 RTLIB::DIV_PPCF128 :
5978 RTLIB::UNKNOWN_LIBCALL),
5981 case ISD::FP_EXTEND:
5982 if (VT == MVT::ppcf128) {
5983 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
5984 Node->getOperand(0).getValueType()==MVT::f64);
5985 const uint64_t zero = 0;
5986 if (Node->getOperand(0).getValueType()==MVT::f32)
5987 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
5989 Hi = Node->getOperand(0);
5990 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
5993 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5996 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5999 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 :
6000 (VT == MVT::f64) ? RTLIB::POWI_F64 :
6001 (VT == MVT::f80) ? RTLIB::POWI_F80 :
6002 (VT == MVT::ppcf128) ?
6003 RTLIB::POWI_PPCF128 :
6004 RTLIB::UNKNOWN_LIBCALL),
6010 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6011 switch(Node->getOpcode()) {
6013 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 :
6014 (VT == MVT::f64) ? RTLIB::SQRT_F64 :
6015 (VT == MVT::f80) ? RTLIB::SQRT_F80 :
6016 (VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 :
6017 RTLIB::UNKNOWN_LIBCALL;
6020 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
6023 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
6025 default: assert(0 && "Unreachable!");
6027 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6031 if (VT == MVT::ppcf128) {
6033 ExpandOp(Node->getOperand(0), Lo, Tmp);
6034 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6035 // lo = hi==fabs(hi) ? lo : -lo;
6036 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6037 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6038 DAG.getCondCode(ISD::SETEQ));
6041 SDOperand Mask = (VT == MVT::f64)
6042 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6043 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6044 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6045 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6046 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6047 if (getTypeAction(NVT) == Expand)
6048 ExpandOp(Lo, Lo, Hi);
6052 if (VT == MVT::ppcf128) {
6053 ExpandOp(Node->getOperand(0), Lo, Hi);
6054 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6055 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6058 SDOperand Mask = (VT == MVT::f64)
6059 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6060 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6061 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6062 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6063 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6064 if (getTypeAction(NVT) == Expand)
6065 ExpandOp(Lo, Lo, Hi);
6068 case ISD::FCOPYSIGN: {
6069 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6070 if (getTypeAction(NVT) == Expand)
6071 ExpandOp(Lo, Lo, Hi);
6074 case ISD::SINT_TO_FP:
6075 case ISD::UINT_TO_FP: {
6076 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6077 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6078 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6079 static uint64_t zero = 0;
6081 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6082 Node->getOperand(0)));
6083 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6085 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6086 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6087 Node->getOperand(0)));
6088 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6089 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6090 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6091 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6092 DAG.getConstant(0, MVT::i32),
6093 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6095 APFloat(APInt(128, 2, TwoE32)),
6098 DAG.getCondCode(ISD::SETLT)),
6103 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6104 // si64->ppcf128 done by libcall, below
6105 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6106 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6108 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6109 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6110 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6111 DAG.getConstant(0, MVT::i64),
6112 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6114 APFloat(APInt(128, 2, TwoE64)),
6117 DAG.getCondCode(ISD::SETLT)),
6121 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6122 if (Node->getOperand(0).getValueType() == MVT::i64) {
6124 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6125 else if (VT == MVT::f64)
6126 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6127 else if (VT == MVT::f80) {
6129 LC = RTLIB::SINTTOFP_I64_F80;
6131 else if (VT == MVT::ppcf128) {
6133 LC = RTLIB::SINTTOFP_I64_PPCF128;
6137 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6139 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6142 // Promote the operand if needed.
6143 if (getTypeAction(SrcVT) == Promote) {
6144 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6146 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6147 DAG.getValueType(SrcVT))
6148 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6149 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6152 const char *LibCall = TLI.getLibcallName(LC);
6154 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6156 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6157 Node->getOperand(0));
6158 if (getTypeAction(Lo.getValueType()) == Expand)
6159 ExpandOp(Lo, Lo, Hi);
6165 // Make sure the resultant values have been legalized themselves, unless this
6166 // is a type that requires multi-step expansion.
6167 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6168 Lo = LegalizeOp(Lo);
6170 // Don't legalize the high part if it is expanded to a single node.
6171 Hi = LegalizeOp(Hi);
6174 // Remember in a map if the values will be reused later.
6175 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6176 assert(isNew && "Value already expanded?!?");
6179 /// SplitVectorOp - Given an operand of vector type, break it down into
6180 /// two smaller values, still of vector type.
6181 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6183 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6184 SDNode *Node = Op.Val;
6185 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6186 assert(NumElements > 1 && "Cannot split a single element vector!");
6187 unsigned NewNumElts = NumElements/2;
6188 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6189 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
6191 // See if we already split it.
6192 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6193 = SplitNodes.find(Op);
6194 if (I != SplitNodes.end()) {
6195 Lo = I->second.first;
6196 Hi = I->second.second;
6200 switch (Node->getOpcode()) {
6205 assert(0 && "Unhandled operation in SplitVectorOp!");
6206 case ISD::BUILD_PAIR:
6207 Lo = Node->getOperand(0);
6208 Hi = Node->getOperand(1);
6210 case ISD::INSERT_VECTOR_ELT: {
6211 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6212 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6213 SDOperand ScalarOp = Node->getOperand(1);
6214 if (Index < NewNumElts)
6215 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Lo, ScalarOp,
6216 DAG.getConstant(Index, TLI.getPointerTy()));
6218 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Hi, ScalarOp,
6219 DAG.getConstant(Index - NewNumElts, TLI.getPointerTy()));
6222 case ISD::BUILD_VECTOR: {
6223 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6224 Node->op_begin()+NewNumElts);
6225 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
6227 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
6229 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
6232 case ISD::CONCAT_VECTORS: {
6233 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6234 if (NewNumSubvectors == 1) {
6235 Lo = Node->getOperand(0);
6236 Hi = Node->getOperand(1);
6238 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6239 Node->op_begin()+NewNumSubvectors);
6240 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
6242 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6244 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
6249 SDOperand Cond = Node->getOperand(0);
6251 SDOperand LL, LH, RL, RH;
6252 SplitVectorOp(Node->getOperand(1), LL, LH);
6253 SplitVectorOp(Node->getOperand(2), RL, RH);
6255 if (MVT::isVector(Cond.getValueType())) {
6256 // Handle a vector merge.
6258 SplitVectorOp(Cond, CL, CH);
6259 Lo = DAG.getNode(Node->getOpcode(), NewVT, CL, LL, RL);
6260 Hi = DAG.getNode(Node->getOpcode(), NewVT, CH, LH, RH);
6262 // Handle a simple select with vector operands.
6263 Lo = DAG.getNode(Node->getOpcode(), NewVT, Cond, LL, RL);
6264 Hi = DAG.getNode(Node->getOpcode(), NewVT, Cond, LH, RH);
6281 SDOperand LL, LH, RL, RH;
6282 SplitVectorOp(Node->getOperand(0), LL, LH);
6283 SplitVectorOp(Node->getOperand(1), RL, RH);
6285 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
6286 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
6291 SplitVectorOp(Node->getOperand(0), L, H);
6293 Lo = DAG.getNode(Node->getOpcode(), NewVT, L, Node->getOperand(1));
6294 Hi = DAG.getNode(Node->getOpcode(), NewVT, H, Node->getOperand(1));
6306 SplitVectorOp(Node->getOperand(0), L, H);
6308 Lo = DAG.getNode(Node->getOpcode(), NewVT, L);
6309 Hi = DAG.getNode(Node->getOpcode(), NewVT, H);
6313 LoadSDNode *LD = cast<LoadSDNode>(Node);
6314 SDOperand Ch = LD->getChain();
6315 SDOperand Ptr = LD->getBasePtr();
6316 const Value *SV = LD->getSrcValue();
6317 int SVOffset = LD->getSrcValueOffset();
6318 unsigned Alignment = LD->getAlignment();
6319 bool isVolatile = LD->isVolatile();
6321 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6322 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
6323 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6324 getIntPtrConstant(IncrementSize));
6325 SVOffset += IncrementSize;
6326 if (Alignment > IncrementSize)
6327 Alignment = IncrementSize;
6328 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6330 // Build a factor node to remember that this load is independent of the
6332 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6335 // Remember that we legalized the chain.
6336 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6339 case ISD::BIT_CONVERT: {
6340 // We know the result is a vector. The input may be either a vector or a
6342 SDOperand InOp = Node->getOperand(0);
6343 if (!MVT::isVector(InOp.getValueType()) ||
6344 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6345 // The input is a scalar or single-element vector.
6346 // Lower to a store/load so that it can be split.
6347 // FIXME: this could be improved probably.
6348 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6350 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6351 InOp, Ptr, NULL, 0);
6352 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
6354 // Split the vector and convert each of the pieces now.
6355 SplitVectorOp(InOp, Lo, Hi);
6356 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
6357 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
6362 // Remember in a map if the values will be reused later.
6364 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6365 assert(isNew && "Value already split?!?");
6369 /// ScalarizeVectorOp - Given an operand of single-element vector type
6370 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6371 /// scalar (e.g. f32) value.
6372 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6373 assert(MVT::isVector(Op.getValueType()) &&
6374 "Bad ScalarizeVectorOp invocation!");
6375 SDNode *Node = Op.Val;
6376 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6377 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6379 // See if we already scalarized it.
6380 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6381 if (I != ScalarizedNodes.end()) return I->second;
6384 switch (Node->getOpcode()) {
6387 Node->dump(&DAG); cerr << "\n";
6389 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6406 Result = DAG.getNode(Node->getOpcode(),
6408 ScalarizeVectorOp(Node->getOperand(0)),
6409 ScalarizeVectorOp(Node->getOperand(1)));
6416 Result = DAG.getNode(Node->getOpcode(),
6418 ScalarizeVectorOp(Node->getOperand(0)));
6421 Result = DAG.getNode(Node->getOpcode(),
6423 ScalarizeVectorOp(Node->getOperand(0)),
6424 Node->getOperand(1));
6427 LoadSDNode *LD = cast<LoadSDNode>(Node);
6428 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6429 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6431 const Value *SV = LD->getSrcValue();
6432 int SVOffset = LD->getSrcValueOffset();
6433 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6434 LD->isVolatile(), LD->getAlignment());
6436 // Remember that we legalized the chain.
6437 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6440 case ISD::BUILD_VECTOR:
6441 Result = Node->getOperand(0);
6443 case ISD::INSERT_VECTOR_ELT:
6444 // Returning the inserted scalar element.
6445 Result = Node->getOperand(1);
6447 case ISD::CONCAT_VECTORS:
6448 assert(Node->getOperand(0).getValueType() == NewVT &&
6449 "Concat of non-legal vectors not yet supported!");
6450 Result = Node->getOperand(0);
6452 case ISD::VECTOR_SHUFFLE: {
6453 // Figure out if the scalar is the LHS or RHS and return it.
6454 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6455 if (cast<ConstantSDNode>(EltNum)->getValue())
6456 Result = ScalarizeVectorOp(Node->getOperand(1));
6458 Result = ScalarizeVectorOp(Node->getOperand(0));
6461 case ISD::EXTRACT_SUBVECTOR:
6462 Result = Node->getOperand(0);
6463 assert(Result.getValueType() == NewVT);
6465 case ISD::BIT_CONVERT:
6466 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6469 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6470 ScalarizeVectorOp(Op.getOperand(1)),
6471 ScalarizeVectorOp(Op.getOperand(2)));
6475 if (TLI.isTypeLegal(NewVT))
6476 Result = LegalizeOp(Result);
6477 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6478 assert(isNew && "Value already scalarized?");
6483 // SelectionDAG::Legalize - This is the entry point for the file.
6485 void SelectionDAG::Legalize() {
6486 if (ViewLegalizeDAGs) viewGraph();
6488 /// run - This is the main entry point to this class.
6490 SelectionDAGLegalize(*this).LegalizeDAG();