1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/CodeGen/Analysis.h"
43 #include "llvm/ADT/Optional.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Analysis/BranchProbabilityInfo.h"
46 #include "llvm/Analysis/Loads.h"
47 #include "llvm/Analysis/TargetLibraryInfo.h"
48 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/CodeGen/FastISel.h"
50 #include "llvm/CodeGen/FunctionLoweringInfo.h"
51 #include "llvm/CodeGen/MachineFrameInfo.h"
52 #include "llvm/CodeGen/MachineInstrBuilder.h"
53 #include "llvm/CodeGen/MachineModuleInfo.h"
54 #include "llvm/CodeGen/MachineRegisterInfo.h"
55 #include "llvm/CodeGen/StackMaps.h"
56 #include "llvm/IR/DataLayout.h"
57 #include "llvm/IR/DebugInfo.h"
58 #include "llvm/IR/Function.h"
59 #include "llvm/IR/GlobalVariable.h"
60 #include "llvm/IR/Instructions.h"
61 #include "llvm/IR/IntrinsicInst.h"
62 #include "llvm/IR/Operator.h"
63 #include "llvm/Support/Debug.h"
64 #include "llvm/Support/ErrorHandling.h"
65 #include "llvm/Support/raw_ostream.h"
66 #include "llvm/Target/TargetInstrInfo.h"
67 #include "llvm/Target/TargetLowering.h"
68 #include "llvm/Target/TargetMachine.h"
69 #include "llvm/Target/TargetSubtargetInfo.h"
72 #define DEBUG_TYPE "isel"
74 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
75 "target-independent selector");
76 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
77 "target-specific selector");
78 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
80 void FastISel::ArgListEntry::setAttributes(ImmutableCallSite *CS,
82 IsSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
83 IsZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
84 IsInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
85 IsSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
86 IsNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
87 IsByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
88 IsInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
89 IsReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
90 Alignment = CS->getParamAlignment(AttrIdx);
93 /// Set the current block to which generated machine instructions will be
94 /// appended, and clear the local CSE map.
95 void FastISel::startNewBlock() {
96 LocalValueMap.clear();
98 // Instructions are appended to FuncInfo.MBB. If the basic block already
99 // contains labels or copies, use the last instruction as the last local
101 EmitStartPt = nullptr;
102 if (!FuncInfo.MBB->empty())
103 EmitStartPt = &FuncInfo.MBB->back();
104 LastLocalValue = EmitStartPt;
107 bool FastISel::lowerArguments() {
108 if (!FuncInfo.CanLowerReturn)
109 // Fallback to SDISel argument lowering code to deal with sret pointer
113 if (!fastLowerArguments())
116 // Enter arguments into ValueMap for uses in non-entry BBs.
117 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
118 E = FuncInfo.Fn->arg_end();
120 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(I);
121 assert(VI != LocalValueMap.end() && "Missed an argument?");
122 FuncInfo.ValueMap[I] = VI->second;
127 void FastISel::flushLocalValueMap() {
128 LocalValueMap.clear();
129 LastLocalValue = EmitStartPt;
131 SavedInsertPt = FuncInfo.InsertPt;
134 bool FastISel::hasTrivialKill(const Value *V) {
135 // Don't consider constants or arguments to have trivial kills.
136 const Instruction *I = dyn_cast<Instruction>(V);
140 // No-op casts are trivially coalesced by fast-isel.
141 if (const auto *Cast = dyn_cast<CastInst>(I))
142 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
143 !hasTrivialKill(Cast->getOperand(0)))
146 // Even the value might have only one use in the LLVM IR, it is possible that
147 // FastISel might fold the use into another instruction and now there is more
148 // than one use at the Machine Instruction level.
149 unsigned Reg = lookUpRegForValue(V);
150 if (Reg && !MRI.use_empty(Reg))
153 // GEPs with all zero indices are trivially coalesced by fast-isel.
154 if (const auto *GEP = dyn_cast<GetElementPtrInst>(I))
155 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
158 // Only instructions with a single use in the same basic block are considered
159 // to have trivial kills.
160 return I->hasOneUse() &&
161 !(I->getOpcode() == Instruction::BitCast ||
162 I->getOpcode() == Instruction::PtrToInt ||
163 I->getOpcode() == Instruction::IntToPtr) &&
164 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
167 unsigned FastISel::getRegForValue(const Value *V) {
168 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
169 // Don't handle non-simple values in FastISel.
170 if (!RealVT.isSimple())
173 // Ignore illegal types. We must do this before looking up the value
174 // in ValueMap because Arguments are given virtual registers regardless
175 // of whether FastISel can handle them.
176 MVT VT = RealVT.getSimpleVT();
177 if (!TLI.isTypeLegal(VT)) {
178 // Handle integer promotions, though, because they're common and easy.
179 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
180 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
185 // Look up the value to see if we already have a register for it.
186 unsigned Reg = lookUpRegForValue(V);
190 // In bottom-up mode, just create the virtual register which will be used
191 // to hold the value. It will be materialized later.
192 if (isa<Instruction>(V) &&
193 (!isa<AllocaInst>(V) ||
194 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
195 return FuncInfo.InitializeRegForValue(V);
197 SavePoint SaveInsertPt = enterLocalValueArea();
199 // Materialize the value in a register. Emit any instructions in the
201 Reg = materializeRegForValue(V, VT);
203 leaveLocalValueArea(SaveInsertPt);
208 unsigned FastISel::materializeConstant(const Value *V, MVT VT) {
210 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
211 if (CI->getValue().getActiveBits() <= 64)
212 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
213 } else if (isa<AllocaInst>(V))
214 Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
215 else if (isa<ConstantPointerNull>(V))
216 // Translate this as an integer zero so that it can be
217 // local-CSE'd with actual integer zeros.
218 Reg = getRegForValue(
219 Constant::getNullValue(DL.getIntPtrType(V->getContext())));
220 else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
221 if (CF->isNullValue())
222 Reg = fastMaterializeFloatZero(CF);
224 // Try to emit the constant directly.
225 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
228 // Try to emit the constant by using an integer constant with a cast.
229 const APFloat &Flt = CF->getValueAPF();
230 EVT IntVT = TLI.getPointerTy();
233 uint32_t IntBitWidth = IntVT.getSizeInBits();
235 (void)Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
236 APFloat::rmTowardZero, &isExact);
238 APInt IntVal(IntBitWidth, x);
240 unsigned IntegerReg =
241 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
243 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
247 } else if (const auto *Op = dyn_cast<Operator>(V)) {
248 if (!selectOperator(Op, Op->getOpcode()))
249 if (!isa<Instruction>(Op) ||
250 !fastSelectInstruction(cast<Instruction>(Op)))
252 Reg = lookUpRegForValue(Op);
253 } else if (isa<UndefValue>(V)) {
254 Reg = createResultReg(TLI.getRegClassFor(VT));
255 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
256 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
261 /// Helper for getRegForValue. This function is called when the value isn't
262 /// already available in a register and must be materialized with new
264 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
266 // Give the target-specific code a try first.
267 if (isa<Constant>(V))
268 Reg = fastMaterializeConstant(cast<Constant>(V));
270 // If target-specific code couldn't or didn't want to handle the value, then
271 // give target-independent code a try.
273 Reg = materializeConstant(V, VT);
275 // Don't cache constant materializations in the general ValueMap.
276 // To do so would require tracking what uses they dominate.
278 LocalValueMap[V] = Reg;
279 LastLocalValue = MRI.getVRegDef(Reg);
284 unsigned FastISel::lookUpRegForValue(const Value *V) {
285 // Look up the value to see if we already have a register for it. We
286 // cache values defined by Instructions across blocks, and other values
287 // only locally. This is because Instructions already have the SSA
288 // def-dominates-use requirement enforced.
289 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
290 if (I != FuncInfo.ValueMap.end())
292 return LocalValueMap[V];
295 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
296 if (!isa<Instruction>(I)) {
297 LocalValueMap[I] = Reg;
301 unsigned &AssignedReg = FuncInfo.ValueMap[I];
302 if (AssignedReg == 0)
303 // Use the new register.
305 else if (Reg != AssignedReg) {
306 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
307 for (unsigned i = 0; i < NumRegs; i++)
308 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
314 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
315 unsigned IdxN = getRegForValue(Idx);
317 // Unhandled operand. Halt "fast" selection and bail.
318 return std::pair<unsigned, bool>(0, false);
320 bool IdxNIsKill = hasTrivialKill(Idx);
322 // If the index is smaller or larger than intptr_t, truncate or extend it.
323 MVT PtrVT = TLI.getPointerTy();
324 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
325 if (IdxVT.bitsLT(PtrVT)) {
326 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
329 } else if (IdxVT.bitsGT(PtrVT)) {
331 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
334 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
337 void FastISel::recomputeInsertPt() {
338 if (getLastLocalValue()) {
339 FuncInfo.InsertPt = getLastLocalValue();
340 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
343 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
345 // Now skip past any EH_LABELs, which must remain at the beginning.
346 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
347 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
351 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
352 MachineBasicBlock::iterator E) {
353 assert(I && E && std::distance(I, E) > 0 && "Invalid iterator!");
355 MachineInstr *Dead = &*I;
357 Dead->eraseFromParent();
363 FastISel::SavePoint FastISel::enterLocalValueArea() {
364 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
365 DebugLoc OldDL = DbgLoc;
368 SavePoint SP = {OldInsertPt, OldDL};
372 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
373 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
374 LastLocalValue = std::prev(FuncInfo.InsertPt);
376 // Restore the previous insert position.
377 FuncInfo.InsertPt = OldInsertPt.InsertPt;
378 DbgLoc = OldInsertPt.DL;
381 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
382 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
383 if (VT == MVT::Other || !VT.isSimple())
384 // Unhandled type. Halt "fast" selection and bail.
387 // We only handle legal types. For example, on x86-32 the instruction
388 // selector contains all of the 64-bit instructions from x86-64,
389 // under the assumption that i64 won't be used if the target doesn't
391 if (!TLI.isTypeLegal(VT)) {
392 // MVT::i1 is special. Allow AND, OR, or XOR because they
393 // don't require additional zeroing, which makes them easy.
394 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
395 ISDOpcode == ISD::XOR))
396 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
401 // Check if the first operand is a constant, and handle it as "ri". At -O0,
402 // we don't have anything that canonicalizes operand order.
403 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
404 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
405 unsigned Op1 = getRegForValue(I->getOperand(1));
408 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
411 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
412 CI->getZExtValue(), VT.getSimpleVT());
416 // We successfully emitted code for the given LLVM Instruction.
417 updateValueMap(I, ResultReg);
421 unsigned Op0 = getRegForValue(I->getOperand(0));
422 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
424 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
426 // Check if the second operand is a constant and handle it appropriately.
427 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
428 uint64_t Imm = CI->getZExtValue();
430 // Transform "sdiv exact X, 8" -> "sra X, 3".
431 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
432 cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
434 ISDOpcode = ISD::SRA;
437 // Transform "urem x, pow2" -> "and x, pow2-1".
438 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
439 isPowerOf2_64(Imm)) {
441 ISDOpcode = ISD::AND;
444 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
445 Op0IsKill, Imm, VT.getSimpleVT());
449 // We successfully emitted code for the given LLVM Instruction.
450 updateValueMap(I, ResultReg);
454 // Check if the second operand is a constant float.
455 if (const auto *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
456 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
457 ISDOpcode, Op0, Op0IsKill, CF);
459 // We successfully emitted code for the given LLVM Instruction.
460 updateValueMap(I, ResultReg);
465 unsigned Op1 = getRegForValue(I->getOperand(1));
466 if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
468 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
470 // Now we have both operands in registers. Emit the instruction.
471 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
472 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
474 // Target-specific code wasn't able to find a machine opcode for
475 // the given ISD opcode and type. Halt "fast" selection and bail.
478 // We successfully emitted code for the given LLVM Instruction.
479 updateValueMap(I, ResultReg);
483 bool FastISel::selectGetElementPtr(const User *I) {
484 unsigned N = getRegForValue(I->getOperand(0));
485 if (!N) // Unhandled operand. Halt "fast" selection and bail.
487 bool NIsKill = hasTrivialKill(I->getOperand(0));
489 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
490 // into a single N = N + TotalOffset.
491 uint64_t TotalOffs = 0;
492 // FIXME: What's a good SWAG number for MaxOffs?
493 uint64_t MaxOffs = 2048;
494 Type *Ty = I->getOperand(0)->getType();
495 MVT VT = TLI.getPointerTy();
496 for (GetElementPtrInst::const_op_iterator OI = I->op_begin() + 1,
499 const Value *Idx = *OI;
500 if (auto *StTy = dyn_cast<StructType>(Ty)) {
501 uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
504 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
505 if (TotalOffs >= MaxOffs) {
506 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
507 if (!N) // Unhandled operand. Halt "fast" selection and bail.
513 Ty = StTy->getElementType(Field);
515 Ty = cast<SequentialType>(Ty)->getElementType();
517 // If this is a constant subscript, handle it quickly.
518 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
522 uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
523 TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
524 if (TotalOffs >= MaxOffs) {
525 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
526 if (!N) // Unhandled operand. Halt "fast" selection and bail.
534 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
535 if (!N) // Unhandled operand. Halt "fast" selection and bail.
541 // N = N + Idx * ElementSize;
542 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
543 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
544 unsigned IdxN = Pair.first;
545 bool IdxNIsKill = Pair.second;
546 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
549 if (ElementSize != 1) {
550 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
551 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
555 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
556 if (!N) // Unhandled operand. Halt "fast" selection and bail.
561 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
562 if (!N) // Unhandled operand. Halt "fast" selection and bail.
566 // We successfully emitted code for the given LLVM Instruction.
567 updateValueMap(I, N);
571 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
572 const CallInst *CI, unsigned StartIdx) {
573 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
574 Value *Val = CI->getArgOperand(i);
575 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
576 if (const auto *C = dyn_cast<ConstantInt>(Val)) {
577 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
578 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
579 } else if (isa<ConstantPointerNull>(Val)) {
580 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
581 Ops.push_back(MachineOperand::CreateImm(0));
582 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
583 // Values coming from a stack location also require a sepcial encoding,
584 // but that is added later on by the target specific frame index
585 // elimination implementation.
586 auto SI = FuncInfo.StaticAllocaMap.find(AI);
587 if (SI != FuncInfo.StaticAllocaMap.end())
588 Ops.push_back(MachineOperand::CreateFI(SI->second));
592 unsigned Reg = getRegForValue(Val);
595 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
601 bool FastISel::selectStackmap(const CallInst *I) {
602 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
603 // [live variables...])
604 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
605 "Stackmap cannot return a value.");
607 // The stackmap intrinsic only records the live variables (the arguments
608 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
609 // intrinsic, this won't be lowered to a function call. This means we don't
610 // have to worry about calling conventions and target-specific lowering code.
611 // Instead we perform the call lowering right here.
614 // STACKMAP(id, nbytes, ...)
617 SmallVector<MachineOperand, 32> Ops;
619 // Add the <id> and <numBytes> constants.
620 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
621 "Expected a constant integer.");
622 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
623 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
625 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
626 "Expected a constant integer.");
627 const auto *NumBytes =
628 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
629 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
631 // Push live variables for the stack map (skipping the first two arguments
632 // <id> and <numBytes>).
633 if (!addStackMapLiveVars(Ops, I, 2))
636 // We are not adding any register mask info here, because the stackmap doesn't
639 // Add scratch registers as implicit def and early clobber.
640 CallingConv::ID CC = I->getCallingConv();
641 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
642 for (unsigned i = 0; ScratchRegs[i]; ++i)
643 Ops.push_back(MachineOperand::CreateReg(
644 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
645 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
647 // Issue CALLSEQ_START
648 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
649 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
653 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
654 TII.get(TargetOpcode::STACKMAP));
655 for (auto const &MO : Ops)
659 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
660 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
664 // Inform the Frame Information that we have a stackmap in this function.
665 FuncInfo.MF->getFrameInfo()->setHasStackMap();
670 /// \brief Lower an argument list according to the target calling convention.
672 /// This is a helper for lowering intrinsics that follow a target calling
673 /// convention or require stack pointer adjustment. Only a subset of the
674 /// intrinsic's operands need to participate in the calling convention.
675 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
676 unsigned NumArgs, const Value *Callee,
677 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
679 Args.reserve(NumArgs);
681 // Populate the argument list.
682 // Attributes for args start at offset 1, after the return attribute.
683 ImmutableCallSite CS(CI);
684 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
685 ArgI != ArgE; ++ArgI) {
686 Value *V = CI->getOperand(ArgI);
688 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
692 Entry.Ty = V->getType();
693 Entry.setAttributes(&CS, AttrI);
694 Args.push_back(Entry);
697 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
699 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
701 return lowerCallTo(CLI);
704 bool FastISel::selectPatchpoint(const CallInst *I) {
705 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
710 // [live variables...])
711 CallingConv::ID CC = I->getCallingConv();
712 bool IsAnyRegCC = CC == CallingConv::AnyReg;
713 bool HasDef = !I->getType()->isVoidTy();
714 Value *Callee = I->getOperand(PatchPointOpers::TargetPos);
716 // Get the real number of arguments participating in the call <numArgs>
717 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
718 "Expected a constant integer.");
719 const auto *NumArgsVal =
720 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
721 unsigned NumArgs = NumArgsVal->getZExtValue();
723 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
724 // This includes all meta-operands up to but not including CC.
725 unsigned NumMetaOpers = PatchPointOpers::CCPos;
726 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
727 "Not enough arguments provided to the patchpoint intrinsic");
729 // For AnyRegCC the arguments are lowered later on manually.
730 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
731 CallLoweringInfo CLI;
732 CLI.setIsPatchPoint();
733 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
736 assert(CLI.Call && "No call instruction specified.");
738 SmallVector<MachineOperand, 32> Ops;
740 // Add an explicit result reg if we use the anyreg calling convention.
741 if (IsAnyRegCC && HasDef) {
742 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
743 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
744 CLI.NumResultRegs = 1;
745 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
748 // Add the <id> and <numBytes> constants.
749 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
750 "Expected a constant integer.");
751 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
752 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
754 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
755 "Expected a constant integer.");
756 const auto *NumBytes =
757 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
758 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
760 // Assume that the callee is a constant address or null pointer.
761 // FIXME: handle function symbols in the future.
763 if (const auto *C = dyn_cast<IntToPtrInst>(Callee))
764 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
765 else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
766 if (C->getOpcode() == Instruction::IntToPtr)
767 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
769 llvm_unreachable("Unsupported ConstantExpr.");
770 } else if (isa<ConstantPointerNull>(Callee))
773 llvm_unreachable("Unsupported callee address.");
775 Ops.push_back(MachineOperand::CreateImm(CalleeAddr));
777 // Adjust <numArgs> to account for any arguments that have been passed on
778 // the stack instead.
779 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
780 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
782 // Add the calling convention
783 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
785 // Add the arguments we omitted previously. The register allocator should
786 // place these in any free register.
788 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
789 unsigned Reg = getRegForValue(I->getArgOperand(i));
792 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
796 // Push the arguments from the call instruction.
797 for (auto Reg : CLI.OutRegs)
798 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
800 // Push live variables for the stack map.
801 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
804 // Push the register mask info.
805 Ops.push_back(MachineOperand::CreateRegMask(
806 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
808 // Add scratch registers as implicit def and early clobber.
809 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
810 for (unsigned i = 0; ScratchRegs[i]; ++i)
811 Ops.push_back(MachineOperand::CreateReg(
812 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
813 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
815 // Add implicit defs (return values).
816 for (auto Reg : CLI.InRegs)
817 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
820 // Insert the patchpoint instruction before the call generated by the target.
821 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
822 TII.get(TargetOpcode::PATCHPOINT));
827 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
829 // Delete the original call instruction.
830 CLI.Call->eraseFromParent();
832 // Inform the Frame Information that we have a patchpoint in this function.
833 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
835 if (CLI.NumResultRegs)
836 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
840 /// Returns an AttributeSet representing the attributes applied to the return
841 /// value of the given call.
842 static AttributeSet getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
843 SmallVector<Attribute::AttrKind, 2> Attrs;
845 Attrs.push_back(Attribute::SExt);
847 Attrs.push_back(Attribute::ZExt);
849 Attrs.push_back(Attribute::InReg);
851 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
855 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
857 ImmutableCallSite CS(CI);
859 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
860 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
861 Type *RetTy = FTy->getReturnType();
864 Args.reserve(NumArgs);
866 // Populate the argument list.
867 // Attributes for args start at offset 1, after the return attribute.
868 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
869 Value *V = CI->getOperand(ArgI);
871 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
875 Entry.Ty = V->getType();
876 Entry.setAttributes(&CS, ArgI + 1);
877 Args.push_back(Entry);
880 CallLoweringInfo CLI;
881 CLI.setCallee(RetTy, FTy, SymName, std::move(Args), CS, NumArgs);
883 return lowerCallTo(CLI);
886 bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
887 // Handle the incoming return values from the call.
889 SmallVector<EVT, 4> RetTys;
890 ComputeValueVTs(TLI, CLI.RetTy, RetTys);
892 SmallVector<ISD::OutputArg, 4> Outs;
893 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI);
895 bool CanLowerReturn = TLI.CanLowerReturn(
896 CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
898 // FIXME: sret demotion isn't supported yet - bail out.
902 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
904 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
905 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
906 for (unsigned i = 0; i != NumRegs; ++i) {
907 ISD::InputArg MyFlags;
908 MyFlags.VT = RegisterVT;
910 MyFlags.Used = CLI.IsReturnValueUsed;
912 MyFlags.Flags.setSExt();
914 MyFlags.Flags.setZExt();
916 MyFlags.Flags.setInReg();
917 CLI.Ins.push_back(MyFlags);
921 // Handle all of the outgoing arguments.
923 for (auto &Arg : CLI.getArgs()) {
924 Type *FinalType = Arg.Ty;
926 FinalType = cast<PointerType>(Arg.Ty)->getElementType();
927 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
928 FinalType, CLI.CallConv, CLI.IsVarArg);
930 ISD::ArgFlagsTy Flags;
941 if (Arg.IsInAlloca) {
943 // Set the byval flag for CCAssignFn callbacks that don't know about
944 // inalloca. This way we can know how many bytes we should've allocated
945 // and how many bytes a callee cleanup function will pop. If we port
946 // inalloca to more targets, we'll have to add custom inalloca handling in
947 // the various CC lowering callbacks.
950 if (Arg.IsByVal || Arg.IsInAlloca) {
951 PointerType *Ty = cast<PointerType>(Arg.Ty);
952 Type *ElementTy = Ty->getElementType();
953 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
954 // For ByVal, alignment should come from FE. BE will guess if this info is
955 // not there, but there are cases it cannot get right.
956 unsigned FrameAlign = Arg.Alignment;
958 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
959 Flags.setByValSize(FrameSize);
960 Flags.setByValAlign(FrameAlign);
965 Flags.setInConsecutiveRegs();
966 unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
967 Flags.setOrigAlign(OriginalAlignment);
969 CLI.OutVals.push_back(Arg.Val);
970 CLI.OutFlags.push_back(Flags);
973 if (!fastLowerCall(CLI))
976 // Set all unused physreg defs as dead.
977 assert(CLI.Call && "No call instruction specified.");
978 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
980 if (CLI.NumResultRegs && CLI.CS)
981 updateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
986 bool FastISel::lowerCall(const CallInst *CI) {
987 ImmutableCallSite CS(CI);
989 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
990 FunctionType *FuncTy = cast<FunctionType>(PT->getElementType());
991 Type *RetTy = FuncTy->getReturnType();
995 Args.reserve(CS.arg_size());
997 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1002 if (V->getType()->isEmptyTy())
1006 Entry.Ty = V->getType();
1008 // Skip the first return-type Attribute to get to params.
1009 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
1010 Args.push_back(Entry);
1013 // Check if target-independent constraints permit a tail call here.
1014 // Target-dependent constraints are checked within fastLowerCall.
1015 bool IsTailCall = CI->isTailCall();
1016 if (IsTailCall && !isInTailCallPosition(CS, TM))
1019 CallLoweringInfo CLI;
1020 CLI.setCallee(RetTy, FuncTy, CI->getCalledValue(), std::move(Args), CS)
1021 .setTailCall(IsTailCall);
1023 return lowerCallTo(CLI);
1026 bool FastISel::selectCall(const User *I) {
1027 const CallInst *Call = cast<CallInst>(I);
1029 // Handle simple inline asms.
1030 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
1031 // If the inline asm has side effects, then make sure that no local value
1032 // lives across by flushing the local value map.
1033 if (IA->hasSideEffects())
1034 flushLocalValueMap();
1036 // Don't attempt to handle constraints.
1037 if (!IA->getConstraintString().empty())
1040 unsigned ExtraInfo = 0;
1041 if (IA->hasSideEffects())
1042 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1043 if (IA->isAlignStack())
1044 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1046 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1047 TII.get(TargetOpcode::INLINEASM))
1048 .addExternalSymbol(IA->getAsmString().c_str())
1053 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
1054 ComputeUsesVAFloatArgument(*Call, &MMI);
1056 // Handle intrinsic function calls.
1057 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1058 return selectIntrinsicCall(II);
1060 // Usually, it does not make sense to initialize a value,
1061 // make an unrelated function call and use the value, because
1062 // it tends to be spilled on the stack. So, we move the pointer
1063 // to the last local value to the beginning of the block, so that
1064 // all the values which have already been materialized,
1065 // appear after the call. It also makes sense to skip intrinsics
1066 // since they tend to be inlined.
1067 flushLocalValueMap();
1069 return lowerCall(Call);
1072 bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
1073 switch (II->getIntrinsicID()) {
1076 // At -O0 we don't care about the lifetime intrinsics.
1077 case Intrinsic::lifetime_start:
1078 case Intrinsic::lifetime_end:
1079 // The donothing intrinsic does, well, nothing.
1080 case Intrinsic::donothing:
1082 case Intrinsic::eh_actions: {
1083 unsigned ResultReg = getRegForValue(UndefValue::get(II->getType()));
1086 updateValueMap(II, ResultReg);
1089 case Intrinsic::dbg_declare: {
1090 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1091 DIVariable DIVar(DI->getVariable());
1092 assert((!DIVar || DIVar.isVariable()) &&
1093 "Variable in DbgDeclareInst should be either null or a DIVariable.");
1094 if (!DIVar || !FuncInfo.MF->getMMI().hasDebugInfo()) {
1095 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1099 const Value *Address = DI->getAddress();
1100 if (!Address || isa<UndefValue>(Address)) {
1101 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1105 unsigned Offset = 0;
1106 Optional<MachineOperand> Op;
1107 if (const auto *Arg = dyn_cast<Argument>(Address))
1108 // Some arguments' frame index is recorded during argument lowering.
1109 Offset = FuncInfo.getArgumentFrameIndex(Arg);
1111 Op = MachineOperand::CreateFI(Offset);
1113 if (unsigned Reg = lookUpRegForValue(Address))
1114 Op = MachineOperand::CreateReg(Reg, false);
1116 // If we have a VLA that has a "use" in a metadata node that's then used
1117 // here but it has no other uses, then we have a problem. E.g.,
1119 // int foo (const int *x) {
1124 // If we assign 'a' a vreg and fast isel later on has to use the selection
1125 // DAG isel, it will want to copy the value to the vreg. However, there are
1126 // no uses, which goes counter to what selection DAG isel expects.
1127 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1128 (!isa<AllocaInst>(Address) ||
1129 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1130 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1135 Op->setIsDebug(true);
1136 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1137 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
1138 DI->getVariable(), DI->getExpression());
1140 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1141 TII.get(TargetOpcode::DBG_VALUE))
1144 .addMetadata(DI->getVariable())
1145 .addMetadata(DI->getExpression());
1147 // We can't yet handle anything else here because it would require
1148 // generating code, thus altering codegen because of debug info.
1149 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1153 case Intrinsic::dbg_value: {
1154 // This form of DBG_VALUE is target-independent.
1155 const DbgValueInst *DI = cast<DbgValueInst>(II);
1156 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1157 const Value *V = DI->getValue();
1159 // Currently the optimizer can produce this; insert an undef to
1160 // help debugging. Probably the optimizer should not do this.
1161 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1163 .addImm(DI->getOffset())
1164 .addMetadata(DI->getVariable())
1165 .addMetadata(DI->getExpression());
1166 } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1167 if (CI->getBitWidth() > 64)
1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1170 .addImm(DI->getOffset())
1171 .addMetadata(DI->getVariable())
1172 .addMetadata(DI->getExpression());
1174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1175 .addImm(CI->getZExtValue())
1176 .addImm(DI->getOffset())
1177 .addMetadata(DI->getVariable())
1178 .addMetadata(DI->getExpression());
1179 } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1182 .addImm(DI->getOffset())
1183 .addMetadata(DI->getVariable())
1184 .addMetadata(DI->getExpression());
1185 } else if (unsigned Reg = lookUpRegForValue(V)) {
1186 // FIXME: This does not handle register-indirect values at offset 0.
1187 bool IsIndirect = DI->getOffset() != 0;
1188 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1189 DI->getOffset(), DI->getVariable(), DI->getExpression());
1191 // We can't yet handle anything else here because it would require
1192 // generating code, thus altering codegen because of debug info.
1193 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1197 case Intrinsic::objectsize: {
1198 ConstantInt *CI = cast<ConstantInt>(II->getArgOperand(1));
1199 unsigned long long Res = CI->isZero() ? -1ULL : 0;
1200 Constant *ResCI = ConstantInt::get(II->getType(), Res);
1201 unsigned ResultReg = getRegForValue(ResCI);
1204 updateValueMap(II, ResultReg);
1207 case Intrinsic::expect: {
1208 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1211 updateValueMap(II, ResultReg);
1214 case Intrinsic::experimental_stackmap:
1215 return selectStackmap(II);
1216 case Intrinsic::experimental_patchpoint_void:
1217 case Intrinsic::experimental_patchpoint_i64:
1218 return selectPatchpoint(II);
1221 return fastLowerIntrinsicCall(II);
1224 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1225 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1226 EVT DstVT = TLI.getValueType(I->getType());
1228 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1230 // Unhandled type. Halt "fast" selection and bail.
1233 // Check if the destination type is legal.
1234 if (!TLI.isTypeLegal(DstVT))
1237 // Check if the source operand is legal.
1238 if (!TLI.isTypeLegal(SrcVT))
1241 unsigned InputReg = getRegForValue(I->getOperand(0));
1243 // Unhandled operand. Halt "fast" selection and bail.
1246 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
1248 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1249 Opcode, InputReg, InputRegIsKill);
1253 updateValueMap(I, ResultReg);
1257 bool FastISel::selectBitCast(const User *I) {
1258 // If the bitcast doesn't change the type, just use the operand value.
1259 if (I->getType() == I->getOperand(0)->getType()) {
1260 unsigned Reg = getRegForValue(I->getOperand(0));
1263 updateValueMap(I, Reg);
1267 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1268 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
1269 EVT DstEVT = TLI.getValueType(I->getType());
1270 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1271 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1272 // Unhandled type. Halt "fast" selection and bail.
1275 MVT SrcVT = SrcEVT.getSimpleVT();
1276 MVT DstVT = DstEVT.getSimpleVT();
1277 unsigned Op0 = getRegForValue(I->getOperand(0));
1278 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1280 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1282 // First, try to perform the bitcast by inserting a reg-reg copy.
1283 unsigned ResultReg = 0;
1284 if (SrcVT == DstVT) {
1285 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1286 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1287 // Don't attempt a cross-class copy. It will likely fail.
1288 if (SrcClass == DstClass) {
1289 ResultReg = createResultReg(DstClass);
1290 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1291 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1295 // If the reg-reg copy failed, select a BITCAST opcode.
1297 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1302 updateValueMap(I, ResultReg);
1306 bool FastISel::selectInstruction(const Instruction *I) {
1307 // Just before the terminator instruction, insert instructions to
1308 // feed PHI nodes in successor blocks.
1309 if (isa<TerminatorInst>(I))
1310 if (!handlePHINodesInSuccessorBlocks(I->getParent()))
1313 DbgLoc = I->getDebugLoc();
1315 SavedInsertPt = FuncInfo.InsertPt;
1317 if (const auto *Call = dyn_cast<CallInst>(I)) {
1318 const Function *F = Call->getCalledFunction();
1321 // As a special case, don't handle calls to builtin library functions that
1322 // may be translated directly to target instructions.
1323 if (F && !F->hasLocalLinkage() && F->hasName() &&
1324 LibInfo->getLibFunc(F->getName(), Func) &&
1325 LibInfo->hasOptimizedCodeGen(Func))
1328 // Don't handle Intrinsic::trap if a trap funciton is specified.
1329 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1330 !TM.Options.getTrapFunctionName().empty())
1334 // First, try doing target-independent selection.
1335 if (!SkipTargetIndependentISel) {
1336 if (selectOperator(I, I->getOpcode())) {
1337 ++NumFastIselSuccessIndependent;
1338 DbgLoc = DebugLoc();
1341 // Remove dead code.
1342 recomputeInsertPt();
1343 if (SavedInsertPt != FuncInfo.InsertPt)
1344 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1345 SavedInsertPt = FuncInfo.InsertPt;
1347 // Next, try calling the target to attempt to handle the instruction.
1348 if (fastSelectInstruction(I)) {
1349 ++NumFastIselSuccessTarget;
1350 DbgLoc = DebugLoc();
1353 // Remove dead code.
1354 recomputeInsertPt();
1355 if (SavedInsertPt != FuncInfo.InsertPt)
1356 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1358 DbgLoc = DebugLoc();
1359 // Undo phi node updates, because they will be added again by SelectionDAG.
1360 if (isa<TerminatorInst>(I))
1361 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1365 /// Emit an unconditional branch to the given block, unless it is the immediate
1366 /// (fall-through) successor, and update the CFG.
1367 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
1368 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
1369 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1370 // For more accurate line information if this is the only instruction
1371 // in the block then emit it, otherwise we have the unconditional
1372 // fall-through case, which needs no instructions.
1374 // The unconditional branch case.
1375 TII.InsertBranch(*FuncInfo.MBB, MSucc, nullptr,
1376 SmallVector<MachineOperand, 0>(), DbgLoc);
1378 uint32_t BranchWeight = 0;
1380 BranchWeight = FuncInfo.BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(),
1381 MSucc->getBasicBlock());
1382 FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
1385 /// Emit an FNeg operation.
1386 bool FastISel::selectFNeg(const User *I) {
1387 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1390 bool OpRegIsKill = hasTrivialKill(I);
1392 // If the target has ISD::FNEG, use it.
1393 EVT VT = TLI.getValueType(I->getType());
1394 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1395 OpReg, OpRegIsKill);
1397 updateValueMap(I, ResultReg);
1401 // Bitcast the value to integer, twiddle the sign bit with xor,
1402 // and then bitcast it back to floating-point.
1403 if (VT.getSizeInBits() > 64)
1405 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1406 if (!TLI.isTypeLegal(IntVT))
1409 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1410 ISD::BITCAST, OpReg, OpRegIsKill);
1414 unsigned IntResultReg = fastEmit_ri_(
1415 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true,
1416 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1420 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1421 IntResultReg, /*IsKill=*/true);
1425 updateValueMap(I, ResultReg);
1429 bool FastISel::selectExtractValue(const User *U) {
1430 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1434 // Make sure we only try to handle extracts with a legal result. But also
1435 // allow i1 because it's easy.
1436 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
1437 if (!RealVT.isSimple())
1439 MVT VT = RealVT.getSimpleVT();
1440 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1443 const Value *Op0 = EVI->getOperand(0);
1444 Type *AggTy = Op0->getType();
1446 // Get the base result register.
1448 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1449 if (I != FuncInfo.ValueMap.end())
1450 ResultReg = I->second;
1451 else if (isa<Instruction>(Op0))
1452 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1454 return false; // fast-isel can't handle aggregate constants at the moment
1456 // Get the actual result register, which is an offset from the base register.
1457 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1459 SmallVector<EVT, 4> AggValueVTs;
1460 ComputeValueVTs(TLI, AggTy, AggValueVTs);
1462 for (unsigned i = 0; i < VTIndex; i++)
1463 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1465 updateValueMap(EVI, ResultReg);
1469 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1471 case Instruction::Add:
1472 return selectBinaryOp(I, ISD::ADD);
1473 case Instruction::FAdd:
1474 return selectBinaryOp(I, ISD::FADD);
1475 case Instruction::Sub:
1476 return selectBinaryOp(I, ISD::SUB);
1477 case Instruction::FSub:
1478 // FNeg is currently represented in LLVM IR as a special case of FSub.
1479 if (BinaryOperator::isFNeg(I))
1480 return selectFNeg(I);
1481 return selectBinaryOp(I, ISD::FSUB);
1482 case Instruction::Mul:
1483 return selectBinaryOp(I, ISD::MUL);
1484 case Instruction::FMul:
1485 return selectBinaryOp(I, ISD::FMUL);
1486 case Instruction::SDiv:
1487 return selectBinaryOp(I, ISD::SDIV);
1488 case Instruction::UDiv:
1489 return selectBinaryOp(I, ISD::UDIV);
1490 case Instruction::FDiv:
1491 return selectBinaryOp(I, ISD::FDIV);
1492 case Instruction::SRem:
1493 return selectBinaryOp(I, ISD::SREM);
1494 case Instruction::URem:
1495 return selectBinaryOp(I, ISD::UREM);
1496 case Instruction::FRem:
1497 return selectBinaryOp(I, ISD::FREM);
1498 case Instruction::Shl:
1499 return selectBinaryOp(I, ISD::SHL);
1500 case Instruction::LShr:
1501 return selectBinaryOp(I, ISD::SRL);
1502 case Instruction::AShr:
1503 return selectBinaryOp(I, ISD::SRA);
1504 case Instruction::And:
1505 return selectBinaryOp(I, ISD::AND);
1506 case Instruction::Or:
1507 return selectBinaryOp(I, ISD::OR);
1508 case Instruction::Xor:
1509 return selectBinaryOp(I, ISD::XOR);
1511 case Instruction::GetElementPtr:
1512 return selectGetElementPtr(I);
1514 case Instruction::Br: {
1515 const BranchInst *BI = cast<BranchInst>(I);
1517 if (BI->isUnconditional()) {
1518 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1519 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1520 fastEmitBranch(MSucc, BI->getDebugLoc());
1524 // Conditional branches are not handed yet.
1525 // Halt "fast" selection and bail.
1529 case Instruction::Unreachable:
1530 if (TM.Options.TrapUnreachable)
1531 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1535 case Instruction::Alloca:
1536 // FunctionLowering has the static-sized case covered.
1537 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1540 // Dynamic-sized alloca is not handled yet.
1543 case Instruction::Call:
1544 return selectCall(I);
1546 case Instruction::BitCast:
1547 return selectBitCast(I);
1549 case Instruction::FPToSI:
1550 return selectCast(I, ISD::FP_TO_SINT);
1551 case Instruction::ZExt:
1552 return selectCast(I, ISD::ZERO_EXTEND);
1553 case Instruction::SExt:
1554 return selectCast(I, ISD::SIGN_EXTEND);
1555 case Instruction::Trunc:
1556 return selectCast(I, ISD::TRUNCATE);
1557 case Instruction::SIToFP:
1558 return selectCast(I, ISD::SINT_TO_FP);
1560 case Instruction::IntToPtr: // Deliberate fall-through.
1561 case Instruction::PtrToInt: {
1562 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1563 EVT DstVT = TLI.getValueType(I->getType());
1564 if (DstVT.bitsGT(SrcVT))
1565 return selectCast(I, ISD::ZERO_EXTEND);
1566 if (DstVT.bitsLT(SrcVT))
1567 return selectCast(I, ISD::TRUNCATE);
1568 unsigned Reg = getRegForValue(I->getOperand(0));
1571 updateValueMap(I, Reg);
1575 case Instruction::ExtractValue:
1576 return selectExtractValue(I);
1578 case Instruction::PHI:
1579 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1582 // Unhandled instruction. Halt "fast" selection and bail.
1587 FastISel::FastISel(FunctionLoweringInfo &FuncInfo,
1588 const TargetLibraryInfo *LibInfo,
1589 bool SkipTargetIndependentISel)
1590 : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1591 MFI(*FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1592 TM(FuncInfo.MF->getTarget()), DL(*TM.getDataLayout()),
1593 TII(*MF->getSubtarget().getInstrInfo()),
1594 TLI(*MF->getSubtarget().getTargetLowering()),
1595 TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1596 SkipTargetIndependentISel(SkipTargetIndependentISel) {}
1598 FastISel::~FastISel() {}
1600 bool FastISel::fastLowerArguments() { return false; }
1602 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1604 bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1608 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1610 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/,
1611 bool /*Op0IsKill*/) {
1615 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1616 bool /*Op0IsKill*/, unsigned /*Op1*/,
1617 bool /*Op1IsKill*/) {
1621 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1625 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1626 const ConstantFP * /*FPImm*/) {
1630 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1631 bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1635 unsigned FastISel::fastEmit_rf(MVT, MVT, unsigned, unsigned /*Op0*/,
1637 const ConstantFP * /*FPImm*/) {
1641 unsigned FastISel::fastEmit_rri(MVT, MVT, unsigned, unsigned /*Op0*/,
1642 bool /*Op0IsKill*/, unsigned /*Op1*/,
1643 bool /*Op1IsKill*/, uint64_t /*Imm*/) {
1647 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1648 /// instruction with an immediate operand using fastEmit_ri.
1649 /// If that fails, it materializes the immediate into a register and try
1650 /// fastEmit_rr instead.
1651 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1652 bool Op0IsKill, uint64_t Imm, MVT ImmType) {
1653 // If this is a multiply by a power of two, emit this as a shift left.
1654 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1657 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1658 // div x, 8 -> srl x, 3
1663 // Horrible hack (to be removed), check to make sure shift amounts are
1665 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1666 Imm >= VT.getSizeInBits())
1669 // First check if immediate type is legal. If not, we can't use the ri form.
1670 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1673 unsigned MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1675 // This is a bit ugly/slow, but failing here means falling out of
1676 // fast-isel, which would be very slow.
1678 IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
1679 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1683 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg,
1687 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) {
1688 return MRI.createVirtualRegister(RC);
1691 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
1693 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1694 const TargetRegisterClass *RegClass =
1695 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1696 if (!MRI.constrainRegClass(Op, RegClass)) {
1697 // If it's not legal to COPY between the register classes, something
1698 // has gone very wrong before we got here.
1699 unsigned NewOp = createResultReg(RegClass);
1700 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1701 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1708 unsigned FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1709 const TargetRegisterClass *RC) {
1710 unsigned ResultReg = createResultReg(RC);
1711 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1713 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1717 unsigned FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1718 const TargetRegisterClass *RC, unsigned Op0,
1720 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1722 unsigned ResultReg = createResultReg(RC);
1723 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1725 if (II.getNumDefs() >= 1)
1726 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1727 .addReg(Op0, getKillRegState(Op0IsKill));
1729 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1730 .addReg(Op0, getKillRegState(Op0IsKill));
1731 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1732 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1738 unsigned FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1739 const TargetRegisterClass *RC, unsigned Op0,
1740 bool Op0IsKill, unsigned Op1,
1742 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1744 unsigned ResultReg = createResultReg(RC);
1745 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1746 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1748 if (II.getNumDefs() >= 1)
1749 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1750 .addReg(Op0, getKillRegState(Op0IsKill))
1751 .addReg(Op1, getKillRegState(Op1IsKill));
1753 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1754 .addReg(Op0, getKillRegState(Op0IsKill))
1755 .addReg(Op1, getKillRegState(Op1IsKill));
1756 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1757 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1762 unsigned FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1763 const TargetRegisterClass *RC, unsigned Op0,
1764 bool Op0IsKill, unsigned Op1,
1765 bool Op1IsKill, unsigned Op2,
1767 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1769 unsigned ResultReg = createResultReg(RC);
1770 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1771 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1772 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1774 if (II.getNumDefs() >= 1)
1775 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1776 .addReg(Op0, getKillRegState(Op0IsKill))
1777 .addReg(Op1, getKillRegState(Op1IsKill))
1778 .addReg(Op2, getKillRegState(Op2IsKill));
1780 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1781 .addReg(Op0, getKillRegState(Op0IsKill))
1782 .addReg(Op1, getKillRegState(Op1IsKill))
1783 .addReg(Op2, getKillRegState(Op2IsKill));
1784 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1785 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1790 unsigned FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1791 const TargetRegisterClass *RC, unsigned Op0,
1792 bool Op0IsKill, uint64_t Imm) {
1793 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1795 unsigned ResultReg = createResultReg(RC);
1796 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1798 if (II.getNumDefs() >= 1)
1799 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1800 .addReg(Op0, getKillRegState(Op0IsKill))
1803 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1804 .addReg(Op0, getKillRegState(Op0IsKill))
1806 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1807 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1812 unsigned FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
1813 const TargetRegisterClass *RC, unsigned Op0,
1814 bool Op0IsKill, uint64_t Imm1,
1816 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1818 unsigned ResultReg = createResultReg(RC);
1819 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1821 if (II.getNumDefs() >= 1)
1822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1823 .addReg(Op0, getKillRegState(Op0IsKill))
1827 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1828 .addReg(Op0, getKillRegState(Op0IsKill))
1831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1832 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1837 unsigned FastISel::fastEmitInst_rf(unsigned MachineInstOpcode,
1838 const TargetRegisterClass *RC, unsigned Op0,
1839 bool Op0IsKill, const ConstantFP *FPImm) {
1840 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1842 unsigned ResultReg = createResultReg(RC);
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1845 if (II.getNumDefs() >= 1)
1846 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1847 .addReg(Op0, getKillRegState(Op0IsKill))
1850 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1851 .addReg(Op0, getKillRegState(Op0IsKill))
1853 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1854 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1859 unsigned FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
1860 const TargetRegisterClass *RC, unsigned Op0,
1861 bool Op0IsKill, unsigned Op1,
1862 bool Op1IsKill, uint64_t Imm) {
1863 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1865 unsigned ResultReg = createResultReg(RC);
1866 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1867 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1869 if (II.getNumDefs() >= 1)
1870 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1871 .addReg(Op0, getKillRegState(Op0IsKill))
1872 .addReg(Op1, getKillRegState(Op1IsKill))
1875 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1876 .addReg(Op0, getKillRegState(Op0IsKill))
1877 .addReg(Op1, getKillRegState(Op1IsKill))
1879 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1880 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1885 unsigned FastISel::fastEmitInst_rrii(unsigned MachineInstOpcode,
1886 const TargetRegisterClass *RC,
1887 unsigned Op0, bool Op0IsKill, unsigned Op1,
1888 bool Op1IsKill, uint64_t Imm1,
1890 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1892 unsigned ResultReg = createResultReg(RC);
1893 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1894 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1896 if (II.getNumDefs() >= 1)
1897 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1898 .addReg(Op0, getKillRegState(Op0IsKill))
1899 .addReg(Op1, getKillRegState(Op1IsKill))
1903 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1904 .addReg(Op0, getKillRegState(Op0IsKill))
1905 .addReg(Op1, getKillRegState(Op1IsKill))
1908 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1909 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1914 unsigned FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
1915 const TargetRegisterClass *RC, uint64_t Imm) {
1916 unsigned ResultReg = createResultReg(RC);
1917 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1919 if (II.getNumDefs() >= 1)
1920 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1923 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1924 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1925 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1930 unsigned FastISel::fastEmitInst_ii(unsigned MachineInstOpcode,
1931 const TargetRegisterClass *RC, uint64_t Imm1,
1933 unsigned ResultReg = createResultReg(RC);
1934 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1936 if (II.getNumDefs() >= 1)
1937 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1)
1943 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1944 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1949 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
1950 bool Op0IsKill, uint32_t Idx) {
1951 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1952 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1953 "Cannot yet extract from physregs");
1954 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1955 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1956 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1957 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
1961 /// Emit MachineInstrs to compute the value of Op with all but the least
1962 /// significant bit set to zero.
1963 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1964 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1967 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1968 /// Emit code to ensure constants are copied into registers when needed.
1969 /// Remember the virtual registers that need to be added to the Machine PHI
1970 /// nodes as input. We cannot just directly add them, because expansion
1971 /// might result in multiple MBB's for one BB. As such, the start of the
1972 /// BB might correspond to a different MBB than the end.
1973 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1974 const TerminatorInst *TI = LLVMBB->getTerminator();
1976 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1977 FuncInfo.OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1979 // Check successor nodes' PHI nodes that expect a constant to be available
1981 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1982 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1983 if (!isa<PHINode>(SuccBB->begin()))
1985 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1987 // If this terminator has multiple identical successors (common for
1988 // switches), only handle each succ once.
1989 if (!SuccsHandled.insert(SuccMBB).second)
1992 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1994 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1995 // nodes and Machine PHI nodes, but the incoming operands have not been
1997 for (BasicBlock::const_iterator I = SuccBB->begin();
1998 const auto *PN = dyn_cast<PHINode>(I); ++I) {
2000 // Ignore dead phi's.
2001 if (PN->use_empty())
2004 // Only handle legal types. Two interesting things to note here. First,
2005 // by bailing out early, we may leave behind some dead instructions,
2006 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2007 // own moves. Second, this check is necessary because FastISel doesn't
2008 // use CreateRegs to create registers, so it always creates
2009 // exactly one register for each non-void instruction.
2010 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
2011 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2012 // Handle integer promotions, though, because they're common and easy.
2013 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2014 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2019 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2021 // Set the DebugLoc for the copy. Prefer the location of the operand
2022 // if there is one; use the location of the PHI otherwise.
2023 DbgLoc = PN->getDebugLoc();
2024 if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2025 DbgLoc = Inst->getDebugLoc();
2027 unsigned Reg = getRegForValue(PHIOp);
2029 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2032 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
2033 DbgLoc = DebugLoc();
2040 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2041 assert(LI->hasOneUse() &&
2042 "tryToFoldLoad expected a LoadInst with a single use");
2043 // We know that the load has a single use, but don't know what it is. If it
2044 // isn't one of the folded instructions, then we can't succeed here. Handle
2045 // this by scanning the single-use users of the load until we get to FoldInst.
2046 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2048 const Instruction *TheUser = LI->user_back();
2049 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2050 // Stay in the right block.
2051 TheUser->getParent() == FoldInst->getParent() &&
2052 --MaxUsers) { // Don't scan too far.
2053 // If there are multiple or no uses of this instruction, then bail out.
2054 if (!TheUser->hasOneUse())
2057 TheUser = TheUser->user_back();
2060 // If we didn't find the fold instruction, then we failed to collapse the
2062 if (TheUser != FoldInst)
2065 // Don't try to fold volatile loads. Target has to deal with alignment
2067 if (LI->isVolatile())
2070 // Figure out which vreg this is going into. If there is no assigned vreg yet
2071 // then there actually was no reference to it. Perhaps the load is referenced
2072 // by a dead instruction.
2073 unsigned LoadReg = getRegForValue(LI);
2077 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2078 // may mean that the instruction got lowered to multiple MIs, or the use of
2079 // the loaded value ended up being multiple operands of the result.
2080 if (!MRI.hasOneUse(LoadReg))
2083 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2084 MachineInstr *User = RI->getParent();
2086 // Set the insertion point properly. Folding the load can cause generation of
2087 // other random instructions (like sign extends) for addressing modes; make
2088 // sure they get inserted in a logical place before the new instruction.
2089 FuncInfo.InsertPt = User;
2090 FuncInfo.MBB = User->getParent();
2092 // Ask the target to try folding the load.
2093 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2096 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2098 if (!isa<AddOperator>(Add))
2100 // Type size needs to match.
2101 if (DL.getTypeSizeInBits(GEP->getType()) !=
2102 DL.getTypeSizeInBits(Add->getType()))
2104 // Must be in the same basic block.
2105 if (isa<Instruction>(Add) &&
2106 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2108 // Must have a constant operand.
2109 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2113 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2120 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2121 Alignment = LI->getAlignment();
2122 IsVolatile = LI->isVolatile();
2123 Flags = MachineMemOperand::MOLoad;
2124 Ptr = LI->getPointerOperand();
2125 ValTy = LI->getType();
2126 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2127 Alignment = SI->getAlignment();
2128 IsVolatile = SI->isVolatile();
2129 Flags = MachineMemOperand::MOStore;
2130 Ptr = SI->getPointerOperand();
2131 ValTy = SI->getValueOperand()->getType();
2135 bool IsNonTemporal = I->getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2136 bool IsInvariant = I->getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2137 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2140 I->getAAMetadata(AAInfo);
2142 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
2143 Alignment = DL.getABITypeAlignment(ValTy);
2145 unsigned Size = DL.getTypeStoreSize(ValTy);
2148 Flags |= MachineMemOperand::MOVolatile;
2150 Flags |= MachineMemOperand::MONonTemporal;
2152 Flags |= MachineMemOperand::MOInvariant;
2154 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2155 Alignment, AAInfo, Ranges);
2158 CmpInst::Predicate FastISel::optimizeCmpPredicate(const CmpInst *CI) const {
2159 // If both operands are the same, then try to optimize or fold the cmp.
2160 CmpInst::Predicate Predicate = CI->getPredicate();
2161 if (CI->getOperand(0) != CI->getOperand(1))
2164 switch (Predicate) {
2165 default: llvm_unreachable("Invalid predicate!");
2166 case CmpInst::FCMP_FALSE: Predicate = CmpInst::FCMP_FALSE; break;
2167 case CmpInst::FCMP_OEQ: Predicate = CmpInst::FCMP_ORD; break;
2168 case CmpInst::FCMP_OGT: Predicate = CmpInst::FCMP_FALSE; break;
2169 case CmpInst::FCMP_OGE: Predicate = CmpInst::FCMP_ORD; break;
2170 case CmpInst::FCMP_OLT: Predicate = CmpInst::FCMP_FALSE; break;
2171 case CmpInst::FCMP_OLE: Predicate = CmpInst::FCMP_ORD; break;
2172 case CmpInst::FCMP_ONE: Predicate = CmpInst::FCMP_FALSE; break;
2173 case CmpInst::FCMP_ORD: Predicate = CmpInst::FCMP_ORD; break;
2174 case CmpInst::FCMP_UNO: Predicate = CmpInst::FCMP_UNO; break;
2175 case CmpInst::FCMP_UEQ: Predicate = CmpInst::FCMP_TRUE; break;
2176 case CmpInst::FCMP_UGT: Predicate = CmpInst::FCMP_UNO; break;
2177 case CmpInst::FCMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2178 case CmpInst::FCMP_ULT: Predicate = CmpInst::FCMP_UNO; break;
2179 case CmpInst::FCMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2180 case CmpInst::FCMP_UNE: Predicate = CmpInst::FCMP_UNO; break;
2181 case CmpInst::FCMP_TRUE: Predicate = CmpInst::FCMP_TRUE; break;
2183 case CmpInst::ICMP_EQ: Predicate = CmpInst::FCMP_TRUE; break;
2184 case CmpInst::ICMP_NE: Predicate = CmpInst::FCMP_FALSE; break;
2185 case CmpInst::ICMP_UGT: Predicate = CmpInst::FCMP_FALSE; break;
2186 case CmpInst::ICMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2187 case CmpInst::ICMP_ULT: Predicate = CmpInst::FCMP_FALSE; break;
2188 case CmpInst::ICMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2189 case CmpInst::ICMP_SGT: Predicate = CmpInst::FCMP_FALSE; break;
2190 case CmpInst::ICMP_SGE: Predicate = CmpInst::FCMP_TRUE; break;
2191 case CmpInst::ICMP_SLT: Predicate = CmpInst::FCMP_FALSE; break;
2192 case CmpInst::ICMP_SLE: Predicate = CmpInst::FCMP_TRUE; break;