1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/ADT/DenseSet.h"
37 #include "llvm/ADT/SetOperations.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 struct MachineVerifier : public MachineFunctionPass {
46 static char ID; // Pass ID, replacement for typeid
48 MachineVerifier(bool allowDoubleDefs = false) :
49 MachineFunctionPass(&ID),
50 allowVirtDoubleDefs(allowDoubleDefs),
51 allowPhysDoubleDefs(allowDoubleDefs),
52 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
55 void getAnalysisUsage(AnalysisUsage &AU) const {
57 MachineFunctionPass::getAnalysisUsage(AU);
60 bool runOnMachineFunction(MachineFunction &MF);
62 const bool allowVirtDoubleDefs;
63 const bool allowPhysDoubleDefs;
65 const char *const OutFileName;
67 const MachineFunction *MF;
68 const TargetMachine *TM;
69 const TargetRegisterInfo *TRI;
70 const MachineRegisterInfo *MRI;
74 typedef SmallVector<unsigned, 16> RegVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78 BitVector regsReserved;
80 RegVector regsDefined, regsDead, regsKilled;
81 RegSet regsLiveInButUnused;
83 // Add Reg and any sub-registers to RV
84 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
86 if (TargetRegisterInfo::isPhysicalRegister(Reg))
87 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
92 // Is this MBB reachable from the MF entry point?
95 // Vregs that must be live in because they are used without being
96 // defined. Map value is the user.
99 // Vregs that must be dead in because they are defined without being
100 // killed first. Map value is the defining instruction.
103 // Regs killed in MBB. They may be defined again, and will then be in both
104 // regsKilled and regsLiveOut.
107 // Regs defined in MBB and live out. Note that vregs passing through may
108 // be live out without being mentioned here.
111 // Vregs that pass through MBB untouched. This set is disjoint from
112 // regsKilled and regsLiveOut.
115 BBInfo() : reachable(false) {}
117 // Add register to vregsPassed if it belongs there. Return true if
119 bool addPassed(unsigned Reg) {
120 if (!TargetRegisterInfo::isVirtualRegister(Reg))
122 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
124 return vregsPassed.insert(Reg).second;
127 // Same for a full set.
128 bool addPassed(const RegSet &RS) {
129 bool changed = false;
130 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
136 // Live-out registers are either in regsLiveOut or vregsPassed.
137 bool isLiveOut(unsigned Reg) const {
138 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
142 // Extra register info per MBB.
143 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
145 bool isReserved(unsigned Reg) {
146 return Reg < regsReserved.size() && regsReserved.test(Reg);
149 void visitMachineFunctionBefore();
150 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
151 void visitMachineInstrBefore(const MachineInstr *MI);
152 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
153 void visitMachineInstrAfter(const MachineInstr *MI);
154 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
155 void visitMachineFunctionAfter();
157 void report(const char *msg, const MachineFunction *MF);
158 void report(const char *msg, const MachineBasicBlock *MBB);
159 void report(const char *msg, const MachineInstr *MI);
160 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
162 void markReachable(const MachineBasicBlock *MBB);
163 void calcMaxRegsPassed();
164 void calcMinRegsPassed();
165 void checkPHIOps(const MachineBasicBlock *MBB);
169 char MachineVerifier::ID = 0;
170 static RegisterPass<MachineVerifier>
171 MachineVer("machineverifier", "Verify generated machine code");
172 static const PassInfo *const MachineVerifyID = &MachineVer;
174 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
175 return new MachineVerifier(allowPhysDoubleDefs);
178 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
179 raw_ostream *OutFile = 0;
181 std::string ErrorInfo;
182 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
183 raw_fd_ostream::F_Append);
184 if (!ErrorInfo.empty()) {
185 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
197 TM = &MF.getTarget();
198 TRI = TM->getRegisterInfo();
199 MRI = &MF.getRegInfo();
201 visitMachineFunctionBefore();
202 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
204 visitMachineBasicBlockBefore(MFI);
205 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
206 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
207 visitMachineInstrBefore(MBBI);
208 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
209 visitMachineOperand(&MBBI->getOperand(I), I);
210 visitMachineInstrAfter(MBBI);
212 visitMachineBasicBlockAfter(MFI);
214 visitMachineFunctionAfter();
218 else if (foundErrors)
219 llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
226 regsLiveInButUnused.clear();
229 return false; // no changes
232 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
237 *OS << "*** Bad machine code: " << msg << " ***\n"
238 << "- function: " << MF->getFunction()->getNameStr() << "\n";
241 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
243 report(msg, MBB->getParent());
244 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
246 << " (BB#" << MBB->getNumber() << ")\n";
249 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
251 report(msg, MI->getParent());
252 *OS << "- instruction: ";
256 void MachineVerifier::report(const char *msg,
257 const MachineOperand *MO, unsigned MONum) {
259 report(msg, MO->getParent());
260 *OS << "- operand " << MONum << ": ";
265 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
266 BBInfo &MInfo = MBBInfoMap[MBB];
267 if (!MInfo.reachable) {
268 MInfo.reachable = true;
269 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
270 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
275 void MachineVerifier::visitMachineFunctionBefore() {
276 regsReserved = TRI->getReservedRegs(*MF);
278 // A sub-register of a reserved register is also reserved
279 for (int Reg = regsReserved.find_first(); Reg>=0;
280 Reg = regsReserved.find_next(Reg)) {
281 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
282 // FIXME: This should probably be:
283 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
284 regsReserved.set(*Sub);
287 markReachable(&MF->front());
290 // Does iterator point to a and b as the first two elements?
291 bool matchPair(MachineBasicBlock::const_succ_iterator i,
292 const MachineBasicBlock *a, const MachineBasicBlock *b) {
301 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
302 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
304 // Start with minimal CFG sanity checks.
305 MachineFunction::const_iterator MBBI = MBB;
307 if (MBBI != MF->end()) {
308 // Block is not last in function.
309 if (!MBB->isSuccessor(MBBI)) {
310 // Block does not fall through.
312 report("MBB doesn't fall through but is empty!", MBB);
315 if (TII->BlockHasNoFallThrough(*MBB)) {
317 report("TargetInstrInfo says the block has no fall through, but the "
318 "block is empty!", MBB);
319 } else if (!MBB->back().getDesc().isBarrier()) {
320 report("TargetInstrInfo says the block has no fall through, but the "
321 "block does not end in a barrier!", MBB);
325 // Block is last in function.
327 report("MBB is last in function but is empty!", MBB);
331 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
332 MachineBasicBlock *TBB = 0, *FBB = 0;
333 SmallVector<MachineOperand, 4> Cond;
334 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
336 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
337 // check whether its answers match up with reality.
339 // Block falls through to its successor.
340 MachineFunction::const_iterator MBBI = MBB;
342 if (MBBI == MF->end()) {
343 // It's possible that the block legitimately ends with a noreturn
344 // call or an unreachable, in which case it won't actually fall
345 // out the bottom of the function.
346 } else if (MBB->succ_empty()) {
347 // It's possible that the block legitimately ends with a noreturn
348 // call or an unreachable, in which case it won't actuall fall
350 } else if (MBB->succ_size() != 1) {
351 report("MBB exits via unconditional fall-through but doesn't have "
352 "exactly one CFG successor!", MBB);
353 } else if (MBB->succ_begin()[0] != MBBI) {
354 report("MBB exits via unconditional fall-through but its successor "
355 "differs from its CFG successor!", MBB);
357 if (!MBB->empty() && MBB->back().getDesc().isBarrier()) {
358 report("MBB exits via unconditional fall-through but ends with a "
359 "barrier instruction!", MBB);
362 report("MBB exits via unconditional fall-through but has a condition!",
365 } else if (TBB && !FBB && Cond.empty()) {
366 // Block unconditionally branches somewhere.
367 if (MBB->succ_size() != 1) {
368 report("MBB exits via unconditional branch but doesn't have "
369 "exactly one CFG successor!", MBB);
370 } else if (MBB->succ_begin()[0] != TBB) {
371 report("MBB exits via unconditional branch but the CFG "
372 "successor doesn't match the actual successor!", MBB);
375 report("MBB exits via unconditional branch but doesn't contain "
376 "any instructions!", MBB);
377 } else if (!MBB->back().getDesc().isBarrier()) {
378 report("MBB exits via unconditional branch but doesn't end with a "
379 "barrier instruction!", MBB);
380 } else if (!MBB->back().getDesc().isTerminator()) {
381 report("MBB exits via unconditional branch but the branch isn't a "
382 "terminator instruction!", MBB);
384 } else if (TBB && !FBB && !Cond.empty()) {
385 // Block conditionally branches somewhere, otherwise falls through.
386 MachineFunction::const_iterator MBBI = MBB;
388 if (MBBI == MF->end()) {
389 report("MBB conditionally falls through out of function!", MBB);
390 } if (MBB->succ_size() != 2) {
391 report("MBB exits via conditional branch/fall-through but doesn't have "
392 "exactly two CFG successors!", MBB);
393 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
394 report("MBB exits via conditional branch/fall-through but the CFG "
395 "successors don't match the actual successors!", MBB);
398 report("MBB exits via conditional branch/fall-through but doesn't "
399 "contain any instructions!", MBB);
400 } else if (MBB->back().getDesc().isBarrier()) {
401 report("MBB exits via conditional branch/fall-through but ends with a "
402 "barrier instruction!", MBB);
403 } else if (!MBB->back().getDesc().isTerminator()) {
404 report("MBB exits via conditional branch/fall-through but the branch "
405 "isn't a terminator instruction!", MBB);
407 } else if (TBB && FBB) {
408 // Block conditionally branches somewhere, otherwise branches
410 if (MBB->succ_size() != 2) {
411 report("MBB exits via conditional branch/branch but doesn't have "
412 "exactly two CFG successors!", MBB);
413 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
414 report("MBB exits via conditional branch/branch but the CFG "
415 "successors don't match the actual successors!", MBB);
418 report("MBB exits via conditional branch/branch but doesn't "
419 "contain any instructions!", MBB);
420 } else if (!MBB->back().getDesc().isBarrier()) {
421 report("MBB exits via conditional branch/branch but doesn't end with a "
422 "barrier instruction!", MBB);
423 } else if (!MBB->back().getDesc().isTerminator()) {
424 report("MBB exits via conditional branch/branch but the branch "
425 "isn't a terminator instruction!", MBB);
428 report("MBB exits via conditinal branch/branch but there's no "
432 report("AnalyzeBranch returned invalid data!", MBB);
437 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
438 E = MBB->livein_end(); I != E; ++I) {
439 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
440 report("MBB live-in list contains non-physical register", MBB);
444 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
447 regsLiveInButUnused = regsLive;
449 const MachineFrameInfo *MFI = MF->getFrameInfo();
450 assert(MFI && "Function has no frame info");
451 BitVector PR = MFI->getPristineRegs(MBB);
452 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
454 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
462 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
463 const TargetInstrDesc &TI = MI->getDesc();
464 if (MI->getNumOperands() < TI.getNumOperands()) {
465 report("Too few operands", MI);
466 *OS << TI.getNumOperands() << " operands expected, but "
467 << MI->getNumExplicitOperands() << " given.\n";
470 // Check the MachineMemOperands for basic consistency.
471 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
472 E = MI->memoperands_end(); I != E; ++I) {
473 if ((*I)->isLoad() && !TI.mayLoad())
474 report("Missing mayLoad flag", MI);
475 if ((*I)->isStore() && !TI.mayStore())
476 report("Missing mayStore flag", MI);
481 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
482 const MachineInstr *MI = MO->getParent();
483 const TargetInstrDesc &TI = MI->getDesc();
485 // The first TI.NumDefs operands must be explicit register defines
486 if (MONum < TI.getNumDefs()) {
488 report("Explicit definition must be a register", MO, MONum);
489 else if (!MO->isDef())
490 report("Explicit definition marked as use", MO, MONum);
491 else if (MO->isImplicit())
492 report("Explicit definition marked as implicit", MO, MONum);
493 } else if (MONum < TI.getNumOperands()) {
496 report("Explicit operand marked as def", MO, MONum);
497 if (MO->isImplicit())
498 report("Explicit operand marked as implicit", MO, MONum);
501 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
502 report("Extra explicit operand on non-variadic instruction", MO, MONum);
505 switch (MO->getType()) {
506 case MachineOperand::MO_Register: {
507 const unsigned Reg = MO->getReg();
511 // Check Live Variables.
513 // An <undef> doesn't refer to any register, so just skip it.
514 } else if (MO->isUse()) {
515 regsLiveInButUnused.erase(Reg);
518 addRegWithSubRegs(regsKilled, Reg);
519 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
520 if (MI->isRegTiedToDefOperand(MONum))
521 report("Illegal kill flag on two-address instruction operand",
524 // TwoAddress instr modifying a reg is treated as kill+def.
526 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
527 MI->getOperand(defIdx).getReg() == Reg)
528 addRegWithSubRegs(regsKilled, Reg);
530 // Use of a dead register.
531 if (!regsLive.count(Reg)) {
532 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
533 // Reserved registers may be used even when 'dead'.
534 if (!isReserved(Reg))
535 report("Using an undefined physical register", MO, MONum);
537 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
538 // We don't know which virtual registers are live in, so only complain
539 // if vreg was killed in this MBB. Otherwise keep track of vregs that
540 // must be live in. PHI instructions are handled separately.
541 if (MInfo.regsKilled.count(Reg))
542 report("Using a killed virtual register", MO, MONum);
543 else if (MI->getOpcode() != TargetInstrInfo::PHI)
544 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
550 // TODO: verify that earlyclobber ops are not used.
552 addRegWithSubRegs(regsDead, Reg);
554 addRegWithSubRegs(regsDefined, Reg);
557 // Check register classes.
558 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
559 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
560 unsigned SubIdx = MO->getSubReg();
562 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
565 unsigned s = TRI->getSubReg(Reg, SubIdx);
567 report("Invalid subregister index for physical register",
573 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
574 if (!DRC->contains(sr)) {
575 report("Illegal physical register for instruction", MO, MONum);
576 *OS << TRI->getName(sr) << " is not a "
577 << DRC->getName() << " register.\n";
582 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
584 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
585 report("Invalid subregister index for virtual register", MO, MONum);
588 RC = *(RC->subregclasses_begin()+SubIdx);
590 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
591 if (RC != DRC && !RC->hasSuperClass(DRC)) {
592 report("Illegal virtual register for instruction", MO, MONum);
593 *OS << "Expected a " << DRC->getName() << " register, but got a "
594 << RC->getName() << " register\n";
602 case MachineOperand::MO_MachineBasicBlock:
603 if (MI->getOpcode() == TargetInstrInfo::PHI) {
604 if (!MO->getMBB()->isSuccessor(MI->getParent()))
605 report("PHI operand is not in the CFG", MO, MONum);
614 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
615 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
616 set_union(MInfo.regsKilled, regsKilled);
617 set_subtract(regsLive, regsKilled);
620 // Verify that both <def> and <def,dead> operands refer to dead registers.
621 RegVector defs(regsDefined);
622 defs.append(regsDead.begin(), regsDead.end());
624 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
626 if (regsLive.count(*I)) {
627 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
628 if (!allowPhysDoubleDefs && !isReserved(*I) &&
629 !regsLiveInButUnused.count(*I)) {
630 report("Redefining a live physical register", MI);
631 *OS << "Register " << TRI->getName(*I)
632 << " was defined but already live.\n";
635 if (!allowVirtDoubleDefs) {
636 report("Redefining a live virtual register", MI);
637 *OS << "Virtual register %reg" << *I
638 << " was defined but already live.\n";
641 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
642 !MInfo.regsKilled.count(*I)) {
643 // Virtual register defined without being killed first must be dead on
645 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
649 set_subtract(regsLive, regsDead); regsDead.clear();
650 set_union(regsLive, regsDefined); regsDefined.clear();
654 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
655 MBBInfoMap[MBB].regsLiveOut = regsLive;
659 // Calculate the largest possible vregsPassed sets. These are the registers that
660 // can pass through an MBB live, but may not be live every time. It is assumed
661 // that all vregsPassed sets are empty before the call.
662 void MachineVerifier::calcMaxRegsPassed() {
663 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
664 // have any vregsPassed.
665 DenseSet<const MachineBasicBlock*> todo;
666 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
668 const MachineBasicBlock &MBB(*MFI);
669 BBInfo &MInfo = MBBInfoMap[&MBB];
670 if (!MInfo.reachable)
672 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
673 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
674 BBInfo &SInfo = MBBInfoMap[*SuI];
675 if (SInfo.addPassed(MInfo.regsLiveOut))
680 // Iteratively push vregsPassed to successors. This will converge to the same
681 // final state regardless of DenseSet iteration order.
682 while (!todo.empty()) {
683 const MachineBasicBlock *MBB = *todo.begin();
685 BBInfo &MInfo = MBBInfoMap[MBB];
686 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
687 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
690 BBInfo &SInfo = MBBInfoMap[*SuI];
691 if (SInfo.addPassed(MInfo.vregsPassed))
697 // Calculate the minimum vregsPassed set. These are the registers that always
698 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
699 // been called earlier.
700 void MachineVerifier::calcMinRegsPassed() {
701 DenseSet<const MachineBasicBlock*> todo;
702 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
706 while (!todo.empty()) {
707 const MachineBasicBlock *MBB = *todo.begin();
709 BBInfo &MInfo = MBBInfoMap[MBB];
711 // Remove entries from vRegsPassed that are not live out from all
712 // reachable predecessors.
714 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
715 E = MInfo.vregsPassed.end(); I != E; ++I) {
716 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
717 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
718 BBInfo &PrInfo = MBBInfoMap[*PrI];
719 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
725 // If any regs removed, we need to recheck successors.
727 set_subtract(MInfo.vregsPassed, dead);
728 todo.insert(MBB->succ_begin(), MBB->succ_end());
733 // Check PHI instructions at the beginning of MBB. It is assumed that
734 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
735 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
736 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
737 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
738 DenseSet<const MachineBasicBlock*> seen;
740 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
741 unsigned Reg = BBI->getOperand(i).getReg();
742 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
743 if (!Pre->isSuccessor(MBB))
746 BBInfo &PrInfo = MBBInfoMap[Pre];
747 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
748 report("PHI operand is not live-out from predecessor",
749 &BBI->getOperand(i), i);
752 // Did we see all predecessors?
753 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
754 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
755 if (!seen.count(*PrI)) {
756 report("Missing PHI operand", BBI);
757 *OS << "BB#" << (*PrI)->getNumber()
758 << " is a predecessor according to the CFG.\n";
764 void MachineVerifier::visitMachineFunctionAfter() {
767 // With the maximal set of vregsPassed we can verify dead-in registers.
768 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
770 BBInfo &MInfo = MBBInfoMap[MFI];
772 // Skip unreachable MBBs.
773 if (!MInfo.reachable)
776 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
777 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
778 BBInfo &PrInfo = MBBInfoMap[*PrI];
779 if (!PrInfo.reachable)
782 // Verify physical live-ins. EH landing pads have magic live-ins so we
784 if (!MFI->isLandingPad()) {
785 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
786 E = MFI->livein_end(); I != E; ++I) {
787 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
788 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
789 report("Live-in physical register is not live-out from predecessor",
791 *OS << "Register " << TRI->getName(*I)
792 << " is not live-out from BB#" << (*PrI)->getNumber()
799 // Verify dead-in virtual registers.
800 if (!allowVirtDoubleDefs) {
801 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
802 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
803 // DeadIn register must be in neither regsLiveOut or vregsPassed of
805 if (PrInfo.isLiveOut(I->first)) {
806 report("Live-in virtual register redefined", I->second);
807 *OS << "Register %reg" << I->first
808 << " was live-out from predecessor MBB #"
809 << (*PrI)->getNumber() << ".\n";
818 // With the minimal set of vregsPassed we can verify live-in virtual
819 // registers, including PHI instructions.
820 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
822 BBInfo &MInfo = MBBInfoMap[MFI];
824 // Skip unreachable MBBs.
825 if (!MInfo.reachable)
830 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
831 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
832 BBInfo &PrInfo = MBBInfoMap[*PrI];
833 if (!PrInfo.reachable)
836 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
837 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
838 if (!PrInfo.isLiveOut(I->first)) {
839 report("Used virtual register is not live-in", I->second);
840 *OS << "Register %reg" << I->first
841 << " is not live-out from predecessor MBB #"
842 << (*PrI)->getNumber()