1 //===- llvm/Transforms/TargetTransformInfo.h --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass exposes codegen information to IR-level passes. Every
11 // transformation that uses codegen information is broken into three parts:
12 // 1. The IR-level analysis pass.
13 // 2. The IR-level transformation interface which provides the needed
15 // 3. Codegen-level implementation which uses target-specific hooks.
17 // This file defines #2, which is the interface that IR-level transformations
18 // use for querying the codegen.
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TRANSFORMS_TARGET_TRANSFORM_INTERFACE
23 #define LLVM_TRANSFORMS_TARGET_TRANSFORM_INTERFACE
25 #include "llvm/IR/Intrinsics.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Pass.h"
29 #include "llvm/Support/DataTypes.h"
33 /// TargetTransformInfo - This pass provides access to the codegen
34 /// interfaces that are needed for IR-level transformations.
35 class TargetTransformInfo {
37 /// \brief The TTI instance one level down the stack.
39 /// This is used to implement the default behavior all of the methods which
40 /// is to delegate up through the stack of TTIs until one can answer the
42 TargetTransformInfo *PrevTTI;
44 /// \brief The top of the stack of TTI analyses available.
46 /// This is a convenience routine maintained as TTI analyses become available
47 /// that complements the PrevTTI delegation chain. When one part of an
48 /// analysis pass wants to query another part of the analysis pass it can use
49 /// this to start back at the top of the stack.
50 TargetTransformInfo *TopTTI;
52 /// All pass subclasses must in their initializePass routine call
53 /// pushTTIStack with themselves to update the pointers tracking the previous
54 /// TTI instance in the analysis group's stack, and the top of the analysis
56 void pushTTIStack(Pass *P);
58 /// All pass subclasses must in their finalizePass routine call popTTIStack
59 /// to update the pointers tracking the previous TTI instance in the analysis
60 /// group's stack, and the top of the analysis group's stack.
63 /// All pass subclasses must call TargetTransformInfo::getAnalysisUsage.
64 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
67 /// This class is intended to be subclassed by real implementations.
68 virtual ~TargetTransformInfo() = 0;
70 /// \name Scalar Target Information
73 /// PopcntHwSupport - Hardware support for population count. Compared to the
74 /// SW implementation, HW support is supposed to significantly boost the
75 /// performance when the population is dense, and it may or may not degrade
76 /// performance if the population is sparse. A HW support is considered as
77 /// "Fast" if it can outperform, or is on a par with, SW implementaion when
78 /// the population is sparse; otherwise, it is considered as "Slow".
79 enum PopcntHwSupport {
85 /// isLegalAddImmediate - Return true if the specified immediate is legal
86 /// add immediate, that is the target has add instructions which can add
87 /// a register with the immediate without having to materialize the
88 /// immediate into a register.
89 virtual bool isLegalAddImmediate(int64_t Imm) const;
91 /// isLegalICmpImmediate - Return true if the specified immediate is legal
92 /// icmp immediate, that is the target has icmp instructions which can compare
93 /// a register against the immediate without having to materialize the
94 /// immediate into a register.
95 virtual bool isLegalICmpImmediate(int64_t Imm) const;
97 /// isLegalAddressingMode - Return true if the addressing mode represented by
98 /// AM is legal for this target, for a load/store of the specified type.
99 /// The type may be VoidTy, in which case only return true if the addressing
100 /// mode is legal for a load/store of any legal type.
101 /// TODO: Handle pre/postinc as well.
102 virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
103 int64_t BaseOffset, bool HasBaseReg,
104 int64_t Scale) const;
106 /// isTruncateFree - Return true if it's free to truncate a value of
107 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
108 /// register EAX to i16 by referencing its sub-register AX.
109 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
111 /// Is this type legal.
112 virtual bool isTypeLegal(Type *Ty) const;
114 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
115 virtual unsigned getJumpBufAlignment() const;
117 /// getJumpBufSize - returns the target's jmp_buf size in bytes.
118 virtual unsigned getJumpBufSize() const;
120 /// shouldBuildLookupTables - Return true if switches should be turned into
121 /// lookup tables for the target.
122 virtual bool shouldBuildLookupTables() const;
124 /// getPopcntHwSupport - Return hardware support for population count.
125 virtual PopcntHwSupport getPopcntHwSupport(unsigned IntTyWidthInBit) const;
127 /// getIntImmCost - Return the expected cost of materializing the given
128 /// integer immediate of the specified type.
129 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
133 /// \name Vector Target Information
137 Broadcast, // Broadcast element 0 to all other elements.
138 Reverse, // Reverse the order of the vector.
139 InsertSubvector, // InsertSubvector. Index indicates start offset.
140 ExtractSubvector // ExtractSubvector Index indicates start offset.
143 /// \return The number of scalar or vector registers that the target has.
144 /// If 'Vectors' is true, it returns the number of vector registers. If it is
145 /// set to false, it returns the number of scalar registers.
146 virtual unsigned getNumberOfRegisters(bool Vector) const;
148 /// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
149 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
151 /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
152 /// The index and subtype parameters are used by the subvector insertion and
153 /// extraction shuffle kinds.
154 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, int Index = 0,
155 Type *SubTp = 0) const;
157 /// \return The expected cost of cast instructions, such as bitcast, trunc,
159 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
162 /// \return The expected cost of control-flow related instrutctions such as
164 virtual unsigned getCFInstrCost(unsigned Opcode) const;
166 /// \returns The expected cost of compare and select instructions.
167 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
168 Type *CondTy = 0) const;
170 /// \return The expected cost of vector Insert and Extract.
171 /// Use -1 to indicate that there is no information on the index value.
172 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
173 unsigned Index = -1) const;
175 /// \return The cost of Load and Store instructions.
176 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
178 unsigned AddressSpace) const;
180 /// \returns The cost of Intrinsic instructions.
181 virtual unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
182 ArrayRef<Type *> Tys) const;
184 /// \returns The number of pieces into which the provided type must be
185 /// split during legalization. Zero is returned when the answer is unknown.
186 virtual unsigned getNumberOfParts(Type *Tp) const;
190 /// Analysis group identification.
194 /// \brief Create the base case instance of a pass in the TTI analysis group.
196 /// This class provides the base case for the stack of TTI analyses. It doesn't
197 /// delegate to anything and uses the STTI and VTTI objects passed in to
198 /// satisfy the queries.
199 ImmutablePass *createNoTargetTransformInfoPass();
201 } // End llvm namespace