1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
36 /// The SubRegs field is a zero terminated array of registers that are
37 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
38 /// The SuperRegs field is a zero terminated array of registers that are
39 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
42 struct TargetRegisterDesc {
43 const char *AsmName; // Assembly language name for the register
44 const char *Name; // Printable name for the reg (for debugging)
45 const unsigned *AliasSet; // Register Alias Set, described above
46 const unsigned *SubRegs; // Sub-register set, described above
47 const unsigned *SuperRegs; // Super-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const MVT* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
66 const iterator RegsBegin, RegsEnd;
68 TargetRegisterClass(unsigned id,
71 const TargetRegisterClass * const *subcs,
72 const TargetRegisterClass * const *supcs,
73 unsigned RS, unsigned Al, int CC,
74 iterator RB, iterator RE)
75 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
76 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
77 virtual ~TargetRegisterClass() {} // Allow subclasses
79 /// getID() - Return the register class ID number.
81 unsigned getID() const { return ID; }
83 /// getName() - Return the register class name for debugging.
85 const char *getName() const { return Name; }
87 /// begin/end - Return all of the registers in this class.
89 iterator begin() const { return RegsBegin; }
90 iterator end() const { return RegsEnd; }
92 /// getNumRegs - Return the number of registers in this class.
94 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
96 /// getRegister - Return the specified register in the class.
98 unsigned getRegister(unsigned i) const {
99 assert(i < getNumRegs() && "Register number out of range!");
103 /// contains - Return true if the specified register is included in this
105 bool contains(unsigned Reg) const {
106 for (iterator I = begin(), E = end(); I != E; ++I)
107 if (*I == Reg) return true;
111 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
113 bool hasType(MVT vt) const {
114 for(int i = 0; VTs[i] != MVT::Other; ++i)
120 /// vt_begin / vt_end - Loop over all of the value types that can be
121 /// represented by values in this register class.
122 vt_iterator vt_begin() const {
126 vt_iterator vt_end() const {
128 while (*I != MVT::Other) ++I;
132 /// hasSubClass - return true if the specified TargetRegisterClass is a
133 /// sub-register class of this TargetRegisterClass.
134 bool hasSubClass(const TargetRegisterClass *cs) const {
135 for (int i = 0; SubClasses[i] != NULL; ++i)
136 if (SubClasses[i] == cs)
141 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
142 /// this register class.
143 sc_iterator subclasses_begin() const {
147 sc_iterator subclasses_end() const {
148 sc_iterator I = SubClasses;
149 while (*I != NULL) ++I;
153 /// hasSuperClass - return true if the specified TargetRegisterClass is a
154 /// super-register class of this TargetRegisterClass.
155 bool hasSuperClass(const TargetRegisterClass *cs) const {
156 for (int i = 0; SuperClasses[i] != NULL; ++i)
157 if (SuperClasses[i] == cs)
162 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
163 /// of this register class.
164 sc_iterator superclasses_begin() const {
168 sc_iterator superclasses_end() const {
169 sc_iterator I = SuperClasses;
170 while (*I != NULL) ++I;
174 /// isASubClass - return true if this TargetRegisterClass is a sub-class of at
175 /// least one other TargetRegisterClass.
176 bool isASubClass() const {
177 return SuperClasses[0] != 0;
180 /// allocation_order_begin/end - These methods define a range of registers
181 /// which specify the registers in this class that are valid to register
182 /// allocate, and the preferred order to allocate them in. For example,
183 /// callee saved registers should be at the end of the list, because it is
184 /// cheaper to allocate caller saved registers.
186 /// These methods take a MachineFunction argument, which can be used to tune
187 /// the allocatable registers based on the characteristics of the function.
188 /// One simple example is that the frame pointer register can be used if
189 /// frame-pointer-elimination is performed.
191 /// By default, these methods return all registers in the class.
193 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
196 virtual iterator allocation_order_end(const MachineFunction &MF) const {
202 /// getSize - Return the size of the register in bytes, which is also the size
203 /// of a stack slot allocated to hold a spilled copy of this register.
204 unsigned getSize() const { return RegSize; }
206 /// getAlignment - Return the minimum required alignment for a register of
208 unsigned getAlignment() const { return Alignment; }
210 /// getCopyCost - Return the cost of copying a value between two registers in
211 /// this class. A negative number means the register class is very expensive
212 /// to copy e.g. status flag register classes.
213 int getCopyCost() const { return CopyCost; }
217 /// TargetRegisterInfo base class - We assume that the target defines a static
218 /// array of TargetRegisterDesc objects that represent all of the machine
219 /// registers that the target has. As such, we simply have to track a pointer
220 /// to this array so that we can turn register number into a register
223 class TargetRegisterInfo {
225 const unsigned* SubregHash;
226 const unsigned SubregHashSize;
227 const unsigned* SuperregHash;
228 const unsigned SuperregHashSize;
230 typedef const TargetRegisterClass * const * regclass_iterator;
232 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
233 unsigned NumRegs; // Number of entries in the array
235 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
237 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
239 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
240 regclass_iterator RegClassBegin,
241 regclass_iterator RegClassEnd,
242 int CallFrameSetupOpcode = -1,
243 int CallFrameDestroyOpcode = -1,
244 const unsigned* subregs = 0,
245 const unsigned subregsize = 0,
246 const unsigned* superregs = 0,
247 const unsigned superregsize = 0);
248 virtual ~TargetRegisterInfo();
251 enum { // Define some target independent constants
252 /// NoRegister - This physical register is not a real target register. It
253 /// is useful as a sentinal.
256 /// FirstVirtualRegister - This is the first register number that is
257 /// considered to be a 'virtual' register, which is part of the SSA
258 /// namespace. This must be the same for all targets, which means that each
259 /// target is limited to 1024 registers.
260 FirstVirtualRegister = 1024
263 /// isPhysicalRegister - Return true if the specified register number is in
264 /// the physical register namespace.
265 static bool isPhysicalRegister(unsigned Reg) {
266 assert(Reg && "this is not a register!");
267 return Reg < FirstVirtualRegister;
270 /// isVirtualRegister - Return true if the specified register number is in
271 /// the virtual register namespace.
272 static bool isVirtualRegister(unsigned Reg) {
273 assert(Reg && "this is not a register!");
274 return Reg >= FirstVirtualRegister;
277 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
278 /// register of the given type. If type is MVT::Other, then just return any
279 /// register class the register belongs to.
280 virtual const TargetRegisterClass *
281 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
283 /// getAllocatableSet - Returns a bitset indexed by register number
284 /// indicating if a register is allocatable or not. If a register class is
285 /// specified, returns the subset for the class.
286 BitVector getAllocatableSet(MachineFunction &MF,
287 const TargetRegisterClass *RC = NULL) const;
289 const TargetRegisterDesc &operator[](unsigned RegNo) const {
290 assert(RegNo < NumRegs &&
291 "Attempting to access record for invalid register number!");
295 /// Provide a get method, equivalent to [], but more useful if we have a
296 /// pointer to this object.
298 const TargetRegisterDesc &get(unsigned RegNo) const {
299 return operator[](RegNo);
302 /// getAliasSet - Return the set of registers aliased by the specified
303 /// register, or a null list of there are none. The list returned is zero
306 const unsigned *getAliasSet(unsigned RegNo) const {
307 return get(RegNo).AliasSet;
310 /// getSubRegisters - Return the list of registers that are sub-registers of
311 /// the specified register, or a null list of there are none. The list
312 /// returned is zero terminated and sorted according to super-sub register
313 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
315 const unsigned *getSubRegisters(unsigned RegNo) const {
316 return get(RegNo).SubRegs;
319 /// getSuperRegisters - Return the list of registers that are super-registers
320 /// of the specified register, or a null list of there are none. The list
321 /// returned is zero terminated and sorted according to super-sub register
322 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
324 const unsigned *getSuperRegisters(unsigned RegNo) const {
325 return get(RegNo).SuperRegs;
328 /// getAsmName - Return the symbolic target-specific name for the
329 /// specified physical register.
330 const char *getAsmName(unsigned RegNo) const {
331 return get(RegNo).AsmName;
334 /// getName - Return the human-readable symbolic target-specific name for the
335 /// specified physical register.
336 const char *getName(unsigned RegNo) const {
337 return get(RegNo).Name;
340 /// getNumRegs - Return the number of registers this target has (useful for
341 /// sizing arrays holding per register information)
342 unsigned getNumRegs() const {
346 /// areAliases - Returns true if the two registers alias each other, false
348 bool areAliases(unsigned regA, unsigned regB) const {
349 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
350 if (*Alias == regB) return true;
354 /// regsOverlap - Returns true if the two registers are equal or alias each
355 /// other. The registers may be virtual register.
356 bool regsOverlap(unsigned regA, unsigned regB) const {
360 if (isVirtualRegister(regA) || isVirtualRegister(regB))
362 return areAliases(regA, regB);
365 /// isSubRegister - Returns true if regB is a sub-register of regA.
367 bool isSubRegister(unsigned regA, unsigned regB) const {
368 // SubregHash is a simple quadratically probed hash table.
369 size_t index = (regA + regB * 37) & (SubregHashSize-1);
370 unsigned ProbeAmt = 2;
371 while (SubregHash[index*2] != 0 &&
372 SubregHash[index*2+1] != 0) {
373 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
376 index = (index + ProbeAmt) & (SubregHashSize-1);
383 /// isSuperRegister - Returns true if regB is a super-register of regA.
385 bool isSuperRegister(unsigned regA, unsigned regB) const {
386 // SuperregHash is a simple quadratically probed hash table.
387 size_t index = (regA + regB * 37) & (SuperregHashSize-1);
388 unsigned ProbeAmt = 2;
389 while (SuperregHash[index*2] != 0 &&
390 SuperregHash[index*2+1] != 0) {
391 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
394 index = (index + ProbeAmt) & (SuperregHashSize-1);
401 /// getCalleeSavedRegs - Return a null-terminated list of all of the
402 /// callee saved registers on this target. The register should be in the
403 /// order of desired callee-save stack frame offset. The first register is
404 /// closed to the incoming stack pointer if stack grows down, and vice versa.
405 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
408 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
409 /// register classes to spill each callee saved register with. The order and
410 /// length of this list match the getCalleeSaveRegs() list.
411 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
412 const MachineFunction *MF) const =0;
414 /// getReservedRegs - Returns a bitset indexed by physical register number
415 /// indicating if a register is a special register that has particular uses
416 /// and should be considered unavailable at all times, e.g. SP, RA. This is
417 /// used by register scavenger to determine what registers are free.
418 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
420 /// getSubReg - Returns the physical register number of sub-register "Index"
421 /// for physical register RegNo. Return zero if the sub-register does not
423 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
425 //===--------------------------------------------------------------------===//
426 // Register Class Information
429 /// Register class iterators
431 regclass_iterator regclass_begin() const { return RegClassBegin; }
432 regclass_iterator regclass_end() const { return RegClassEnd; }
434 unsigned getNumRegClasses() const {
435 return (unsigned)(regclass_end()-regclass_begin());
438 /// getRegClass - Returns the register class associated with the enumeration
439 /// value. See class TargetOperandInfo.
440 const TargetRegisterClass *getRegClass(unsigned i) const {
441 assert(i <= getNumRegClasses() && "Register Class ID out of range");
442 return i ? RegClassBegin[i - 1] : NULL;
445 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
447 virtual const TargetRegisterClass *getPointerRegClass() const {
448 assert(0 && "Target didn't implement getPointerRegClass!");
449 return 0; // Must return a value in order to compile with VS 2005
452 /// getCrossCopyRegClass - Returns a legal register class to copy a register
453 /// in the specified class to or from. Returns NULL if it is possible to copy
454 /// between a two registers of the specified class.
455 virtual const TargetRegisterClass *
456 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
460 /// targetHandlesStackFrameRounding - Returns true if the target is
461 /// responsible for rounding up the stack frame (probably at emitPrologue
463 virtual bool targetHandlesStackFrameRounding() const {
467 /// requiresRegisterScavenging - returns true if the target requires (and can
468 /// make use of) the register scavenger.
469 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
473 /// hasFP - Return true if the specified function should have a dedicated
474 /// frame pointer register. For most targets this is true only if the function
475 /// has variable sized allocas or if frame pointer elimination is disabled.
476 virtual bool hasFP(const MachineFunction &MF) const = 0;
478 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
479 // not required, we reserve argument space for call sites in the function
480 // immediately on entry to the current function. This eliminates the need for
481 // add/sub sp brackets around call sites. Returns true if the call frame is
482 // included as part of the stack frame.
483 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
487 // needsStackRealignment - true if storage within the function requires the
488 // stack pointer to be aligned more than the normal calling convention calls
490 virtual bool needsStackRealignment(const MachineFunction &MF) const {
494 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
495 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
496 /// targets use pseudo instructions in order to abstract away the difference
497 /// between operating with a frame pointer and operating without, through the
498 /// use of these two instructions.
500 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
501 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
503 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
504 /// code insertion to eliminate call frame setup and destroy pseudo
505 /// instructions (but only if the Target is using them). It is responsible
506 /// for eliminating these instructions, replacing them with concrete
507 /// instructions. This method need only be implemented if using call frame
508 /// setup/destroy pseudo instructions.
511 eliminateCallFramePseudoInstr(MachineFunction &MF,
512 MachineBasicBlock &MBB,
513 MachineBasicBlock::iterator MI) const {
514 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
515 "eliminateCallFramePseudoInstr must be implemented if using"
516 " call frame setup/destroy pseudo instructions!");
517 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
520 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
521 /// before PrologEpilogInserter scans the physical registers used to determine
522 /// what callee saved registers should be spilled. This method is optional.
523 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
524 RegScavenger *RS = NULL) const {
528 /// processFunctionBeforeFrameFinalized - This method is called immediately
529 /// before the specified functions frame layout (MF.getFrameInfo()) is
530 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
531 /// replaced with direct constants. This method is optional.
533 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
536 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
537 /// frame indices from instructions which may use them. The instruction
538 /// referenced by the iterator contains an MO_FrameIndex operand which must be
539 /// eliminated by this method. This method may modify or replace the
540 /// specified instruction, as long as it keeps the iterator pointing the the
541 /// finished product. SPAdj is the SP adjustment due to call frame setup
543 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
544 int SPAdj, RegScavenger *RS=NULL) const = 0;
546 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
548 virtual void emitPrologue(MachineFunction &MF) const = 0;
549 virtual void emitEpilogue(MachineFunction &MF,
550 MachineBasicBlock &MBB) const = 0;
552 //===--------------------------------------------------------------------===//
553 /// Debug information queries.
555 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
556 /// number. Returns -1 if there is no equivalent value. The second
557 /// parameter allows targets to use different numberings for EH info and
559 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
561 /// getFrameRegister - This method should return the register used as a base
562 /// for values allocated in the current stack frame.
563 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
565 /// getFrameIndexOffset - Returns the displacement from the frame register to
566 /// the stack frame of the specified index.
567 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
569 /// getRARegister - This method should return the register where the return
570 /// address can be found.
571 virtual unsigned getRARegister() const = 0;
573 /// getInitialFrameState - Returns a list of machine moves that are assumed
574 /// on entry to all functions. Note that LabelID is ignored (assumed to be
575 /// the beginning of the function.)
576 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
579 // This is useful when building IndexedMaps keyed on virtual registers
580 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
581 unsigned operator()(unsigned Reg) const {
582 return Reg - TargetRegisterInfo::FirstVirtualRegister;
586 } // End llvm namespace