1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/MC/MCCodeGenInfo.h"
18 #include "llvm/ADT/StringRef.h"
24 class InstrItineraryData;
31 class PassManagerBase;
34 class TargetELFWriterInfo;
35 class TargetFrameLowering;
36 class TargetInstrInfo;
37 class TargetIntrinsicInfo;
40 class TargetRegisterInfo;
41 class TargetSelectionDAGInfo;
42 class TargetSubtargetInfo;
43 class formatted_raw_ostream;
46 // Code generation optimization level.
47 namespace CodeGenOpt {
58 None, // No preference
59 RegPressure, // Scheduling for lowest register pressure.
60 Hybrid, // Scheduling for both latency and register pressure.
61 ILP // Scheduling for ILP in low register pressure mode.
65 //===----------------------------------------------------------------------===//
67 /// TargetMachine - Primary interface to the complete machine description for
68 /// the target machine. All target-specific information should be accessible
69 /// through this interface.
72 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
73 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
74 protected: // Can only create subclasses.
75 TargetMachine(const Target &T, StringRef TargetTriple,
76 StringRef CPU, StringRef FS);
78 /// getSubtargetImpl - virtual method implemented by subclasses that returns
79 /// a reference to that target's TargetSubtargetInfo-derived member variable.
80 virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
82 /// TheTarget - The Target that this machine was created for.
83 const Target &TheTarget;
85 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
86 /// feature strings the TargetMachine instance is created with.
87 std::string TargetTriple;
88 std::string TargetCPU;
91 /// CodeGenInfo - Low level target information such as relocation model.
92 const MCCodeGenInfo *CodeGenInfo;
94 /// AsmInfo - Contains target specific asm information.
96 const MCAsmInfo *AsmInfo;
98 unsigned MCRelaxAll : 1;
99 unsigned MCNoExecStack : 1;
100 unsigned MCSaveTempLabels : 1;
101 unsigned MCUseLoc : 1;
102 unsigned MCUseCFI : 1;
103 unsigned MCUseDwarfDirectory : 1;
106 virtual ~TargetMachine();
108 const Target &getTarget() const { return TheTarget; }
110 const StringRef getTargetTriple() const { return TargetTriple; }
111 const StringRef getTargetCPU() const { return TargetCPU; }
112 const StringRef getTargetFeatureString() const { return TargetFS; }
114 // Interfaces to the major aspects of target machine information:
115 // -- Instruction opcode and operand information
116 // -- Pipelines and scheduling information
117 // -- Stack frame information
118 // -- Selection DAG lowering information
120 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
121 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
122 virtual const TargetLowering *getTargetLowering() const { return 0; }
123 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
124 virtual const TargetData *getTargetData() const { return 0; }
126 /// getMCAsmInfo - Return target specific asm information.
128 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
130 /// getSubtarget - This method returns a pointer to the specified type of
131 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
132 /// returned is of the correct type.
133 template<typename STC> const STC &getSubtarget() const {
134 return *static_cast<const STC*>(getSubtargetImpl());
137 /// getRegisterInfo - If register information is available, return it. If
138 /// not, return null. This is kept separate from RegInfo until RegInfo has
139 /// details of graph coloring register allocation removed from it.
141 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
143 /// getIntrinsicInfo - If intrinsic information is available, return it. If
144 /// not, return null.
146 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
148 /// getJITInfo - If this target supports a JIT, return information for it,
149 /// otherwise return null.
151 virtual TargetJITInfo *getJITInfo() { return 0; }
153 /// getInstrItineraryData - Returns instruction itinerary data for the target
154 /// or specific subtarget.
156 virtual const InstrItineraryData *getInstrItineraryData() const {
160 /// getELFWriterInfo - If this target supports an ELF writer, return
161 /// information for it, otherwise return null.
163 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
165 /// hasMCRelaxAll - Check whether all machine code instructions should be
167 bool hasMCRelaxAll() const { return MCRelaxAll; }
169 /// setMCRelaxAll - Set whether all machine code instructions should be
171 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
173 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
174 /// (i.e., not treated as temporary).
175 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
177 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
178 /// (i.e., not treated as temporary).
179 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
181 /// hasMCNoExecStack - Check whether an executable stack is not needed.
182 bool hasMCNoExecStack() const { return MCNoExecStack; }
184 /// setMCNoExecStack - Set whether an executabel stack is not needed.
185 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
187 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
188 bool hasMCUseLoc() const { return MCUseLoc; }
190 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
191 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
193 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
194 bool hasMCUseCFI() const { return MCUseCFI; }
196 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
197 void setMCUseCFI(bool Value) { MCUseCFI = Value; }
199 /// hasMCUseDwarfDirectory - Check whether we should use .file directives with
200 /// explicit directories.
201 bool hasMCUseDwarfDirectory() const { return MCUseDwarfDirectory; }
203 /// setMCUseDwarfDirectory - Set whether all we should use .file directives
204 /// with explicit directories.
205 void setMCUseDwarfDirectory(bool Value) { MCUseDwarfDirectory = Value; }
207 /// getRelocationModel - Returns the code generation relocation model. The
208 /// choices are static, PIC, and dynamic-no-pic, and target default.
209 Reloc::Model getRelocationModel() const;
211 /// getCodeModel - Returns the code model. The choices are small, kernel,
212 /// medium, large, and target default.
213 CodeModel::Model getCodeModel() const;
215 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
217 static bool getAsmVerbosityDefault();
219 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
221 static void setAsmVerbosityDefault(bool);
223 /// getDataSections - Return true if data objects should be emitted into their
224 /// own section, corresponds to -fdata-sections.
225 static bool getDataSections();
227 /// getFunctionSections - Return true if functions should be emitted into
228 /// their own section, corresponding to -ffunction-sections.
229 static bool getFunctionSections();
231 /// setDataSections - Set if the data are emit into separate sections.
232 static void setDataSections(bool);
234 /// setFunctionSections - Set if the functions are emit into separate
236 static void setFunctionSections(bool);
238 /// CodeGenFileType - These enums are meant to be passed into
239 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
240 /// it to indicate what type of file could actually be made.
241 enum CodeGenFileType {
244 CGFT_Null // Do not emit any output.
247 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
248 /// on this target. User flag overrides.
249 virtual bool getEnableTailMergeDefault() const { return true; }
251 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
252 /// specified file emitted. Typically this will involve several steps of code
253 /// generation. This method should return true if emission of this file type
254 /// is not supported, or false on success.
255 virtual bool addPassesToEmitFile(PassManagerBase &,
256 formatted_raw_ostream &,
263 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
264 /// get machine code emitted. This uses a JITCodeEmitter object to handle
265 /// actually outputting the machine code and resolving things like the address
266 /// of functions. This method returns true if machine code emission is
269 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
276 /// addPassesToEmitMC - Add passes to the specified pass manager to get
277 /// machine code emitted with the MCJIT. This method returns true if machine
278 /// code is not supported. It fills the MCContext Ctx pointer which can be
279 /// used to build custom MCStreamer.
281 virtual bool addPassesToEmitMC(PassManagerBase &,
290 /// LLVMTargetMachine - This class describes a target machine that is
291 /// implemented with the LLVM target-independent code generator.
293 class LLVMTargetMachine : public TargetMachine {
294 protected: // Can only create subclasses.
295 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
296 StringRef CPU, StringRef FS,
297 Reloc::Model RM, CodeModel::Model CM);
300 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
301 /// both emitting to assembly files or machine code output.
303 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
304 bool DisableVerify, MCContext *&OutCtx);
307 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
308 /// specified file emitted. Typically this will involve several steps of code
309 /// generation. If OptLevel is None, the code generator should emit code as
310 /// fast as possible, though the generated code may be less efficient.
311 virtual bool addPassesToEmitFile(PassManagerBase &PM,
312 formatted_raw_ostream &Out,
313 CodeGenFileType FileType,
315 bool DisableVerify = true);
317 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
318 /// get machine code emitted. This uses a JITCodeEmitter object to handle
319 /// actually outputting the machine code and resolving things like the address
320 /// of functions. This method returns true if machine code emission is
323 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
326 bool DisableVerify = true);
328 /// addPassesToEmitMC - Add passes to the specified pass manager to get
329 /// machine code emitted with the MCJIT. This method returns true if machine
330 /// code is not supported. It fills the MCContext Ctx pointer which can be
331 /// used to build custom MCStreamer.
333 virtual bool addPassesToEmitMC(PassManagerBase &PM,
336 CodeGenOpt::Level OptLevel,
337 bool DisableVerify = true);
339 /// Target-Independent Code Generator Pass Configuration Options.
341 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
342 /// passes (which are run just before instruction selector).
343 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
347 /// addInstSelector - This method should install an instruction selector pass,
348 /// which converts from LLVM code to machine instructions.
349 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
353 /// addPreRegAlloc - This method may be implemented by targets that want to
354 /// run passes immediately before register allocation. This should return
355 /// true if -print-machineinstrs should print after these passes.
356 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
360 /// addPostRegAlloc - This method may be implemented by targets that want
361 /// to run passes after register allocation but before prolog-epilog
362 /// insertion. This should return true if -print-machineinstrs should print
363 /// after these passes.
364 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
368 /// addPreSched2 - This method may be implemented by targets that want to
369 /// run passes after prolog-epilog insertion and before the second instruction
370 /// scheduling pass. This should return true if -print-machineinstrs should
371 /// print after these passes.
372 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
376 /// addPreEmitPass - This pass may be implemented by targets that want to run
377 /// passes immediately before machine code is emitted. This should return
378 /// true if -print-machineinstrs should print out the code after the passes.
379 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
384 /// addCodeEmitter - This pass should be overridden by the target to add a
385 /// code emitter, if supported. If this is not supported, 'true' should be
387 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
392 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
393 /// on this target. User flag overrides.
394 virtual bool getEnableTailMergeDefault() const { return true; }
397 } // End llvm namespace